1 /* 2 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * Copyright (c) 2008 Atheros Communications Inc. 8 * 9 * Permission to use, copy, modify, and/or distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 #ifndef _ARN_CORE_H 23 #define _ARN_CORE_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 #include <sys/note.h> 30 #include <sys/list.h> 31 #include <sys/net80211.h> 32 33 #include "arn_ath9k.h" 34 #include "arn_rc.h" 35 36 struct ath_node; 37 38 /* 39 * Node type of wifi device 40 */ 41 #ifndef DDI_NT_NET_WIFI 42 #define DDI_NT_NET_WIFI "ddi_network:wifi" 43 #endif 44 #define ARN_NODENAME "arn" 45 46 #define ARN_LOCK(_sc) mutex_enter(&(_sc)->sc_genlock) 47 #define ARN_UNLOCK(_sc) mutex_exit(&(_sc)->sc_genlock) 48 #define ARN_LOCK_ASSERT(_sc) ASSERT(mutex_owned(&(_sc)->sc_genlock)) 49 50 #define ARRAY_SIZE(x) (sizeof (x) / sizeof (x[0])) 51 52 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 53 54 #define ARN_MIN(a, b) ((a) < (b) ? (a) : (b)) 55 #define ARN_MAX(a, b) ((a) > (b) ? (a) : (b)) 56 57 #define abs(x) ((x) >= 0 ? (x) : -(x)) 58 59 enum ath9k_key_len { 60 ATH9K_LEN_WEP40 = 5, 61 ATH9K_LEN_WEP104 = 13, 62 }; 63 64 /* 65 * Sync a DMA area described by a dma_area_t 66 */ 67 #define ARN_DMA_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_hdl, \ 68 (area).offset, (area).alength, (flag))) 69 70 #define list_empty(a) ((a)->list_head.list_next == &(a)->list_head) 71 72 #define ARN_LE_READ_16(p) \ 73 ((uint16_t) \ 74 ((((uint8_t *)(p))[0]) | (((uint8_t *)(p))[1] << 8))) 75 76 #define ARN_LE_READ_32(p) \ 77 ((uint32_t) \ 78 ((((uint8_t *)(p))[0]) | (((uint8_t *)(p))[1] << 8) | \ 79 (((uint8_t *)(p))[2] << 16) | (((uint8_t *)(p))[3] << 24))) 80 81 #define swab16(value) \ 82 ((((value) & 0xff) << 8) | ((value) >> 8)) 83 84 #define swab32(value) \ 85 (((uint32_t)swab16((uint16_t)((value) & 0xffff)) << 16) | \ 86 (uint32_t)swab16((uint16_t)((value) >> 16))) 87 88 #define swab64(value) \ 89 (((uint64_t)swab32((uint32_t)((value) & 0xffffffff)) \ 90 << 32) | \ 91 (uint64_t)swab32((uint32_t)((value) >> 32))) 92 93 /* Bit map related macros. */ 94 #define set_bit(i, a) ((a)[(i)/NBBY] |= (1 << ((i)%NBBY))) 95 #define clr_bit(i, a) ((a)[(i)/NBBY] &= ~(1 << ((i)%NBBY))) 96 #define is_set(i, a) ((a)[(i)/NBBY] & (1 << ((i)%NBBY))) 97 #define is_clr(i, a) (!((a)[(i)/NBBY] & (1 << ((i)%NBBY)))) 98 99 /* Macro to expand scalars to 64-bit objects */ 100 101 #define ito64(x) (sizeof (x) == 8) ? \ 102 (((unsigned long long int)(x)) & (0xff)) : \ 103 (sizeof (x) == 16) ? \ 104 (((unsigned long long int)(x)) & 0xffff) : \ 105 ((sizeof (x) == 32) ? \ 106 (((unsigned long long int)(x)) & 0xffffffff) : \ 107 (unsigned long long int)(x)) 108 109 /* increment with wrap-around */ 110 #define INCR(_l, _sz) do { \ 111 (_l)++; \ 112 (_l) &= ((_sz) - 1); \ 113 } while (0) 114 115 /* decrement with wrap-around */ 116 #define DECR(_l, _sz) do { \ 117 (_l)--; \ 118 (_l) &= ((_sz) - 1); \ 119 } while (0) 120 121 #define A_MAX(a, b) ((a) > (b) ? (a) : (b)) 122 123 #define TSF_TO_TU(_h, _l) \ 124 ((((uint32_t)(_h)) << 22) | (((uint32_t)(_l)) >> 10)) 125 126 #define ARN_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 127 128 // static const uint8_t ath_bcast_mac[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 129 130 /* Debugging */ 131 enum ARN_DEBUG { 132 ARN_DBG_HW = 0x00000001, 133 ARN_DBG_REG_IO = 0x00000002, 134 ARN_DBG_QUEUE = 0x00000004, 135 ARN_DBG_EEPROM = 0x00000008, 136 ARN_DBG_XMIT = 0x00000010, 137 ARN_DBG_RECV = 0x00000020, 138 ARN_DBG_CALIBRATE = 0x00000040, 139 ARN_DBG_CHANNEL = 0x00000080, 140 ARN_DBG_INTERRUPT = 0x00000100, 141 ARN_DBG_REGULATORY = 0x00000200, 142 ARN_DBG_ANI = 0x00000400, 143 ARN_DBG_POWER_MGMT = 0x00000800, 144 ARN_DBG_KEYCACHE = 0x00001000, 145 ARN_DBG_BEACON = 0x00002000, 146 ARN_DBG_RATE = 0x00004000, 147 ARN_DBG_INIT = 0x00008000, 148 ARN_DBG_ATTACH = 0x00010000, 149 ARN_DBG_DEATCH = 0x00020000, 150 ARN_DBG_AGGR = 0x00040000, 151 ARN_DBG_RESET = 0x00080000, 152 ARN_DBG_FATAL = 0x00100000, 153 ARN_DBG_ANY = 0x00200000, 154 ARN_DBG_ALL = 0x00FFFFFF, 155 }; 156 157 /* Debug and log functions */ 158 void arn_dbg(uint32_t dbg_flags, const int8_t *fmt, ...); /* debug function */ 159 void arn_log(const int8_t *fmt, ...); /* event log function */ 160 void arn_problem(const int8_t *fmt, ...); /* run-time problem function */ 161 162 #ifdef DEBUG 163 #define ARN_DDB(command) do { \ 164 { command; } \ 165 _NOTE(CONSTANTCONDITION)\ 166 } while (0) 167 #else 168 #define ARN_DDB(command) 169 #endif /* DEBUG */ 170 171 #define ARN_DBG(args) ARN_DDB(arn_dbg args) 172 173 struct ath_stats { 174 uint32_t ast_hardware; /* fatal hardware error interrupts */ 175 uint32_t ast_rxorn; /* rx overrun interrupts */ 176 uint32_t ast_rxeol; /* rx eol interrupts */ 177 uint32_t ast_txurn; /* tx underrun interrupts */ 178 uint32_t ast_tx_mgmt; /* management frames transmitted */ 179 uint32_t ast_tx_discard; /* frames discarded prior to assoc */ 180 uint32_t ast_tx_invalid; /* frames discarded 'cuz device gone */ 181 uint32_t ast_tx_qstop; /* tx queue stopped 'cuz full */ 182 uint32_t ast_tx_nobuf; /* tx failed 'cuz no tx buffer (data) */ 183 uint32_t ast_tx_nobufmgt; /* tx failed 'cuz no tx buffer(mgmt) */ 184 uint32_t ast_tx_xretries; /* tx failed 'cuz too many retries */ 185 uint32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */ 186 uint32_t ast_tx_filtered; /* tx failed 'cuz xmit filtered */ 187 uint32_t ast_tx_shortretry; /* tx on-chip retries (short) */ 188 uint32_t ast_tx_longretry; /* tx on-chip retries (long) */ 189 uint32_t ast_tx_noack; /* tx frames with no ack marked */ 190 uint32_t ast_tx_rts; /* tx frames with rts enabled */ 191 uint32_t ast_tx_shortpre; /* tx frames with short preamble */ 192 uint32_t ast_tx_altrate; /* tx frames with alternate rate */ 193 uint32_t ast_tx_protect; /* tx frames with protection */ 194 int16_t ast_tx_rssi; /* tx rssi of last ack */ 195 int16_t ast_tx_rssidelta; /* tx rssi delta */ 196 uint32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */ 197 uint32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */ 198 uint32_t ast_rx_badcrypt; /* rx failed 'cuz decryption */ 199 uint32_t ast_rx_phyerr; /* rx PHY error summary count */ 200 uint32_t ast_rx_phy[32]; /* rx PHY error per-code counts */ 201 uint32_t ast_rx_tooshort; /* rx discarded 'cuz frame too short */ 202 uint32_t ast_per_cal; /* periodic calibration calls */ 203 uint32_t ast_per_calfail; /* periodic calibration failed */ 204 uint32_t ast_per_rfgain; /* periodic calibration rfgain reset */ 205 uint32_t ast_rate_calls; /* rate control checks */ 206 uint32_t ast_rate_raise; /* rate control raised xmit rate */ 207 uint32_t ast_rate_drop; /* rate control dropped xmit rate */ 208 }; 209 210 struct dma_area { 211 ddi_acc_handle_t acc_hdl; /* handle for memory */ 212 caddr_t mem_va; /* CPU VA of memory */ 213 uint32_t nslots; /* number of slots */ 214 uint32_t size; /* size per slot */ 215 size_t alength; /* allocated size */ 216 /* >= product of above */ 217 218 ddi_dma_handle_t dma_hdl; /* DMA handle */ 219 offset_t offset; /* relative to handle */ 220 ddi_dma_cookie_t cookie; /* associated cookie */ 221 uint32_t ncookies; /* must be 1 */ 222 uint32_t token; /* arbitrary identifier */ 223 }; 224 typedef struct dma_area dma_area_t; 225 226 /* Load-time Configuration */ 227 228 /* 229 * Per-instance load-time (note: NOT run-time) 230 * configurations for Atheros Device 231 */ 232 struct ath_config { 233 uint32_t ath_aggr_prot; 234 uint16_t txpowlimit; 235 uint16_t txpowlimit_override; 236 uint8_t cabqReadytime; /* Cabq Readytime % */ 237 uint8_t swBeaconProcess; /* Process received beacons in SW (vs HW) */ 238 }; 239 240 /* Descriptor Management */ 241 242 #define ATH_TXBUF_RESET(_bf) do { \ 243 (_bf)->bf_status = 0; \ 244 (_bf)->bf_lastbf = NULL; \ 245 (_bf)->bf_lastfrm = NULL; \ 246 (_bf)->bf_next = NULL; \ 247 memset(&((_bf)->bf_state), 0, \ 248 sizeof (struct ath_buf_state)); \ 249 } while (0) 250 251 enum buffer_type { 252 BUF_DATA = BIT(0), 253 BUF_AGGR = BIT(1), 254 BUF_AMPDU = BIT(2), 255 BUF_HT = BIT(3), 256 BUF_RETRY = BIT(4), 257 BUF_XRETRY = BIT(5), 258 BUF_SHORT_PREAMBLE = BIT(6), 259 BUF_BAR = BIT(7), 260 BUF_PSPOLL = BIT(8), 261 BUF_AGGR_BURST = BIT(9), 262 BUF_CALC_AIRTIME = BIT(10), 263 }; 264 265 struct ath_buf_state { 266 int bfs_nframes; /* # frames in aggregate */ 267 uint16_t bfs_al; /* length of aggregate */ 268 uint16_t bfs_frmlen; /* length of frame */ 269 int bfs_seqno; /* sequence number */ 270 int bfs_tidno; /* tid of this frame */ 271 int bfs_retries; /* current retries */ 272 uint32_t bf_type; /* BUF_* (enum buffer_type) */ 273 /* key type used to encrypt this frame */ 274 uint32_t bfs_keyix; 275 enum ath9k_key_type bfs_keytype; 276 }; 277 278 #define bf_nframes bf_state.bfs_nframes 279 #define bf_al bf_state.bfs_al 280 #define bf_frmlen bf_state.bfs_frmlen 281 #define bf_retries bf_state.bfs_retries 282 #define bf_seqno bf_state.bfs_seqno 283 #define bf_tidno bf_state.bfs_tidno 284 #define bf_rcs bf_state.bfs_rcs 285 #define bf_keyix bf_state.bfs_keyix 286 #define bf_keytype bf_state.bfs_keytype 287 #define bf_isdata(bf) (bf->bf_state.bf_type & BUF_DATA) 288 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) 289 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) 290 #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT) 291 #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY) 292 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY) 293 #define bf_isshpreamble(bf) (bf->bf_state.bf_type & BUF_SHORT_PREAMBLE) 294 #define bf_isbar(bf) (bf->bf_state.bf_type & BUF_BAR) 295 #define bf_ispspoll(bf) (bf->bf_state.bf_type & BUF_PSPOLL) 296 #define bf_isaggrburst(bf) (bf->bf_state.bf_type & BUF_AGGR_BURST) 297 298 /* 299 * Abstraction of a contiguous buffer to transmit/receive. 300 * There is only a single hw descriptor encapsulated here. 301 */ 302 struct ath_buf { 303 /* last buf of this unit (a frame or an aggregate) */ 304 struct ath_buf *bf_lastbf; 305 struct ath_buf *bf_lastfrm; /* last buf of this frame */ 306 struct ath_buf *bf_next; /* next subframe in the aggregate */ 307 mblk_t *bf_m; 308 struct ath_desc *bf_desc; /* virtual addr of desc */ 309 uint32_t bf_daddr; /* physical addr of desc */ 310 dma_area_t bf_dma; /* dma area for buf */ 311 struct ieee80211_node *bf_in; /* pointer to the node */ 312 uint32_t bf_status; 313 uint16_t bf_flags; /* tx descriptor flags */ 314 struct ath_buf_state bf_state; /* buffer state */ 315 316 /* we're in list of sc->sc_txbuf_list or asc->asc_rxbuf_list */ 317 list_node_t bf_node; 318 }; 319 320 /* 321 * reset the rx buffer. 322 * any new fields added to the athbuf and require 323 * reset need to be added to this macro. 324 * currently bf_status is the only one requires that 325 * requires reset. 326 */ 327 #define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0) 328 329 /* hw processing complete, desc processed by hal */ 330 #define ATH_BUFSTATUS_DONE 0x00000001 331 /* hw processing complete, desc hold for hw */ 332 #define ATH_BUFSTATUS_STALE 0x00000002 333 /* Rx-only: OS is done with this packet and it's ok to queued it to hw */ 334 #define ATH_BUFSTATUS_FREE 0x00000004 335 336 /* RX / TX */ 337 338 #define ATH_MAX_ANTENNA 3 339 #define ATH_RXBUF 512 340 #define WME_NUM_TID 16 341 342 void arn_rx_buf_link(struct arn_softc *sc, struct ath_buf *bf); 343 int arn_startrecv(struct arn_softc *sc); 344 boolean_t arn_stoprecv(struct arn_softc *sc); 345 void arn_flushrecv(struct arn_softc *sc); 346 uint32_t arn_calcrxfilter(struct arn_softc *sc); 347 int arn_rx_init(struct arn_softc *sc, int nbufs); 348 void arn_rx_cleanup(struct arn_softc *sc); 349 uint_t arn_softint_handler(caddr_t data); 350 void arn_setdefantenna(struct arn_softc *sc, uint32_t antenna); 351 352 #define ATH_TXBUF 512 353 /* max number of transmit attempts (tries) */ 354 #define ATH_TXMAXTRY 13 355 /* max number of 11n transmit attempts (tries) */ 356 #define ATH_11N_TXMAXTRY 10 357 /* max number of tries for management and control frames */ 358 #define ATH_MGT_TXMAXTRY 4 359 #define WME_BA_BMP_SIZE 64 360 #define WME_MAX_BA WME_BA_BMP_SIZE 361 #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA) 362 363 /* Wireless Multimedia Extension Defines */ 364 #define WME_AC_BE 0 /* best effort */ 365 #define WME_AC_BK 1 /* background */ 366 #define WME_AC_VI 2 /* video */ 367 #define WME_AC_VO 3 /* voice */ 368 #define WME_NUM_AC 4 369 370 /* 371 * Data transmit queue state. One of these exists for each 372 * hardware transmit queue. Packets sent to us from above 373 * are assigned to queues based on their priority. Not all 374 * devices support a complete set of hardware transmit queues. 375 * For those devices the array sc_ac2q will map multiple 376 * priorities to fewer hardware queues (typically all to one 377 * hardware queue). 378 */ 379 380 struct ath_txq { 381 uint_t axq_qnum; /* hardware q number */ 382 uint32_t *axq_link; /* link ptr in last TX desc */ 383 list_t axq_list; /* transmit queue */ 384 kmutex_t axq_lock; /* lock on q and link */ 385 unsigned long axq_lockflags; /* intr state when must cli */ 386 uint_t axq_depth; /* queue depth (stat only) */ 387 uint8_t axq_aggr_depth; /* aggregates queued */ 388 uint32_t axq_totalqueued; /* total ever queued */ 389 struct ath_buf *axq_linkbuf; /* virtual addr of last buffer */ 390 /* first desc of the last descriptor that contains CTS */ 391 struct ath_desc *axq_lastdsWithCTS; 392 uint_t axq_intrcnt; /* interrupt count */ 393 }; 394 395 396 #define AGGR_CLEANUP BIT(1) 397 #define AGGR_ADDBA_COMPLETE BIT(2) 398 #define AGGR_ADDBA_PROGRESS BIT(3) 399 400 /* per TID aggregate tx state for a destination */ 401 struct ath_atx_tid { 402 list_node_t list; 403 list_node_t buf_q; 404 struct ath_node *an; 405 struct ath_atx_ac *ac; 406 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */ 407 uint16_t seq_start; 408 uint16_t seq_next; 409 uint16_t baw_size; 410 int tidno; 411 int baw_head; /* first un-acked tx buffer */ 412 int baw_tail; /* next unused tx buffer slot */ 413 int sched; 414 int paused; 415 uint8_t state; 416 int addba_exchangeattempts; 417 }; 418 419 /* per access-category aggregate tx state for a destination */ 420 struct ath_atx_ac { 421 int sched; /* dest-ac is scheduled */ 422 int qnum; /* H/W queue number associated with this AC */ 423 list_node_t list; 424 list_node_t tid_q; 425 }; 426 427 /* per dest tx state */ 428 struct ath_atx { 429 struct ath_atx_tid tid[WME_NUM_TID]; 430 struct ath_atx_ac ac[WME_NUM_AC]; 431 }; 432 433 /* per-frame tx control block */ 434 struct ath_tx_control { 435 struct ath_txq *txq; 436 int if_id; 437 }; 438 439 /* per frame tx status block */ 440 struct ath_xmit_status { 441 /* number of retries to successufully transmit this frame */ 442 int retries; 443 int flags; /* status of transmit */ 444 #define ATH_TX_ERROR 0x01 445 #define ATH_TX_XRETRY 0x02 446 #define ATH_TX_BAR 0x04 447 }; 448 449 struct ath_tx_stat { 450 int rssi; /* RSSI (noise floor ajusted) */ 451 int rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */ 452 int rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */ 453 int rateieee; /* data rate xmitted (IEEE rate code) */ 454 int rateKbps; /* data rate xmitted (Kbps) */ 455 int ratecode; /* phy rate code */ 456 int flags; /* validity flags */ 457 /* if any of ctl,extn chain rssis are valid */ 458 #define ATH_TX_CHAIN_RSSI_VALID 0x01 459 /* if extn chain rssis are valid */ 460 #define ATH_TX_RSSI_EXTN_VALID 0x02 461 uint32_t airtime; /* time on air per final tx rate */ 462 }; 463 464 struct ath_txq *arn_txq_setup(struct arn_softc *sc, int qtype, int subtype); 465 void arn_tx_cleanupq(struct arn_softc *sc, struct ath_txq *txq); 466 int arn_tx_setup(struct arn_softc *sc, int haltype); 467 void arn_draintxq(struct arn_softc *sc, boolean_t retry_tx); 468 void arn_tx_draintxq(struct arn_softc *sc, struct ath_txq *txq); 469 int arn_tx(ieee80211com_t *ic, mblk_t *mp, uint8_t type); 470 int arn_txq_update(struct arn_softc *sc, int qnum, 471 struct ath9k_tx_queue_info *qinfo); 472 void arn_tx_int_proc(void *arg); 473 474 /* Node / Aggregation */ 475 476 #define ADDBA_EXCHANGE_ATTEMPTS 10 477 #define ATH_AGGR_DELIM_SZ 4 /* delimiter size */ 478 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ 479 /* number of delimiters for encryption padding */ 480 #define ATH_AGGR_ENCRYPTDELIM 10 481 /* minimum h/w qdepth to be sustained to maximize aggregation */ 482 #define ATH_AGGR_MIN_QDEPTH 2 483 #define ATH_AMPDU_SUBFRAME_DEFAULT 32 484 #define IEEE80211_SEQ_SEQ_SHIFT 4 485 #define IEEE80211_SEQ_MAX 4096 486 #define IEEE80211_MIN_AMPDU_BUF 0x8 487 #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13 488 489 /* 490 * return whether a bit at index _n in bitmap _bm is set 491 * _sz is the size of the bitmap 492 */ 493 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ 494 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) 495 496 /* return block-ack bitmap index given sequence and starting sequence */ 497 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) 498 499 /* returns delimiter padding required given the packet length */ 500 #define ATH_AGGR_GET_NDELIM(_len) \ 501 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \ 502 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2) 503 504 #define BAW_WITHIN(_start, _bawsz, _seqno) \ 505 ((((_seqno) - (_start)) & 4095) < (_bawsz)) 506 507 #define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum) 508 #define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low) 509 #define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA) 510 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->an_aggr.tx.tid[(_tidno)]) 511 512 enum ATH_AGGR_STATUS { 513 ATH_AGGR_DONE, 514 ATH_AGGR_BAW_CLOSED, 515 ATH_AGGR_LIMITED, 516 ATH_AGGR_SHORTPKT, 517 ATH_AGGR_8K_LIMITED, 518 }; 519 520 struct aggr_rifs_param { 521 int param_max_frames; 522 int param_max_len; 523 int param_rl; 524 int param_al; 525 struct ath_rc_series *param_rcs; 526 }; 527 528 /* driver-specific node state */ 529 struct ath_node { 530 struct ieee80211_node an_node; /* base class */ 531 uint32_t an_tx_times; /* rate ctl times on one rate */ 532 uint32_t an_tx_ok; /* tx ok pkt */ 533 uint32_t an_tx_err; /* tx !ok pkt */ 534 uint32_t an_tx_retr; /* tx retry count */ 535 int32_t an_tx_upper; /* tx upper rate req cnt */ 536 uint32_t an_tx_antenna; /* antenna for last good frame */ 537 uint8_t an_tx_rix0; /* series 0 rate index */ 538 uint8_t an_tx_try0; /* series 0 try count */ 539 uint8_t an_tx_mgtrate; /* h/w rate for management/ctl frames */ 540 uint8_t an_tx_mgtratesp; /* short preamble h/w rate for " " */ 541 uint8_t an_tx_rate0; /* series 0 h/w rate */ 542 uint8_t an_tx_rate1; /* series 1 h/w rate */ 543 uint8_t an_tx_rate2; /* series 2 h/w rate */ 544 uint8_t an_tx_rate3; /* series 3 h/w rate */ 545 uint8_t an_tx_rate0sp; /* series 0 short preamble h/w rate */ 546 uint8_t an_tx_rate1sp; /* series 1 short preamble h/w rate */ 547 uint8_t an_tx_rate2sp; /* series 2 short preamble h/w rate */ 548 uint8_t an_tx_rate3sp; /* series 3 short preamble h/w rate */ 549 struct arn_softc *an_sc; 550 #ifdef ARN_11N 551 struct ath_node_aggr an_aggr; 552 #endif 553 uint16_t maxampdu; 554 uint8_t mpdudensity; 555 }; 556 #define ATH_NODE(_n) ((struct ath_node *)(_n)) 557 558 /* 559 * Define the scheme that we select MAC address for multiple 560 * BSS on the same radio. The very first VAP will just use the MAC 561 * address from the EEPROM. For the next 3 VAPs, we set the 562 * U/L bit (bit 1) in MAC address, and use the next two bits as the 563 * index of the VAP. 564 */ 565 566 #define ATH_SET_VAP_BSSID_MASK(bssid_mask) \ 567 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02)) 568 569 570 /* driver-specific vap state */ 571 struct ath_vap { 572 int av_bslot; /* beacon slot index */ 573 enum ath9k_opmode av_opmode; /* VAP operational mode */ 574 struct ath_buf *av_bcbuf; /* beacon buffer */ 575 struct ath_tx_control av_btxctl; /* txctl information for beacon */ 576 }; 577 578 /* Beacon Handling */ 579 580 /* 581 * Regardless of the number of beacons we stagger, (i.e. regardless of the 582 * number of BSSIDs) if a given beacon does not go out even after waiting this 583 * number of beacon intervals, the game's up. 584 */ 585 #define BSTUCK_THRESH (9 * ATH_BCBUF) 586 #define ATH_BCBUF 4 /* number of beacon buffers */ 587 #define ATH_DEFAULT_BINTVAL 100 /* default beacon interval in TU */ 588 #define ATH_DEFAULT_BMISS_LIMIT 10 589 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) 590 591 /* beacon configuration */ 592 struct ath_beacon_config { 593 uint16_t beacon_interval; 594 uint16_t listen_interval; 595 uint16_t dtim_period; 596 uint16_t bmiss_timeout; 597 uint8_t dtim_count; 598 uint8_t tim_offset; 599 union { 600 uint64_t last_tsf; 601 uint8_t last_tstamp[8]; 602 } u; /* last received beacon/probe response timestamp of this BSS. */ 603 }; 604 605 uint32_t arn_beaconq_setup(struct ath_hal *ah); 606 int arn_beacon_alloc(struct arn_softc *sc, struct ieee80211_node *in); 607 void arn_beacon_config(struct arn_softc *sc); 608 void arn_beacon_return(struct arn_softc *sc); 609 void arn_beacon_sync(struct arn_softc *sc); 610 void arn_bmiss_proc(void *arg); 611 612 void arn_recv_mgmt(struct ieee80211com *ic, mblk_t *mp, 613 struct ieee80211_node *in, int subtype, int rssi, uint32_t rstamp); 614 615 /* ANI */ 616 617 /* 618 * ANI values for STA only. 619 * FIXME: Add appropriate values for AP later 620 */ 621 622 #define ATH_ANI_POLLINTERVAL 100 /* 100 milliseconds between ANI poll */ 623 #define ATH_SHORT_CALINTERVAL 1000 /* 1 second between calibrations */ 624 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds between calibrations */ 625 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */ 626 627 struct ath_ani { 628 boolean_t sc_caldone; 629 int16_t sc_noise_floor; 630 unsigned int sc_longcal_timer; 631 unsigned int sc_shortcal_timer; 632 unsigned int sc_resetcal_timer; 633 unsigned int sc_checkani_timer; 634 }; 635 636 /* LED Control */ 637 #define ATH_LED_PIN 1 638 639 enum ath_led_type { 640 ATH_LED_RADIO, 641 ATH_LED_ASSOC, 642 ATH_LED_TX, 643 ATH_LED_RX 644 }; 645 646 struct ath_led { 647 struct arn_softc *sc; 648 enum ath_led_type led_type; 649 char name[32]; 650 boolean_t registered; 651 }; 652 653 /* Rfkill */ 654 #define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */ 655 656 /* Main driver core */ 657 /* 658 * Default cache line size, in bytes. 659 * Used when PCI device not fully initialized by bootrom/BIOS 660 */ 661 #define DEFAULT_CACHELINE 32 662 #define ATH_DEFAULT_NOISE_FLOOR -95 663 #define ATH_REGCLASSIDS_MAX 10 664 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ 665 #define ATH_MAX_SW_RETRIES 10 666 #define ATH_CHAN_MAX 255 667 #define IEEE80211_WEP_NKID 4 /* number of key ids */ 668 #define IEEE80211_RATE_VAL 0x7f 669 /* 670 * The key cache is used for h/w cipher state and also for 671 * tracking station state such as the current tx antenna. 672 * We also setup a mapping table between key cache slot indices 673 * and station state to short-circuit node lookups on rx. 674 * Different parts have different size key caches. We handle 675 * up to ATH_KEYMAX entries (could dynamically allocate state). 676 */ 677 #define ATH_KEYMAX 128 /* max key cache size we handle */ 678 679 #define ATH_IF_ID_ANY 0xff 680 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ 681 #define ATH_RSSI_DUMMY_MARKER 0x127 682 #define ATH_RATE_DUMMY_MARKER 0 683 684 enum PROT_MODE { 685 PROT_M_NONE = 0, 686 PROT_M_RTSCTS, 687 PROT_M_CTSONLY 688 }; 689 690 #define SC_OP_INVALID BIT(0) 691 #define SC_OP_BEACONS BIT(1) 692 #define SC_OP_RXAGGR BIT(2) 693 #define SC_OP_TXAGGR BIT(3) 694 #define SC_OP_CHAINMASK_UPDATE BIT(4) 695 #define SC_OP_FULL_RESET BIT(5) 696 #define SC_OP_NO_RESET BIT(6) 697 #define SC_OP_PREAMBLE_SHORT BIT(7) 698 #define SC_OP_PROTECT_ENABLE BIT(8) 699 #define SC_OP_RXFLUSH BIT(9) 700 #define SC_OP_LED_ASSOCIATED BIT(10) 701 #define SC_OP_RFKILL_REGISTERED BIT(11) 702 #define SC_OP_RFKILL_SW_BLOCKED BIT(12) 703 #define SC_OP_RFKILL_HW_BLOCKED BIT(13) 704 705 struct arn_softc { 706 ieee80211com_t sc_isc; /* IEEE 802.11 common */ 707 dev_info_t *sc_dev; /* back pointer to dev_info_t */ 708 ddi_taskq_t *sc_tq; /* private task queue */ 709 struct ath_hal *sc_ah; 710 struct ath_config sc_config; 711 caddr_t mem; 712 713 uint8_t sc_isrunning; /* device is operational */ 714 uint8_t sc_mrretry; /* multi-rate retry support */ 715 uint8_t sc_have11g; /* have 11g support */ 716 uint8_t sc_bsync; /* beacon sync */ 717 718 ddi_acc_handle_t sc_cfg_handle; /* DDI I/O handle */ 719 ddi_acc_handle_t sc_io_handle; /* DDI I/O handle */ 720 ddi_acc_handle_t sc_EEPROM_handle; /* DDI I/O handle */ 721 ddi_iblock_cookie_t sc_iblock; 722 ddi_softintr_t sc_softint_id; 723 724 /* TX/RX descriptors */ 725 struct ath_desc *sc_desc; 726 /* descriptor structure */ 727 dma_area_t sc_desc_dma; 728 /* pointer to the first "struct ath_buf" */ 729 struct ath_buf *sc_vbufptr; 730 /* length of all allocated "struct ath_buf" */ 731 uint32_t sc_vbuflen; 732 /* size of one DMA TX/RX buffer based on 802.11 MTU */ 733 int32_t sc_dmabuf_size; 734 735 uint8_t sc_curbssid[6]; 736 uint8_t sc_myaddr[6]; 737 uint8_t sc_bssidmask[6]; 738 739 int sc_debug; 740 uint32_t sc_intrstatus; 741 uint32_t sc_flags; /* SC_OP_* */ 742 unsigned int rx_filter; 743 uint16_t sc_curtxpow; 744 uint16_t sc_curaid; 745 uint16_t sc_cachelsz; 746 int sc_slotupdate; /* slot to next advance fsm */ 747 int sc_slottime; 748 int sc_bslot[ATH_BCBUF]; 749 uint8_t sc_tx_chainmask; 750 uint8_t sc_rx_chainmask; 751 enum ath9k_int sc_imask; 752 enum PROT_MODE sc_protmode; 753 754 uint8_t sc_nbcnvaps; /* # of vaps sending beacons */ 755 uint16_t sc_nvaps; /* # of active virtual ap's */ 756 757 uint8_t sc_mcastantenna; 758 uint8_t sc_defant; /* current default antenna */ 759 uint8_t sc_rxotherant; /* rx's on non-default antenna */ 760 761 struct ath9k_node_stats sc_halstats; /* station-mode rssi stats */ 762 enum ath9k_ht_extprotspacing sc_ht_extprotspacing; 763 enum ath9k_ht_macmode tx_chan_width; 764 765 enum { 766 OK, /* no change needed */ 767 UPDATE, /* update pending */ 768 COMMIT /* beacon sent, commit change */ 769 } sc_updateslot; /* slot time update fsm */ 770 771 /* Crypto */ 772 uint32_t sc_keymax; /* size of key cache */ 773 uint8_t sc_keymap[16]; /* bit map of key cache use */ 774 uint8_t sc_splitmic; /* split TKIP MIC keys */ 775 776 /* RX */ 777 list_t sc_rxbuf_list; 778 int sc_rxbufsize; /* rx size based on mtu */ 779 uint32_t *sc_rxlink; /* link ptr in last RX desc */ 780 uint32_t sc_rx_pend; 781 uint64_t sc_lastrx; /* tsf at last rx'd frame */ 782 783 /* TX */ 784 list_t sc_txbuf_list; 785 struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES]; 786 uint32_t sc_txqsetup; 787 int sc_haltype2q[ATH9K_WME_AC_VO+1]; /* HAL WME AC -> h/w qnum */ 788 uint16_t seq_no; /* TX sequence number */ 789 790 /* Beacon */ 791 struct ath9k_tx_queue_info sc_beacon_qi; 792 struct ath_txq *sc_cabq; 793 list_t sc_bcbuf_list; /* beacon buffer */ 794 uint32_t sc_beaconq; 795 uint32_t sc_bmisscount; 796 uint32_t ast_be_xmit; /* beacons transmitted */ 797 uint64_t bc_tstamp; 798 struct ieee80211_beacon_offsets asc_boff; /* dynamic update state */ 799 800 /* Rate */ 801 struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX]; 802 struct ath_rate_table *sc_currates; /* current rate table */ 803 uint8_t asc_rixmap[256]; /* IEEE to h/w rate table ix */ 804 uint8_t sc_protrix; /* protection rate index */ 805 806 /* mode */ 807 enum wireless_mode sc_curmode; /* current phy mode */ 808 809 /* Channel, Band */ 810 struct ath9k_channel sc_curchan; 811 812 /* Locks */ 813 kmutex_t sc_genlock; 814 kmutex_t sc_serial_rw; 815 kmutex_t sc_rxbuflock; /* recv lock */ 816 kmutex_t sc_txbuflock; /* txbuf lock */ 817 kmutex_t sc_rxflushlock; 818 kmutex_t sc_resetlock; 819 kmutex_t sc_bcbuflock; /* beacon buffer lock */ 820 kmutex_t sc_resched_lock; 821 boolean_t sc_resched_needed; 822 823 /* LEDs */ 824 struct ath_led radio_led; 825 struct ath_led assoc_led; 826 struct ath_led tx_led; 827 struct ath_led rx_led; 828 829 uint8_t sc_mcast_refs[64]; /* refer count */ 830 uint32_t sc_mcast_hash[2]; /* multicast hash table */ 831 832 /* Rfkill */ 833 834 /* ANI */ 835 struct ath_ani sc_ani; 836 837 /* interface statistics */ 838 struct ath_stats sc_stats; 839 840 boolean_t sc_promisc; /* Promiscuous mode enabled */ 841 842 timeout_id_t sc_scan_timer; 843 timeout_id_t sc_cal_timer; 844 845 int (*sc_newstate)(ieee80211com_t *, enum ieee80211_state, int); 846 void (*sc_recv_mgmt)(ieee80211com_t *, mblk_t *, ieee80211_node_t *, 847 int, int, uint32_t); 848 }; 849 850 int arn_reset(ieee80211com_t *ic); 851 852 int arn_get_hal_qnum(uint16_t queue, struct arn_softc *sc); 853 854 int ath_cabq_update(struct arn_softc *); 855 856 /* 857 * Read and write, they both share the same lock. We do this to serialize 858 * reads and writes on Atheros 802.11n PCI devices only. This is required 859 * as the FIFO on these devices can only accept sanely 2 requests. After 860 * that the device goes bananas. Serializing the reads/writes prevents this 861 * from happening. 862 */ 863 void 864 arn_iowrite32(struct ath_hal *ah, uint32_t reg_offset, uint32_t val); 865 unsigned int 866 arn_ioread32(struct ath_hal *ah, uint32_t reg_offset); 867 868 #ifdef __cplusplus 869 } 870 #endif 871 872 #endif /* _ARN_CORE_H */ 873