1*eb00b1c8SRobert Mustacchi /*
2*eb00b1c8SRobert Mustacchi  * This file and its contents are supplied under the terms of the
3*eb00b1c8SRobert Mustacchi  * Common Development and Distribution License ("CDDL"), version 1.0.
4*eb00b1c8SRobert Mustacchi  * You may only use this file in accordance with the terms of version
5*eb00b1c8SRobert Mustacchi  * 1.0 of the CDDL.
6*eb00b1c8SRobert Mustacchi  *
7*eb00b1c8SRobert Mustacchi  * A full copy of the text of the CDDL should have accompanied this
8*eb00b1c8SRobert Mustacchi  * source.  A copy of the CDDL is also available via the Internet at
9*eb00b1c8SRobert Mustacchi  * http://www.illumos.org/license/CDDL.
10*eb00b1c8SRobert Mustacchi  */
11*eb00b1c8SRobert Mustacchi 
12*eb00b1c8SRobert Mustacchi /*
13*eb00b1c8SRobert Mustacchi  * Copyright 2019 Joyent, Inc.
14*eb00b1c8SRobert Mustacchi  */
15*eb00b1c8SRobert Mustacchi 
16*eb00b1c8SRobert Mustacchi #include "imc_test.h"
17*eb00b1c8SRobert Mustacchi 
18*eb00b1c8SRobert Mustacchi /*
19*eb00b1c8SRobert Mustacchi  * This tests various aspects of the target address decoder.
20*eb00b1c8SRobert Mustacchi  *
21*eb00b1c8SRobert Mustacchi  * o TAD rules with different channel interleaving
22*eb00b1c8SRobert Mustacchi  * o TAD rules with channel shifting (IVB->BRD)
23*eb00b1c8SRobert Mustacchi  * o TAD rules with channel hashing (IVB->BRD)
24*eb00b1c8SRobert Mustacchi  * o TAD rules with different granularities (SKX)
25*eb00b1c8SRobert Mustacchi  * o Channel rules with mod2/3 variants (SKX)
26*eb00b1c8SRobert Mustacchi  *
27*eb00b1c8SRobert Mustacchi  * We use the most basic of SAD rules and RIR rules when constructing these.
28*eb00b1c8SRobert Mustacchi  * Those are more generally exercised elsewhere. Basic socket granularity rules
29*eb00b1c8SRobert Mustacchi  * are tested in imc_test_sad.c.
30*eb00b1c8SRobert Mustacchi  *
31*eb00b1c8SRobert Mustacchi  * There are currently no tests for mirroring or lockstep mode as that's not
32*eb00b1c8SRobert Mustacchi  * more generally supported.
33*eb00b1c8SRobert Mustacchi  */
34*eb00b1c8SRobert Mustacchi 
35*eb00b1c8SRobert Mustacchi static const imc_t imc_tad_1s_2cw = {
36*eb00b1c8SRobert Mustacchi 	.imc_gen = IMC_GEN_SANDY,
37*eb00b1c8SRobert Mustacchi 	.imc_nsockets = 1,
38*eb00b1c8SRobert Mustacchi 	.imc_sockets[0] = {
39*eb00b1c8SRobert Mustacchi 		.isock_valid = IMC_SOCKET_V_VALID,
40*eb00b1c8SRobert Mustacchi 		.isock_sad = {
41*eb00b1c8SRobert Mustacchi 			.isad_flags = 0,
42*eb00b1c8SRobert Mustacchi 			.isad_valid = IMC_SAD_V_VALID,
43*eb00b1c8SRobert Mustacchi 			.isad_tolm = 0x80000000,
44*eb00b1c8SRobert Mustacchi 			.isad_tohm = 0,
45*eb00b1c8SRobert Mustacchi 			.isad_nrules = 10,
46*eb00b1c8SRobert Mustacchi 			.isad_rules[0] = {
47*eb00b1c8SRobert Mustacchi 				.isr_enable = B_TRUE,
48*eb00b1c8SRobert Mustacchi 				.isr_limit = 0x80000000,
49*eb00b1c8SRobert Mustacchi 				.isr_imode = IMC_SAD_IMODE_8t6,
50*eb00b1c8SRobert Mustacchi 				.isr_ntargets = IMC_MAX_SAD_INTERLEAVE,
51*eb00b1c8SRobert Mustacchi 				.isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 }
52*eb00b1c8SRobert Mustacchi 			}
53*eb00b1c8SRobert Mustacchi 		},
54*eb00b1c8SRobert Mustacchi 		.isock_ntad = 1,
55*eb00b1c8SRobert Mustacchi 		.isock_tad[0] = {
56*eb00b1c8SRobert Mustacchi 			.itad_flags = 0,
57*eb00b1c8SRobert Mustacchi 			.itad_nrules = 12,
58*eb00b1c8SRobert Mustacchi 			.itad_rules[0] = {
59*eb00b1c8SRobert Mustacchi 				.itr_base = 0x0,
60*eb00b1c8SRobert Mustacchi 				.itr_limit = 0x80000000,
61*eb00b1c8SRobert Mustacchi 				.itr_sock_way = 1,
62*eb00b1c8SRobert Mustacchi 				.itr_chan_way = 2,
63*eb00b1c8SRobert Mustacchi 				.itr_sock_gran = IMC_TAD_GRAN_64B,
64*eb00b1c8SRobert Mustacchi 				.itr_chan_gran = IMC_TAD_GRAN_64B,
65*eb00b1c8SRobert Mustacchi 				.itr_ntargets = 4,
66*eb00b1c8SRobert Mustacchi 				.itr_targets = { 0, 1, 0, 0 }
67*eb00b1c8SRobert Mustacchi 			}
68*eb00b1c8SRobert Mustacchi 		},
69*eb00b1c8SRobert Mustacchi 		.isock_nimc = 1,
70*eb00b1c8SRobert Mustacchi 		.isock_imcs[0] = {
71*eb00b1c8SRobert Mustacchi 			.icn_nchannels = 2,
72*eb00b1c8SRobert Mustacchi 			.icn_dimm_type = IMC_DIMM_DDR3,
73*eb00b1c8SRobert Mustacchi 			.icn_ecc = B_TRUE,
74*eb00b1c8SRobert Mustacchi 			.icn_lockstep = B_FALSE,
75*eb00b1c8SRobert Mustacchi 			.icn_closed = B_FALSE,
76*eb00b1c8SRobert Mustacchi 			.icn_channels[0] = {
77*eb00b1c8SRobert Mustacchi 				.ich_ndimms = 1,
78*eb00b1c8SRobert Mustacchi 				.ich_dimms[0] = {
79*eb00b1c8SRobert Mustacchi 					.idimm_present = B_TRUE,
80*eb00b1c8SRobert Mustacchi 					.idimm_nbanks = 3,
81*eb00b1c8SRobert Mustacchi 					.idimm_width = 8,
82*eb00b1c8SRobert Mustacchi 					.idimm_density = 2,
83*eb00b1c8SRobert Mustacchi 					.idimm_nranks = 2,
84*eb00b1c8SRobert Mustacchi 					.idimm_nrows = 14,
85*eb00b1c8SRobert Mustacchi 					.idimm_ncolumns = 10,
86*eb00b1c8SRobert Mustacchi 					.idimm_size = 0x40000000
87*eb00b1c8SRobert Mustacchi 				},
88*eb00b1c8SRobert Mustacchi 				.ich_ntad_offsets = 12,
89*eb00b1c8SRobert Mustacchi 				.ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
90*eb00b1c8SRobert Mustacchi 				    0, 0 },
91*eb00b1c8SRobert Mustacchi 				.ich_nrankileaves = 8,
92*eb00b1c8SRobert Mustacchi 				.ich_rankileaves[0] = {
93*eb00b1c8SRobert Mustacchi 					.irle_enabled = B_TRUE,
94*eb00b1c8SRobert Mustacchi 					.irle_nways = 1,
95*eb00b1c8SRobert Mustacchi 					.irle_nwaysbits = 1,
96*eb00b1c8SRobert Mustacchi 					.irle_limit = 0x40000000,
97*eb00b1c8SRobert Mustacchi 					.irle_nentries = 8,
98*eb00b1c8SRobert Mustacchi 					.irle_entries[0] = { 0x0, 0x0 },
99*eb00b1c8SRobert Mustacchi 				}
100*eb00b1c8SRobert Mustacchi 			},
101*eb00b1c8SRobert Mustacchi 			.icn_channels[1] = {
102*eb00b1c8SRobert Mustacchi 				.ich_ndimms = 1,
103*eb00b1c8SRobert Mustacchi 				.ich_dimms[0] = {
104*eb00b1c8SRobert Mustacchi 					.idimm_present = B_TRUE,
105*eb00b1c8SRobert Mustacchi 					.idimm_nbanks = 3,
106*eb00b1c8SRobert Mustacchi 					.idimm_width = 8,
107*eb00b1c8SRobert Mustacchi 					.idimm_density = 2,
108*eb00b1c8SRobert Mustacchi 					.idimm_nranks = 2,
109*eb00b1c8SRobert Mustacchi 					.idimm_nrows = 14,
110*eb00b1c8SRobert Mustacchi 					.idimm_ncolumns = 10,
111*eb00b1c8SRobert Mustacchi 					.idimm_size = 0x40000000
112*eb00b1c8SRobert Mustacchi 				},
113*eb00b1c8SRobert Mustacchi 				.ich_ntad_offsets = 12,
114*eb00b1c8SRobert Mustacchi 				.ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
115*eb00b1c8SRobert Mustacchi 				    0, 0 },
116*eb00b1c8SRobert Mustacchi 				.ich_nrankileaves = 8,
117*eb00b1c8SRobert Mustacchi 				.ich_rankileaves[0] = {
118*eb00b1c8SRobert Mustacchi 					.irle_enabled = B_TRUE,
119*eb00b1c8SRobert Mustacchi 					.irle_nways = 1,
120*eb00b1c8SRobert Mustacchi 					.irle_nwaysbits = 1,
121*eb00b1c8SRobert Mustacchi 					.irle_limit = 0x40000000,
122*eb00b1c8SRobert Mustacchi 					.irle_nentries = 8,
123*eb00b1c8SRobert Mustacchi 					.irle_entries[0] = { 0x0, 0x0 },
124*eb00b1c8SRobert Mustacchi 				}
125*eb00b1c8SRobert Mustacchi 			}
126*eb00b1c8SRobert Mustacchi 		}
127*eb00b1c8SRobert Mustacchi 	}
128*eb00b1c8SRobert Mustacchi };
129*eb00b1c8SRobert Mustacchi 
130*eb00b1c8SRobert Mustacchi /*
131*eb00b1c8SRobert Mustacchi  * This IMC has the a7mode/McChanShiftUp set. This means that instead of using
132*eb00b1c8SRobert Mustacchi  * bits 0-6 for an address, it should use bits 0-7.
133*eb00b1c8SRobert Mustacchi  */
134*eb00b1c8SRobert Mustacchi static const imc_t imc_tad_1s_2cw_shiftup = {
135*eb00b1c8SRobert Mustacchi 	.imc_gen = IMC_GEN_IVY,
136*eb00b1c8SRobert Mustacchi 	.imc_nsockets = 1,
137*eb00b1c8SRobert Mustacchi 	.imc_sockets[0] = {
138*eb00b1c8SRobert Mustacchi 		.isock_valid = IMC_SOCKET_V_VALID,
139*eb00b1c8SRobert Mustacchi 		.isock_sad = {
140*eb00b1c8SRobert Mustacchi 			.isad_flags = 0,
141*eb00b1c8SRobert Mustacchi 			.isad_valid = IMC_SAD_V_VALID,
142*eb00b1c8SRobert Mustacchi 			.isad_tolm = 0x80000000,
143*eb00b1c8SRobert Mustacchi 			.isad_tohm = 0,
144*eb00b1c8SRobert Mustacchi 			.isad_nrules = 10,
145*eb00b1c8SRobert Mustacchi 			.isad_rules[0] = {
146*eb00b1c8SRobert Mustacchi 				.isr_enable = B_TRUE,
147*eb00b1c8SRobert Mustacchi 				.isr_limit = 0x80000000,
148*eb00b1c8SRobert Mustacchi 				.isr_imode = IMC_SAD_IMODE_8t6,
149*eb00b1c8SRobert Mustacchi 				.isr_ntargets = IMC_MAX_SAD_INTERLEAVE,
150*eb00b1c8SRobert Mustacchi 				.isr_a7mode = B_TRUE,
151*eb00b1c8SRobert Mustacchi 				.isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 }
152*eb00b1c8SRobert Mustacchi 			}
153*eb00b1c8SRobert Mustacchi 		},
154*eb00b1c8SRobert Mustacchi 		.isock_ntad = 1,
155*eb00b1c8SRobert Mustacchi 		.isock_tad[0] = {
156*eb00b1c8SRobert Mustacchi 			.itad_flags = IMC_TAD_FLAG_CHANSHIFT,
157*eb00b1c8SRobert Mustacchi 			.itad_nrules = 12,
158*eb00b1c8SRobert Mustacchi 			.itad_rules[0] = {
159*eb00b1c8SRobert Mustacchi 				.itr_base = 0x0,
160*eb00b1c8SRobert Mustacchi 				.itr_limit = 0x80000000,
161*eb00b1c8SRobert Mustacchi 				.itr_sock_way = 1,
162*eb00b1c8SRobert Mustacchi 				.itr_chan_way = 2,
163*eb00b1c8SRobert Mustacchi 				.itr_sock_gran = IMC_TAD_GRAN_64B,
164*eb00b1c8SRobert Mustacchi 				.itr_chan_gran = IMC_TAD_GRAN_64B,
165*eb00b1c8SRobert Mustacchi 				.itr_ntargets = 4,
166*eb00b1c8SRobert Mustacchi 				.itr_targets = { 0, 1, 0, 0 }
167*eb00b1c8SRobert Mustacchi 			}
168*eb00b1c8SRobert Mustacchi 		},
169*eb00b1c8SRobert Mustacchi 		.isock_nimc = 1,
170*eb00b1c8SRobert Mustacchi 		.isock_imcs[0] = {
171*eb00b1c8SRobert Mustacchi 			.icn_nchannels = 2,
172*eb00b1c8SRobert Mustacchi 			.icn_dimm_type = IMC_DIMM_DDR3,
173*eb00b1c8SRobert Mustacchi 			.icn_ecc = B_TRUE,
174*eb00b1c8SRobert Mustacchi 			.icn_lockstep = B_FALSE,
175*eb00b1c8SRobert Mustacchi 			.icn_closed = B_FALSE,
176*eb00b1c8SRobert Mustacchi 			.icn_channels[0] = {
177*eb00b1c8SRobert Mustacchi 				.ich_ndimms = 1,
178*eb00b1c8SRobert Mustacchi 				.ich_dimms[0] = {
179*eb00b1c8SRobert Mustacchi 					.idimm_present = B_TRUE,
180*eb00b1c8SRobert Mustacchi 					.idimm_nbanks = 3,
181*eb00b1c8SRobert Mustacchi 					.idimm_width = 8,
182*eb00b1c8SRobert Mustacchi 					.idimm_density = 2,
183*eb00b1c8SRobert Mustacchi 					.idimm_nranks = 2,
184*eb00b1c8SRobert Mustacchi 					.idimm_nrows = 14,
185*eb00b1c8SRobert Mustacchi 					.idimm_ncolumns = 10,
186*eb00b1c8SRobert Mustacchi 					.idimm_size = 0x40000000
187*eb00b1c8SRobert Mustacchi 				},
188*eb00b1c8SRobert Mustacchi 				.ich_ntad_offsets = 12,
189*eb00b1c8SRobert Mustacchi 				.ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
190*eb00b1c8SRobert Mustacchi 				    0, 0 },
191*eb00b1c8SRobert Mustacchi 				.ich_nrankileaves = 8,
192*eb00b1c8SRobert Mustacchi 				.ich_rankileaves[0] = {
193*eb00b1c8SRobert Mustacchi 					.irle_enabled = B_TRUE,
194*eb00b1c8SRobert Mustacchi 					.irle_nways = 1,
195*eb00b1c8SRobert Mustacchi 					.irle_nwaysbits = 1,
196*eb00b1c8SRobert Mustacchi 					.irle_limit = 0x40000000,
197*eb00b1c8SRobert Mustacchi 					.irle_nentries = 8,
198*eb00b1c8SRobert Mustacchi 					.irle_entries[0] = { 0x0, 0x0 },
199*eb00b1c8SRobert Mustacchi 				}
200*eb00b1c8SRobert Mustacchi 			},
201*eb00b1c8SRobert Mustacchi 			.icn_channels[1] = {
202*eb00b1c8SRobert Mustacchi 				.ich_ndimms = 1,
203*eb00b1c8SRobert Mustacchi 				.ich_dimms[0] = {
204*eb00b1c8SRobert Mustacchi 					.idimm_present = B_TRUE,
205*eb00b1c8SRobert Mustacchi 					.idimm_nbanks = 3,
206*eb00b1c8SRobert Mustacchi 					.idimm_width = 8,
207*eb00b1c8SRobert Mustacchi 					.idimm_density = 2,
208*eb00b1c8SRobert Mustacchi 					.idimm_nranks = 2,
209*eb00b1c8SRobert Mustacchi 					.idimm_nrows = 14,
210*eb00b1c8SRobert Mustacchi 					.idimm_ncolumns = 10,
211*eb00b1c8SRobert Mustacchi 					.idimm_size = 0x40000000
212*eb00b1c8SRobert Mustacchi 				},
213*eb00b1c8SRobert Mustacchi 				.ich_ntad_offsets = 12,
214*eb00b1c8SRobert Mustacchi 				.ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
215*eb00b1c8SRobert Mustacchi 				    0, 0 },
216*eb00b1c8SRobert Mustacchi 				.ich_nrankileaves = 8,
217*eb00b1c8SRobert Mustacchi 				.ich_rankileaves[0] = {
218*eb00b1c8SRobert Mustacchi 					.irle_enabled = B_TRUE,
219*eb00b1c8SRobert Mustacchi 					.irle_nways = 1,
220*eb00b1c8SRobert Mustacchi 					.irle_nwaysbits = 1,
221*eb00b1c8SRobert Mustacchi 					.irle_limit = 0x40000000,
222*eb00b1c8SRobert Mustacchi 					.irle_nentries = 8,
223*eb00b1c8SRobert Mustacchi 					.irle_entries[0] = { 0x0, 0x0 },
224*eb00b1c8SRobert Mustacchi 				}
225*eb00b1c8SRobert Mustacchi 			}
226*eb00b1c8SRobert Mustacchi 		}
227*eb00b1c8SRobert Mustacchi 	}
228*eb00b1c8SRobert Mustacchi };
229*eb00b1c8SRobert Mustacchi 
230*eb00b1c8SRobert Mustacchi /*
231*eb00b1c8SRobert Mustacchi  * This IMC has the channel hashing mode set on all of the channels in question.
232*eb00b1c8SRobert Mustacchi  * This means that the TAD will hash the upper address bits into the channel
233*eb00b1c8SRobert Mustacchi  * determination.
234*eb00b1c8SRobert Mustacchi  */
235*eb00b1c8SRobert Mustacchi static const imc_t imc_tad_1s_2cw_chanhash = {
236*eb00b1c8SRobert Mustacchi 	.imc_gen = IMC_GEN_HASWELL,
237*eb00b1c8SRobert Mustacchi 	.imc_nsockets = 1,
238*eb00b1c8SRobert Mustacchi 	.imc_sockets[0] = {
239*eb00b1c8SRobert Mustacchi 		.isock_valid = IMC_SOCKET_V_VALID,
240*eb00b1c8SRobert Mustacchi 		.isock_sad = {
241*eb00b1c8SRobert Mustacchi 			.isad_flags = 0,
242*eb00b1c8SRobert Mustacchi 			.isad_valid = IMC_SAD_V_VALID,
243*eb00b1c8SRobert Mustacchi 			.isad_tolm = 0x80000000,
244*eb00b1c8SRobert Mustacchi 			.isad_tohm = 0,
245*eb00b1c8SRobert Mustacchi 			.isad_nrules = 10,
246*eb00b1c8SRobert Mustacchi 			.isad_rules[0] = {
247*eb00b1c8SRobert Mustacchi 				.isr_enable = B_TRUE,
248*eb00b1c8SRobert Mustacchi 				.isr_limit = 0x80000000,
249*eb00b1c8SRobert Mustacchi 				.isr_imode = IMC_SAD_IMODE_8t6,
250*eb00b1c8SRobert Mustacchi 				.isr_ntargets = IMC_MAX_SAD_INTERLEAVE,
251*eb00b1c8SRobert Mustacchi 				.isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 }
252*eb00b1c8SRobert Mustacchi 			}
253*eb00b1c8SRobert Mustacchi 		},
254*eb00b1c8SRobert Mustacchi 		.isock_ntad = 1,
255*eb00b1c8SRobert Mustacchi 		.isock_tad[0] = {
256*eb00b1c8SRobert Mustacchi 			.itad_flags = IMC_TAD_FLAG_CHANHASH,
257*eb00b1c8SRobert Mustacchi 			.itad_nrules = 12,
258*eb00b1c8SRobert Mustacchi 			.itad_rules[0] = {
259*eb00b1c8SRobert Mustacchi 				.itr_base = 0x0,
260*eb00b1c8SRobert Mustacchi 				.itr_limit = 0x80000000,
261*eb00b1c8SRobert Mustacchi 				.itr_sock_way = 1,
262*eb00b1c8SRobert Mustacchi 				.itr_chan_way = 2,
263*eb00b1c8SRobert Mustacchi 				.itr_sock_gran = IMC_TAD_GRAN_64B,
264*eb00b1c8SRobert Mustacchi 				.itr_chan_gran = IMC_TAD_GRAN_64B,
265*eb00b1c8SRobert Mustacchi 				.itr_ntargets = 4,
266*eb00b1c8SRobert Mustacchi 				.itr_targets = { 0, 1, 0, 0 }
267*eb00b1c8SRobert Mustacchi 			}
268*eb00b1c8SRobert Mustacchi 		},
269*eb00b1c8SRobert Mustacchi 		.isock_nimc = 1,
270*eb00b1c8SRobert Mustacchi 		.isock_imcs[0] = {
271*eb00b1c8SRobert Mustacchi 			.icn_nchannels = 2,
272*eb00b1c8SRobert Mustacchi 			.icn_dimm_type = IMC_DIMM_DDR3,
273*eb00b1c8SRobert Mustacchi 			.icn_ecc = B_TRUE,
274*eb00b1c8SRobert Mustacchi 			.icn_lockstep = B_FALSE,
275*eb00b1c8SRobert Mustacchi 			.icn_closed = B_FALSE,
276*eb00b1c8SRobert Mustacchi 			.icn_channels[0] = {
277*eb00b1c8SRobert Mustacchi 				.ich_ndimms = 1,
278*eb00b1c8SRobert Mustacchi 				.ich_dimms[0] = {
279*eb00b1c8SRobert Mustacchi 					.idimm_present = B_TRUE,
280*eb00b1c8SRobert Mustacchi 					.idimm_nbanks = 3,
281*eb00b1c8SRobert Mustacchi 					.idimm_width = 8,
282*eb00b1c8SRobert Mustacchi 					.idimm_density = 2,
283*eb00b1c8SRobert Mustacchi 					.idimm_nranks = 2,
284*eb00b1c8SRobert Mustacchi 					.idimm_nrows = 14,
285*eb00b1c8SRobert Mustacchi 					.idimm_ncolumns = 10,
286*eb00b1c8SRobert Mustacchi 					.idimm_size = 0x40000000
287*eb00b1c8SRobert Mustacchi 				},
288*eb00b1c8SRobert Mustacchi 				.ich_ntad_offsets = 12,
289*eb00b1c8SRobert Mustacchi 				.ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
290*eb00b1c8SRobert Mustacchi 				    0, 0 },
291*eb00b1c8SRobert Mustacchi 				.ich_nrankileaves = 8,
292*eb00b1c8SRobert Mustacchi 				.ich_rankileaves[0] = {
293*eb00b1c8SRobert Mustacchi 					.irle_enabled = B_TRUE,
294*eb00b1c8SRobert Mustacchi 					.irle_nways = 1,
295*eb00b1c8SRobert Mustacchi 					.irle_nwaysbits = 1,
296*eb00b1c8SRobert Mustacchi 					.irle_limit = 0x40000000,
297*eb00b1c8SRobert Mustacchi 					.irle_nentries = 8,
298*eb00b1c8SRobert Mustacchi 					.irle_entries[0] = { 0x0, 0x0 },
299*eb00b1c8SRobert Mustacchi 				}
300*eb00b1c8SRobert Mustacchi 			},
301*eb00b1c8SRobert Mustacchi 			.icn_channels[1] = {
302*eb00b1c8SRobert Mustacchi 				.ich_ndimms = 1,
303*eb00b1c8SRobert Mustacchi 				.ich_dimms[0] = {
304*eb00b1c8SRobert Mustacchi 					.idimm_present = B_TRUE,
305*eb00b1c8SRobert Mustacchi 					.idimm_nbanks = 3,
306*eb00b1c8SRobert Mustacchi 					.idimm_width = 8,
307*eb00b1c8SRobert Mustacchi 					.idimm_density = 2,
308*eb00b1c8SRobert Mustacchi 					.idimm_nranks = 2,
309*eb00b1c8SRobert Mustacchi 					.idimm_nrows = 14,
310*eb00b1c8SRobert Mustacchi 					.idimm_ncolumns = 10,
311*eb00b1c8SRobert Mustacchi 					.idimm_size = 0x40000000
312*eb00b1c8SRobert Mustacchi 				},
313*eb00b1c8SRobert Mustacchi 				.ich_ntad_offsets = 12,
314*eb00b1c8SRobert Mustacchi 				.ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
315*eb00b1c8SRobert Mustacchi 				    0, 0 },
316*eb00b1c8SRobert Mustacchi 				.ich_nrankileaves = 8,
317*eb00b1c8SRobert Mustacchi 				.ich_rankileaves[0] = {
318*eb00b1c8SRobert Mustacchi 					.irle_enabled = B_TRUE,
319*eb00b1c8SRobert Mustacchi 					.irle_nways = 1,
320*eb00b1c8SRobert Mustacchi 					.irle_nwaysbits = 1,
321*eb00b1c8SRobert Mustacchi 					.irle_limit = 0x40000000,
322*eb00b1c8SRobert Mustacchi 					.irle_nentries = 8,
323*eb00b1c8SRobert Mustacchi 					.irle_entries[0] = { 0x0, 0x0 },
324*eb00b1c8SRobert Mustacchi 				}
325*eb00b1c8SRobert Mustacchi 			}
326*eb00b1c8SRobert Mustacchi 		}
327*eb00b1c8SRobert Mustacchi 	}
328*eb00b1c8SRobert Mustacchi };
329*eb00b1c8SRobert Mustacchi 
330*eb00b1c8SRobert Mustacchi /*
331*eb00b1c8SRobert Mustacchi  * This IMC has different TAD rules that cover different ranges, which change
332*eb00b1c8SRobert Mustacchi  * how we interleave. The main goal is to make sure that we're always going to
333*eb00b1c8SRobert Mustacchi  * the right place. This also requires us to set TAD offsets on a
334*eb00b1c8SRobert Mustacchi  * per-channel/TAD rule basis. These are required to correctly make sure that we
335*eb00b1c8SRobert Mustacchi  * map things. The following is how the address space should in theory look. We
336*eb00b1c8SRobert Mustacchi  * have 2 GiB (0x80000000) of address space. We break that into 4 512 MiB
337*eb00b1c8SRobert Mustacchi  * chunks. The first and last are 2-way interleaved. The middle two are 1-way
338*eb00b1c8SRobert Mustacchi  * interleaved to a specific channel.
339*eb00b1c8SRobert Mustacchi  */
340*eb00b1c8SRobert Mustacchi static const imc_t imc_tad_1s_multirule = {
341*eb00b1c8SRobert Mustacchi 	.imc_gen = IMC_GEN_BROADWELL,
342*eb00b1c8SRobert Mustacchi 	.imc_nsockets = 1,
343*eb00b1c8SRobert Mustacchi 	.imc_sockets[0] = {
344*eb00b1c8SRobert Mustacchi 		.isock_valid = IMC_SOCKET_V_VALID,
345*eb00b1c8SRobert Mustacchi 		.isock_sad = {
346*eb00b1c8SRobert Mustacchi 			.isad_flags = 0,
347*eb00b1c8SRobert Mustacchi 			.isad_valid = IMC_SAD_V_VALID,
348*eb00b1c8SRobert Mustacchi 			.isad_tolm = 0x80000000,
349*eb00b1c8SRobert Mustacchi 			.isad_tohm = 0,
350*eb00b1c8SRobert Mustacchi 			.isad_nrules = 10,
351*eb00b1c8SRobert Mustacchi 			.isad_rules[0] = {
352*eb00b1c8SRobert Mustacchi 				.isr_enable = B_TRUE,
353*eb00b1c8SRobert Mustacchi 				.isr_limit = 0x80000000,
354*eb00b1c8SRobert Mustacchi 				.isr_imode = IMC_SAD_IMODE_8t6,
355*eb00b1c8SRobert Mustacchi 				.isr_ntargets = IMC_MAX_SAD_INTERLEAVE,
356*eb00b1c8SRobert Mustacchi 				.isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 }
357*eb00b1c8SRobert Mustacchi 			}
358*eb00b1c8SRobert Mustacchi 		},
359*eb00b1c8SRobert Mustacchi 		.isock_ntad = 1,
360*eb00b1c8SRobert Mustacchi 		.isock_tad[0] = {
361*eb00b1c8SRobert Mustacchi 			.itad_flags = 0,
362*eb00b1c8SRobert Mustacchi 			.itad_nrules = 12,
363*eb00b1c8SRobert Mustacchi 			.itad_rules[0] = {
364*eb00b1c8SRobert Mustacchi 				.itr_base = 0x0,
365*eb00b1c8SRobert Mustacchi 				.itr_limit = 0x20000000,
366*eb00b1c8SRobert Mustacchi 				.itr_sock_way = 1,
367*eb00b1c8SRobert Mustacchi 				.itr_chan_way = 2,
368*eb00b1c8SRobert Mustacchi 				.itr_sock_gran = IMC_TAD_GRAN_64B,
369*eb00b1c8SRobert Mustacchi 				.itr_chan_gran = IMC_TAD_GRAN_64B,
370*eb00b1c8SRobert Mustacchi 				.itr_ntargets = 4,
371*eb00b1c8SRobert Mustacchi 				.itr_targets = { 0, 1, 0, 0 }
372*eb00b1c8SRobert Mustacchi 			},
373*eb00b1c8SRobert Mustacchi 			.itad_rules[1] = {
374*eb00b1c8SRobert Mustacchi 				.itr_base = 0x20000000,
375*eb00b1c8SRobert Mustacchi 				.itr_limit = 0x40000000,
376*eb00b1c8SRobert Mustacchi 				.itr_sock_way = 1,
377*eb00b1c8SRobert Mustacchi 				.itr_chan_way = 1,
378*eb00b1c8SRobert Mustacchi 				.itr_sock_gran = IMC_TAD_GRAN_64B,
379*eb00b1c8SRobert Mustacchi 				.itr_chan_gran = IMC_TAD_GRAN_64B,
380*eb00b1c8SRobert Mustacchi 				.itr_ntargets = 4,
381*eb00b1c8SRobert Mustacchi 				.itr_targets = { 1, 1, 0, 0 }
382*eb00b1c8SRobert Mustacchi 			},
383*eb00b1c8SRobert Mustacchi 			.itad_rules[2] = {
384*eb00b1c8SRobert Mustacchi 				.itr_base = 0x40000000,
385*eb00b1c8SRobert Mustacchi 				.itr_limit = 0x60000000,
386*eb00b1c8SRobert Mustacchi 				.itr_sock_way = 1,
387*eb00b1c8SRobert Mustacchi 				.itr_chan_way = 1,
388*eb00b1c8SRobert Mustacchi 				.itr_sock_gran = IMC_TAD_GRAN_64B,
389*eb00b1c8SRobert Mustacchi 				.itr_chan_gran = IMC_TAD_GRAN_64B,
390*eb00b1c8SRobert Mustacchi 				.itr_ntargets = 4,
391*eb00b1c8SRobert Mustacchi 				.itr_targets = { 0, 0, 0, 0 }
392*eb00b1c8SRobert Mustacchi 			},
393*eb00b1c8SRobert Mustacchi 			.itad_rules[3] = {
394*eb00b1c8SRobert Mustacchi 				.itr_base = 0x60000000,
395*eb00b1c8SRobert Mustacchi 				.itr_limit = 0x80000000,
396*eb00b1c8SRobert Mustacchi 				.itr_sock_way = 1,
397*eb00b1c8SRobert Mustacchi 				.itr_chan_way = 2,
398*eb00b1c8SRobert Mustacchi 				.itr_sock_gran = IMC_TAD_GRAN_64B,
399*eb00b1c8SRobert Mustacchi 				.itr_chan_gran = IMC_TAD_GRAN_64B,
400*eb00b1c8SRobert Mustacchi 				.itr_ntargets = 4,
401*eb00b1c8SRobert Mustacchi 				.itr_targets = { 1, 0, 0, 0 }
402*eb00b1c8SRobert Mustacchi 			}
403*eb00b1c8SRobert Mustacchi 		},
404*eb00b1c8SRobert Mustacchi 		.isock_nimc = 1,
405*eb00b1c8SRobert Mustacchi 		.isock_imcs[0] = {
406*eb00b1c8SRobert Mustacchi 			.icn_nchannels = 2,
407*eb00b1c8SRobert Mustacchi 			.icn_dimm_type = IMC_DIMM_DDR3,
408*eb00b1c8SRobert Mustacchi 			.icn_ecc = B_TRUE,
409*eb00b1c8SRobert Mustacchi 			.icn_lockstep = B_FALSE,
410*eb00b1c8SRobert Mustacchi 			.icn_closed = B_FALSE,
411*eb00b1c8SRobert Mustacchi 			.icn_channels[0] = {
412*eb00b1c8SRobert Mustacchi 				.ich_ndimms = 1,
413*eb00b1c8SRobert Mustacchi 				.ich_dimms[0] = {
414*eb00b1c8SRobert Mustacchi 					.idimm_present = B_TRUE,
415*eb00b1c8SRobert Mustacchi 					.idimm_nbanks = 3,
416*eb00b1c8SRobert Mustacchi 					.idimm_width = 8,
417*eb00b1c8SRobert Mustacchi 					.idimm_density = 2,
418*eb00b1c8SRobert Mustacchi 					.idimm_nranks = 2,
419*eb00b1c8SRobert Mustacchi 					.idimm_nrows = 14,
420*eb00b1c8SRobert Mustacchi 					.idimm_ncolumns = 10,
421*eb00b1c8SRobert Mustacchi 					.idimm_size = 0x40000000
422*eb00b1c8SRobert Mustacchi 				},
423*eb00b1c8SRobert Mustacchi 				.ich_ntad_offsets = 12,
424*eb00b1c8SRobert Mustacchi 				.ich_tad_offsets = { 0, 0, 0x30000000, 0, 0,
425*eb00b1c8SRobert Mustacchi 				    0, 0, 0, 0, 0, 0 },
426*eb00b1c8SRobert Mustacchi 				.ich_nrankileaves = 8,
427*eb00b1c8SRobert Mustacchi 				.ich_rankileaves[0] = {
428*eb00b1c8SRobert Mustacchi 					.irle_enabled = B_TRUE,
429*eb00b1c8SRobert Mustacchi 					.irle_nways = 1,
430*eb00b1c8SRobert Mustacchi 					.irle_nwaysbits = 1,
431*eb00b1c8SRobert Mustacchi 					.irle_limit = 0x40000000,
432*eb00b1c8SRobert Mustacchi 					.irle_nentries = 8,
433*eb00b1c8SRobert Mustacchi 					.irle_entries[0] = { 0x0, 0x0 },
434*eb00b1c8SRobert Mustacchi 				}
435*eb00b1c8SRobert Mustacchi 			},
436*eb00b1c8SRobert Mustacchi 			.icn_channels[1] = {
437*eb00b1c8SRobert Mustacchi 				.ich_ndimms = 1,
438*eb00b1c8SRobert Mustacchi 				.ich_dimms[0] = {
439*eb00b1c8SRobert Mustacchi 					.idimm_present = B_TRUE,
440*eb00b1c8SRobert Mustacchi 					.idimm_nbanks = 3,
441*eb00b1c8SRobert Mustacchi 					.idimm_width = 8,
442*eb00b1c8SRobert Mustacchi 					.idimm_density = 2,
443*eb00b1c8SRobert Mustacchi 					.idimm_nranks = 2,
444*eb00b1c8SRobert Mustacchi 					.idimm_nrows = 14,
445*eb00b1c8SRobert Mustacchi 					.idimm_ncolumns = 10,
446*eb00b1c8SRobert Mustacchi 					.idimm_size = 0x40000000
447*eb00b1c8SRobert Mustacchi 				},
448*eb00b1c8SRobert Mustacchi 				.ich_ntad_offsets = 12,
449*eb00b1c8SRobert Mustacchi 				.ich_tad_offsets = { 0, 0x10000000, 0, 0, 0, 0,
450*eb00b1c8SRobert Mustacchi 				    0, 0, 0, 0, 0 },
451*eb00b1c8SRobert Mustacchi 				.ich_nrankileaves = 8,
452*eb00b1c8SRobert Mustacchi 				.ich_rankileaves[0] = {
453*eb00b1c8SRobert Mustacchi 					.irle_enabled = B_TRUE,
454*eb00b1c8SRobert Mustacchi 					.irle_nways = 1,
455*eb00b1c8SRobert Mustacchi 					.irle_nwaysbits = 1,
456*eb00b1c8SRobert Mustacchi 					.irle_limit = 0x40000000,
457*eb00b1c8SRobert Mustacchi 					.irle_nentries = 8,
458*eb00b1c8SRobert Mustacchi 					.irle_entries[0] = { 0x0, 0x0 },
459*eb00b1c8SRobert Mustacchi 				}
460*eb00b1c8SRobert Mustacchi 			}
461*eb00b1c8SRobert Mustacchi 		}
462*eb00b1c8SRobert Mustacchi 	}
463*eb00b1c8SRobert Mustacchi };
464*eb00b1c8SRobert Mustacchi 
465*eb00b1c8SRobert Mustacchi /*
466*eb00b1c8SRobert Mustacchi  * The purpse of this IMC is to use a combination of both socket and channel
467*eb00b1c8SRobert Mustacchi  * interleaving. It employs a system with two sockets, each which have 2 IMCs.
468*eb00b1c8SRobert Mustacchi  * Each IMC has two channels. We have a 4-way socket interleave followed by a
469*eb00b1c8SRobert Mustacchi  * 2-way channel interleave. We use a simplified memory layout (TOLM = 4 GiB) to
470*eb00b1c8SRobert Mustacchi  * simplify other rules.
471*eb00b1c8SRobert Mustacchi  */
472*eb00b1c8SRobert Mustacchi static const imc_t imc_tad_2s_2cw_4sw = {
473*eb00b1c8SRobert Mustacchi 	.imc_gen = IMC_GEN_IVY,
474*eb00b1c8SRobert Mustacchi 	.imc_nsockets = 2,
475*eb00b1c8SRobert Mustacchi 	.imc_sockets[0] = {
476*eb00b1c8SRobert Mustacchi 		.isock_nodeid = 0,
477*eb00b1c8SRobert Mustacchi 		.isock_valid = IMC_SOCKET_V_VALID,
478*eb00b1c8SRobert Mustacchi 		.isock_sad = {
479*eb00b1c8SRobert Mustacchi 			.isad_flags = 0,
480*eb00b1c8SRobert Mustacchi 			.isad_valid = IMC_SAD_V_VALID,
481*eb00b1c8SRobert Mustacchi 			.isad_tolm = 0x100000000ULL,
482*eb00b1c8SRobert Mustacchi 			.isad_tohm = 0x200000000ULL,
483*eb00b1c8SRobert Mustacchi 			.isad_nrules = 10,
484*eb00b1c8SRobert Mustacchi 			.isad_rules[0] = {
485*eb00b1c8SRobert Mustacchi 				.isr_enable = B_TRUE,
486*eb00b1c8SRobert Mustacchi 				.isr_limit = 0x200000000ULL,
487*eb00b1c8SRobert Mustacchi 				.isr_imode = IMC_SAD_IMODE_8t6,
488*eb00b1c8SRobert Mustacchi 				.isr_ntargets = IMC_MAX_SAD_INTERLEAVE,
489*eb00b1c8SRobert Mustacchi 				.isr_targets = { 0, 4, 1, 5, 0, 4, 1, 5 }
490*eb00b1c8SRobert Mustacchi 			}
491*eb00b1c8SRobert Mustacchi 		},
492*eb00b1c8SRobert Mustacchi 		.isock_ntad = 2,
493*eb00b1c8SRobert Mustacchi 		.isock_tad[0] = {
494*eb00b1c8SRobert Mustacchi 			.itad_flags = 0,
495*eb00b1c8SRobert Mustacchi 			.itad_nrules = 12,
496*eb00b1c8SRobert Mustacchi 			.itad_rules[0] = {
497*eb00b1c8SRobert Mustacchi 				.itr_base = 0x0,
498*eb00b1c8SRobert Mustacchi 				.itr_limit = 0x200000000ULL,
499*eb00b1c8SRobert Mustacchi 				.itr_sock_way = 4,
500*eb00b1c8SRobert Mustacchi 				.itr_chan_way = 2,
501*eb00b1c8SRobert Mustacchi 				.itr_sock_gran = IMC_TAD_GRAN_64B,
502*eb00b1c8SRobert Mustacchi 				.itr_chan_gran = IMC_TAD_GRAN_64B,
503*eb00b1c8SRobert Mustacchi 				.itr_ntargets = 4,
504*eb00b1c8SRobert Mustacchi 				.itr_targets = { 0, 1, 0, 0 }
505*eb00b1c8SRobert Mustacchi 			}
506*eb00b1c8SRobert Mustacchi 		},
507*eb00b1c8SRobert Mustacchi 		.isock_tad[1] = {
508*eb00b1c8SRobert Mustacchi 			.itad_flags = 0,
509*eb00b1c8SRobert Mustacchi 			.itad_nrules = 12,
510*eb00b1c8SRobert Mustacchi 			.itad_rules[0] = {
511*eb00b1c8SRobert Mustacchi 				.itr_base = 0x0,
512*eb00b1c8SRobert Mustacchi 				.itr_limit = 0x200000000ULL,
513*eb00b1c8SRobert Mustacchi 				.itr_sock_way = 4,
514*eb00b1c8SRobert Mustacchi 				.itr_chan_way = 2,
515*eb00b1c8SRobert Mustacchi 				.itr_sock_gran = IMC_TAD_GRAN_64B,
516*eb00b1c8SRobert Mustacchi 				.itr_chan_gran = IMC_TAD_GRAN_64B,
517*eb00b1c8SRobert Mustacchi 				.itr_ntargets = 4,
518*eb00b1c8SRobert Mustacchi 				.itr_targets = { 1, 0, 0, 0 }
519*eb00b1c8SRobert Mustacchi 			}
520*eb00b1c8SRobert Mustacchi 		},
521*eb00b1c8SRobert Mustacchi 		.isock_nimc = 2,
522*eb00b1c8SRobert Mustacchi 		.isock_imcs[0] = {
523*eb00b1c8SRobert Mustacchi 			.icn_nchannels = 2,
524*eb00b1c8SRobert Mustacchi 			.icn_dimm_type = IMC_DIMM_DDR3,
525*eb00b1c8SRobert Mustacchi 			.icn_ecc = B_TRUE,
526*eb00b1c8SRobert Mustacchi 			.icn_lockstep = B_FALSE,
527*eb00b1c8SRobert Mustacchi 			.icn_closed = B_FALSE,
528*eb00b1c8SRobert Mustacchi 			.icn_channels[0] = {
529*eb00b1c8SRobert Mustacchi 				.ich_ndimms = 1,
530*eb00b1c8SRobert Mustacchi 				.ich_dimms[0] = {
531*eb00b1c8SRobert Mustacchi 					.idimm_present = B_TRUE,
532*eb00b1c8SRobert Mustacchi 					.idimm_nbanks = 3,
533*eb00b1c8SRobert Mustacchi 					.idimm_width = 8,
534*eb00b1c8SRobert Mustacchi 					.idimm_density = 2,
535*eb00b1c8SRobert Mustacchi 					.idimm_nranks = 2,
536*eb00b1c8SRobert Mustacchi 					.idimm_nrows = 14,
537*eb00b1c8SRobert Mustacchi 					.idimm_ncolumns = 10,
538*eb00b1c8SRobert Mustacchi 					.idimm_size = 0x40000000
539*eb00b1c8SRobert Mustacchi 				},
540*eb00b1c8SRobert Mustacchi 				.ich_ntad_offsets = 12,
541*eb00b1c8SRobert Mustacchi 				.ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
542*eb00b1c8SRobert Mustacchi 				    0, 0 },
543*eb00b1c8SRobert Mustacchi 				.ich_nrankileaves = 8,
544*eb00b1c8SRobert Mustacchi 				.ich_rankileaves[0] = {
545*eb00b1c8SRobert Mustacchi 					.irle_enabled = B_TRUE,
546*eb00b1c8SRobert Mustacchi 					.irle_nways = 1,
547*eb00b1c8SRobert Mustacchi 					.irle_nwaysbits = 1,
548*eb00b1c8SRobert Mustacchi 					.irle_limit = 0x40000000,
549*eb00b1c8SRobert Mustacchi 					.irle_nentries = 8,
550*eb00b1c8SRobert Mustacchi 					.irle_entries[0] = { 0x0, 0x0 },
551*eb00b1c8SRobert Mustacchi 				}
552*eb00b1c8SRobert Mustacchi 			},
553*eb00b1c8SRobert Mustacchi 			.icn_channels[1] = {
554*eb00b1c8SRobert Mustacchi 				.ich_ndimms = 1,
555*eb00b1c8SRobert Mustacchi 				.ich_dimms[0] = {
556*eb00b1c8SRobert Mustacchi 					.idimm_present = B_TRUE,
557*eb00b1c8SRobert Mustacchi 					.idimm_nbanks = 3,
558*eb00b1c8SRobert Mustacchi 					.idimm_width = 8,
559*eb00b1c8SRobert Mustacchi 					.idimm_density = 2,
560*eb00b1c8SRobert Mustacchi 					.idimm_nranks = 2,
561*eb00b1c8SRobert Mustacchi 					.idimm_nrows = 14,
562*eb00b1c8SRobert Mustacchi 					.idimm_ncolumns = 10,
563*eb00b1c8SRobert Mustacchi 					.idimm_size = 0x40000000
564*eb00b1c8SRobert Mustacchi 				},
565*eb00b1c8SRobert Mustacchi 				.ich_ntad_offsets = 12,
566*eb00b1c8SRobert Mustacchi 				.ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
567*eb00b1c8SRobert Mustacchi 				    0, 0 },
568*eb00b1c8SRobert Mustacchi 				.ich_nrankileaves = 8,
569*eb00b1c8SRobert Mustacchi 				.ich_rankileaves[0] = {
570*eb00b1c8SRobert Mustacchi 					.irle_enabled = B_TRUE,
571*eb00b1c8SRobert Mustacchi 					.irle_nways = 1,
572*eb00b1c8SRobert Mustacchi 					.irle_nwaysbits = 1,
573*eb00b1c8SRobert Mustacchi 					.irle_limit = 0x40000000,
574*eb00b1c8SRobert Mustacchi 					.irle_nentries = 8,
575*eb00b1c8SRobert Mustacchi 					.irle_entries[0] = { 0x0, 0x0 },
576*eb00b1c8SRobert Mustacchi 				}
577*eb00b1c8SRobert Mustacchi 			}
578*eb00b1c8SRobert Mustacchi 		},
579*eb00b1c8SRobert Mustacchi 		.isock_imcs[1] = {
580*eb00b1c8SRobert Mustacchi 			.icn_nchannels = 2,
581*eb00b1c8SRobert Mustacchi 			.icn_dimm_type = IMC_DIMM_DDR3,
582*eb00b1c8SRobert Mustacchi 			.icn_ecc = B_TRUE,
583*eb00b1c8SRobert Mustacchi 			.icn_lockstep = B_FALSE,
584*eb00b1c8SRobert Mustacchi 			.icn_closed = B_FALSE,
585*eb00b1c8SRobert Mustacchi 			.icn_channels[0] = {
586*eb00b1c8SRobert Mustacchi 				.ich_ndimms = 1,
587*eb00b1c8SRobert Mustacchi 				.ich_dimms[0] = {
588*eb00b1c8SRobert Mustacchi 					.idimm_present = B_TRUE,
589*eb00b1c8SRobert Mustacchi 					.idimm_nbanks = 3,
590*eb00b1c8SRobert Mustacchi 					.idimm_width = 8,
591*eb00b1c8SRobert Mustacchi 					.idimm_density = 2,
592*eb00b1c8SRobert Mustacchi 					.idimm_nranks = 2,
593*eb00b1c8SRobert Mustacchi 					.idimm_nrows = 14,
594*eb00b1c8SRobert Mustacchi 					.idimm_ncolumns = 10,
595*eb00b1c8SRobert Mustacchi 					.idimm_size = 0x40000000
596*eb00b1c8SRobert Mustacchi 				},
597*eb00b1c8SRobert Mustacchi 				.ich_ntad_offsets = 12,
598*eb00b1c8SRobert Mustacchi 				.ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
599*eb00b1c8SRobert Mustacchi 				    0, 0 },
600*eb00b1c8SRobert Mustacchi 				.ich_nrankileaves = 8,
601*eb00b1c8SRobert Mustacchi 				.ich_rankileaves[0] = {
602*eb00b1c8SRobert Mustacchi 					.irle_enabled = B_TRUE,
603*eb00b1c8SRobert Mustacchi 					.irle_nways = 1,
604*eb00b1c8SRobert Mustacchi 					.irle_nwaysbits = 1,
605*eb00b1c8SRobert Mustacchi 					.irle_limit = 0x40000000,
606*eb00b1c8SRobert Mustacchi 					.irle_nentries = 8,
607*eb00b1c8SRobert Mustacchi 					.irle_entries[0] = { 0x0, 0x0 },
608*eb00b1c8SRobert Mustacchi 				}
609*eb00b1c8SRobert Mustacchi 			},
610*eb00b1c8SRobert Mustacchi 			.icn_channels[1] = {
611*eb00b1c8SRobert Mustacchi 				.ich_ndimms = 1,
612*eb00b1c8SRobert Mustacchi 				.ich_dimms[0] = {
613*eb00b1c8SRobert Mustacchi 					.idimm_present = B_TRUE,
614*eb00b1c8SRobert Mustacchi 					.idimm_nbanks = 3,
615*eb00b1c8SRobert Mustacchi 					.idimm_width = 8,
616*eb00b1c8SRobert Mustacchi 					.idimm_density = 2,
617*eb00b1c8SRobert Mustacchi 					.idimm_nranks = 2,
618*eb00b1c8SRobert Mustacchi 					.idimm_nrows = 14,
619*eb00b1c8SRobert Mustacchi 					.idimm_ncolumns = 10,
620*eb00b1c8SRobert Mustacchi 					.idimm_size = 0x40000000
621*eb00b1c8SRobert Mustacchi 				},
622*eb00b1c8SRobert Mustacchi 				.ich_ntad_offsets = 12,
623*eb00b1c8SRobert Mustacchi 				.ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
624*eb00b1c8SRobert Mustacchi 				    0, 0 },
625*eb00b1c8SRobert Mustacchi 				.ich_nrankileaves = 8,
626*eb00b1c8SRobert Mustacchi 				.ich_rankileaves[0] = {
627*eb00b1c8SRobert Mustacchi 					.irle_enabled = B_TRUE,
628*eb00b1c8SRobert Mustacchi 					.irle_nways = 1,
629*eb00b1c8SRobert Mustacchi 					.irle_nwaysbits = 1,
630*eb00b1c8SRobert Mustacchi 					.irle_limit = 0x40000000,
631*eb00b1c8SRobert Mustacchi 					.irle_nentries = 8,
632*eb00b1c8SRobert Mustacchi 					.irle_entries[0] = { 0x0, 0x0 },
633*eb00b1c8SRobert Mustacchi 				}
634*eb00b1c8SRobert Mustacchi 			}
635*eb00b1c8SRobert Mustacchi 		}
636*eb00b1c8SRobert Mustacchi 	},
637*eb00b1c8SRobert Mustacchi 	.imc_sockets[1] = {
638*eb00b1c8SRobert Mustacchi 		.isock_nodeid = 1,
639*eb00b1c8SRobert Mustacchi 		.isock_valid = IMC_SOCKET_V_VALID,
640*eb00b1c8SRobert Mustacchi 		.isock_sad = {
641*eb00b1c8SRobert Mustacchi 			.isad_flags = 0,
642*eb00b1c8SRobert Mustacchi 			.isad_valid = IMC_SAD_V_VALID,
643*eb00b1c8SRobert Mustacchi 			.isad_tolm = 0x80000000,
644*eb00b1c8SRobert Mustacchi 			.isad_tohm = 0,
645*eb00b1c8SRobert Mustacchi 			.isad_nrules = 10,
646*eb00b1c8SRobert Mustacchi 			.isad_rules[0] = {
647*eb00b1c8SRobert Mustacchi 				.isr_enable = B_TRUE,
648*eb00b1c8SRobert Mustacchi 				.isr_limit = 0x80000000,
649*eb00b1c8SRobert Mustacchi 				.isr_imode = IMC_SAD_IMODE_8t6,
650*eb00b1c8SRobert Mustacchi 				.isr_ntargets = IMC_MAX_SAD_INTERLEAVE,
651*eb00b1c8SRobert Mustacchi 				.isr_targets = { 0, 4, 1, 5, 0, 4, 1, 5 }
652*eb00b1c8SRobert Mustacchi 			}
653*eb00b1c8SRobert Mustacchi 		},
654*eb00b1c8SRobert Mustacchi 		.isock_ntad = 2,
655*eb00b1c8SRobert Mustacchi 		.isock_tad[0] = {
656*eb00b1c8SRobert Mustacchi 			.itad_flags = 0,
657*eb00b1c8SRobert Mustacchi 			.itad_nrules = 12,
658*eb00b1c8SRobert Mustacchi 			.itad_rules[0] = {
659*eb00b1c8SRobert Mustacchi 				.itr_base = 0x0,
660*eb00b1c8SRobert Mustacchi 				.itr_limit = 0x200000000ULL,
661*eb00b1c8SRobert Mustacchi 				.itr_sock_way = 4,
662*eb00b1c8SRobert Mustacchi 				.itr_chan_way = 2,
663*eb00b1c8SRobert Mustacchi 				.itr_sock_gran = IMC_TAD_GRAN_64B,
664*eb00b1c8SRobert Mustacchi 				.itr_chan_gran = IMC_TAD_GRAN_64B,
665*eb00b1c8SRobert Mustacchi 				.itr_ntargets = 4,
666*eb00b1c8SRobert Mustacchi 				.itr_targets = { 1, 0, 0, 0 }
667*eb00b1c8SRobert Mustacchi 			}
668*eb00b1c8SRobert Mustacchi 		},
669*eb00b1c8SRobert Mustacchi 		.isock_tad[1] = {
670*eb00b1c8SRobert Mustacchi 			.itad_flags = 0,
671*eb00b1c8SRobert Mustacchi 			.itad_nrules = 12,
672*eb00b1c8SRobert Mustacchi 			.itad_rules[0] = {
673*eb00b1c8SRobert Mustacchi 				.itr_base = 0x0,
674*eb00b1c8SRobert Mustacchi 				.itr_limit = 0x200000000ULL,
675*eb00b1c8SRobert Mustacchi 				.itr_sock_way = 4,
676*eb00b1c8SRobert Mustacchi 				.itr_chan_way = 2,
677*eb00b1c8SRobert Mustacchi 				.itr_sock_gran = IMC_TAD_GRAN_64B,
678*eb00b1c8SRobert Mustacchi 				.itr_chan_gran = IMC_TAD_GRAN_64B,
679*eb00b1c8SRobert Mustacchi 				.itr_ntargets = 4,
680*eb00b1c8SRobert Mustacchi 				.itr_targets = { 0, 1, 0, 0 }
681*eb00b1c8SRobert Mustacchi 			}
682*eb00b1c8SRobert Mustacchi 		},
683*eb00b1c8SRobert Mustacchi 		.isock_nimc = 2,
684*eb00b1c8SRobert Mustacchi 		.isock_imcs[0] = {
685*eb00b1c8SRobert Mustacchi 			.icn_nchannels = 2,
686*eb00b1c8SRobert Mustacchi 			.icn_dimm_type = IMC_DIMM_DDR3,
687*eb00b1c8SRobert Mustacchi 			.icn_ecc = B_TRUE,
688*eb00b1c8SRobert Mustacchi 			.icn_lockstep = B_FALSE,
689*eb00b1c8SRobert Mustacchi 			.icn_closed = B_FALSE,
690*eb00b1c8SRobert Mustacchi 			.icn_channels[0] = {
691*eb00b1c8SRobert Mustacchi 				.ich_ndimms = 1,
692*eb00b1c8SRobert Mustacchi 				.ich_dimms[0] = {
693*eb00b1c8SRobert Mustacchi 					.idimm_present = B_TRUE,
694*eb00b1c8SRobert Mustacchi 					.idimm_nbanks = 3,
695*eb00b1c8SRobert Mustacchi 					.idimm_width = 8,
696*eb00b1c8SRobert Mustacchi 					.idimm_density = 2,
697*eb00b1c8SRobert Mustacchi 					.idimm_nranks = 2,
698*eb00b1c8SRobert Mustacchi 					.idimm_nrows = 14,
699*eb00b1c8SRobert Mustacchi 					.idimm_ncolumns = 10,
700*eb00b1c8SRobert Mustacchi 					.idimm_size = 0x40000000
701*eb00b1c8SRobert Mustacchi 				},
702*eb00b1c8SRobert Mustacchi 				.ich_ntad_offsets = 12,
703*eb00b1c8SRobert Mustacchi 				.ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
704*eb00b1c8SRobert Mustacchi 				    0, 0 },
705*eb00b1c8SRobert Mustacchi 				.ich_nrankileaves = 8,
706*eb00b1c8SRobert Mustacchi 				.ich_rankileaves[0] = {
707*eb00b1c8SRobert Mustacchi 					.irle_enabled = B_TRUE,
708*eb00b1c8SRobert Mustacchi 					.irle_nways = 1,
709*eb00b1c8SRobert Mustacchi 					.irle_nwaysbits = 1,
710*eb00b1c8SRobert Mustacchi 					.irle_limit = 0x40000000,
711*eb00b1c8SRobert Mustacchi 					.irle_nentries = 8,
712*eb00b1c8SRobert Mustacchi 					.irle_entries[0] = { 0x0, 0x0 },
713*eb00b1c8SRobert Mustacchi 				}
714*eb00b1c8SRobert Mustacchi 			},
715*eb00b1c8SRobert Mustacchi 			.icn_channels[1] = {
716*eb00b1c8SRobert Mustacchi 				.ich_ndimms = 1,
717*eb00b1c8SRobert Mustacchi 				.ich_dimms[0] = {
718*eb00b1c8SRobert Mustacchi 					.idimm_present = B_TRUE,
719*eb00b1c8SRobert Mustacchi 					.idimm_nbanks = 3,
720*eb00b1c8SRobert Mustacchi 					.idimm_width = 8,
721*eb00b1c8SRobert Mustacchi 					.idimm_density = 2,
722*eb00b1c8SRobert Mustacchi 					.idimm_nranks = 2,
723*eb00b1c8SRobert Mustacchi 					.idimm_nrows = 14,
724*eb00b1c8SRobert Mustacchi 					.idimm_ncolumns = 10,
725*eb00b1c8SRobert Mustacchi 					.idimm_size = 0x40000000
726*eb00b1c8SRobert Mustacchi 				},
727*eb00b1c8SRobert Mustacchi 				.ich_ntad_offsets = 12,
728*eb00b1c8SRobert Mustacchi 				.ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
729*eb00b1c8SRobert Mustacchi 				    0, 0 },
730*eb00b1c8SRobert Mustacchi 				.ich_nrankileaves = 8,
731*eb00b1c8SRobert Mustacchi 				.ich_rankileaves[0] = {
732*eb00b1c8SRobert Mustacchi 					.irle_enabled = B_TRUE,
733*eb00b1c8SRobert Mustacchi 					.irle_nways = 1,
734*eb00b1c8SRobert Mustacchi 					.irle_nwaysbits = 1,
735*eb00b1c8SRobert Mustacchi 					.irle_limit = 0x40000000,
736*eb00b1c8