1*eb00b1c8SRobert Mustacchi /*
2*eb00b1c8SRobert Mustacchi  * This file and its contents are supplied under the terms of the
3*eb00b1c8SRobert Mustacchi  * Common Development and Distribution License ("CDDL"), version 1.0.
4*eb00b1c8SRobert Mustacchi  * You may only use this file in accordance with the terms of version
5*eb00b1c8SRobert Mustacchi  * 1.0 of the CDDL.
6*eb00b1c8SRobert Mustacchi  *
7*eb00b1c8SRobert Mustacchi  * A full copy of the text of the CDDL should have accompanied this
8*eb00b1c8SRobert Mustacchi  * source.  A copy of the CDDL is also available via the Internet at
9*eb00b1c8SRobert Mustacchi  * http://www.illumos.org/license/CDDL.
10*eb00b1c8SRobert Mustacchi  */
11*eb00b1c8SRobert Mustacchi 
12*eb00b1c8SRobert Mustacchi /*
13*eb00b1c8SRobert Mustacchi  * Copyright 2019 Joyent, Inc.
14*eb00b1c8SRobert Mustacchi  */
15*eb00b1c8SRobert Mustacchi 
16*eb00b1c8SRobert Mustacchi #include "imc_test.h"
17*eb00b1c8SRobert Mustacchi 
18*eb00b1c8SRobert Mustacchi /*
19*eb00b1c8SRobert Mustacchi  * This tests various aspects of the source address decoder. We need to test
20*eb00b1c8SRobert Mustacchi  * several of the following:
21*eb00b1c8SRobert Mustacchi  *
22*eb00b1c8SRobert Mustacchi  * o SAD rules with different interleave options
23*eb00b1c8SRobert Mustacchi  *    - XOR (SNB->BRD)
24*eb00b1c8SRobert Mustacchi  *    - 10t8, 14t12, 32t30 (SKX)
25*eb00b1c8SRobert Mustacchi  * o SAD rules with a7mode (IVB->BRD)
26*eb00b1c8SRobert Mustacchi  *    - And XOR
27*eb00b1c8SRobert Mustacchi  * o Different SAD rules for different regions
28*eb00b1c8SRobert Mustacchi  */
29*eb00b1c8SRobert Mustacchi 
30*eb00b1c8SRobert Mustacchi /*
31*eb00b1c8SRobert Mustacchi  * This tests basics SAD interleaving with a 2 socket system that has a single
32*eb00b1c8SRobert Mustacchi  * channel and DIMM. The other aspects are simplified to try and make life
33*eb00b1c8SRobert Mustacchi  * easier.
34*eb00b1c8SRobert Mustacchi  */
35*eb00b1c8SRobert Mustacchi 
36*eb00b1c8SRobert Mustacchi static const imc_t imc_sad_2s_basic = {
37*eb00b1c8SRobert Mustacchi 	.imc_gen = IMC_GEN_SANDY,
38*eb00b1c8SRobert Mustacchi 	.imc_nsockets = 2,
39*eb00b1c8SRobert Mustacchi 	.imc_sockets[0] = {
40*eb00b1c8SRobert Mustacchi 		.isock_nodeid = 0,
41*eb00b1c8SRobert Mustacchi 		.isock_valid = IMC_SOCKET_V_VALID,
42*eb00b1c8SRobert Mustacchi 		.isock_sad = {
43*eb00b1c8SRobert Mustacchi 			.isad_flags = 0,
44*eb00b1c8SRobert Mustacchi 			.isad_valid = IMC_SAD_V_VALID,
45*eb00b1c8SRobert Mustacchi 			.isad_tolm = 0x80000000,
46*eb00b1c8SRobert Mustacchi 			.isad_tohm = 0,
47*eb00b1c8SRobert Mustacchi 			.isad_nrules = 10,
48*eb00b1c8SRobert Mustacchi 			.isad_rules[0] = {
49*eb00b1c8SRobert Mustacchi 				.isr_enable = B_TRUE,
50*eb00b1c8SRobert Mustacchi 				.isr_limit = 0x80000000,
51*eb00b1c8SRobert Mustacchi 				.isr_imode = IMC_SAD_IMODE_8t6,
52*eb00b1c8SRobert Mustacchi 				.isr_ntargets = IMC_MAX_SAD_INTERLEAVE,
53*eb00b1c8SRobert Mustacchi 				.isr_targets = { 0, 1, 0, 1, 0, 1, 0, 1 }
54*eb00b1c8SRobert Mustacchi 			}
55*eb00b1c8SRobert Mustacchi 		},
56*eb00b1c8SRobert Mustacchi 		.isock_ntad = 1,
57*eb00b1c8SRobert Mustacchi 		.isock_tad[0] = {
58*eb00b1c8SRobert Mustacchi 			.itad_flags = 0,
59*eb00b1c8SRobert Mustacchi 			.itad_nrules = 12,
60*eb00b1c8SRobert Mustacchi 			.itad_rules[0] = {
61*eb00b1c8SRobert Mustacchi 				.itr_base = 0x0,
62*eb00b1c8SRobert Mustacchi 				.itr_limit = 0x80000000,
63*eb00b1c8SRobert Mustacchi 				.itr_sock_way = 2,
64*eb00b1c8SRobert Mustacchi 				.itr_chan_way = 1,
65*eb00b1c8SRobert Mustacchi 				.itr_sock_gran = IMC_TAD_GRAN_64B,
66*eb00b1c8SRobert Mustacchi 				.itr_chan_gran = IMC_TAD_GRAN_64B,
67*eb00b1c8SRobert Mustacchi 				.itr_ntargets = 4,
68*eb00b1c8SRobert Mustacchi 				.itr_targets = { 0, 0, 0, 0 }
69*eb00b1c8SRobert Mustacchi 			}
70*eb00b1c8SRobert Mustacchi 		},
71*eb00b1c8SRobert Mustacchi 		.isock_nimc = 1,
72*eb00b1c8SRobert Mustacchi 		.isock_imcs[0] = {
73*eb00b1c8SRobert Mustacchi 			.icn_nchannels = 1,
74*eb00b1c8SRobert Mustacchi 			.icn_dimm_type = IMC_DIMM_DDR3,
75*eb00b1c8SRobert Mustacchi 			.icn_ecc = B_TRUE,
76*eb00b1c8SRobert Mustacchi 			.icn_lockstep = B_FALSE,
77*eb00b1c8SRobert Mustacchi 			.icn_closed = B_FALSE,
78*eb00b1c8SRobert Mustacchi 			.icn_channels[0] = {
79*eb00b1c8SRobert Mustacchi 				.ich_ndimms = 1,
80*eb00b1c8SRobert Mustacchi 				.ich_dimms[0] = {
81*eb00b1c8SRobert Mustacchi 					.idimm_present = B_TRUE,
82*eb00b1c8SRobert Mustacchi 					.idimm_nbanks = 3,
83*eb00b1c8SRobert Mustacchi 					.idimm_width = 8,
84*eb00b1c8SRobert Mustacchi 					.idimm_density = 2,
85*eb00b1c8SRobert Mustacchi 					.idimm_nranks = 2,
86*eb00b1c8SRobert Mustacchi 					.idimm_nrows = 14,
87*eb00b1c8SRobert Mustacchi 					.idimm_ncolumns = 10,
88*eb00b1c8SRobert Mustacchi 					.idimm_size = 0x40000000
89*eb00b1c8SRobert Mustacchi 				},
90*eb00b1c8SRobert Mustacchi 				.ich_ntad_offsets = 12,
91*eb00b1c8SRobert Mustacchi 				.ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
92*eb00b1c8SRobert Mustacchi 				    0, 0 },
93*eb00b1c8SRobert Mustacchi 				.ich_nrankileaves = 8,
94*eb00b1c8SRobert Mustacchi 				.ich_rankileaves[0] = {
95*eb00b1c8SRobert Mustacchi 					.irle_enabled = B_TRUE,
96*eb00b1c8SRobert Mustacchi 					.irle_nways = 1,
97*eb00b1c8SRobert Mustacchi 					.irle_nwaysbits = 1,
98*eb00b1c8SRobert Mustacchi 					.irle_limit = 0x40000000,
99*eb00b1c8SRobert Mustacchi 					.irle_nentries = 8,
100*eb00b1c8SRobert Mustacchi 					.irle_entries[0] = { 0x0, 0x0 },
101*eb00b1c8SRobert Mustacchi 				}
102*eb00b1c8SRobert Mustacchi 			}
103*eb00b1c8SRobert Mustacchi 		}
104*eb00b1c8SRobert Mustacchi 	},
105*eb00b1c8SRobert Mustacchi 	.imc_sockets[1] = {
106*eb00b1c8SRobert Mustacchi 		.isock_nodeid = 1,
107*eb00b1c8SRobert Mustacchi 		.isock_valid = IMC_SOCKET_V_VALID,
108*eb00b1c8SRobert Mustacchi 		.isock_sad = {
109*eb00b1c8SRobert Mustacchi 			.isad_flags = 0,
110*eb00b1c8SRobert Mustacchi 			.isad_valid = IMC_SAD_V_VALID,
111*eb00b1c8SRobert Mustacchi 			.isad_tolm = 0x80000000,
112*eb00b1c8SRobert Mustacchi 			.isad_tohm = 0,
113*eb00b1c8SRobert Mustacchi 			.isad_nrules = 10,
114*eb00b1c8SRobert Mustacchi 			.isad_rules[0] = {
115*eb00b1c8SRobert Mustacchi 				.isr_enable = B_TRUE,
116*eb00b1c8SRobert Mustacchi 				.isr_limit = 0x80000000,
117*eb00b1c8SRobert Mustacchi 				.isr_imode = IMC_SAD_IMODE_8t6,
118*eb00b1c8SRobert Mustacchi 				.isr_ntargets = IMC_MAX_SAD_INTERLEAVE,
119*eb00b1c8SRobert Mustacchi 				.isr_targets = { 0, 1, 0, 1, 0, 1, 0, 1 }
120*eb00b1c8SRobert Mustacchi 			}
121*eb00b1c8SRobert Mustacchi 		},
122*eb00b1c8SRobert Mustacchi 		.isock_ntad = 1,
123*eb00b1c8SRobert Mustacchi 		.isock_tad[0] = {
124*eb00b1c8SRobert Mustacchi 			.itad_flags = 0,
125*eb00b1c8SRobert Mustacchi 			.itad_nrules = 12,
126*eb00b1c8SRobert Mustacchi 			.itad_rules[0] = {
127*eb00b1c8SRobert Mustacchi 				.itr_base = 0x0,
128*eb00b1c8SRobert Mustacchi 				.itr_limit = 0x80000000,
129*eb00b1c8SRobert Mustacchi 				.itr_sock_way = 2,
130*eb00b1c8SRobert Mustacchi 				.itr_chan_way = 1,
131*eb00b1c8SRobert Mustacchi 				.itr_sock_gran = IMC_TAD_GRAN_64B,
132*eb00b1c8SRobert Mustacchi 				.itr_chan_gran = IMC_TAD_GRAN_64B,
133*eb00b1c8SRobert Mustacchi 				.itr_ntargets = 4,
134*eb00b1c8SRobert Mustacchi 				.itr_targets = { 0, 0, 0, 0 }
135*eb00b1c8SRobert Mustacchi 			}
136*eb00b1c8SRobert Mustacchi 		},
137*eb00b1c8SRobert Mustacchi 		.isock_nimc = 1,
138*eb00b1c8SRobert Mustacchi 		.isock_imcs[0] = {
139*eb00b1c8SRobert Mustacchi 			.icn_nchannels = 1,
140*eb00b1c8SRobert Mustacchi 			.icn_dimm_type = IMC_DIMM_DDR3,
141*eb00b1c8SRobert Mustacchi 			.icn_ecc = B_TRUE,
142*eb00b1c8SRobert Mustacchi 			.icn_lockstep = B_FALSE,
143*eb00b1c8SRobert Mustacchi 			.icn_closed = B_FALSE,
144*eb00b1c8SRobert Mustacchi 			.icn_channels[0] = {
145*eb00b1c8SRobert Mustacchi 				.ich_ndimms = 1,
146*eb00b1c8SRobert Mustacchi 				.ich_dimms[0] = {
147*eb00b1c8SRobert Mustacchi 					.idimm_present = B_TRUE,
148*eb00b1c8SRobert Mustacchi 					.idimm_nbanks = 3,
149*eb00b1c8SRobert Mustacchi 					.idimm_width = 8,
150*eb00b1c8SRobert Mustacchi 					.idimm_density = 2,
151*eb00b1c8SRobert Mustacchi 					.idimm_nranks = 2,
152*eb00b1c8SRobert Mustacchi 					.idimm_nrows = 14,
153*eb00b1c8SRobert Mustacchi 					.idimm_ncolumns = 10,
154*eb00b1c8SRobert Mustacchi 					.idimm_size = 0x40000000
155*eb00b1c8SRobert Mustacchi 				},
156*eb00b1c8SRobert Mustacchi 				.ich_ntad_offsets = 12,
157*eb00b1c8SRobert Mustacchi 				.ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
158*eb00b1c8SRobert Mustacchi 				    0, 0 },
159*eb00b1c8SRobert Mustacchi 				.ich_nrankileaves = 8,
160*eb00b1c8SRobert Mustacchi 				.ich_rankileaves[0] = {
161*eb00b1c8SRobert Mustacchi 					.irle_enabled = B_TRUE,
162*eb00b1c8SRobert Mustacchi 					.irle_nways = 1,
163*eb00b1c8SRobert Mustacchi 					.irle_nwaysbits = 1,
164*eb00b1c8SRobert Mustacchi 					.irle_limit = 0x40000000,
165*eb00b1c8SRobert Mustacchi 					.irle_nentries = 8,
166*eb00b1c8SRobert Mustacchi 					.irle_entries[0] = { 0x0, 0x0 },
167*eb00b1c8SRobert Mustacchi 				}
168*eb00b1c8SRobert Mustacchi 			}
169*eb00b1c8SRobert Mustacchi 		}
170*eb00b1c8SRobert Mustacchi 	}
171*eb00b1c8SRobert Mustacchi };
172*eb00b1c8SRobert Mustacchi 
173*eb00b1c8SRobert Mustacchi /*
174*eb00b1c8SRobert Mustacchi  * This is a 4 socket variants of the previous one. Each DIMM now has a much
175*eb00b1c8SRobert Mustacchi  * smaller amount of memory in it.
176*eb00b1c8SRobert Mustacchi  */
177*eb00b1c8SRobert Mustacchi static const imc_t imc_sad_4s_basic = {
178*eb00b1c8SRobert Mustacchi 	.imc_gen = IMC_GEN_SANDY,
179*eb00b1c8SRobert Mustacchi 	.imc_nsockets = 4,
180*eb00b1c8SRobert Mustacchi 	.imc_sockets[0] = {
181*eb00b1c8SRobert Mustacchi 		.isock_nodeid = 0,
182*eb00b1c8SRobert Mustacchi 		.isock_valid = IMC_SOCKET_V_VALID,
183*eb00b1c8SRobert Mustacchi 		.isock_sad = {
184*eb00b1c8SRobert Mustacchi 			.isad_flags = 0,
185*eb00b1c8SRobert Mustacchi 			.isad_valid = IMC_SAD_V_VALID,
186*eb00b1c8SRobert Mustacchi 			.isad_tolm = 0x80000000,
187*eb00b1c8SRobert Mustacchi 			.isad_tohm = 0,
188*eb00b1c8SRobert Mustacchi 			.isad_nrules = 10,
189*eb00b1c8SRobert Mustacchi 			.isad_rules[0] = {
190*eb00b1c8SRobert Mustacchi 				.isr_enable = B_TRUE,
191*eb00b1c8SRobert Mustacchi 				.isr_limit = 0x80000000,
192*eb00b1c8SRobert Mustacchi 				.isr_imode = IMC_SAD_IMODE_8t6,
193*eb00b1c8SRobert Mustacchi 				.isr_ntargets = IMC_MAX_SAD_INTERLEAVE,
194*eb00b1c8SRobert Mustacchi 				.isr_targets = { 0, 1, 2, 3, 0, 1, 2, 3 }
195*eb00b1c8SRobert Mustacchi 			}
196*eb00b1c8SRobert Mustacchi 		},
197*eb00b1c8SRobert Mustacchi 		.isock_ntad = 1,
198*eb00b1c8SRobert Mustacchi 		.isock_tad[0] = {
199*eb00b1c8SRobert Mustacchi 			.itad_flags = 0,
200*eb00b1c8SRobert Mustacchi 			.itad_nrules = 12,
201*eb00b1c8SRobert Mustacchi 			.itad_rules[0] = {
202*eb00b1c8SRobert Mustacchi 				.itr_base = 0x0,
203*eb00b1c8SRobert Mustacchi 				.itr_limit = 0x80000000,
204*eb00b1c8SRobert Mustacchi 				.itr_sock_way = 4,
205*eb00b1c8SRobert Mustacchi 				.itr_chan_way = 1,
206*eb00b1c8SRobert Mustacchi 				.itr_sock_gran = IMC_TAD_GRAN_64B,
207*eb00b1c8SRobert Mustacchi 				.itr_chan_gran = IMC_TAD_GRAN_64B,
208*eb00b1c8SRobert Mustacchi 				.itr_ntargets = 4,
209*eb00b1c8SRobert Mustacchi 				.itr_targets = { 0, 0, 0, 0 }
210*eb00b1c8SRobert Mustacchi 			}
211*eb00b1c8SRobert Mustacchi 		},
212*eb00b1c8SRobert Mustacchi 		.isock_nimc = 1,
213*eb00b1c8SRobert Mustacchi 		.isock_imcs[0] = {
214*eb00b1c8SRobert Mustacchi 			.icn_nchannels = 1,
215*eb00b1c8SRobert Mustacchi 			.icn_dimm_type = IMC_DIMM_DDR3,
216*eb00b1c8SRobert Mustacchi 			.icn_ecc = B_TRUE,
217*eb00b1c8SRobert Mustacchi 			.icn_lockstep = B_FALSE,
218*eb00b1c8SRobert Mustacchi 			.icn_closed = B_FALSE,
219*eb00b1c8SRobert Mustacchi 			.icn_channels[0] = {
220*eb00b1c8SRobert Mustacchi 				.ich_ndimms = 1,
221*eb00b1c8SRobert Mustacchi 				.ich_dimms[0] = {
222*eb00b1c8SRobert Mustacchi 					.idimm_present = B_TRUE,
223*eb00b1c8SRobert Mustacchi 					.idimm_nbanks = 3,
224*eb00b1c8SRobert Mustacchi 					.idimm_width = 8,
225*eb00b1c8SRobert Mustacchi 					.idimm_density = 2,
226*eb00b1c8SRobert Mustacchi 					.idimm_nranks = 2,
227*eb00b1c8SRobert Mustacchi 					.idimm_nrows = 14,
228*eb00b1c8SRobert Mustacchi 					.idimm_ncolumns = 10,
229*eb00b1c8SRobert Mustacchi 					.idimm_size = 0x20000000
230*eb00b1c8SRobert Mustacchi 				},
231*eb00b1c8SRobert Mustacchi 				.ich_ntad_offsets = 12,
232*eb00b1c8SRobert Mustacchi 				.ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
233*eb00b1c8SRobert Mustacchi 				    0, 0 },
234*eb00b1c8SRobert Mustacchi 				.ich_nrankileaves = 8,
235*eb00b1c8SRobert Mustacchi 				.ich_rankileaves[0] = {
236*eb00b1c8SRobert Mustacchi 					.irle_enabled = B_TRUE,
237*eb00b1c8SRobert Mustacchi 					.irle_nways = 1,
238*eb00b1c8SRobert Mustacchi 					.irle_nwaysbits = 1,
239*eb00b1c8SRobert Mustacchi 					.irle_limit = 0x20000000,
240*eb00b1c8SRobert Mustacchi 					.irle_nentries = 8,
241*eb00b1c8SRobert Mustacchi 					.irle_entries[0] = { 0x0, 0x0 },
242*eb00b1c8SRobert Mustacchi 				}
243*eb00b1c8SRobert Mustacchi 			}
244*eb00b1c8SRobert Mustacchi 		}
245*eb00b1c8SRobert Mustacchi 	},
246*eb00b1c8SRobert Mustacchi 	.imc_sockets[1] = {
247*eb00b1c8SRobert Mustacchi 		.isock_nodeid = 1,
248*eb00b1c8SRobert Mustacchi 		.isock_valid = IMC_SOCKET_V_VALID,
249*eb00b1c8SRobert Mustacchi 		.isock_sad = {
250*eb00b1c8SRobert Mustacchi 			.isad_flags = 0,
251*eb00b1c8SRobert Mustacchi 			.isad_valid = IMC_SAD_V_VALID,
252*eb00b1c8SRobert Mustacchi 			.isad_tolm = 0x80000000,
253*eb00b1c8SRobert Mustacchi 			.isad_tohm = 0,
254*eb00b1c8SRobert Mustacchi 			.isad_nrules = 10,
255*eb00b1c8SRobert Mustacchi 			.isad_rules[0] = {
256*eb00b1c8SRobert Mustacchi 				.isr_enable = B_TRUE,
257*eb00b1c8SRobert Mustacchi 				.isr_limit = 0x80000000,
258*eb00b1c8SRobert Mustacchi 				.isr_imode = IMC_SAD_IMODE_8t6,
259*eb00b1c8SRobert Mustacchi 				.isr_ntargets = IMC_MAX_SAD_INTERLEAVE,
260*eb00b1c8SRobert Mustacchi 				.isr_targets = { 0, 1, 2, 3, 0, 1, 2, 3 }
261*eb00b1c8SRobert Mustacchi 			}
262*eb00b1c8SRobert Mustacchi 		},
263*eb00b1c8SRobert Mustacchi 		.isock_ntad = 1,
264*eb00b1c8SRobert Mustacchi 		.isock_tad[0] = {
265*eb00b1c8SRobert Mustacchi 			.itad_flags = 0,
266*eb00b1c8SRobert Mustacchi 			.itad_nrules = 12,
267*eb00b1c8SRobert Mustacchi 			.itad_rules[0] = {
268*eb00b1c8SRobert Mustacchi 				.itr_base = 0x0,
269*eb00b1c8SRobert Mustacchi 				.itr_limit = 0x80000000,
270*eb00b1c8SRobert Mustacchi 				.itr_sock_way = 4,
271*eb00b1c8SRobert Mustacchi 				.itr_chan_way = 1,
272*eb00b1c8SRobert Mustacchi 				.itr_sock_gran = IMC_TAD_GRAN_64B,
273*eb00b1c8SRobert Mustacchi 				.itr_chan_gran = IMC_TAD_GRAN_64B,
274*eb00b1c8SRobert Mustacchi 				.itr_ntargets = 4,
275*eb00b1c8SRobert Mustacchi 				.itr_targets = { 0, 0, 0, 0 }
276*eb00b1c8SRobert Mustacchi 			}
277*eb00b1c8SRobert Mustacchi 		},
278*eb00b1c8SRobert Mustacchi 		.isock_nimc = 1,
279*eb00b1c8SRobert Mustacchi 		.isock_imcs[0] = {
280*eb00b1c8SRobert Mustacchi 			.icn_nchannels = 1,
281*eb00b1c8SRobert Mustacchi 			.icn_dimm_type = IMC_DIMM_DDR3,
282*eb00b1c8SRobert Mustacchi 			.icn_ecc = B_TRUE,
283*eb00b1c8SRobert Mustacchi 			.icn_lockstep = B_FALSE,
284*eb00b1c8SRobert Mustacchi 			.icn_closed = B_FALSE,
285*eb00b1c8SRobert Mustacchi 			.icn_channels[0] = {
286*eb00b1c8SRobert Mustacchi 				.ich_ndimms = 1,
287*eb00b1c8SRobert Mustacchi 				.ich_dimms[0] = {
288*eb00b1c8SRobert Mustacchi 					.idimm_present = B_TRUE,
289*eb00b1c8SRobert Mustacchi 					.idimm_nbanks = 3,
290*eb00b1c8SRobert Mustacchi 					.idimm_width = 8,
291*eb00b1c8SRobert Mustacchi 					.idimm_density = 2,
292*eb00b1c8SRobert Mustacchi 					.idimm_nranks = 2,
293*eb00b1c8SRobert Mustacchi 					.idimm_nrows = 14,
294*eb00b1c8SRobert Mustacchi 					.idimm_ncolumns = 10,
295*eb00b1c8SRobert Mustacchi 					.idimm_size = 0x20000000
296*eb00b1c8SRobert Mustacchi 				},
297*eb00b1c8SRobert Mustacchi 				.ich_ntad_offsets = 12,
298*eb00b1c8SRobert Mustacchi 				.ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
299*eb00b1c8SRobert Mustacchi 				    0, 0 },
300*eb00b1c8SRobert Mustacchi 				.ich_nrankileaves = 8,
301*eb00b1c8SRobert Mustacchi 				.ich_rankileaves[0] = {
302*eb00b1c8SRobert Mustacchi 					.irle_enabled = B_TRUE,
303*eb00b1c8SRobert Mustacchi 					.irle_nways = 1,
304*eb00b1c8SRobert Mustacchi 					.irle_nwaysbits = 1,
305*eb00b1c8SRobert Mustacchi 					.irle_limit = 0x20000000,
306*eb00b1c8SRobert Mustacchi 					.irle_nentries = 8,
307*eb00b1c8SRobert Mustacchi 					.irle_entries[0] = { 0x0, 0x0 },
308*eb00b1c8SRobert Mustacchi 				}
309*eb00b1c8SRobert Mustacchi 			}
310*eb00b1c8SRobert Mustacchi 		}
311*eb00b1c8SRobert Mustacchi 	},
312*eb00b1c8SRobert Mustacchi 	.imc_sockets[2] = {
313*eb00b1c8SRobert Mustacchi 		.isock_nodeid = 2,
314*eb00b1c8SRobert Mustacchi 		.isock_valid = IMC_SOCKET_V_VALID,
315*eb00b1c8SRobert Mustacchi 		.isock_sad = {
316*eb00b1c8SRobert Mustacchi 			.isad_flags = 0,
317*eb00b1c8SRobert Mustacchi 			.isad_valid = IMC_SAD_V_VALID,
318*eb00b1c8SRobert Mustacchi 			.isad_tolm = 0x80000000,
319*eb00b1c8SRobert Mustacchi 			.isad_tohm = 0,
320*eb00b1c8SRobert Mustacchi 			.isad_nrules = 10,
321*eb00b1c8SRobert Mustacchi 			.isad_rules[0] = {
322*eb00b1c8SRobert Mustacchi 				.isr_enable = B_TRUE,
323*eb00b1c8SRobert Mustacchi 				.isr_limit = 0x80000000,
324*eb00b1c8SRobert Mustacchi 				.isr_imode = IMC_SAD_IMODE_8t6,
325*eb00b1c8SRobert Mustacchi 				.isr_ntargets = IMC_MAX_SAD_INTERLEAVE,
326*eb00b1c8SRobert Mustacchi 				.isr_targets = { 0, 1, 2, 3, 0, 1, 2, 3 }
327*eb00b1c8SRobert Mustacchi 			}
328*eb00b1c8SRobert Mustacchi 		},
329*eb00b1c8SRobert Mustacchi 		.isock_ntad = 1,
330*eb00b1c8SRobert Mustacchi 		.isock_tad[0] = {
331*eb00b1c8SRobert Mustacchi 			.itad_flags = 0,
332*eb00b1c8SRobert Mustacchi 			.itad_nrules = 12,
333*eb00b1c8SRobert Mustacchi 			.itad_rules[0] = {
334*eb00b1c8SRobert Mustacchi 				.itr_base = 0x0,
335*eb00b1c8SRobert Mustacchi 				.itr_limit = 0x80000000,
336*eb00b1c8SRobert Mustacchi 				.itr_sock_way = 4,
337*eb00b1c8SRobert Mustacchi 				.itr_chan_way = 1,
338*eb00b1c8SRobert Mustacchi 				.itr_sock_gran = IMC_TAD_GRAN_64B,
339*eb00b1c8SRobert Mustacchi 				.itr_chan_gran = IMC_TAD_GRAN_64B,
340*eb00b1c8SRobert Mustacchi 				.itr_ntargets = 4,
341*eb00b1c8SRobert Mustacchi 				.itr_targets = { 0, 0, 0, 0 }
342*eb00b1c8SRobert Mustacchi 			}
343*eb00b1c8SRobert Mustacchi 		},
344*eb00b1c8SRobert Mustacchi 		.isock_nimc = 1,
345*eb00b1c8SRobert Mustacchi 		.isock_imcs[0] = {
346*eb00b1c8SRobert Mustacchi 			.icn_nchannels = 1,
347*eb00b1c8SRobert Mustacchi 			.icn_dimm_type = IMC_DIMM_DDR3,
348*eb00b1c8SRobert Mustacchi 			.icn_ecc = B_TRUE,
349*eb00b1c8SRobert Mustacchi 			.icn_lockstep = B_FALSE,
350*eb00b1c8SRobert Mustacchi 			.icn_closed = B_FALSE,
351*eb00b1c8SRobert Mustacchi 			.icn_channels[0] = {
352*eb00b1c8SRobert Mustacchi 				.ich_ndimms = 1,
353*eb00b1c8SRobert Mustacchi 				.ich_dimms[0] = {
354*eb00b1c8SRobert Mustacchi 					.idimm_present = B_TRUE,
355*eb00b1c8SRobert Mustacchi 					.idimm_nbanks = 3,
356*eb00b1c8SRobert Mustacchi 					.idimm_width = 8,
357*eb00b1c8SRobert Mustacchi 					.idimm_density = 2,
358*eb00b1c8SRobert Mustacchi 					.idimm_nranks = 2,
359*eb00b1c8SRobert Mustacchi 					.idimm_nrows = 14,
360*eb00b1c8SRobert Mustacchi 					.idimm_ncolumns = 10,
361*eb00b1c8SRobert Mustacchi 					.idimm_size = 0x20000000
362*eb00b1c8SRobert Mustacchi 				},
363*eb00b1c8SRobert Mustacchi 				.ich_ntad_offsets = 12,
364*eb00b1c8SRobert Mustacchi 				.ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
365*eb00b1c8SRobert Mustacchi 				    0, 0 },
366*eb00b1c8SRobert Mustacchi 				.ich_nrankileaves = 8,
367*eb00b1c8SRobert Mustacchi 				.ich_rankileaves[0] = {
368*eb00b1c8SRobert Mustacchi 					.irle_enabled = B_TRUE,
369*eb00b1c8SRobert Mustacchi 					.irle_nways = 1,
370*eb00b1c8SRobert Mustacchi 					.irle_nwaysbits = 1,
371*eb00b1c8SRobert Mustacchi 					.irle_limit = 0x20000000,
372*eb00b1c8SRobert Mustacchi 					.irle_nentries = 8,
373*eb00b1c8SRobert Mustacchi 					.irle_entries[0] = { 0x0, 0x0 },
374*eb00b1c8SRobert Mustacchi 				}
375*eb00b1c8SRobert Mustacchi 			}
376*eb00b1c8SRobert Mustacchi 		}
377*eb00b1c8SRobert Mustacchi 	},
378*eb00b1c8SRobert Mustacchi 	.imc_sockets[3] = {
379*eb00b1c8SRobert Mustacchi 		.isock_nodeid = 3,
380*eb00b1c8SRobert Mustacchi 		.isock_valid = IMC_SOCKET_V_VALID,
381*eb00b1c8SRobert Mustacchi 		.isock_sad = {
382*eb00b1c8SRobert Mustacchi 			.isad_flags = 0,
383*eb00b1c8SRobert Mustacchi 			.isad_valid = IMC_SAD_V_VALID,
384*eb00b1c8SRobert Mustacchi 			.isad_tolm = 0x80000000,
385*eb00b1c8SRobert Mustacchi 			.isad_tohm = 0,
386*eb00b1c8SRobert Mustacchi 			.isad_nrules = 10,
387*eb00b1c8SRobert Mustacchi 			.isad_rules[0] = {
388*eb00b1c8SRobert Mustacchi 				.isr_enable = B_TRUE,
389*eb00b1c8SRobert Mustacchi 				.isr_limit = 0x80000000,
390*eb00b1c8SRobert Mustacchi 				.isr_imode = IMC_SAD_IMODE_8t6,
391*eb00b1c8SRobert Mustacchi 				.isr_ntargets = IMC_MAX_SAD_INTERLEAVE,
392*eb00b1c8SRobert Mustacchi 				.isr_targets = { 0, 1, 2, 3, 0, 1, 2, 3 }
393*eb00b1c8SRobert Mustacchi 			}
394*eb00b1c8SRobert Mustacchi 		},
395*eb00b1c8SRobert Mustacchi 		.isock_ntad = 1,
396*eb00b1c8SRobert Mustacchi 		.isock_tad[0] = {
397*eb00b1c8SRobert Mustacchi 			.itad_flags = 0,
398*eb00b1c8SRobert Mustacchi 			.itad_nrules = 12,
399*eb00b1c8SRobert Mustacchi 			.itad_rules[0] = {
400*eb00b1c8SRobert Mustacchi 				.itr_base = 0x0,
401*eb00b1c8SRobert Mustacchi 				.itr_limit = 0x80000000,
402*eb00b1c8SRobert Mustacchi 				.itr_sock_way = 4,
403*eb00b1c8SRobert Mustacchi 				.itr_chan_way = 1,
404*eb00b1c8SRobert Mustacchi 				.itr_sock_gran = IMC_TAD_GRAN_64B,
405*eb00b1c8SRobert Mustacchi 				.itr_chan_gran = IMC_TAD_GRAN_64B,
406*eb00b1c8SRobert Mustacchi 				.itr_ntargets = 4,
407*eb00b1c8SRobert Mustacchi 				.itr_targets = { 0, 0, 0, 0 }
408*eb00b1c8SRobert Mustacchi 			}
409*eb00b1c8SRobert Mustacchi 		},
410*eb00b1c8SRobert Mustacchi 		.isock_nimc = 1,
411*eb00b1c8SRobert Mustacchi 		.isock_imcs[0] = {
412*eb00b1c8SRobert Mustacchi 			.icn_nchannels = 1,
413*eb00b1c8SRobert Mustacchi 			.icn_dimm_type = IMC_DIMM_DDR3,
414*eb00b1c8SRobert Mustacchi 			.icn_ecc = B_TRUE,
415*eb00b1c8SRobert Mustacchi 			.icn_lockstep = B_FALSE,
416*eb00b1c8SRobert Mustacchi 			.icn_closed = B_FALSE,
417*eb00b1c8SRobert Mustacchi 			.icn_channels[0] = {
418*eb00b1c8SRobert Mustacchi 				.ich_ndimms = 1,
419*eb00b1c8SRobert Mustacchi 				.ich_dimms[0] = {
420*eb00b1c8SRobert Mustacchi 					.idimm_present = B_TRUE,
421*eb00b1c8SRobert Mustacchi 					.idimm_nbanks = 3,
422*eb00b1c8SRobert Mustacchi 					.idimm_width = 8,
423*eb00b1c8SRobert Mustacchi 					.idimm_density = 2,
424*eb00b1c8SRobert Mustacchi 					.idimm_nranks = 2,
425*eb00b1c8SRobert Mustacchi 					.idimm_nrows = 14,
426*eb00b1c8SRobert Mustacchi 					.idimm_ncolumns = 10,
427*eb00b1c8SRobert Mustacchi 					.idimm_size = 0x20000000
428*eb00b1c8SRobert Mustacchi 				},
429*eb00b1c8SRobert Mustacchi 				.ich_ntad_offsets = 12,
430*eb00b1c8SRobert Mustacchi 				.ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
431*eb00b1c8SRobert Mustacchi 				    0, 0 },
432*eb00b1c8SRobert Mustacchi 				.ich_nrankileaves = 8,
433*eb00b1c8SRobert Mustacchi 				.ich_rankileaves[0] = {
434*eb00b1c8SRobert Mustacchi 					.irle_enabled = B_TRUE,
435*eb00b1c8SRobert Mustacchi 					.irle_nways = 1,
436*eb00b1c8SRobert Mustacchi 					.irle_nwaysbits = 1,
437*eb00b1c8SRobert Mustacchi 					.irle_limit = 0x20000000,
438*eb00b1c8SRobert Mustacchi 					.irle_nentries = 8,
439*eb00b1c8SRobert Mustacchi 					.irle_entries[0] = { 0x0, 0x0 },
440*eb00b1c8SRobert Mustacchi 				}
441*eb00b1c8SRobert Mustacchi 			}
442*eb00b1c8SRobert Mustacchi 		}
443*eb00b1c8SRobert Mustacchi 	}
444*eb00b1c8SRobert Mustacchi };
445*eb00b1c8SRobert Mustacchi 
446*eb00b1c8SRobert Mustacchi /*
447*eb00b1c8SRobert Mustacchi  * This is similar to imc_sad_2s_basic; however, it enables the XOR mode.
448*eb00b1c8SRobert Mustacchi  */
449*eb00b1c8SRobert Mustacchi static const imc_t imc_sad_2s_xor = {
450*eb00b1c8SRobert Mustacchi 	.imc_gen = IMC_GEN_IVY,
451*eb00b1c8SRobert Mustacchi 	.imc_nsockets = 2,
452*eb00b1c8SRobert Mustacchi 	.imc_sockets[0] = {
453*eb00b1c8SRobert Mustacchi 		.isock_nodeid = 0,
454*eb00b1c8SRobert Mustacchi 		.isock_valid = IMC_SOCKET_V_VALID,
455*eb00b1c8SRobert Mustacchi 		.isock_sad = {
456*eb00b1c8SRobert Mustacchi 			.isad_flags = 0,
457*eb00b1c8SRobert Mustacchi 			.isad_valid = IMC_SAD_V_VALID,
458*eb00b1c8SRobert Mustacchi 			.isad_tolm = 0x80000000,
459*eb00b1c8SRobert Mustacchi 			.isad_tohm = 0,
460*eb00b1c8SRobert Mustacchi 			.isad_nrules = 10,
461*eb00b1c8SRobert Mustacchi 			.isad_rules[0] = {
462*eb00b1c8SRobert Mustacchi 				.isr_enable = B_TRUE,
463*eb00b1c8SRobert Mustacchi 				.isr_limit = 0x80000000,
464*eb00b1c8SRobert Mustacchi 				.isr_imode = IMC_SAD_IMODE_8t6XOR,
465*eb00b1c8SRobert Mustacchi 				.isr_ntargets = IMC_MAX_SAD_INTERLEAVE,
466*eb00b1c8SRobert Mustacchi 				.isr_targets = { 0, 1, 0, 1, 0, 1, 0, 1 }
467*eb00b1c8SRobert Mustacchi 			}
468*eb00b1c8SRobert Mustacchi 		},
469*eb00b1c8SRobert Mustacchi 		.isock_ntad = 1,
470*eb00b1c8SRobert Mustacchi 		.isock_tad[0] = {
471*eb00b1c8SRobert Mustacchi 			.itad_flags = 0,
472*eb00b1c8SRobert Mustacchi 			.itad_nrules = 12,
473*eb00b1c8SRobert Mustacchi 			.itad_rules[0] = {
474*eb00b1c8SRobert Mustacchi 				.itr_base = 0x0,
475*eb00b1c8SRobert Mustacchi 				.itr_limit = 0x80000000,
476*eb00b1c8SRobert Mustacchi 				.itr_sock_way = 2,
477*eb00b1c8SRobert Mustacchi 				.itr_chan_way = 1,
478*eb00b1c8SRobert Mustacchi 				.itr_sock_gran = IMC_TAD_GRAN_64B,
479*eb00b1c8SRobert Mustacchi 				.itr_chan_gran = IMC_TAD_GRAN_64B,
480*eb00b1c8SRobert Mustacchi 				.itr_ntargets = 4,
481*eb00b1c8SRobert Mustacchi 				.itr_targets = { 0, 0, 0, 0 }
482*eb00b1c8SRobert Mustacchi 			}
483*eb00b1c8SRobert Mustacchi 		},
484*eb00b1c8SRobert Mustacchi 		.isock_nimc = 1,
485*eb00b1c8SRobert Mustacchi 		.isock_imcs[0] = {
486*eb00b1c8SRobert Mustacchi 			.icn_nchannels = 1,
487*eb00b1c8SRobert Mustacchi 			.icn_dimm_type = IMC_DIMM_DDR3,
488*eb00b1c8SRobert Mustacchi 			.icn_ecc = B_TRUE,
489*eb00b1c8SRobert Mustacchi 			.icn_lockstep = B_FALSE,
490*eb00b1c8SRobert Mustacchi 			.icn_closed = B_FALSE,
491*eb00b1c8SRobert Mustacchi 			.icn_channels[0] = {
492*eb00b1c8SRobert Mustacchi 				.ich_ndimms = 1,
493*eb00b1c8SRobert Mustacchi 				.ich_dimms[0] = {
494*eb00b1c8SRobert Mustacchi 					.idimm_present = B_TRUE,
495*eb00b1c8SRobert Mustacchi 					.idimm_nbanks = 3,
496*eb00b1c8SRobert Mustacchi 					.idimm_width = 8,
497*eb00b1c8SRobert Mustacchi 					.idimm_density = 2,
498*eb00b1c8SRobert Mustacchi 					.idimm_nranks = 2,
499*eb00b1c8SRobert Mustacchi 					.idimm_nrows = 14,
500*eb00b1c8SRobert Mustacchi 					.idimm_ncolumns = 10,
501*eb00b1c8SRobert Mustacchi 					.idimm_size = 0x40000000
502*eb00b1c8SRobert Mustacchi 				},
503*eb00b1c8SRobert Mustacchi 				.ich_ntad_offsets = 12,
504*eb00b1c8SRobert Mustacchi 				.ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
505*eb00b1c8SRobert Mustacchi 				    0, 0 },
506*eb00b1c8SRobert Mustacchi 				.ich_nrankileaves = 8,
507*eb00b1c8SRobert Mustacchi 				.ich_rankileaves[0] = {
508*eb00b1c8SRobert Mustacchi 					.irle_enabled = B_TRUE,
509*eb00b1c8SRobert Mustacchi 					.irle_nways = 1,
510*eb00b1c8SRobert Mustacchi 					.irle_nwaysbits = 1,
511*eb00b1c8SRobert Mustacchi 					.irle_limit = 0x40000000,
512*eb00b1c8SRobert Mustacchi 					.irle_nentries = 8,
513*eb00b1c8SRobert Mustacchi 					.irle_entries[0] = { 0x0, 0x0 },
514*eb00b1c8SRobert Mustacchi 				}
515*eb00b1c8SRobert Mustacchi 			}
516*eb00b1c8SRobert Mustacchi 		}
517*eb00b1c8SRobert Mustacchi 	},
518*eb00b1c8SRobert Mustacchi 	.imc_sockets[1] = {
519*eb00b1c8SRobert Mustacchi 		.isock_nodeid = 1,
520*eb00b1c8SRobert Mustacchi 		.isock_valid = IMC_SOCKET_V_VALID,
521*eb00b1c8SRobert Mustacchi 		.isock_sad = {
522*eb00b1c8SRobert Mustacchi 			.isad_flags = 0,
523*eb00b1c8SRobert Mustacchi 			.isad_valid = IMC_SAD_V_VALID,
524*eb00b1c8SRobert Mustacchi 			.isad_tolm = 0x80000000,
525*eb00b1c8SRobert Mustacchi 			.isad_tohm = 0,
526*eb00b1c8SRobert Mustacchi 			.isad_nrules = 10,
527*eb00b1c8SRobert Mustacchi 			.isad_rules[0] = {
528*eb00b1c8SRobert Mustacchi 				.isr_enable = B_TRUE,
529*eb00b1c8SRobert Mustacchi 				.isr_limit = 0x80000000,
530*eb00b1c8SRobert Mustacchi 				.isr_imode = IMC_SAD_IMODE_8t6XOR,
531*eb00b1c8SRobert Mustacchi 				.isr_ntargets = IMC_MAX_SAD_INTERLEAVE,
532*eb00b1c8SRobert Mustacchi 				.isr_targets = { 0, 1, 0, 1, 0, 1, 0, 1 }
533*eb00b1c8SRobert Mustacchi 			}
534*eb00b1c8SRobert Mustacchi 		},
535*eb00b1c8SRobert Mustacchi 		.isock_ntad = 1,
536*eb00b1c8SRobert Mustacchi 		.isock_tad[0] = {
537*eb00b1c8SRobert Mustacchi 			.itad_flags = 0,
538*eb00b1c8SRobert Mustacchi 			.itad_nrules = 12,
539*eb00b1c8SRobert Mustacchi 			.itad_rules[0] = {
540*eb00b1c8SRobert Mustacchi 				.itr_base = 0x0,
541*eb00b1c8SRobert Mustacchi 				.itr_limit = 0x80000000,
542*eb00b1c8SRobert Mustacchi 				.itr_sock_way = 2,
543*eb00b1c8SRobert Mustacchi 				.itr_chan_way = 1,
544*eb00b1c8SRobert Mustacchi 				.itr_sock_gran = IMC_TAD_GRAN_64B,
545*eb00b1c8SRobert Mustacchi 				.itr_chan_gran = IMC_TAD_GRAN_64B,
546*eb00b1c8SRobert Mustacchi 				.itr_ntargets = 4,
547*eb00b1c8SRobert Mustacchi 				.itr_targets = { 0, 0, 0, 0 }
548*eb00b1c8SRobert Mustacchi 			}
549*eb00b1c8SRobert Mustacchi 		},
550*eb00b1c8SRobert Mustacchi 		.isock_nimc = 1,
551*eb00b1c8SRobert Mustacchi 		.isock_imcs[0] = {
552*eb00b1c8SRobert Mustacchi 			.icn_nchannels = 1,
553*eb00b1c8SRobert Mustacchi 			.icn_dimm_type = IMC_DIMM_DDR3,
554*eb00b1c8SRobert Mustacchi 			.icn_ecc = B_TRUE,
555*eb00b1c8SRobert Mustacchi 			.icn_lockstep = B_FALSE,
556*eb00b1c8SRobert Mustacchi 			.icn_closed = B_FALSE,
557*eb00b1c8SRobert Mustacchi 			.icn_channels[0] = {
558*eb00b1c8SRobert Mustacchi 				.ich_ndimms = 1,
559*eb00b1c8SRobert Mustacchi 				.ich_dimms[0] = {
560*eb00b1c8SRobert Mustacchi 					.idimm_present = B_TRUE,
561*eb00b1c8SRobert Mustacchi 					.idimm_nbanks = 3,
562*eb00b1c8SRobert Mustacchi 					.idimm_width = 8,
563*eb00b1c8SRobert Mustacchi 					.idimm_density = 2,
564*eb00b1c8SRobert Mustacchi 					.idimm_nranks = 2,
565*eb00b1c8SRobert Mustacchi 					.idimm_nrows = 14,
566*eb00b1c8SRobert Mustacchi 					.idimm_ncolumns = 10,
567*eb00b1c8SRobert Mustacchi 					.idimm_size = 0x40000000
568*eb00b1c8SRobert Mustacchi 				},
569*eb00b1c8SRobert Mustacchi 				.ich_ntad_offsets = 12,
570*eb00b1c8SRobert Mustacchi 				.ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
571*eb00b1c8SRobert Mustacchi 				    0, 0 },
572*eb00b1c8SRobert Mustacchi 				.ich_nrankileaves = 8,
573*eb00b1c8SRobert Mustacchi 				.ich_rankileaves[0] = {
574*eb00b1c8SRobert Mustacchi 					.irle_enabled = B_TRUE,
575*eb00b1c8SRobert Mustacchi 					.irle_nways = 1,
576*eb00b1c8SRobert Mustacchi 					.irle_nwaysbits = 1,
577*eb00b1c8SRobert Mustacchi 					.irle_limit = 0x40000000,
578*eb00b1c8SRobert Mustacchi 					.irle_nentries = 8,
579*eb00b1c8SRobert Mustacchi 					.irle_entries[0] = { 0x0, 0x0 },
580*eb00b1c8SRobert Mustacchi 				}
581*eb00b1c8SRobert Mustacchi 			}
582*eb00b1c8SRobert Mustacchi 		}
583*eb00b1c8SRobert Mustacchi 	}
584*eb00b1c8SRobert Mustacchi };
585*eb00b1c8SRobert Mustacchi 
586*eb00b1c8SRobert Mustacchi static const imc_t imc_sad_2s_a7 = {
587*eb00b1c8SRobert Mustacchi 	.imc_gen = IMC_GEN_IVY,
588*eb00b1c8SRobert Mustacchi 	.imc_nsockets = 2,
589*eb00b1c8SRobert Mustacchi 	.imc_sockets[0] = {
590*eb00b1c8SRobert Mustacchi 		.isock_nodeid = 0,
591*eb00b1c8SRobert Mustacchi 		.isock_valid = IMC_SOCKET_V_VALID,
592*eb00b1c8SRobert Mustacchi 		.isock_sad = {
593*eb00b1c8SRobert Mustacchi 			.isad_flags = 0,
594*eb00b1c8SRobert Mustacchi 			.isad_valid = IMC_SAD_V_VALID,
595*eb00b1c8SRobert Mustacchi 			.isad_tolm = 0x80000000,
596*eb00b1c8SRobert Mustacchi 			.isad_tohm = 0,
597*eb00b1c8SRobert Mustacchi 			.isad_nrules = 10,
598*eb00b1c8SRobert Mustacchi 			.isad_rules[0] = {
599*eb00b1c8SRobert Mustacchi 				.isr_enable = B_TRUE,
600*eb00b1c8SRobert Mustacchi 				.isr_limit = 0x80000000,
601*eb00b1c8SRobert Mustacchi 				.isr_imode = IMC_SAD_IMODE_8t6,
602*eb00b1c8SRobert Mustacchi 				.isr_a7mode = B_TRUE,
603*eb00b1c8SRobert Mustacchi 				.isr_ntargets = IMC_MAX_SAD_INTERLEAVE,
604*eb00b1c8SRobert Mustacchi 				.isr_targets = { 0, 1, 0, 1, 0, 1, 0, 1 }
605*eb00b1c8SRobert Mustacchi 			}
606*eb00b1c8SRobert Mustacchi 		},
607*eb00b1c8SRobert Mustacchi 		.isock_ntad = 1,
608*eb00b1c8SRobert Mustacchi 		.isock_tad[0] = {
609*eb00b1c8SRobert Mustacchi 			.itad_flags = IMC_TAD_FLAG_CHANSHIFT,
610*eb00b1c8SRobert Mustacchi 			.itad_nrules = 12,
611*eb00b1c8SRobert Mustacchi 			.itad_rules[0] = {
612*eb00b1c8SRobert Mustacchi 				.itr_base = 0x0,
613*eb00b1c8SRobert Mustacchi 				.itr_limit = 0x80000000,
614*eb00b1c8SRobert Mustacchi 				.itr_sock_way = 2,
615*eb00b1c8SRobert Mustacchi 				.itr_chan_way = 1,
616*eb00b1c8SRobert Mustacchi 				.itr_sock_gran = IMC_TAD_GRAN_64B,
617*eb00b1c8SRobert Mustacchi 				.itr_chan_gran = IMC_TAD_GRAN_64B,
618*eb00b1c8SRobert Mustacchi 				.itr_ntargets = 4,
619*eb00b1c8SRobert Mustacchi 				.itr_targets = { 0, 0, 0, 0 }
620*eb00b1c8SRobert Mustacchi 			}
621*eb00b1c8SRobert Mustacchi 		},
622*eb00b1c8SRobert Mustacchi 		.isock_nimc = 1,
623*eb00b1c8SRobert Mustacchi 		.isock_imcs[0] = {
624*eb00b1c8SRobert Mustacchi 			.icn_nchannels = 1,
625*eb00b1c8SRobert Mustacchi 			.icn_dimm_type = IMC_DIMM_DDR3,
626*eb00b1c8SRobert Mustacchi 			.icn_ecc = B_TRUE,
627*eb00b1c8SRobert Mustacchi 			.icn_lockstep = B_FALSE,
628*eb00b1c8SRobert Mustacchi 			.icn_closed = B_FALSE,
629*eb00b1c8SRobert Mustacchi 			.icn_channels[0] = {
630*eb00b1c8SRobert Mustacchi 				.ich_ndimms = 1,
631*eb00b1c8SRobert Mustacchi 				.ich_dimms[0] = {
632*eb00b1c8SRobert Mustacchi 					.idimm_present = B_TRUE,
633*eb00b1c8SRobert Mustacchi 					.idimm_nbanks = 3,
634*eb00b1c8SRobert Mustacchi 					.idimm_width = 8,
635*eb00b1c8SRobert Mustacchi 					.idimm_density = 2,
636*eb00b1c8SRobert Mustacchi 					.idimm_nranks = 2,
637*eb00b1c8SRobert Mustacchi 					.idimm_nrows = 14,
638*eb00b1c8SRobert Mustacchi 					.idimm_ncolumns = 10,
639*eb00b1c8SRobert Mustacchi 					.idimm_size = 0x40000000
640*eb00b1c8SRobert Mustacchi 				},
641*eb00b1c8SRobert Mustacchi 				.ich_ntad_offsets = 12,
642*eb00b1c8SRobert Mustacchi 				.ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
643*eb00b1c8SRobert Mustacchi 				    0, 0 },
644*eb00b1c8SRobert Mustacchi 				.ich_nrankileaves = 8,
645*eb00b1c8SRobert Mustacchi 				.ich_rankileaves[0] = {
646*eb00b1c8SRobert Mustacchi 					.irle_enabled = B_TRUE,
647*eb00b1c8SRobert Mustacchi 					.irle_nways = 1,
648*eb00b1c8SRobert Mustacchi 					.irle_nwaysbits = 1,
649*eb00b1c8SRobert Mustacchi 					.irle_limit = 0x40000000,
650*eb00b1c8SRobert Mustacchi 					.irle_nentries = 8,
651*eb00b1c8SRobert Mustacchi 					.irle_entries[0] = { 0x0, 0x0 },
652*eb00b1c8SRobert Mustacchi 				}
653*eb00b1c8SRobert Mustacchi 			}
654*eb00b1c8SRobert Mustacchi 		}
655*eb00b1c8SRobert Mustacchi 	},
656*eb00b1c8SRobert Mustacchi 	.imc_sockets[1] = {
657*eb00b1c8SRobert Mustacchi 		.isock_nodeid = 1,
658*eb00b1c8SRobert Mustacchi 		.isock_valid = IMC_SOCKET_V_VALID,
659*eb00b1c8SRobert Mustacchi 		.isock_sad = {
660*eb00b1c8SRobert Mustacchi 			.isad_flags = 0,
661*eb00b1c8SRobert Mustacchi 			.isad_valid = IMC_SAD_V_VALID,
662*eb00b1c8SRobert Mustacchi 			.isad_tolm = 0x80000000,
663*eb00b1c8SRobert Mustacchi 			.isad_tohm = 0,
664*eb00b1c8SRobert Mustacchi 			.isad_nrules = 10,
665*eb00b1c8SRobert Mustacchi 			.isad_rules[0] = {
666*eb00b1c8SRobert Mustacchi 				.isr_enable = B_TRUE,
667*eb00b1c8SRobert Mustacchi 				.isr_limit = 0x80000000,
668*eb00b1c8SRobert Mustacchi 				.isr_imode = IMC_SAD_IMODE_8t6,
669*eb00b1c8SRobert Mustacchi 				.isr_a7mode = B_TRUE,
670*eb00b1c8SRobert Mustacchi 				.isr_ntargets = IMC_MAX_SAD_INTERLEAVE,
671*eb00b1c8SRobert Mustacchi 				.isr_targets = { 0, 1, 0, 1, 0, 1, 0, 1 }
672*eb00b1c8SRobert Mustacchi 			}
673*eb00b1c8SRobert Mustacchi 		},
674*eb00b1c8SRobert Mustacchi 		.isock_ntad = 1,
675*eb00b1c8SRobert Mustacchi 		.isock_tad[0] = {
676*eb00b1c8SRobert Mustacchi 			.itad_flags = IMC_TAD_FLAG_CHANSHIFT,
677*eb00b1c8SRobert Mustacchi 			.itad_nrules = 12,
678*eb00b1c8SRobert Mustacchi 			.itad_rules[0] = {
679*eb00b1c8SRobert Mustacchi 				.itr_base = 0x0,
680*eb00b1c8SRobert Mustacchi 				.itr_limit = 0x80000000,
681*eb00b1c8SRobert Mustacchi 				.itr_sock_way = 2,
682*eb00b1c8SRobert Mustacchi 				.itr_chan_way = 1,
683*eb00b1c8SRobert Mustacchi 				.itr_sock_gran = IMC_TAD_GRAN_64B,
684*eb00b1c8SRobert Mustacchi 				.itr_chan_gran = IMC_TAD_GRAN_64B,
685*eb00b1c8SRobert Mustacchi 				.itr_ntargets = 4,
686*eb00b1c8SRobert Mustacchi 				.itr_targets = { 0, 0, 0, 0 }
687*eb00b1c8SRobert Mustacchi 			}
688*eb00b1c8SRobert Mustacchi 		},
689*eb00b1c8SRobert Mustacchi 		.isock_nimc = 1,
690*eb00b1c8SRobert Mustacchi 		.isock_imcs[0] = {
691*eb00b1c8SRobert Mustacchi 			.icn_nchannels = 1,
692*eb00b1c8SRobert Mustacchi 			.icn_dimm_type = IMC_DIMM_DDR3,
693*eb00b1c8SRobert Mustacchi 			.icn_ecc = B_TRUE,
694*eb00b1c8SRobert Mustacchi 			.icn_lockstep = B_FALSE,
695*eb00b1c8SRobert Mustacchi 			.icn_closed = B_FALSE,
696*eb00b1c8SRobert Mustacchi 			.icn_channels[0] = {
697*eb00b1c8SRobert Mustacchi 				.ich_ndimms = 1,
698*eb00b1c8SRobert Mustacchi 				.ich_dimms[0] = {
699*eb00b1c8SRobert Mustacchi 					.idimm_present = B_TRUE,
700*eb00b1c8SRobert Mustacchi 					.idimm_nbanks = 3,
701*eb00b1c8SRobert Mustacchi 					.idimm_width = 8,
702*eb00b1c8SRobert Mustacchi 					.idimm_density = 2,
703*eb00b1c8SRobert Mustacchi 					.idimm_nranks = 2,
704*eb00b1c8SRobert Mustacchi 					.idimm_nrows = 14,
705*eb00b1c8SRobert Mustacchi 					.idimm_ncolumns = 10,
706*eb00b1c8SRobert Mustacchi 					.idimm_size = 0x40000000
707*eb00b1c8SRobert Mustacchi 				},
708*eb00b1c8SRobert Mustacchi 				.ich_ntad_offsets = 12,
709*eb00b1c8SRobert Mustacchi 				.ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
710*eb00b1c8SRobert Mustacchi 				    0, 0 },
711*eb00b1c8SRobert Mustacchi 				.ich_nrankileaves = 8,
712*eb00b1c8SRobert Mustacchi 				.ich_rankileaves[0] = {
713*eb00b1c8SRobert Mustacchi 					.irle_enabled = B_TRUE,
714*eb00b1c8SRobert Mustacchi 					.irle_nways = 1,
715*eb00b1c8SRobert Mustacchi 					.irle_nwaysbits = 1,
716*eb00b1c8SRobert Mustacchi 					.irle_limit = 0x40000000,
717*eb00b1c8SRobert Mustacchi 					.irle_nentries = 8,
718*eb00b1c8SRobert Mustacchi 					.irle_entries[0] = { 0x0, 0x0 },
719*eb00b1c8SRobert Mustacchi 				}
720*eb00b1c8SRobert Mustacchi 			}
721*eb00b1c8SRobert Mustacchi 		}
722*eb00b1c8SRobert Mustacchi 	}
723*eb00b1c8SRobert Mustacchi };
724*eb00b1c8SRobert Mustacchi 
725*eb00b1c8SRobert Mustacchi /*
726*eb00b1c8SRobert Mustacchi  * This is a 4 socket variants of the previous one. Each DIMM now has a much
727*eb00b1c8SRobert Mustacchi  * smaller amount of memory in it.
728*eb00b1c8SRobert Mustacchi  */
729*eb00b1c8SRobert Mustacchi static const imc_t imc_sad_4s_a7 = {
730*eb00b1c8SRobert Mustacchi 	.imc_gen = IMC_GEN_HASWELL,
731*eb00b1c8SRobert Mustacchi 	.imc_nsockets = 4,
732*eb00b1c8SRobert Mustacchi 	.imc_sockets[0] = {
733*eb00b1c8SRobert Mustacchi 		.isock_nodeid = 0,
734*eb00b1c8SRobert Mustacchi 		.isock_valid = IMC_SOCKET_V_VALID,