1 /*
2  * This file and its contents are supplied under the terms of the
3  * Common Development and Distribution License ("CDDL"), version 1.0.
4  * You may only use this file in accordance with the terms of version
5  * 1.0 of the CDDL.
6  *
7  * A full copy of the text of the CDDL should have accompanied this
8  * source.  A copy of the CDDL is also available via the Internet at
9  * http://www.illumos.org/license/CDDL.
10  */
11 
12 /*
13  * Copyright 2019 Joyent, Inc.
14  */
15 
16 #include "imc_test.h"
17 
18 /*
19  * This represents a basic configuration with a single socket, channel, and
20  * DIMM that is 2 GiB in size. This entirely punts on the fact that the legacy
21  * ranges overlap here.
22  */
23 static const imc_t imc_basic_snb = {
24 	.imc_gen = IMC_GEN_SANDY,
25 	.imc_nsockets = 1,
26 	.imc_sockets[0] = {
27 		.isock_valid = IMC_SOCKET_V_VALID,
28 		.isock_sad = {
29 			.isad_flags = 0,
30 			.isad_valid = IMC_SAD_V_VALID,
31 			.isad_tolm = 0x80000000,
32 			.isad_tohm = 0,
33 			.isad_nrules = 10,
34 			.isad_rules[0] = {
35 				.isr_enable = B_TRUE,
36 				.isr_limit = 0x80000000,
37 				.isr_imode = IMC_SAD_IMODE_8t6,
38 				.isr_ntargets = IMC_MAX_SAD_INTERLEAVE,
39 				.isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 }
40 			}
41 		},
42 		.isock_ntad = 1,
43 		.isock_tad[0] = {
44 			.itad_flags = 0,
45 			.itad_nrules = 12,
46 			.itad_rules[0] = {
47 				.itr_base = 0x0,
48 				.itr_limit = 0x80000000,
49 				.itr_sock_way = 1,
50 				.itr_chan_way = 1,
51 				.itr_sock_gran = IMC_TAD_GRAN_64B,
52 				.itr_chan_gran = IMC_TAD_GRAN_64B,
53 				.itr_ntargets = 4,
54 				.itr_targets = { 0, 0, 0, 0 }
55 			}
56 		},
57 		.isock_nimc = 1,
58 		.isock_imcs[0] = {
59 			.icn_nchannels = 1,
60 			.icn_dimm_type = IMC_DIMM_DDR3,
61 			.icn_ecc = B_TRUE,
62 			.icn_lockstep = B_FALSE,
63 			.icn_closed = B_TRUE,
64 			.icn_channels[0] = {
65 				.ich_ndimms = 1,
66 				.ich_dimms[0] = {
67 					.idimm_present = B_TRUE,
68 					.idimm_nbanks = 3,
69 					.idimm_width = 8,
70 					.idimm_density = 2,
71 					.idimm_nranks = 2,
72 					.idimm_nrows = 14,
73 					.idimm_ncolumns = 10,
74 					.idimm_size = 0x80000000
75 				},
76 				.ich_ntad_offsets = 12,
77 				.ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
78 				    0, 0 },
79 				.ich_nrankileaves = 8,
80 				.ich_rankileaves[0] = {
81 					.irle_enabled = B_TRUE,
82 					.irle_nways = 2,
83 					.irle_nwaysbits = 1,
84 					.irle_limit = 0x80000000,
85 					.irle_nentries = 5,
86 					.irle_entries[0] = { 0x0, 0x0 },
87 					.irle_entries[1] = { 0x1, 0x0 }
88 				}
89 			}
90 		}
91 	}
92 };
93 
94 const imc_test_case_t imc_test_basics[] = { {
95 	.itc_desc = "decode basic single socket/channel/DIMM, dual rank (1)",
96 	.itc_imc = &imc_basic_snb,
97 	.itc_pa = 0x0,
98 	.itc_pass = B_TRUE,
99 	.itc_nodeid = 0,
100 	.itc_tadid = 0,
101 	.itc_channelid = 0,
102 	.itc_chanaddr = 0,
103 	.itc_dimmid = 0,
104 	.itc_rankid = 0,
105 	.itc_rankaddr = 0
106 }, {
107 	.itc_desc = "decode basic single socket/channel/DIMM, dual rank (2)",
108 	.itc_imc = &imc_basic_snb,
109 	.itc_pa = 0x1000,
110 	.itc_pass = B_TRUE,
111 	.itc_nodeid = 0,
112 	.itc_tadid = 0,
113 	.itc_channelid = 0,
114 	.itc_chanaddr = 0x1000,
115 	.itc_dimmid = 0,
116 	.itc_rankid = 0,
117 	.itc_rankaddr = 0x800
118 }, {
119 	.itc_desc = "decode basic single socket/channel/DIMM, dual rank (3)",
120 	.itc_imc = &imc_basic_snb,
121 	.itc_pa = 0x7fffffff,
122 	.itc_pass = B_TRUE,
123 	.itc_nodeid = 0,
124 	.itc_tadid = 0,
125 	.itc_channelid = 0,
126 	.itc_chanaddr = 0x7fffffff,
127 	.itc_dimmid = 0,
128 	.itc_rankid = 1,
129 	.itc_rankaddr = 0x3fffffff,
130 }, {
131 	.itc_desc = NULL
132 } };
133