17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 57c478bd9Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 67c478bd9Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 77c478bd9Sstevel@tonic-gate * with the License. 87c478bd9Sstevel@tonic-gate * 97c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 107c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 117c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 127c478bd9Sstevel@tonic-gate * and limitations under the License. 137c478bd9Sstevel@tonic-gate * 147c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 157c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 167c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 177c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 187c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 197c478bd9Sstevel@tonic-gate * 207c478bd9Sstevel@tonic-gate * CDDL HEADER END 217c478bd9Sstevel@tonic-gate */ 227c478bd9Sstevel@tonic-gate /* 237c478bd9Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 247c478bd9Sstevel@tonic-gate * Use is subject to license terms. 257c478bd9Sstevel@tonic-gate */ 267c478bd9Sstevel@tonic-gate 277c478bd9Sstevel@tonic-gate #ifndef _DT_PCB_H 287c478bd9Sstevel@tonic-gate #define _DT_PCB_H 297c478bd9Sstevel@tonic-gate 307c478bd9Sstevel@tonic-gate #include <dtrace.h> 317c478bd9Sstevel@tonic-gate #include <setjmp.h> 327c478bd9Sstevel@tonic-gate #include <stdio.h> 337c478bd9Sstevel@tonic-gate 347c478bd9Sstevel@tonic-gate #ifdef __cplusplus 357c478bd9Sstevel@tonic-gate extern "C" { 367c478bd9Sstevel@tonic-gate #endif 377c478bd9Sstevel@tonic-gate 387c478bd9Sstevel@tonic-gate #include <dt_parser.h> 397c478bd9Sstevel@tonic-gate #include <dt_regset.h> 407c478bd9Sstevel@tonic-gate #include <dt_inttab.h> 417c478bd9Sstevel@tonic-gate #include <dt_strtab.h> 427c478bd9Sstevel@tonic-gate #include <dt_decl.h> 437c478bd9Sstevel@tonic-gate #include <dt_as.h> 447c478bd9Sstevel@tonic-gate 457c478bd9Sstevel@tonic-gate typedef struct dt_pcb { 467c478bd9Sstevel@tonic-gate dtrace_hdl_t *pcb_hdl; /* pointer to library handle */ 477c478bd9Sstevel@tonic-gate struct dt_pcb *pcb_prev; /* pointer to previous pcb in stack */ 487c478bd9Sstevel@tonic-gate FILE *pcb_fileptr; /* pointer to input file (or NULL) */ 497c478bd9Sstevel@tonic-gate char *pcb_filetag; /* optional file name string (or NULL) */ 507c478bd9Sstevel@tonic-gate const char *pcb_string; /* pointer to input string (or NULL) */ 517c478bd9Sstevel@tonic-gate const char *pcb_strptr; /* pointer to input position */ 527c478bd9Sstevel@tonic-gate size_t pcb_strlen; /* length of pcb_string */ 537c478bd9Sstevel@tonic-gate int pcb_sargc; /* number of script arguments (if any) */ 547c478bd9Sstevel@tonic-gate char *const *pcb_sargv; /* script argument strings (if any) */ 557c478bd9Sstevel@tonic-gate ushort_t *pcb_sflagv; /* script argument flags (DT_IDFLG_* bits) */ 567c478bd9Sstevel@tonic-gate dt_scope_t pcb_dstack; /* declaration processing stack */ 577c478bd9Sstevel@tonic-gate dt_node_t *pcb_list; /* list of allocated parse tree nodes */ 587c478bd9Sstevel@tonic-gate dt_node_t *pcb_hold; /* parse tree nodes on hold until end of defn */ 597c478bd9Sstevel@tonic-gate dt_node_t *pcb_root; /* root of current parse tree */ 607c478bd9Sstevel@tonic-gate dt_idstack_t pcb_globals; /* stack of global identifier hash tables */ 617c478bd9Sstevel@tonic-gate dt_idhash_t *pcb_locals; /* current hash table of local identifiers */ 627c478bd9Sstevel@tonic-gate dt_idhash_t *pcb_idents; /* current hash table of ambiguous idents */ 637c478bd9Sstevel@tonic-gate dt_idhash_t *pcb_pragmas; /* current hash table of pending pragmas */ 647c478bd9Sstevel@tonic-gate dt_inttab_t *pcb_inttab; /* integer table for constant references */ 657c478bd9Sstevel@tonic-gate dt_strtab_t *pcb_strtab; /* string table for string references */ 667c478bd9Sstevel@tonic-gate dt_regset_t *pcb_regs; /* register set for code generation */ 677c478bd9Sstevel@tonic-gate dt_irlist_t pcb_ir; /* list of unrelocated IR instructions */ 68*1a7c1b72Smws uint_t pcb_asvidx; /* assembler vartab index (see dt_as.c) */ 69*1a7c1b72Smws ulong_t **pcb_asxrefs; /* assembler imported xlators (see dt_as.c) */ 70*1a7c1b72Smws uint_t pcb_asxreflen; /* assembler xlator map length (see dt_as.c) */ 717c478bd9Sstevel@tonic-gate const dtrace_probedesc_t *pcb_pdesc; /* probedesc for current context */ 727c478bd9Sstevel@tonic-gate struct dt_probe *pcb_probe; /* probe associated with current context */ 737c478bd9Sstevel@tonic-gate dtrace_probeinfo_t pcb_pinfo; /* info associated with current context */ 747c478bd9Sstevel@tonic-gate dtrace_attribute_t pcb_amin; /* stability minimum for compilation */ 757c478bd9Sstevel@tonic-gate dt_node_t *pcb_dret; /* node containing return type for assembler */ 767c478bd9Sstevel@tonic-gate dtrace_difo_t *pcb_difo; /* intermediate DIF object made by assembler */ 777c478bd9Sstevel@tonic-gate dtrace_prog_t *pcb_prog; /* intermediate program made by compiler */ 787c478bd9Sstevel@tonic-gate dtrace_stmtdesc_t *pcb_stmt; /* intermediate stmt made by compiler */ 797c478bd9Sstevel@tonic-gate dtrace_ecbdesc_t *pcb_ecbdesc; /* intermediate ecbdesc made by cmplr */ 807c478bd9Sstevel@tonic-gate jmp_buf pcb_jmpbuf; /* setjmp(3C) buffer for error return */ 817c478bd9Sstevel@tonic-gate const char *pcb_region; /* optional region name for yyerror() suffix */ 827c478bd9Sstevel@tonic-gate dtrace_probespec_t pcb_pspec; /* probe description evaluation context */ 837c478bd9Sstevel@tonic-gate uint_t pcb_cflags; /* optional compilation flags (see dtrace.h) */ 847c478bd9Sstevel@tonic-gate uint_t pcb_idepth; /* preprocessor #include nesting depth */ 857c478bd9Sstevel@tonic-gate yystate_t pcb_yystate; /* lex/yacc parsing state (see yybegin()) */ 867c478bd9Sstevel@tonic-gate int pcb_context; /* yyparse() rules context (DT_CTX_* value) */ 877c478bd9Sstevel@tonic-gate int pcb_token; /* token to be returned by yylex() (if != 0) */ 887c478bd9Sstevel@tonic-gate int pcb_cstate; /* state to be restored by lexer at state end */ 897c478bd9Sstevel@tonic-gate int pcb_braces; /* number of open curly braces in lexer */ 907c478bd9Sstevel@tonic-gate int pcb_brackets; /* number of open square brackets in lexer */ 917c478bd9Sstevel@tonic-gate int pcb_parens; /* number of open parentheses in lexer */ 927c478bd9Sstevel@tonic-gate } dt_pcb_t; 937c478bd9Sstevel@tonic-gate 947c478bd9Sstevel@tonic-gate extern void dt_pcb_push(dtrace_hdl_t *, dt_pcb_t *); 957c478bd9Sstevel@tonic-gate extern void dt_pcb_pop(dtrace_hdl_t *, int); 967c478bd9Sstevel@tonic-gate 977c478bd9Sstevel@tonic-gate #ifdef __cplusplus 987c478bd9Sstevel@tonic-gate } 997c478bd9Sstevel@tonic-gate #endif 1007c478bd9Sstevel@tonic-gate 1017c478bd9Sstevel@tonic-gate #endif /* _DT_PCB_H */ 102