xref: /illumos-gate/usr/src/lib/libdisasm/common/dis_riscv.c (revision 38848811)

/*
 * This file and its contents are supplied under the terms of the
 * Common Development and Distribution License ("CDDL"), version 1.0.
 * You may only use this file in accordance with the terms of version
 * 1.0 of the CDDL.
 *
 * A full copy of the text of the CDDL should have accompanied this
 * source.  A copy of the CDDL is also available via the Internet at
 * http://www.illumos.org/license/CDDL.
 */

/*
 * Copyright (c) 2018, Joyent, Inc.
 */

/*
 * RISC-V Instruction set decoder
 */

#include <libdisasm.h>
#include <sys/byteorder.h>
#include <sys/debug.h>

#include "libdisasm_impl.h"

#include <stdio.h>

extern int strcmp(const char *, const char *);

/*
 * Register names based on their ABI name.
 */
static const char *dis_riscv_regs[32] = {
	"x0", "ra", "sp", "gp", "tp", "t0", "t1", "t2",
	"s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5",
	"a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7",
	"s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"
};

static const char *dis_riscv_fpregs[32] = {
	"ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",
	"fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
	"fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
	"fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11",
};

static const char *dis_riscv_c_regs[8] = {
	"s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5"
};

static const char *dis_riscv_c_fpregs[8] = {
	"fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5"
};

/*
 * RM names have the leading comma in them because the last value represents
 * that the hardware register decides the rounding mode and therefore nothing
 * should be appended to the instruction.
 */
static const char *dis_riscv_rm[8] = {
	",rne", ",rtz", ",rdn", ",rup", ",rmm", ",???", ",???", ""
};

typedef struct dis_riscv_csr {
	uint_t		drc_val;
	const char	*drc_name;
} dis_riscv_csr_t;

/*
 * The current set of CSR names as per Table 2.2-2.5 from RISC-V Privileged
 * Architectures V1.10. These include all of the ones in the User-Level ISA.
 * These are ordered per the doc.
 */
static dis_riscv_csr_t dis_riscv_csr_map[] = {
	/* User Trap */
	{ 0x000, "ustatus" },	{ 0x004, "uie" },	{ 0x005, "utvec" },
	/* User Trap Handling */
	{ 0x040, "uscratch" },	{ 0x041, "uepc" },	{ 0x042, "ucause" },
	{ 0x043, "utval" },	{ 0x044, "uip" },
	/* User Floating-Point CSRs */
	{ 0x001, "fflags" },	{ 0x002, "frm" },	{ 0x003, "fcsr" },
	/* User Counters/Timers */
	{ 0xc00, "cycle" },	{ 0xc01, "time" },	{ 0xc02, "instret" },
	{ 0xc03, "hpmcounter3" },	{ 0xc04, "hpmcounter4" },
	{ 0xc05, "hpmcounter5" },	{ 0xc06, "hpmcounter6" },
	{ 0xc07, "hpmcounter7" },	{ 0xc08, "hpmcounter8" },
	{ 0xc09, "hpmcounter9" },	{ 0xc0a, "hpmcounter10" },
	{ 0xc0b, "hpmcounter11" },	{ 0xc0c, "hpmcounter12" },
	{ 0xc0d, "hpmcounter13" },	{ 0xc0e, "hpmcounter14" },
	{ 0xc0f, "hpmcounter15" },	{ 0xc10, "hpmcounter16" },
	{ 0xc11, "hpmcounter17" },	{ 0xc12, "hpmcounter18" },
	{ 0xc13, "hpmcounter19" },	{ 0xc14, "hpmcounter20" },
	{ 0xc15, "hpmcounter21" },	{ 0xc16, "hpmcounter22" },
	{ 0xc17, "hpmcounter23" },	{ 0xc18, "hpmcounter24" },
	{ 0xc19, "hpmcounter25" },	{ 0xc1a, "hpmcounter26" },
	{ 0xc1b, "hpmcounter27" },	{ 0xc1c, "hpmcounter28" },
	{ 0xc1d, "hpmcounter29" },	{ 0xc1e, "hpmcounter30" },
	{ 0xc1f, "hpmcounter31" },
	{ 0xc80, "cycleh" },	{ 0xc81, "timeh" },	{ 0xc82, "instreth" },
	{ 0xc83, "hpmcounter3h" },	{ 0xc84, "hpmcounter4h" },
	{ 0xc85, "hpmcounter5h" },	{ 0xc86, "hpmcounter6h" },
	{ 0xc87, "hpmcounter7h" },	{ 0xc88, "hpmcounter8h" },
	{ 0xc89, "hpmcounter9h" },	{ 0xc8a, "hpmcounter10h" },
	{ 0xc8b, "hpmcounter11h" },	{ 0xc8c, "hpmcounter12h" },
	{ 0xc8d, "hpmcounter13h" },	{ 0xc8e, "hpmcounter14h" },
	{ 0xc8f, "hpmcounter15h" },	{ 0xc90, "hpmcounter16h" },
	{ 0xc91, "hpmcounter17h" },	{ 0xc92, "hpmcounter18h" },
	{ 0xc93, "hpmcounter19h" },	{ 0xc94, "hpmcounter20h" },
	{ 0xc95, "hpmcounter21h" },	{ 0xc96, "hpmcounter22h" },
	{ 0xc97, "hpmcounter23h" },	{ 0xc98, "hpmcounter24h" },
	{ 0xc99, "hpmcounter25h" },	{ 0xc9a, "hpmcounter26h" },
	{ 0xc9b, "hpmcounter27h" },	{ 0xc9c, "hpmcounter28h" },
	{ 0xc9d, "hpmcounter29h" },	{ 0xc9e, "hpmcounter30h" },
	{ 0xc9f, "hpmcounter31h" },
	/* Supervisor Trap Status */
	{ 0x100, "sstatus" },	{ 0x102, "sedeleg" },	{ 0x103, "sideleg" },
	{ 0x104, "sie" },	{ 0x105, "stvec" },	{ 0x106, "scounteren" },
	/* Supervisor Trap Handling */
	{ 0x140, "sscratch" },	{ 0x141, "sepc" },	{ 0x142, "scause" },
	{ 0x143, "stval" },	{ 0x144, "sip" },
	/* Supervisor Protection and Translation */
	{ 0x180, "satp" },
	/* Machine Information Registers */
	{ 0xf11, "mvendorid" },	{ 0xf12, "marchid" },
	{ 0xf13, "mimpid" },	{ 0xf14, "mhartid" },
	/* Machine Trap Setup */
	{ 0x300, "mstatus" },	{ 0x301, "misa" },	{ 0x302, "medeleg" },
	{ 0x303, "mideleg" },	{ 0x304, "mie" },	{ 0x305, "mtvec" },
	{ 0x306, "mcounteren" },
	/* Machine Trap Handling */
	{ 0x340, "mscratch" },	{ 0x341, "mepc" },	{ 0x342, "mcause" },
	{ 0x343, "mtval" },	{ 0x344, "mip" },
	/* Machine Protection and Translation */
	{ 0x3a0, "pmpcfg0" },	{ 0x3a1, "pmpcfg1" },
	{ 0x3a2, "pmpcfg2" },	{ 0x3a3, "pmpcfg3" },
	{ 0x3b0, "pmpaddr0" },	{ 0x3b1, "pmpaddr1" },
	{ 0x3b2, "pmpaddr2" },	{ 0x3b3, "pmpaddr3" },
	{ 0x3b4, "pmpaddr4" },	{ 0x3b5, "pmpaddr5" },
	{ 0x3b6, "pmpaddr6" },	{ 0x3b7, "pmpaddr7" },
	{ 0x3b8, "pmpaddr8" },	{ 0x3b9, "pmpaddr9" },
	{ 0x3ba, "pmpaddr10" },	{ 0x3bb, "pmpaddr11" },
	{ 0x3bc, "pmpaddr12" },	{ 0x3bd, "pmpaddr13" },
	{ 0x3be, "pmpaddr14" },	{ 0x3bf, "pmpaddr15" }
};

typedef enum dis_riscv_csr_alias_type {
	DIS_RISCV_CSR_READ,
	DIS_RISCV_CSR_READ_GEN,
	DIS_RISCV_CSR_SWAP,
	DIS_RISCV_CSR_SWAP_IMM,
	DIS_RISCV_CSR_WRITE,
	DIS_RISCV_CSR_WRITE_GEN,
	DIS_RISCV_CSR_WRITE_IMM,
	DIS_RISCV_CSR_WRITE_IMM_GEN
} dis_riscv_csr_alias_type_t;

typedef struct dis_riscv_csr_alias {
	const char *drca_alias;
	dis_riscv_csr_alias_type_t drca_type;
	const char *drca_base;
	const char *drca_csr;
	int drca_rd;
	int drca_rs;
} dis_riscv_csr_alias_t;

/*
 * Table of aliases. A NULL or -1 indicates a don't care.
 */
static dis_riscv_csr_alias_t dis_riscv_csr_alias[] = {
	{ "rdinstret", DIS_RISCV_CSR_READ, "csrrs", "instret", -1, 0 },
	{ "rdinstreth", DIS_RISCV_CSR_READ, "csrrs", "instreth", -1, 0 },
	{ "rdcycle", DIS_RISCV_CSR_READ, "csrrs", "cycle", -1, 0 },
	{ "rdcycleh", DIS_RISCV_CSR_READ, "csrrs", "cycleh", -1, 0 },
	{ "rdtime", DIS_RISCV_CSR_READ, "csrrs", "time", -1, 0 },
	{ "rdtimeh", DIS_RISCV_CSR_READ, "csrrs", "timeh", -1, 0 },
	{ "frcsr", DIS_RISCV_CSR_READ, "csrrs", "fcsr", -1, 0 },
	{ "fscsr", DIS_RISCV_CSR_WRITE, "csrrw", "fcsr", 0, -1 },
	{ "fscsr", DIS_RISCV_CSR_SWAP, "csrrw", "fcsr", -1, -1 },
	{ "frrm", DIS_RISCV_CSR_READ, "csrrs", "frm", -1, 0 },
	{ "fsrm", DIS_RISCV_CSR_WRITE, "csrrw", "frm", 0, -1 },
	{ "fsrm", DIS_RISCV_CSR_SWAP, "csrrw", "frm", -1, -1 },
	{ "fsrmi", DIS_RISCV_CSR_WRITE_IMM, "csrrwi", "frm", 0, -1 },
	{ "fsrmi", DIS_RISCV_CSR_SWAP_IMM, "csrrwi", "frm", -1, -1 },
	{ "frflags", DIS_RISCV_CSR_READ, "csrrs", "fflags", -1, 0 },
	{ "fsflags", DIS_RISCV_CSR_WRITE, "csrrw", "fflags", 0, -1 },
	{ "fsflags", DIS_RISCV_CSR_SWAP, "csrrw", "fflags", -1, -1 },
	{ "fsflagsi", DIS_RISCV_CSR_WRITE_IMM, "csrrwi", "fflags", 0, -1 },
	{ "fsflagsi", DIS_RISCV_CSR_SWAP_IMM, "csrrwi", "fflags", -1, -1 },
	/*
	 * These are the generic aliases that aren't based on the CSR. Keep
	 * them last.
	 */
	{ "csrr", DIS_RISCV_CSR_READ_GEN, "csrrs", NULL, -1, 0 },
	{ "csrw", DIS_RISCV_CSR_WRITE_GEN, "csrrw", NULL, 0, -1 },
	{ "csrs", DIS_RISCV_CSR_WRITE_GEN, "csrrs", NULL, 0, -1 },
	{ "csrc", DIS_RISCV_CSR_WRITE_GEN, "csrrc", NULL, 0, -1 },
	{ "csrwi", DIS_RISCV_CSR_WRITE_IMM_GEN, "csrrwi", NULL, 0, -1 },
	{ "csrsi", DIS_RISCV_CSR_WRITE_IMM_GEN, "csrrsi", NULL, 0, -1 },
	{ "csrci", DIS_RISCV_CSR_WRITE_IMM_GEN, "csrrci", NULL, 0, -1 },
};

/*
 * Take an n-bit value whose sign bit is indicated by the big sign and convert
 * to a signed type.
 */
static uint_t
dis_riscv_sign_extend(uint_t val, uint_t sbit, const char **sign)
{
	VERIFY3U(sbit, <=, 31);

	if (val >= 1 << sbit) {
		*sign = "-";
		return ((1 << (sbit + 1)) - val);
	} else {
		*sign = "";
		return (val);
	}
}

/*
 * Four byte decode tables. This is derived from the RV32/64G Instruction Set
 * Listings. We describe a table entry based on the opcode and optional opcodes
 * based on the type of instruction that it is and its encoding format. Most
 * sets of instructions have one of several uniform encoding types.
 *
 *  31             25 24     20 19  15 14    12  11        7  6      0
 * |    funct7       |   r2    |  rs1 | funct3 | rd          | opcode | R-type
 * |    imm[11:0]              |  rs1 | funct3 | rd          | opcode | I-type
 * |    imm[11:5]    |   r2    |  rs1 | funct3 | imm[4:0]    | opcode | S-type
 * |    imm[12|10:5] |   r2    |  rs1 | funct3 | imm[4:1|11] | opcode | B-type
 * |    imm[31:12]                             | rd          | opcode | U-type
 * |    imm[10|10:1|11|19:12]                  | rd          | opcode | J-type
 */
typedef enum dis_riscv_itype {
	DIS_RISCV_I_R_TYPE,
	DIS_RISCV_I_I_TYPE,
	DIS_RISCV_I_S_TYPE,
	DIS_RISCV_I_B_TYPE,
	DIS_RISCV_I_U_TYPE,
	DIS_RISCV_I_J_TYPE,
	DIS_RISCV_I_R4_TYPE,
	/*
	 * This is a variant of the standard R type where the first bit of
	 * funct7 is actually used for this shift.
	 */
	DIS_RISCV_I_SHIFT64_TYPE,
	/*
	 * This type isn't explicitly defined in the ISA doc; however, it is a
	 * standard format that is for all of the Atomic class instructions.
	 * This is treated like an R-type, except the funct7 is really a funct5.
	 * The load variant is similar; however, rs2 must be zero.
	 */
	DIS_RISCV_I_RV32A_TYPE,
	DIS_RISCV_I_RV32A_LOAD_TYPE,
	/*
	 * This is a custom type we've defined where the first value is the
	 * instruction mask and the second value is the value of the bits in it.
	 * This is used for a few irregular instructions ala FENCE and ECALL.
	 */
	DIS_RISCV_I_MASK_TYPE,
	/*
	 * This type is used for FP arguments that use rs2 as an opcode.
	 */
	DIS_RISCV_I_FP_RS2OP_TYPE,
	/*
	 * This type uses the opcode and funct7 and uses funct3 as a rounding
	 * mode argument.
	 */
	DIS_RISCV_I_FP_RM_TYPE,
	/*
	 * This fp type uses the opcode, funct7, funct3, and rs2 as an op type.
	 */
	DIS_RISCV_I_FP_R_RS2_TYPE,
} dis_riscv_itype_t;

#define	DIS_RISCV_OPCODE(x)	((x) & 0x7f)
#define	DIS_RISCV_FUNCT3(x)	(((x) >> 12) & 0x7)
#define	DIS_RISCV_FUNCT7(x)	(((x) >> 25) & 0x7f)
#define	DIS_RISCV_RD(x)		(((x) >> 7) & 0x1f)
#define	DIS_RISCV_RS1(x)	(((x) >> 15) & 0x1f)
#define	DIS_RISCV_RS2(x)	(((x) >> 20) & 0x1f)
#define	DIS_RISCV_FP_RS3(x)	(((x) >> 27) & 0x1f)
#define	DIS_RISCV_FUNCT2(x)	(((x) >> 25) & 0x03)

/*
 * SHIFT funct7 variant.
 */
#define	DIS_RISCV_SFUNCT7(x)	(((x) >> 26) & 0x3f)

#define	DIS_RISCV_UIMM(x)	(((x) >> 12) & 0xfffff)

#define	DIS_RISCV_IIMM(x)	(((x) >> 20) & 0xfff)

#define	DIS_RISCV_BIMM_12(x)	(((x) >> 19) & 0x1000)
#define	DIS_RISCV_BIMM_11(x)	(((x) & 0x80) << 4)
#define	DIS_RISCV_BIMM_10_5(x)	(((x) >> 20) & 0x7e0)
#define	DIS_RISCV_BIMM_4_1(x)	(((x) >> 7) & 0x1e)

#define	DIS_RISCV_SIMM_UP(x)	((((x) >> 25) & 0x7f) << 5)
#define	DIS_RISCV_SIMM_LOW(x)	(((x) >> 7) & 0x1f)

#define	DIS_RISCV_JIMM_20(x)	(((x) & 0x80000000) >> 11)
#define	DIS_RISCV_JIMM_19_12(x)	((x) & 0xff000)
#define	DIS_RISCV_JIMM_11(x)	(((x) & 100000) >> 9)
#define	DIS_RISCV_JIMM_10_1(x)	(((x) & 0x7fe00000) >> 20)

#define	DIS_RISCV_RVA_FUNCT5(x)	(((x) >> 27) & 0x1f)
#define	DIS_RISCV_RVA_AQ(x)	(((x) >> 26) & 0x1)
#define	DIS_RISCV_RVA_RL(x)	(((x) >> 25) & 0x1)

struct dis_riscv_instr;
typedef void (*dis_riscv_func_t)(dis_handle_t *, uint32_t,
    struct dis_riscv_instr *, char *, size_t);

typedef struct dis_riscv_instr {
	const char		*drv_name;
	dis_riscv_itype_t	drv_type;
	dis_riscv_func_t	drv_print;
	uint_t			drv_opcode;
	uint_t			drv_funct3;
	uint_t			drv_funct7;
	uint_t			drv_funct2;
} dis_riscv_instr_t;

/*ARGSUSED*/
static void
dis_riscv_rtype_32(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
    char *buf, size_t buflen)
{
	(void) dis_snprintf(buf, buflen, "%s %s,%s,%s", table->drv_name,
	    dis_riscv_regs[DIS_RISCV_RD(instr)],
	    dis_riscv_regs[DIS_RISCV_RS1(instr)],
	    dis_riscv_regs[DIS_RISCV_RS2(instr)]);
}

static void
dis_riscv_itype_32(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
    char *buf, size_t buflen)
{
	const char *s;
	uint_t imm = dis_riscv_sign_extend(DIS_RISCV_IIMM(instr), 11, &s);

	if ((dhp->dh_flags & DIS_OCTAL) != 0) {
		(void) dis_snprintf(buf, buflen, "%s %s,%s,%s0%o",
		    table->drv_name, dis_riscv_regs[DIS_RISCV_RD(instr)],
		    dis_riscv_regs[DIS_RISCV_RS1(instr)], s, imm);
	} else {
		(void) dis_snprintf(buf, buflen, "%s %s,%s,%s0x%x",
		    table->drv_name, dis_riscv_regs[DIS_RISCV_RD(instr)],
		    dis_riscv_regs[DIS_RISCV_RS1(instr)], s, imm);
	}
}

static void
dis_riscv_btype_32(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
    char *buf, size_t buflen)
{
	const char *s;
	uint_t bimm = DIS_RISCV_BIMM_12(instr) | DIS_RISCV_BIMM_11(instr) |
	    DIS_RISCV_BIMM_10_5(instr) | DIS_RISCV_BIMM_4_1(instr);
	uint_t imm = dis_riscv_sign_extend(bimm, 12, &s);

	if ((dhp->dh_flags & DIS_OCTAL) != 0) {
		(void) dis_snprintf(buf, buflen, "%s %s,%s,%s0%o",
		    table->drv_name, dis_riscv_regs[DIS_RISCV_RD(instr)],
		    dis_riscv_regs[DIS_RISCV_RS1(instr)], s, imm);
	} else {
		(void) dis_snprintf(buf, buflen, "%s %s,%s,%s0x%x",
		    table->drv_name, dis_riscv_regs[DIS_RISCV_RD(instr)],
		    dis_riscv_regs[DIS_RISCV_RS1(instr)], s, imm);
	}
}

static void
dis_riscv_load(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
    char *buf, size_t buflen)
{
	const char *s;
	uint_t imm = dis_riscv_sign_extend(DIS_RISCV_IIMM(instr), 11, &s);

	if ((dhp->dh_flags & DIS_OCTAL) != 0) {
		(void) dis_snprintf(buf, buflen, "%s %s,%s0%o(%s)",
		    table->drv_name, dis_riscv_regs[DIS_RISCV_RD(instr)],
		    s, imm, dis_riscv_regs[DIS_RISCV_RS1(instr)]);
	} else {
		(void) dis_snprintf(buf, buflen, "%s %s,%s0x%x(%s)",
		    table->drv_name, dis_riscv_regs[DIS_RISCV_RD(instr)],
		    s, imm, dis_riscv_regs[DIS_RISCV_RS1(instr)]);
	}
}

static void
dis_riscv_stype_32(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
    char *buf, size_t buflen)
{
	const char *s;
	uint_t simm = DIS_RISCV_SIMM_UP(instr) | DIS_RISCV_SIMM_LOW(instr);
	uint_t val = dis_riscv_sign_extend(simm, 11, &s);

	if ((dhp->dh_flags & DIS_OCTAL) != 0) {
		(void) dis_snprintf(buf, buflen, "%s %s,%s0%o(%s)",
		    table->drv_name, dis_riscv_regs[DIS_RISCV_RS2(instr)],
		    s, val, dis_riscv_regs[DIS_RISCV_RS1(instr)]);
	} else {
		(void) dis_snprintf(buf, buflen, "%s %s,%s0x%x(%s)",
		    table->drv_name, dis_riscv_regs[DIS_RISCV_RS2(instr)],
		    s, val, dis_riscv_regs[DIS_RISCV_RS1(instr)]);
	}
}

/*ARGSUSED*/
static void
dis_riscv_utype_32(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
    char *buf, size_t buflen)
{
	(void) dis_snprintf(buf, buflen, "%s %s,0x%x", table->drv_name,
	    dis_riscv_regs[DIS_RISCV_RD(instr)], DIS_RISCV_UIMM(instr));
}

static void
dis_riscv_jtype_32(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
    char *buf, size_t buflen)
{
	const char *s;
	uint_t jimm = DIS_RISCV_JIMM_20(instr) | DIS_RISCV_JIMM_19_12(instr) |
	    DIS_RISCV_JIMM_11(instr) | DIS_RISCV_JIMM_10_1(instr);
	uint_t imm = dis_riscv_sign_extend(jimm, 20, &s);

	if ((dhp->dh_flags & DIS_OCTAL) != 0) {
		(void) dis_snprintf(buf, buflen, "%s %s,%s0%o",
		    table->drv_name, dis_riscv_regs[DIS_RISCV_RD(instr)],
		    s, imm);
	} else {
		(void) dis_snprintf(buf, buflen, "%s %s,%s0x%x",
		    table->drv_name, dis_riscv_regs[DIS_RISCV_RD(instr)],
		    s, imm);
	}
}

/*
 * The shift instructions are a variant on the R-type instructions where RS2 is
 * an immediate to perform the shift by as opposed to a register.
 */
static void
dis_riscv_shift_32(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
    char *buf, size_t buflen)
{
	if ((dhp->dh_flags & DIS_OCTAL) != 0) {
		(void) dis_snprintf(buf, buflen, "%s %s,%s,0%o",
		    table->drv_name, dis_riscv_regs[DIS_RISCV_RD(instr)],
		    dis_riscv_regs[DIS_RISCV_RS1(instr)], DIS_RISCV_RS2(instr));
	} else {
		(void) dis_snprintf(buf, buflen, "%s %s,%s,0x%x",
		    table->drv_name, dis_riscv_regs[DIS_RISCV_RD(instr)],
		    dis_riscv_regs[DIS_RISCV_RS1(instr)], DIS_RISCV_RS2(instr));
	}
}

/*
 * The 64-bit version of shift instructions steals an extra bit from funct7 to
 * construct the shift amount.
 */
static void
dis_riscv_shift_64(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
    char *buf, size_t buflen)
{
	uint_t shift = DIS_RISCV_RS2(instr) | ((instr & (1UL << 25)) >> 20);
	if ((dhp->dh_flags & DIS_OCTAL) != 0) {
		(void) dis_snprintf(buf, buflen, "%s %s,%s,0%o",
		    table->drv_name, dis_riscv_regs[DIS_RISCV_RD(instr)],
		    dis_riscv_regs[DIS_RISCV_RS1(instr)], shift);
	} else {
		(void) dis_snprintf(buf, buflen, "%s %s,%s,0x%x",
		    table->drv_name, dis_riscv_regs[DIS_RISCV_RD(instr)],
		    dis_riscv_regs[DIS_RISCV_RS1(instr)], shift);
	}
}

/*ARGSUSED*/
static void
dis_riscv_csr(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
    char *buf, size_t buflen)
{
	uint_t rd, csr, rs, i;
	const char *csrstr = NULL;
	char csrval[32];
	dis_riscv_csr_alias_t *alias = NULL;

	rd = DIS_RISCV_RD(instr);
	rs = DIS_RISCV_RS1(instr);
	csr = DIS_RISCV_IIMM(instr);

	for (i = 0; i < ARRAY_SIZE(dis_riscv_csr_map); i++) {
		if (csr == dis_riscv_csr_map[i].drc_val) {
			csrstr = dis_riscv_csr_map[i].drc_name;
			break;
		}
	}

	if (csrstr == NULL) {
		(void) dis_snprintf(csrval, sizeof (csrval), "0x%x", csr);
		csrstr = csrval;
	}

	for (i = 0; i < ARRAY_SIZE(dis_riscv_csr_alias); i++) {
		dis_riscv_csr_alias_t *a = &dis_riscv_csr_alias[i];
		if (strcmp(a->drca_base, table->drv_name) != 0)
			continue;
		if (a->drca_csr != NULL && strcmp(a->drca_csr, csrstr) != 0)
			continue;
		if (a->drca_rd != -1 && a->drca_rd != rd)
			continue;
		if (a->drca_rs != -1 && a->drca_rs != rs)
			continue;
		alias = a;
		break;
	}

	if (alias == NULL) {
		(void) dis_snprintf(buf, buflen, "%s %s,%s,%s", table->drv_name,
		    dis_riscv_regs[rd], csrstr, dis_riscv_regs[rs]);
		return;
	}

	switch (alias->drca_type) {
	case DIS_RISCV_CSR_READ:
		(void) dis_snprintf(buf, buflen, "%s %s", alias->drca_alias,
		    dis_riscv_regs[rd]);
		break;
	case DIS_RISCV_CSR_READ_GEN:
		(void) dis_snprintf(buf, buflen, "%s %s,%s", alias->drca_alias,
		    dis_riscv_regs[rd], csrstr);
		break;
	case DIS_RISCV_CSR_SWAP:
		(void) dis_snprintf(buf, buflen, "%s %s,%s", alias->drca_alias,
		    dis_riscv_regs[rd], dis_riscv_regs[rs]);
		break;
	case DIS_RISCV_CSR_WRITE:
		(void) dis_snprintf(buf, buflen, "%s %s", alias->drca_alias,
		    dis_riscv_regs[rs]);
		break;
	case DIS_RISCV_CSR_WRITE_GEN:
		(void) dis_snprintf(buf, buflen, "%s %s,%s", alias->drca_alias,
		    csrstr, dis_riscv_regs[rs]);
		break;
	default:
		(void) dis_snprintf(buf, buflen, "<unknown>");
		break;
	}
}

static void
dis_riscv_csri(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
    char *buf, size_t buflen)
{
	uint_t rd, csr, imm, i;
	const char *csrstr = NULL;
	char csrval[32];
	dis_riscv_csr_alias_t *alias = NULL;

	rd = DIS_RISCV_RD(instr);
	imm = DIS_RISCV_RS1(instr);
	csr = DIS_RISCV_IIMM(instr);

	for (i = 0; i < ARRAY_SIZE(dis_riscv_csr_map); i++) {
		if (csr == dis_riscv_csr_map[i].drc_val) {
			csrstr = dis_riscv_csr_map[i].drc_name;
			break;
		}
	}

	if (csrstr == NULL) {
		(void) dis_snprintf(csrval, sizeof (csrval), "0x%x", csr);
		csrstr = csrval;
	}

	for (i = 0; i < ARRAY_SIZE(dis_riscv_csr_alias); i++) {
		dis_riscv_csr_alias_t *a = &dis_riscv_csr_alias[i];
		if (strcmp(a->drca_base, table->drv_name) != 0)
			continue;
		if (a->drca_csr != NULL && strcmp(a->drca_csr, csrstr) != 0)
			continue;
		if (a->drca_rd != -1 && a->drca_rd != rd)
			continue;
		if (a->drca_rs != -1)
			continue;
		alias = a;
		break;
	}

	if (alias == NULL) {
		if ((dhp->dh_flags & DIS_OCTAL) != 0) {
			(void) dis_snprintf(buf, buflen, "%s %s,%s,0%o",
			    table->drv_name, dis_riscv_regs[rd], csrstr, imm);
		} else {
			(void) dis_snprintf(buf, buflen, "%s %s,%s,0x%x",
			    table->drv_name, dis_riscv_regs[rd], csrstr, imm);
		}
		return;
	}

	switch (alias->drca_type) {
	case DIS_RISCV_CSR_SWAP_IMM:
		if ((dhp->dh_flags & DIS_OCTAL) != 0) {
			(void) dis_snprintf(buf, buflen, "%s %s,0%o",
			    alias->drca_alias, dis_riscv_regs[rd], imm);
		} else {
			(void) dis_snprintf(buf, buflen, "%s %s,0x%x",
			    alias->drca_alias, dis_riscv_regs[rd], imm);
		}
		break;
	case DIS_RISCV_CSR_WRITE_IMM:
		if ((dhp->dh_flags & DIS_OCTAL) != 0) {
			(void) dis_snprintf(buf, buflen, "%s 0%o",
			    alias->drca_alias, imm);
		} else {
			(void) dis_snprintf(buf, buflen, "%s 0x%x",
			    alias->drca_alias, imm);
		}
		break;
	case DIS_RISCV_CSR_WRITE_IMM_GEN:
		if ((dhp->dh_flags & DIS_OCTAL) != 0) {
			(void) dis_snprintf(buf, buflen, "%s %s,0%o",
			    alias->drca_alias, csrstr, imm);
		} else {
			(void) dis_snprintf(buf, buflen, "%s %s,0x%x",
			    alias->drca_alias, csrstr, imm);
		}
		break;
	default:
		(void) dis_snprintf(buf, buflen, "<unknown>");
		break;
	}
}

#define	DIS_RISCV_FENCE_PRED(x)	(((x) >> 24) & 0xf)
#define	DIS_RISCV_FENCE_SUCC(x)	(((x) >> 20) & 0xf)
#define	DIS_RISCV_FENCE_I	0x8
#define	DIS_RISCV_FENCE_O	0x4
#define	DIS_RISCV_FENCE_R	0x2
#define	DIS_RISCV_FENCE_W	0x1
#define	DIS_RISCV_FENCE_IORW	0xf

/*ARGSUSED*/
static void
dis_riscv_fence(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
    char *buf, size_t buflen)
{
	uint_t pred, succ;

	pred = DIS_RISCV_FENCE_PRED(instr);
	succ = DIS_RISCV_FENCE_SUCC(instr);

	/*
	 * If both halves are iorw that is aliased to just an empty fence
	 * instruction per Chapter 20 - RISC-V Assembly Programmer's Handbook in
	 * the RISC-V user spec.
	 */
	if (pred == DIS_RISCV_FENCE_IORW && succ == DIS_RISCV_FENCE_IORW) {
		(void) dis_snprintf(buf, buflen, "%s", table->drv_name);
		return;
	}

	(void) dis_snprintf(buf, buflen, "%s %s%s%s%s, %s%s%s%s",
	    table->drv_name,
	    pred & DIS_RISCV_FENCE_I ? "i" : "",
	    pred & DIS_RISCV_FENCE_O ? "o" : "",
	    pred & DIS_RISCV_FENCE_R ? "r" : "",
	    pred & DIS_RISCV_FENCE_W ? "w" : "",
	    succ & DIS_RISCV_FENCE_I ? "i" : "",
	    succ & DIS_RISCV_FENCE_O ? "o" : "",
	    succ & DIS_RISCV_FENCE_R ? "r" : "",
	    succ & DIS_RISCV_FENCE_W ? "w" : "");
}

/*ARGSUSED*/
static void
dis_riscv_name(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
    char *buf, size_t buflen)
{
	(void) dis_snprintf(buf, buflen, "%s", table->drv_name);
}

/*ARGSUSED*/
static void
dis_riscv_rs1_rs2(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
    char *buf, size_t buflen)
{
	(void) dis_snprintf(buf, buflen, "%s %s,%s", table->drv_name,
	    dis_riscv_regs[DIS_RISCV_RS1(instr)],
	    dis_riscv_regs[DIS_RISCV_RS2(instr)]);
}

/*ARGSUSED*/
static void
dis_riscv_rv32a_load(dis_handle_t *dhp, uint32_t instr,
    dis_riscv_instr_t *table, char *buf, size_t buflen)
{
	const char *suffix = "";

	if (DIS_RISCV_RVA_AQ(instr) && DIS_RISCV_RVA_RL(instr)) {
		suffix = ".aqrl";
	} else if (DIS_RISCV_RVA_AQ(instr)) {
		suffix = ".aq";
	} else if (DIS_RISCV_RVA_RL(instr)) {
		suffix = ".rl";
	}

	(void) dis_snprintf(buf, buflen, "%s%s %s,(%s)", table->drv_name,
	    suffix, dis_riscv_regs[DIS_RISCV_RD(instr)],
	    dis_riscv_regs[DIS_RISCV_RS1(instr)]);
}

/*ARGSUSED*/
static void
dis_riscv_rv32a(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
    char *buf, size_t buflen)
{
	const char *suffix = "";

	if (DIS_RISCV_RVA_AQ(instr) && DIS_RISCV_RVA_RL(instr)) {
		suffix = ".aqrl";
	} else if (DIS_RISCV_RVA_AQ(instr)) {
		suffix = ".aq";
	} else if (DIS_RISCV_RVA_RL(instr)) {
		suffix = ".rl";
	}

	(void) dis_snprintf(buf, buflen, "%s%s %s,%s,(%s)", table->drv_name,
	    suffix, dis_riscv_regs[DIS_RISCV_RD(instr)],
	    dis_riscv_regs[DIS_RISCV_RS2(instr)],
	    dis_riscv_regs[DIS_RISCV_RS1(instr)]);
}

static void
dis_riscv_fp_load(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
    char *buf, size_t buflen)
{
	const char *s;
	uint_t imm = dis_riscv_sign_extend(DIS_RISCV_IIMM(instr), 11, &s);

	if ((dhp->dh_flags & DIS_OCTAL) != 0) {
		(void) dis_snprintf(buf, buflen, "%s %s,%s0%o(%s)",
		    table->drv_name, dis_riscv_fpregs[DIS_RISCV_RD(instr)],
		    s, imm, dis_riscv_regs[DIS_RISCV_RS1(instr)]);
	} else {
		(void) dis_snprintf(buf, buflen, "%s %s,%s0x%x(%s)",
		    table->drv_name, dis_riscv_fpregs[DIS_RISCV_RD(instr)],
		    s, imm, dis_riscv_regs[DIS_RISCV_RS1(instr)]);
	}
}

static void
dis_riscv_fp_store(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
    char *buf, size_t buflen)
{
	const char *s;
	uint_t simm = DIS_RISCV_SIMM_UP(instr) | DIS_RISCV_SIMM_LOW(instr);
	uint_t val = dis_riscv_sign_extend(simm, 11, &s);

	if ((dhp->dh_flags & DIS_OCTAL) != 0) {
		(void) dis_snprintf(buf, buflen, "%s %s,%s0%o(%s)",
		    table->drv_name, dis_riscv_fpregs[DIS_RISCV_RS2(instr)],
		    s, val, dis_riscv_regs[DIS_RISCV_RS1(instr)]);
	} else {
		(void) dis_snprintf(buf, buflen, "%s %s,%s0x%x(%s)",
		    table->drv_name, dis_riscv_fpregs[DIS_RISCV_RS2(instr)],
		    s, val, dis_riscv_regs[DIS_RISCV_RS1(instr)]);
	}
}

/*ARGSUSED*/
static void
dis_riscv_fp_r(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
    char *buf, size_t buflen)
{
	(void) dis_snprintf(buf, buflen, "%s %s,%s,%s", table->drv_name,
	    dis_riscv_fpregs[DIS_RISCV_RD(instr)],
	    dis_riscv_fpregs[DIS_RISCV_RS1(instr)],
	    dis_riscv_fpregs[DIS_RISCV_RS2(instr)]);
}

/*
 * Variant of fp_r type that goes to integer destination registers.
 */
/*ARGSUSED*/
static void
dis_riscv_fp_r_fpi(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
    char *buf, size_t buflen)
{
	(void) dis_snprintf(buf, buflen, "%s %s,%s,%s", table->drv_name,
	    dis_riscv_regs[DIS_RISCV_RD(instr)],
	    dis_riscv_fpregs[DIS_RISCV_RS1(instr)],
	    dis_riscv_fpregs[DIS_RISCV_RS2(instr)]);
}

/*ARGSUSED*/