120c794b3Sgavinm /* 220c794b3Sgavinm * CDDL HEADER START 320c794b3Sgavinm * 420c794b3Sgavinm * The contents of this file are subject to the terms of the 520c794b3Sgavinm * Common Development and Distribution License (the "License"). 620c794b3Sgavinm * You may not use this file except in compliance with the License. 720c794b3Sgavinm * 820c794b3Sgavinm * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 920c794b3Sgavinm * or http://www.opensolaris.org/os/licensing. 1020c794b3Sgavinm * See the License for the specific language governing permissions 1120c794b3Sgavinm * and limitations under the License. 1220c794b3Sgavinm * 1320c794b3Sgavinm * When distributing Covered Code, include this CDDL HEADER in each 1420c794b3Sgavinm * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1520c794b3Sgavinm * If applicable, add the following below this CDDL HEADER, with the 1620c794b3Sgavinm * fields enclosed by brackets "[]" replaced with your own identifying 1720c794b3Sgavinm * information: Portions Copyright [yyyy] [name of copyright owner] 1820c794b3Sgavinm * 1920c794b3Sgavinm * CDDL HEADER END 2020c794b3Sgavinm */ 2120c794b3Sgavinm 2220c794b3Sgavinm /* 232cb5535aSrobj * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 2420c794b3Sgavinm * Use is subject to license terms. 2520c794b3Sgavinm */ 2620c794b3Sgavinm 2720c794b3Sgavinm #pragma ident "%Z%%M% %I% %E% SMI" 2820c794b3Sgavinm 2920c794b3Sgavinm /* 3020c794b3Sgavinm * AMD memory enumeration 3120c794b3Sgavinm */ 3220c794b3Sgavinm 3320c794b3Sgavinm #include <sys/types.h> 3420c794b3Sgavinm #include <unistd.h> 3520c794b3Sgavinm #include <stropts.h> 3620c794b3Sgavinm #include <sys/fm/protocol.h> 3720c794b3Sgavinm #include <sys/mc.h> 3820c794b3Sgavinm #include <sys/mc_amd.h> 3920c794b3Sgavinm #include <fm/topo_mod.h> 4020c794b3Sgavinm #include <strings.h> 4120c794b3Sgavinm #include <sys/stat.h> 4220c794b3Sgavinm #include <fcntl.h> 4320c794b3Sgavinm 4420c794b3Sgavinm #include "chip.h" 4520c794b3Sgavinm 4620c794b3Sgavinm #define MAX_CHANNUM 1 4720c794b3Sgavinm #define MAX_DIMMNUM 7 4820c794b3Sgavinm #define MAX_CSNUM 7 4920c794b3Sgavinm 5020c794b3Sgavinm static const topo_pgroup_info_t cs_pgroup = 5120c794b3Sgavinm { PGNAME(CS), TOPO_STABILITY_PRIVATE, TOPO_STABILITY_PRIVATE, 1 }; 5220c794b3Sgavinm static const topo_pgroup_info_t dimm_pgroup = 5320c794b3Sgavinm { PGNAME(DIMM), TOPO_STABILITY_PRIVATE, TOPO_STABILITY_PRIVATE, 1 }; 5420c794b3Sgavinm static const topo_pgroup_info_t mc_pgroup = 5520c794b3Sgavinm { PGNAME(MCT), TOPO_STABILITY_PRIVATE, TOPO_STABILITY_PRIVATE, 1 }; 5620c794b3Sgavinm static const topo_pgroup_info_t rank_pgroup = 5720c794b3Sgavinm { PGNAME(RANK), TOPO_STABILITY_PRIVATE, TOPO_STABILITY_PRIVATE, 1 }; 5820c794b3Sgavinm static const topo_pgroup_info_t chan_pgroup = 5920c794b3Sgavinm { PGNAME(CHAN), TOPO_STABILITY_PRIVATE, TOPO_STABILITY_PRIVATE, 1 }; 6020c794b3Sgavinm 6120c794b3Sgavinm static const topo_method_t dimm_methods[] = { 6220c794b3Sgavinm { SIMPLE_DIMM_LBL, "Property method", 0, 6320c794b3Sgavinm TOPO_STABILITY_INTERNAL, simple_dimm_label}, 6420c794b3Sgavinm { SIMPLE_DIMM_LBL_MP, "Property method", 0, 6520c794b3Sgavinm TOPO_STABILITY_INTERNAL, simple_dimm_label_mp}, 6620c794b3Sgavinm { SEQ_DIMM_LBL, "Property method", 0, 6720c794b3Sgavinm TOPO_STABILITY_INTERNAL, seq_dimm_label}, 682cb5535aSrobj { G4_DIMM_LBL, "Property method", 0, 692cb5535aSrobj TOPO_STABILITY_INTERNAL, g4_dimm_label}, 70918a0d8aSrobj { G12F_DIMM_LBL, "Property method", 0, 71918a0d8aSrobj TOPO_STABILITY_INTERNAL, g12f_dimm_label}, 722cb5535aSrobj { GET_DIMM_SERIAL, "Property method", 0, 732cb5535aSrobj TOPO_STABILITY_INTERNAL, get_dimm_serial}, 7420c794b3Sgavinm { NULL } 7520c794b3Sgavinm }; 7620c794b3Sgavinm 7720c794b3Sgavinm static const topo_method_t rank_methods[] = { 7820c794b3Sgavinm { TOPO_METH_ASRU_COMPUTE, TOPO_METH_ASRU_COMPUTE_DESC, 7920c794b3Sgavinm TOPO_METH_ASRU_COMPUTE_VERSION, TOPO_STABILITY_INTERNAL, 8020c794b3Sgavinm mem_asru_compute }, 812cb5535aSrobj { TOPO_METH_PRESENT, TOPO_METH_PRESENT_DESC, 822cb5535aSrobj TOPO_METH_PRESENT_VERSION, TOPO_STABILITY_INTERNAL, 832cb5535aSrobj rank_fmri_present }, 84*25c6ff4bSstephh { TOPO_METH_REPLACED, TOPO_METH_REPLACED_DESC, 85*25c6ff4bSstephh TOPO_METH_REPLACED_VERSION, TOPO_STABILITY_INTERNAL, 86*25c6ff4bSstephh rank_fmri_replaced }, 8720c794b3Sgavinm { NULL } 8820c794b3Sgavinm }; 8920c794b3Sgavinm 9020c794b3Sgavinm static const topo_method_t gen_cs_methods[] = { 9120c794b3Sgavinm { TOPO_METH_ASRU_COMPUTE, TOPO_METH_ASRU_COMPUTE_DESC, 9220c794b3Sgavinm TOPO_METH_ASRU_COMPUTE_VERSION, TOPO_STABILITY_INTERNAL, 9320c794b3Sgavinm mem_asru_compute }, 945108f83cSrobj { SIMPLE_CS_LBL_MP, "Property method", 0, 955108f83cSrobj TOPO_STABILITY_INTERNAL, simple_cs_label_mp}, 9620c794b3Sgavinm { NULL } 9720c794b3Sgavinm }; 9820c794b3Sgavinm 9920c794b3Sgavinm static nvlist_t *cs_fmri[MC_CHIP_NCS]; 10020c794b3Sgavinm 10120c794b3Sgavinm /* 10220c794b3Sgavinm * Called when there is no memory-controller driver to provide topology 10320c794b3Sgavinm * information. Generate a maximal memory topology that is appropriate 10420c794b3Sgavinm * for the chip revision. The memory-controller node has already been 10520c794b3Sgavinm * bound as mcnode, and the parent of that is cnode. 10620c794b3Sgavinm * 10720c794b3Sgavinm * We create a tree of dram-channel and chip-select nodes below the 10820c794b3Sgavinm * memory-controller node. There will be two dram channels and 8 chip-selects 10920c794b3Sgavinm * below each, regardless of actual socket type, processor revision and so on. 11020c794b3Sgavinm * This is adequate for generic diagnosis up to family 0x10 revision C. 11120c794b3Sgavinm * When support for revision D is implemented (or maybe C) we should take 11220c794b3Sgavinm * the opportunity to rework the topology tree completely (socket change will 11320c794b3Sgavinm * mean there can be no diagnosis history tied to the topology). 11420c794b3Sgavinm */ 11520c794b3Sgavinm /*ARGSUSED*/ 11620c794b3Sgavinm static int 11720c794b3Sgavinm amd_generic_mc_create(topo_mod_t *mod, tnode_t *cnode, tnode_t *mcnode, 11820c794b3Sgavinm int family, int model, int stepping, nvlist_t *auth) 11920c794b3Sgavinm { 12020c794b3Sgavinm int chan, cs; 12120c794b3Sgavinm 12220c794b3Sgavinm /* 12320c794b3Sgavinm * Elsewhere we have already returned for families less than 0xf. 12420c794b3Sgavinm * This "generic" topology is adequate for all of family 0xf and 12520c794b3Sgavinm * for revisions A, B and C of family 0x10 (A = model 0, B = model 1, 12620c794b3Sgavinm * we'll guess C = model 3 at this point). 12720c794b3Sgavinm */ 12820c794b3Sgavinm if (family > 0x10 || (family == 0x10 && model > 3)) 12920c794b3Sgavinm return (1); 13020c794b3Sgavinm 13120c794b3Sgavinm if (topo_node_range_create(mod, mcnode, CHAN_NODE_NAME, 0, 13220c794b3Sgavinm MAX_CHANNUM) < 0) { 13320c794b3Sgavinm whinge(mod, NULL, "amd_generic_mc_create: range create for " 13420c794b3Sgavinm "channels failed\n"); 13520c794b3Sgavinm return (-1); 13620c794b3Sgavinm } 13720c794b3Sgavinm 13820c794b3Sgavinm for (chan = 0; chan <= MAX_CHANNUM; chan++) { 13920c794b3Sgavinm tnode_t *chnode; 14020c794b3Sgavinm nvlist_t *fmri; 14120c794b3Sgavinm int err; 14220c794b3Sgavinm 14320c794b3Sgavinm if (mkrsrc(mod, mcnode, CHAN_NODE_NAME, chan, auth, 14420c794b3Sgavinm &fmri) != 0) { 14520c794b3Sgavinm whinge(mod, NULL, "amd_generic_mc_create: mkrsrc " 14620c794b3Sgavinm "failed\n"); 14720c794b3Sgavinm return (-1); 14820c794b3Sgavinm } 14920c794b3Sgavinm 15020c794b3Sgavinm if ((chnode = topo_node_bind(mod, mcnode, CHAN_NODE_NAME, 15120c794b3Sgavinm chan, fmri)) == NULL) { 15220c794b3Sgavinm nvlist_free(fmri); 15320c794b3Sgavinm whinge(mod, NULL, "amd_generic_mc_create: node " 15420c794b3Sgavinm "bind failed\n"); 15520c794b3Sgavinm return (-1); 15620c794b3Sgavinm } 15720c794b3Sgavinm 15820c794b3Sgavinm nvlist_free(fmri); 15920c794b3Sgavinm 16020c794b3Sgavinm (void) topo_pgroup_create(chnode, &chan_pgroup, &err); 16120c794b3Sgavinm 16220c794b3Sgavinm (void) topo_prop_set_string(chnode, PGNAME(CHAN), "channel", 16320c794b3Sgavinm TOPO_PROP_IMMUTABLE, chan == 0 ? "A" : "B", &err); 16420c794b3Sgavinm 16520c794b3Sgavinm if (topo_node_range_create(mod, chnode, CS_NODE_NAME, 16620c794b3Sgavinm 0, MAX_CSNUM) < 0) { 16720c794b3Sgavinm whinge(mod, NULL, "amd_generic_mc_create: " 16820c794b3Sgavinm "range create for cs failed\n"); 16920c794b3Sgavinm return (-1); 17020c794b3Sgavinm } 17120c794b3Sgavinm 17220c794b3Sgavinm for (cs = 0; cs <= MAX_CSNUM; cs++) { 17320c794b3Sgavinm tnode_t *csnode; 17420c794b3Sgavinm 17520c794b3Sgavinm if (mkrsrc(mod, chnode, CS_NODE_NAME, cs, auth, 17620c794b3Sgavinm &fmri) != 0) { 17720c794b3Sgavinm whinge(mod, NULL, "amd_generic_mc_create: " 17820c794b3Sgavinm "mkrsrc for cs failed\n"); 17920c794b3Sgavinm return (-1); 18020c794b3Sgavinm } 18120c794b3Sgavinm 18220c794b3Sgavinm if ((csnode = topo_node_bind(mod, chnode, CS_NODE_NAME, 18320c794b3Sgavinm cs, fmri)) == NULL) { 18420c794b3Sgavinm nvlist_free(fmri); 18520c794b3Sgavinm whinge(mod, NULL, "amd_generic_mc_create: " 18620c794b3Sgavinm "bind for cs failed\n"); 18720c794b3Sgavinm return (-1); 18820c794b3Sgavinm } 18920c794b3Sgavinm 19020c794b3Sgavinm /* 19120c794b3Sgavinm * Dynamic ASRU for page faults within a chip-select. 19220c794b3Sgavinm * The topology does not represent pages (there are 19320c794b3Sgavinm * too many) so when a page is faulted we generate 19420c794b3Sgavinm * an ASRU to represent the individual page. 19520c794b3Sgavinm */ 19620c794b3Sgavinm if (topo_method_register(mod, csnode, 19720c794b3Sgavinm gen_cs_methods) < 0) 19820c794b3Sgavinm whinge(mod, NULL, "amd_generic_mc_create: " 19920c794b3Sgavinm "method registration failed\n"); 20020c794b3Sgavinm 20120c794b3Sgavinm (void) topo_node_asru_set(csnode, fmri, 20220c794b3Sgavinm TOPO_ASRU_COMPUTE, &err); 20320c794b3Sgavinm 20420c794b3Sgavinm nvlist_free(fmri); 20520c794b3Sgavinm } 20620c794b3Sgavinm } 20720c794b3Sgavinm 20820c794b3Sgavinm return (0); 20920c794b3Sgavinm } 21020c794b3Sgavinm 21120c794b3Sgavinm static nvlist_t * 21220c794b3Sgavinm amd_lookup_by_mcid(topo_mod_t *mod, topo_instance_t id) 21320c794b3Sgavinm { 21420c794b3Sgavinm mc_snapshot_info_t mcs; 21520c794b3Sgavinm void *buf = NULL; 21620c794b3Sgavinm uint8_t ver; 21720c794b3Sgavinm 21820c794b3Sgavinm nvlist_t *nvl = NULL; 21920c794b3Sgavinm char path[64]; 22020c794b3Sgavinm int fd, err; 22120c794b3Sgavinm 22220c794b3Sgavinm (void) snprintf(path, sizeof (path), "/dev/mc/mc%d", id); 22320c794b3Sgavinm fd = open(path, O_RDONLY); 22420c794b3Sgavinm 22520c794b3Sgavinm if (fd == -1) { 22620c794b3Sgavinm /* 22720c794b3Sgavinm * Some v20z and v40z systems may have had the 3rd-party 22820c794b3Sgavinm * NWSnps packagae installed which installs a /dev/mc 22920c794b3Sgavinm * link. So try again via /devices. 23020c794b3Sgavinm */ 23120c794b3Sgavinm (void) snprintf(path, sizeof (path), 23220c794b3Sgavinm "/devices/pci@0,0/pci1022,1102@%x,2:mc-amd", 23320c794b3Sgavinm MC_AMD_DEV_OFFSET + id); 23420c794b3Sgavinm fd = open(path, O_RDONLY); 23520c794b3Sgavinm } 23620c794b3Sgavinm 23720c794b3Sgavinm if (fd == -1) 23820c794b3Sgavinm return (NULL); /* do not whinge */ 23920c794b3Sgavinm 24020c794b3Sgavinm if (ioctl(fd, MC_IOC_SNAPSHOT_INFO, &mcs) == -1 || 24120c794b3Sgavinm (buf = topo_mod_alloc(mod, mcs.mcs_size)) == NULL || 24220c794b3Sgavinm ioctl(fd, MC_IOC_SNAPSHOT, buf) == -1) { 24320c794b3Sgavinm 24420c794b3Sgavinm whinge(mod, NULL, "mc failed to snapshot %s: %s\n", 24520c794b3Sgavinm path, strerror(errno)); 24620c794b3Sgavinm 24720c794b3Sgavinm free(buf); 24820c794b3Sgavinm (void) close(fd); 24920c794b3Sgavinm return (NULL); 25020c794b3Sgavinm } 25120c794b3Sgavinm 25220c794b3Sgavinm (void) close(fd); 25320c794b3Sgavinm err = nvlist_unpack(buf, mcs.mcs_size, &nvl, 0); 25420c794b3Sgavinm topo_mod_free(mod, buf, mcs.mcs_size); 25520c794b3Sgavinm 25620c794b3Sgavinm 25720c794b3Sgavinm if (nvlist_lookup_uint8(nvl, MC_NVLIST_VERSTR, &ver) != 0) { 25820c794b3Sgavinm whinge(mod, NULL, "mc nvlist is not versioned\n"); 25920c794b3Sgavinm nvlist_free(nvl); 26020c794b3Sgavinm return (NULL); 26120c794b3Sgavinm } else if (ver != MC_NVLIST_VERS1) { 26220c794b3Sgavinm whinge(mod, NULL, "mc nvlist version mismatch\n"); 26320c794b3Sgavinm nvlist_free(nvl); 26420c794b3Sgavinm return (NULL); 26520c794b3Sgavinm } 26620c794b3Sgavinm 26720c794b3Sgavinm return (err ? NULL : nvl); 26820c794b3Sgavinm } 26920c794b3Sgavinm 27020c794b3Sgavinm int 27120c794b3Sgavinm amd_rank_create(topo_mod_t *mod, tnode_t *pnode, nvlist_t *dimmnvl, 27220c794b3Sgavinm nvlist_t *auth) 27320c794b3Sgavinm { 27420c794b3Sgavinm uint64_t *csnumarr; 27520c794b3Sgavinm char **csnamearr; 27620c794b3Sgavinm uint_t ncs, ncsname; 27720c794b3Sgavinm tnode_t *ranknode; 27820c794b3Sgavinm nvlist_t *fmri, *pfmri = NULL; 27920c794b3Sgavinm uint64_t dsz, rsz; 28020c794b3Sgavinm int nerr = 0; 28120c794b3Sgavinm int err; 28220c794b3Sgavinm int i; 28320c794b3Sgavinm 28420c794b3Sgavinm if (nvlist_lookup_uint64_array(dimmnvl, "csnums", &csnumarr, 28520c794b3Sgavinm &ncs) != 0 || nvlist_lookup_string_array(dimmnvl, "csnames", 28620c794b3Sgavinm &csnamearr, &ncsname) != 0 || ncs != ncsname) { 28720c794b3Sgavinm whinge(mod, &nerr, "amd_rank_create: " 28820c794b3Sgavinm "csnums/csnames extraction failed\n"); 28920c794b3Sgavinm return (nerr); 29020c794b3Sgavinm } 29120c794b3Sgavinm 29220c794b3Sgavinm if (topo_node_resource(pnode, &pfmri, &err) < 0) { 29320c794b3Sgavinm whinge(mod, &nerr, "amd_rank_create: parent fmri lookup " 29420c794b3Sgavinm "failed\n"); 29520c794b3Sgavinm return (nerr); 29620c794b3Sgavinm } 29720c794b3Sgavinm 29820c794b3Sgavinm if (topo_node_range_create(mod, pnode, RANK_NODE_NAME, 0, ncs) < 0) { 29920c794b3Sgavinm whinge(mod, &nerr, "amd_rank_create: range create failed\n"); 30020c794b3Sgavinm nvlist_free(pfmri); 30120c794b3Sgavinm return (nerr); 30220c794b3Sgavinm } 30320c794b3Sgavinm 30420c794b3Sgavinm if (topo_prop_get_uint64(pnode, PGNAME(DIMM), "size", &dsz, 30520c794b3Sgavinm &err) == 0) { 30620c794b3Sgavinm rsz = dsz / ncs; 30720c794b3Sgavinm } else { 30820c794b3Sgavinm whinge(mod, &nerr, "amd_rank_create: parent dimm has no " 30920c794b3Sgavinm "size\n"); 31020c794b3Sgavinm return (nerr); 31120c794b3Sgavinm } 31220c794b3Sgavinm 31320c794b3Sgavinm for (i = 0; i < ncs; i++) { 31420c794b3Sgavinm if (mkrsrc(mod, pnode, RANK_NODE_NAME, i, auth, &fmri) < 0) { 31520c794b3Sgavinm whinge(mod, &nerr, "amd_rank_create: mkrsrc failed\n"); 31620c794b3Sgavinm continue; 31720c794b3Sgavinm } 31820c794b3Sgavinm 31920c794b3Sgavinm if ((ranknode = topo_node_bind(mod, pnode, RANK_NODE_NAME, i, 32020c794b3Sgavinm fmri)) == NULL) { 32120c794b3Sgavinm nvlist_free(fmri); 32220c794b3Sgavinm whinge(mod, &nerr, "amd_rank_create: node bind " 32320c794b3Sgavinm "failed\n"); 32420c794b3Sgavinm continue; 32520c794b3Sgavinm } 32620c794b3Sgavinm 32720c794b3Sgavinm nvlist_free(fmri); 32820c794b3Sgavinm 32920c794b3Sgavinm (void) topo_node_fru_set(ranknode, pfmri, 0, &err); 33020c794b3Sgavinm 33120c794b3Sgavinm /* 33220c794b3Sgavinm * If a rank is faulted the asru is the associated 33320c794b3Sgavinm * chip-select, but if a page within a rank is faulted 33420c794b3Sgavinm * the asru is just that page. Hence the dual preconstructed 33520c794b3Sgavinm * and computed ASRU. 33620c794b3Sgavinm */ 33720c794b3Sgavinm if (topo_method_register(mod, ranknode, rank_methods) < 0) 33820c794b3Sgavinm whinge(mod, &nerr, "amd_rank_create: " 33920c794b3Sgavinm "topo_method_register failed"); 34020c794b3Sgavinm 34120c794b3Sgavinm (void) topo_node_asru_set(ranknode, cs_fmri[csnumarr[i]], 34220c794b3Sgavinm TOPO_ASRU_COMPUTE, &err); 34320c794b3Sgavinm 34420c794b3Sgavinm (void) topo_pgroup_create(ranknode, &rank_pgroup, &err); 34520c794b3Sgavinm 34620c794b3Sgavinm (void) topo_prop_set_uint64(ranknode, PGNAME(RANK), "size", 34720c794b3Sgavinm TOPO_PROP_IMMUTABLE, rsz, &err); 34820c794b3Sgavinm 34920c794b3Sgavinm (void) topo_prop_set_string(ranknode, PGNAME(RANK), "csname", 35020c794b3Sgavinm TOPO_PROP_IMMUTABLE, csnamearr[i], &err); 35120c794b3Sgavinm 35220c794b3Sgavinm (void) topo_prop_set_uint64(ranknode, PGNAME(RANK), "csnum", 35320c794b3Sgavinm TOPO_PROP_IMMUTABLE, csnumarr[i], &err); 35420c794b3Sgavinm } 35520c794b3Sgavinm 35620c794b3Sgavinm nvlist_free(pfmri); 35720c794b3Sgavinm 35820c794b3Sgavinm return (nerr); 35920c794b3Sgavinm } 36020c794b3Sgavinm 36120c794b3Sgavinm static int 36220c794b3Sgavinm amd_dimm_create(topo_mod_t *mod, tnode_t *pnode, const char *name, 36320c794b3Sgavinm nvlist_t *mc, nvlist_t *auth) 36420c794b3Sgavinm { 36520c794b3Sgavinm int i, err, nerr = 0; 36620c794b3Sgavinm nvpair_t *nvp; 36720c794b3Sgavinm tnode_t *dimmnode; 36820c794b3Sgavinm nvlist_t *fmri, *asru, **dimmarr = NULL; 36920c794b3Sgavinm uint64_t num; 37020c794b3Sgavinm uint_t ndimm; 37120c794b3Sgavinm 37220c794b3Sgavinm if (nvlist_lookup_nvlist_array(mc, "dimmlist", &dimmarr, &ndimm) != 0) { 37320c794b3Sgavinm whinge(mod, NULL, "amd_dimm_create: dimmlist lookup failed\n"); 37420c794b3Sgavinm return (-1); 37520c794b3Sgavinm } 37620c794b3Sgavinm 37720c794b3Sgavinm if (ndimm == 0) 37820c794b3Sgavinm return (0); /* no dimms present on this node */ 37920c794b3Sgavinm 38020c794b3Sgavinm if (topo_node_range_create(mod, pnode, name, 0, MAX_DIMMNUM) < 0) { 38120c794b3Sgavinm whinge(mod, NULL, "amd_dimm_create: range create failed\n"); 38220c794b3Sgavinm return (-1); 38320c794b3Sgavinm } 38420c794b3Sgavinm 38520c794b3Sgavinm for (i = 0; i < ndimm; i++) { 38620c794b3Sgavinm if (nvlist_lookup_uint64(dimmarr[i], "num", &num) != 0) { 38720c794b3Sgavinm whinge(mod, &nerr, "amd_dimm_create: dimm num property " 38820c794b3Sgavinm "missing\n"); 38920c794b3Sgavinm continue; 39020c794b3Sgavinm } 39120c794b3Sgavinm 39220c794b3Sgavinm if (mkrsrc(mod, pnode, name, num, auth, &fmri) < 0) { 39320c794b3Sgavinm whinge(mod, &nerr, "amd_dimm_create: mkrsrc failed\n"); 39420c794b3Sgavinm continue; 39520c794b3Sgavinm } 39620c794b3Sgavinm 39720c794b3Sgavinm if ((dimmnode = topo_node_bind(mod, pnode, name, num, fmri)) 39820c794b3Sgavinm == NULL) { 39920c794b3Sgavinm nvlist_free(fmri); 40020c794b3Sgavinm whinge(mod, &nerr, "amd_dimm_create: node bind " 40120c794b3Sgavinm "failed\n"); 40220c794b3Sgavinm continue; 40320c794b3Sgavinm } 40420c794b3Sgavinm 40520c794b3Sgavinm if (topo_method_register(mod, dimmnode, dimm_methods) < 0) 4062cb5535aSrobj whinge(mod, &nerr, "amd_dimm_create: " 40720c794b3Sgavinm "topo_method_register failed"); 40820c794b3Sgavinm 40920c794b3Sgavinm /* 41020c794b3Sgavinm * Use the mem computation method directly to publish the asru 41120c794b3Sgavinm * in the "mem" scheme. 41220c794b3Sgavinm */ 41320c794b3Sgavinm if (mem_asru_create(mod, fmri, &asru) == 0) { 41420c794b3Sgavinm (void) topo_node_asru_set(dimmnode, asru, 0, &err); 41520c794b3Sgavinm nvlist_free(asru); 41620c794b3Sgavinm } else { 41720c794b3Sgavinm 41820c794b3Sgavinm nvlist_free(fmri); 41920c794b3Sgavinm whinge(mod, &nerr, "amd_dimm_create: " 42020c794b3Sgavinm "mem_asru_create failed\n"); 42120c794b3Sgavinm continue; 42220c794b3Sgavinm } 42320c794b3Sgavinm 42420c794b3Sgavinm (void) topo_node_fru_set(dimmnode, fmri, 0, &err); 42520c794b3Sgavinm 42620c794b3Sgavinm nvlist_free(fmri); 42720c794b3Sgavinm 42820c794b3Sgavinm (void) topo_pgroup_create(dimmnode, &dimm_pgroup, &err); 42920c794b3Sgavinm 43020c794b3Sgavinm for (nvp = nvlist_next_nvpair(dimmarr[i], NULL); nvp != NULL; 43120c794b3Sgavinm nvp = nvlist_next_nvpair(dimmarr[i], nvp)) { 43220c794b3Sgavinm if (nvpair_type(nvp) == DATA_TYPE_UINT64_ARRAY && 43320c794b3Sgavinm strcmp(nvpair_name(nvp), "csnums") == 0 || 43420c794b3Sgavinm nvpair_type(nvp) == DATA_TYPE_STRING_ARRAY && 43520c794b3Sgavinm strcmp(nvpair_name(nvp), "csnames") == 0) 43620c794b3Sgavinm continue; /* used in amd_rank_create() */ 43720c794b3Sgavinm 43820c794b3Sgavinm nerr += nvprop_add(mod, nvp, PGNAME(DIMM), dimmnode); 43920c794b3Sgavinm } 44020c794b3Sgavinm 44120c794b3Sgavinm nerr += amd_rank_create(mod, dimmnode, dimmarr[i], auth); 44220c794b3Sgavinm } 44320c794b3Sgavinm 44420c794b3Sgavinm return (nerr == 0 ? 0 : -1); 44520c794b3Sgavinm } 44620c794b3Sgavinm 44720c794b3Sgavinm static int 44820c794b3Sgavinm amd_cs_create(topo_mod_t *mod, tnode_t *pnode, const char *name, nvlist_t *mc, 44920c794b3Sgavinm nvlist_t *auth) 45020c794b3Sgavinm { 45120c794b3Sgavinm int i, err, nerr = 0; 45220c794b3Sgavinm nvpair_t *nvp; 45320c794b3Sgavinm tnode_t *csnode; 45420c794b3Sgavinm nvlist_t *fmri, **csarr = NULL; 45520c794b3Sgavinm uint64_t csnum; 45620c794b3Sgavinm uint_t ncs; 45720c794b3Sgavinm 45820c794b3Sgavinm if (nvlist_lookup_nvlist_array(mc, "cslist", &csarr, &ncs) != 0) 45920c794b3Sgavinm return (-1); 46020c794b3Sgavinm 46120c794b3Sgavinm if (ncs == 0) 46220c794b3Sgavinm return (0); /* no chip-selects configured on this node */ 46320c794b3Sgavinm 46420c794b3Sgavinm if (topo_node_range_create(mod, pnode, name, 0, MAX_CSNUM) < 0) 46520c794b3Sgavinm return (-1); 46620c794b3Sgavinm 46720c794b3Sgavinm for (i = 0; i < ncs; i++) { 46820c794b3Sgavinm if (nvlist_lookup_uint64(csarr[i], "num", &csnum) != 0) { 46920c794b3Sgavinm whinge(mod, &nerr, "amd_cs_create: cs num property " 47020c794b3Sgavinm "missing\n"); 47120c794b3Sgavinm continue; 47220c794b3Sgavinm } 47320c794b3Sgavinm 47420c794b3Sgavinm if (mkrsrc(mod, pnode, name, csnum, auth, &fmri) != 0) { 47520c794b3Sgavinm whinge(mod, &nerr, "amd_cs_create: mkrsrc failed\n"); 47620c794b3Sgavinm continue; 47720c794b3Sgavinm } 47820c794b3Sgavinm 47920c794b3Sgavinm if ((csnode = topo_node_bind(mod, pnode, name, csnum, fmri)) 48020c794b3Sgavinm == NULL) { 48120c794b3Sgavinm nvlist_free(fmri); 48220c794b3Sgavinm whinge(mod, &nerr, "amd_cs_create: node bind failed\n"); 48320c794b3Sgavinm continue; 48420c794b3Sgavinm } 48520c794b3Sgavinm 48620c794b3Sgavinm cs_fmri[csnum] = fmri; /* nvlist will be freed in mc_create */ 48720c794b3Sgavinm 48820c794b3Sgavinm (void) topo_node_asru_set(csnode, fmri, 0, &err); 48920c794b3Sgavinm 490b7d3956bSstephh (void) topo_node_fru_set(csnode, fmri, 0, &err); 491b7d3956bSstephh 49220c794b3Sgavinm (void) topo_pgroup_create(csnode, &cs_pgroup, &err); 49320c794b3Sgavinm 49420c794b3Sgavinm for (nvp = nvlist_next_nvpair(csarr[i], NULL); nvp != NULL; 49520c794b3Sgavinm nvp = nvlist_next_nvpair(csarr[i], nvp)) { 49620c794b3Sgavinm nerr += nvprop_add(mod, nvp, PGNAME(CS), csnode); 49720c794b3Sgavinm } 49820c794b3Sgavinm } 49920c794b3Sgavinm 50020c794b3Sgavinm return (nerr == 0 ? 0 : -1); 50120c794b3Sgavinm } 50220c794b3Sgavinm 50320c794b3Sgavinm static int 50420c794b3Sgavinm amd_dramchan_create(topo_mod_t *mod, tnode_t *pnode, const char *name, 50520c794b3Sgavinm nvlist_t *auth) 50620c794b3Sgavinm { 50720c794b3Sgavinm tnode_t *chnode; 50820c794b3Sgavinm nvlist_t *fmri; 50920c794b3Sgavinm char *socket; 51020c794b3Sgavinm int i, nchan; 511b7d3956bSstephh nvlist_t *pfmri = NULL; 51220c794b3Sgavinm int err, nerr = 0; 51320c794b3Sgavinm 51420c794b3Sgavinm /* 51520c794b3Sgavinm * We will enumerate the number of channels present even if only 51620c794b3Sgavinm * channel A is in use (i.e., running in 64-bit mode). Only 51720c794b3Sgavinm * the socket 754 package has a single channel. 51820c794b3Sgavinm */ 51920c794b3Sgavinm if (topo_prop_get_string(pnode, PGNAME(MCT), "socket", 52020c794b3Sgavinm &socket, &err) == 0 && strcmp(socket, "Socket 754") == 0) 52120c794b3Sgavinm nchan = 1; 52220c794b3Sgavinm else 52320c794b3Sgavinm nchan = 2; 52420c794b3Sgavinm 52520c794b3Sgavinm topo_mod_strfree(mod, socket); 52620c794b3Sgavinm 52720c794b3Sgavinm if (topo_node_range_create(mod, pnode, name, 0, nchan - 1) < 0) 52820c794b3Sgavinm return (-1); 52920c794b3Sgavinm 530b7d3956bSstephh (void) topo_node_fru(pnode, &pfmri, NULL, &err); 531b7d3956bSstephh 53220c794b3Sgavinm for (i = 0; i < nchan; i++) { 53320c794b3Sgavinm if (mkrsrc(mod, pnode, name, i, auth, &fmri) != 0) { 53420c794b3Sgavinm whinge(mod, &nerr, "amd_dramchan_create: mkrsrc " 53520c794b3Sgavinm "failed\n"); 53620c794b3Sgavinm continue; 53720c794b3Sgavinm } 53820c794b3Sgavinm 53920c794b3Sgavinm if ((chnode = topo_node_bind(mod, pnode, name, i, fmri)) 54020c794b3Sgavinm == NULL) { 54120c794b3Sgavinm nvlist_free(fmri); 54220c794b3Sgavinm whinge(mod, &nerr, "amd_dramchan_create: node bind " 54320c794b3Sgavinm "failed\n"); 54420c794b3Sgavinm continue; 54520c794b3Sgavinm } 54620c794b3Sgavinm 547b7d3956bSstephh (void) topo_node_asru_set(chnode, fmri, 0, &err); 548b7d3956bSstephh if (pfmri) 549b7d3956bSstephh (void) topo_node_fru_set(chnode, pfmri, 0, &err); 550b7d3956bSstephh 55120c794b3Sgavinm nvlist_free(fmri); 55220c794b3Sgavinm 55320c794b3Sgavinm (void) topo_pgroup_create(chnode, &chan_pgroup, &err); 55420c794b3Sgavinm 55520c794b3Sgavinm (void) topo_prop_set_string(chnode, PGNAME(CHAN), "channel", 55620c794b3Sgavinm TOPO_PROP_IMMUTABLE, i == 0 ? "A" : "B", &err); 55720c794b3Sgavinm } 558b7d3956bSstephh if (pfmri) 559b7d3956bSstephh nvlist_free(pfmri); 56020c794b3Sgavinm 56120c794b3Sgavinm return (nerr == 0 ? 0 : -1); 56220c794b3Sgavinm } 56320c794b3Sgavinm 56420c794b3Sgavinm static int 56520c794b3Sgavinm amd_htconfig(topo_mod_t *mod, tnode_t *cnode, nvlist_t *htnvl) 56620c794b3Sgavinm { 56720c794b3Sgavinm nvpair_t *nvp; 56820c794b3Sgavinm int nerr = 0; 56920c794b3Sgavinm 57020c794b3Sgavinm if (strcmp(topo_node_name(cnode), CHIP_NODE_NAME) != 0) { 57120c794b3Sgavinm whinge(mod, &nerr, "amd_htconfig: must pass a chip node!"); 57220c794b3Sgavinm return (-1); 57320c794b3Sgavinm } 57420c794b3Sgavinm 57520c794b3Sgavinm for (nvp = nvlist_next_nvpair(htnvl, NULL); nvp != NULL; 57620c794b3Sgavinm nvp = nvlist_next_nvpair(htnvl, nvp)) { 57720c794b3Sgavinm if (nvprop_add(mod, nvp, PGNAME(CHIP), cnode) != 0) 57820c794b3Sgavinm nerr++; 57920c794b3Sgavinm } 58020c794b3Sgavinm 58120c794b3Sgavinm return (nerr == 0 ? 0 : -1); 58220c794b3Sgavinm } 58320c794b3Sgavinm 58420c794b3Sgavinm void 58520c794b3Sgavinm amd_mc_create(topo_mod_t *mod, tnode_t *pnode, const char *name, nvlist_t *auth, 58620c794b3Sgavinm int family, int model, int stepping, int *nerrp) 58720c794b3Sgavinm { 58820c794b3Sgavinm tnode_t *mcnode; 58920c794b3Sgavinm nvlist_t *fmri; 59020c794b3Sgavinm nvpair_t *nvp; 59120c794b3Sgavinm nvlist_t *mc = NULL; 59220c794b3Sgavinm int i; 59320c794b3Sgavinm 59420c794b3Sgavinm /* 59520c794b3Sgavinm * Return with no error for anything before AMD family 0xf - we 59620c794b3Sgavinm * won't generate even a generic memory topolofy for earlier 59720c794b3Sgavinm * families. 59820c794b3Sgavinm */ 59920c794b3Sgavinm if (family < 0xf) 60020c794b3Sgavinm return; 60120c794b3Sgavinm 60220c794b3Sgavinm if (mkrsrc(mod, pnode, name, 0, auth, &fmri) != 0) { 60320c794b3Sgavinm whinge(mod, nerrp, "mc_create: mkrsrc failed\n"); 60420c794b3Sgavinm return; 60520c794b3Sgavinm } 60620c794b3Sgavinm 60720c794b3Sgavinm if (topo_node_range_create(mod, pnode, name, 0, 0) < 0) { 60820c794b3Sgavinm nvlist_free(fmri); 60920c794b3Sgavinm whinge(mod, nerrp, "mc_create: node range create failed\n"); 61020c794b3Sgavinm return; 61120c794b3Sgavinm } 61220c794b3Sgavinm 61320c794b3Sgavinm if ((mcnode = topo_node_bind(mod, pnode, name, 0, 61420c794b3Sgavinm fmri)) == NULL) { 61520c794b3Sgavinm nvlist_free(mc); 61620c794b3Sgavinm topo_node_range_destroy(pnode, name); 61720c794b3Sgavinm nvlist_free(fmri); 61820c794b3Sgavinm whinge(mod, nerrp, "mc_create: mc bind failed\n"); 61920c794b3Sgavinm return; 62020c794b3Sgavinm } 62120c794b3Sgavinm (void) topo_node_fru_set(mcnode, NULL, 0, nerrp); 62220c794b3Sgavinm nvlist_free(fmri); 62320c794b3Sgavinm 62420c794b3Sgavinm if ((mc = amd_lookup_by_mcid(mod, topo_node_instance(pnode))) == NULL) { 62520c794b3Sgavinm /* 62620c794b3Sgavinm * If a memory-controller driver exists for this chip model 62720c794b3Sgavinm * it has not attached or has otherwise malfunctioned; 62820c794b3Sgavinm * alternatively no memory-controller driver exists for this 62920c794b3Sgavinm * (presumably newly-released) cpu model. We fallback to 63020c794b3Sgavinm * creating a generic maximal topology. 63120c794b3Sgavinm */ 63220c794b3Sgavinm if (amd_generic_mc_create(mod, pnode, mcnode, 63320c794b3Sgavinm family, model, stepping, auth) != 0) 63420c794b3Sgavinm ++*nerrp; 63520c794b3Sgavinm return; 63620c794b3Sgavinm } 63720c794b3Sgavinm 63820c794b3Sgavinm /* 63920c794b3Sgavinm * Add memory controller properties 64020c794b3Sgavinm */ 64120c794b3Sgavinm (void) topo_pgroup_create(mcnode, &mc_pgroup, nerrp); 64220c794b3Sgavinm 64320c794b3Sgavinm for (nvp = nvlist_next_nvpair(mc, NULL); nvp != NULL; 64420c794b3Sgavinm nvp = nvlist_next_nvpair(mc, nvp)) { 64520c794b3Sgavinm char *name = nvpair_name(nvp); 64620c794b3Sgavinm data_type_t type = nvpair_type(nvp); 64720c794b3Sgavinm 64820c794b3Sgavinm if (type == DATA_TYPE_NVLIST_ARRAY && 64920c794b3Sgavinm (strcmp(name, "cslist") == 0 || 65020c794b3Sgavinm strcmp(name, "dimmlist") == 0)) { 65120c794b3Sgavinm continue; 65220c794b3Sgavinm } else if (type == DATA_TYPE_UINT8 && 65320c794b3Sgavinm strcmp(name, MC_NVLIST_VERSTR) == 0) { 65420c794b3Sgavinm continue; 65520c794b3Sgavinm } else if (type == DATA_TYPE_NVLIST && 65620c794b3Sgavinm strcmp(name, "htconfig") == 0) { 65720c794b3Sgavinm nvlist_t *htnvl; 65820c794b3Sgavinm 65920c794b3Sgavinm (void) nvpair_value_nvlist(nvp, &htnvl); 66020c794b3Sgavinm if (amd_htconfig(mod, pnode, htnvl) != 0) 66120c794b3Sgavinm ++*nerrp; 66220c794b3Sgavinm } else { 66320c794b3Sgavinm if (nvprop_add(mod, nvp, PGNAME(MCT), mcnode) != 0) 66420c794b3Sgavinm ++*nerrp; 66520c794b3Sgavinm } 66620c794b3Sgavinm } 66720c794b3Sgavinm 66820c794b3Sgavinm if (amd_dramchan_create(mod, mcnode, CHAN_NODE_NAME, auth) != 0 || 66920c794b3Sgavinm amd_cs_create(mod, mcnode, CS_NODE_NAME, mc, auth) != 0 || 67020c794b3Sgavinm amd_dimm_create(mod, mcnode, DIMM_NODE_NAME, mc, auth) != 0) 67120c794b3Sgavinm ++*nerrp; 67220c794b3Sgavinm 67320c794b3Sgavinm /* 67420c794b3Sgavinm * Free the fmris for the chip-selects allocated in amd_cs_create 67520c794b3Sgavinm */ 67620c794b3Sgavinm for (i = 0; i < MC_CHIP_NCS; i++) { 67720c794b3Sgavinm if (cs_fmri[i] != NULL) { 67820c794b3Sgavinm nvlist_free(cs_fmri[i]); 67920c794b3Sgavinm cs_fmri[i] = NULL; 68020c794b3Sgavinm } 68120c794b3Sgavinm } 68220c794b3Sgavinm 68320c794b3Sgavinm nvlist_free(mc); 68420c794b3Sgavinm } 685