1 /* 2 * GRUB -- GRand Unified Bootloader 3 * Copyright (C) 2006 Free Software Foundation, Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 */ 19 20 /* 21 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 22 * Use is subject to license terms. 23 */ 24 25 #ifndef _SYS_CONTROLREGS_H 26 #define _SYS_CONTROLREGS_H 27 28 #ifdef __cplusplus 29 extern "C" { 30 #endif 31 32 /* 33 * This file describes the x86 architecture control registers which 34 * are part of the privileged architecture. 35 * 36 * Many of these definitions are shared between IA-32-style and 37 * AMD64-style processors. 38 */ 39 40 /* CR0 Register */ 41 42 #define CR0_PG 0x80000000 /* paging enabled */ 43 #define CR0_CD 0x40000000 /* cache disable */ 44 #define CR0_NW 0x20000000 /* not writethrough */ 45 #define CR0_AM 0x00040000 /* alignment mask */ 46 #define CR0_WP 0x00010000 /* write protect */ 47 #define CR0_NE 0x00000020 /* numeric error */ 48 #define CR0_ET 0x00000010 /* extension type */ 49 #define CR0_TS 0x00000008 /* task switch */ 50 #define CR0_EM 0x00000004 /* emulation */ 51 #define CR0_MP 0x00000002 /* monitor coprocessor */ 52 #define CR0_PE 0x00000001 /* protection enabled */ 53 54 /* XX64 eliminate these compatibility defines */ 55 56 #define CR0_CE CR0_CD 57 #define CR0_WT CR0_NW 58 59 #define FMT_CR0 \ 60 "\20\40pg\37cd\36nw\35am\21wp\6ne\5et\4ts\3em\2mp\1pe" 61 62 /* CR3 Register */ 63 64 #define CR3_PCD 0x00000010 /* cache disable */ 65 #define CR3_PWT 0x00000008 /* write through */ 66 67 #define FMT_CR3 "\20\5pcd\4pwt" 68 69 /* CR4 Register */ 70 71 #define CR4_VME 0x0001 /* virtual-8086 mode extensions */ 72 #define CR4_PVI 0x0002 /* protected-mode virtual interrupts */ 73 #define CR4_TSD 0x0004 /* time stamp disable */ 74 #define CR4_DE 0x0008 /* debugging extensions */ 75 #define CR4_PSE 0x0010 /* page size extensions */ 76 #define CR4_PAE 0x0020 /* physical address extension */ 77 #define CR4_MCE 0x0040 /* machine check enable */ 78 #define CR4_PGE 0x0080 /* page global enable */ 79 #define CR4_PCE 0x0100 /* perf-monitoring counter enable */ 80 #define CR4_OSFXSR 0x0200 /* OS fxsave/fxrstor support */ 81 #define CR4_OSXMMEXCPT 0x0400 /* OS unmasked exception support */ 82 83 #define FMT_CR4 \ 84 "\20\13xmme\12fxsr\11pce\10pge\7mce\6pae\5pse\4de\3tsd\2pvi\1vme" 85 86 /* Intel's SYSENTER configuration registers */ 87 88 #define MSR_INTC_SEP_CS 0x174 /* kernel code selector MSR */ 89 #define MSR_INTC_SEP_ESP 0x175 /* kernel esp MSR */ 90 #define MSR_INTC_SEP_EIP 0x176 /* kernel eip MSR */ 91 92 /* AMD's EFER register */ 93 94 #define MSR_AMD_EFER 0xc0000080 /* extended feature enable MSR */ 95 96 #define AMD_EFER_NXE 0x800 /* no-execute enable */ 97 #define AMD_EFER_LMA 0x400 /* long mode active (read-only) */ 98 #define AMD_EFER_LME 0x100 /* long mode enable */ 99 #define AMD_EFER_SCE 0x001 /* system call extensions */ 100 101 #define FMT_AMD_EFER \ 102 "\20\14nxe\13lma\11lme\1sce" 103 104 /* AMD's SYSCFG register */ 105 106 #define MSR_AMD_SYSCFG 0xc0000010 /* system configuration MSR */ 107 108 #define AMD_SYSCFG_TOM2 0x200000 /* MtrrTom2En */ 109 #define AMD_SYSCFG_MVDM 0x100000 /* MtrrVarDramEn */ 110 #define AMD_SYSCFG_MFDM 0x080000 /* MtrrFixDramModEn */ 111 #define AMD_SYSCFG_MFDE 0x040000 /* MtrrFixDramEn */ 112 113 #define FMT_AMD_SYSCFG \ 114 "\20\26tom2\25mvdm\24mfdm\23mfde" 115 116 /* AMD's syscall/sysret MSRs */ 117 118 #define MSR_AMD_STAR 0xc0000081 /* %cs:%ss:%cs:%ss:%eip for syscall */ 119 #define MSR_AMD_LSTAR 0xc0000082 /* target %rip of 64-bit syscall */ 120 #define MSR_AMD_CSTAR 0xc0000083 /* target %rip of 32-bit syscall */ 121 #define MSR_AMD_SFMASK 0xc0000084 /* syscall flag mask */ 122 123 /* AMD's FS.base and GS.base MSRs */ 124 125 #define MSR_AMD_FSBASE 0xc0000100 /* 64-bit base address for %fs */ 126 #define MSR_AMD_GSBASE 0xc0000101 /* 64-bit base address for %gs */ 127 #define MSR_AMD_KGSBASE 0xc0000102 /* swapgs swaps this with gsbase */ 128 129 /* AMD's configuration MSRs, weakly documented in the revision guide */ 130 131 #define MSR_AMD_DC_CFG 0xc0011022 132 133 #define AMD_DC_CFG_DIS_CNV_WC_SSO (UINT64_C(1) << 3) 134 #define AMD_DC_CFG_DIS_SMC_CHK_BUF (UINT64_C(1) << 10) 135 136 /* AMD's HWCR MSR */ 137 138 #define MSR_AMD_HWCR 0xc0010015 139 140 #define AMD_HWCR_FFDIS 0x00040 /* disable TLB Flush Filter */ 141 #define AMD_HWCR_MCI_STATUS_WREN 0x40000 /* enable write of MCi_STATUS */ 142 143 /* AMD's NorthBridge Config MSR, SHOULD ONLY BE WRITTEN TO BY BIOS */ 144 145 #define MSR_AMD_NB_CFG 0xc001001f 146 147 #define MSR_BU_CFG 0xc0011023 148 149 #define AMD_NB_CFG_SRQ_HEARTBEAT (UINT64_C(1) << 20) 150 #define AMD_NB_CFG_SRQ_SPR (UINT64_C(1) << 32) 151 152 /* AMD */ 153 #define MSR_AMD_PATCHLEVEL 0x8b 154 155 #ifdef __cplusplus 156 } 157 #endif 158 159 #endif /* !_SYS_CONTROLREGS_H */ 160