17c478bd9Sstevel@tonic-gate /* $Id: tg3.h,v 1.3 2003/02/25 06:02:58 ebiederm Exp $ 27c478bd9Sstevel@tonic-gate * tg3.h: Definitions for Broadcom Tigon3 ethernet driver. 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) 57c478bd9Sstevel@tonic-gate * Copyright (C) 2001 Jeff Garzik (jgarzik@mandrakesoft.com) 67c478bd9Sstevel@tonic-gate */ 77c478bd9Sstevel@tonic-gate 87c478bd9Sstevel@tonic-gate #ifndef _T3_H 97c478bd9Sstevel@tonic-gate #define _T3_H 107c478bd9Sstevel@tonic-gate 117c478bd9Sstevel@tonic-gate #include "stdint.h" 127c478bd9Sstevel@tonic-gate 137c478bd9Sstevel@tonic-gate typedef unsigned long dma_addr_t; 147c478bd9Sstevel@tonic-gate 157c478bd9Sstevel@tonic-gate /* From mii.h */ 167c478bd9Sstevel@tonic-gate 177c478bd9Sstevel@tonic-gate /* Indicates what features are advertised by the interface. */ 187c478bd9Sstevel@tonic-gate #define ADVERTISED_10baseT_Half (1 << 0) 197c478bd9Sstevel@tonic-gate #define ADVERTISED_10baseT_Full (1 << 1) 207c478bd9Sstevel@tonic-gate #define ADVERTISED_100baseT_Half (1 << 2) 217c478bd9Sstevel@tonic-gate #define ADVERTISED_100baseT_Full (1 << 3) 227c478bd9Sstevel@tonic-gate #define ADVERTISED_1000baseT_Half (1 << 4) 237c478bd9Sstevel@tonic-gate #define ADVERTISED_1000baseT_Full (1 << 5) 247c478bd9Sstevel@tonic-gate #define ADVERTISED_Autoneg (1 << 6) 257c478bd9Sstevel@tonic-gate #define ADVERTISED_TP (1 << 7) 267c478bd9Sstevel@tonic-gate #define ADVERTISED_AUI (1 << 8) 277c478bd9Sstevel@tonic-gate #define ADVERTISED_MII (1 << 9) 287c478bd9Sstevel@tonic-gate #define ADVERTISED_FIBRE (1 << 10) 297c478bd9Sstevel@tonic-gate #define ADVERTISED_BNC (1 << 11) 307c478bd9Sstevel@tonic-gate 317c478bd9Sstevel@tonic-gate /* The following are all involved in forcing a particular link 327c478bd9Sstevel@tonic-gate * mode for the device for setting things. When getting the 337c478bd9Sstevel@tonic-gate * devices settings, these indicate the current mode and whether 347c478bd9Sstevel@tonic-gate * it was foced up into this mode or autonegotiated. 357c478bd9Sstevel@tonic-gate */ 367c478bd9Sstevel@tonic-gate 377c478bd9Sstevel@tonic-gate /* The forced speed, 10Mb, 100Mb, gigabit. */ 387c478bd9Sstevel@tonic-gate #define SPEED_10 0 397c478bd9Sstevel@tonic-gate #define SPEED_100 1 407c478bd9Sstevel@tonic-gate #define SPEED_1000 2 417c478bd9Sstevel@tonic-gate #define SPEED_INVALID 3 427c478bd9Sstevel@tonic-gate 437c478bd9Sstevel@tonic-gate 447c478bd9Sstevel@tonic-gate /* Duplex, half or full. */ 457c478bd9Sstevel@tonic-gate #define DUPLEX_HALF 0x00 467c478bd9Sstevel@tonic-gate #define DUPLEX_FULL 0x01 477c478bd9Sstevel@tonic-gate #define DUPLEX_INVALID 0x02 487c478bd9Sstevel@tonic-gate 497c478bd9Sstevel@tonic-gate /* Which connector port. */ 507c478bd9Sstevel@tonic-gate #define PORT_TP 0x00 517c478bd9Sstevel@tonic-gate #define PORT_AUI 0x01 527c478bd9Sstevel@tonic-gate #define PORT_MII 0x02 537c478bd9Sstevel@tonic-gate #define PORT_FIBRE 0x03 547c478bd9Sstevel@tonic-gate #define PORT_BNC 0x04 557c478bd9Sstevel@tonic-gate 567c478bd9Sstevel@tonic-gate /* Which tranceiver to use. */ 577c478bd9Sstevel@tonic-gate #define XCVR_INTERNAL 0x00 587c478bd9Sstevel@tonic-gate #define XCVR_EXTERNAL 0x01 597c478bd9Sstevel@tonic-gate #define XCVR_DUMMY1 0x02 607c478bd9Sstevel@tonic-gate #define XCVR_DUMMY2 0x03 617c478bd9Sstevel@tonic-gate #define XCVR_DUMMY3 0x04 627c478bd9Sstevel@tonic-gate 637c478bd9Sstevel@tonic-gate /* Enable or disable autonegotiation. If this is set to enable, 647c478bd9Sstevel@tonic-gate * the forced link modes above are completely ignored. 657c478bd9Sstevel@tonic-gate */ 667c478bd9Sstevel@tonic-gate #define AUTONEG_DISABLE 0x00 677c478bd9Sstevel@tonic-gate #define AUTONEG_ENABLE 0x01 687c478bd9Sstevel@tonic-gate 697c478bd9Sstevel@tonic-gate /* Wake-On-Lan options. */ 707c478bd9Sstevel@tonic-gate #define WAKE_PHY (1 << 0) 717c478bd9Sstevel@tonic-gate #define WAKE_UCAST (1 << 1) 727c478bd9Sstevel@tonic-gate #define WAKE_MCAST (1 << 2) 737c478bd9Sstevel@tonic-gate #define WAKE_BCAST (1 << 3) 747c478bd9Sstevel@tonic-gate #define WAKE_ARP (1 << 4) 757c478bd9Sstevel@tonic-gate #define WAKE_MAGIC (1 << 5) 767c478bd9Sstevel@tonic-gate #define WAKE_MAGICSECURE (1 << 6) /* only meaningful if WAKE_MAGIC */ 777c478bd9Sstevel@tonic-gate 787c478bd9Sstevel@tonic-gate /* Generic MII registers. */ 797c478bd9Sstevel@tonic-gate 807c478bd9Sstevel@tonic-gate #define MII_BMCR 0x00 /* Basic mode control register */ 817c478bd9Sstevel@tonic-gate #define MII_BMSR 0x01 /* Basic mode status register */ 827c478bd9Sstevel@tonic-gate #define MII_PHYSID1 0x02 /* PHYS ID 1 */ 837c478bd9Sstevel@tonic-gate #define MII_PHYSID2 0x03 /* PHYS ID 2 */ 847c478bd9Sstevel@tonic-gate #define MII_ADVERTISE 0x04 /* Advertisement control reg */ 857c478bd9Sstevel@tonic-gate #define MII_LPA 0x05 /* Link partner ability reg */ 867c478bd9Sstevel@tonic-gate #define MII_EXPANSION 0x06 /* Expansion register */ 877c478bd9Sstevel@tonic-gate #define MII_DCOUNTER 0x12 /* Disconnect counter */ 887c478bd9Sstevel@tonic-gate #define MII_FCSCOUNTER 0x13 /* False carrier counter */ 897c478bd9Sstevel@tonic-gate #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ 907c478bd9Sstevel@tonic-gate #define MII_RERRCOUNTER 0x15 /* Receive error counter */ 917c478bd9Sstevel@tonic-gate #define MII_SREVISION 0x16 /* Silicon revision */ 927c478bd9Sstevel@tonic-gate #define MII_RESV1 0x17 /* Reserved... */ 937c478bd9Sstevel@tonic-gate #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ 947c478bd9Sstevel@tonic-gate #define MII_PHYADDR 0x19 /* PHY address */ 957c478bd9Sstevel@tonic-gate #define MII_RESV2 0x1a /* Reserved... */ 967c478bd9Sstevel@tonic-gate #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ 977c478bd9Sstevel@tonic-gate #define MII_NCONFIG 0x1c /* Network interface config */ 987c478bd9Sstevel@tonic-gate 997c478bd9Sstevel@tonic-gate /* Basic mode control register. */ 1007c478bd9Sstevel@tonic-gate #define BMCR_RESV 0x007f /* Unused... */ 1017c478bd9Sstevel@tonic-gate #define BMCR_CTST 0x0080 /* Collision test */ 1027c478bd9Sstevel@tonic-gate #define BMCR_FULLDPLX 0x0100 /* Full duplex */ 1037c478bd9Sstevel@tonic-gate #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ 1047c478bd9Sstevel@tonic-gate #define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ 1057c478bd9Sstevel@tonic-gate #define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ 1067c478bd9Sstevel@tonic-gate #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ 1077c478bd9Sstevel@tonic-gate #define BMCR_SPEED100 0x2000 /* Select 100Mbps */ 1087c478bd9Sstevel@tonic-gate #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ 1097c478bd9Sstevel@tonic-gate #define BMCR_RESET 0x8000 /* Reset the DP83840 */ 1107c478bd9Sstevel@tonic-gate 1117c478bd9Sstevel@tonic-gate /* Basic mode status register. */ 1127c478bd9Sstevel@tonic-gate #define BMSR_ERCAP 0x0001 /* Ext-reg capability */ 1137c478bd9Sstevel@tonic-gate #define BMSR_JCD 0x0002 /* Jabber detected */ 1147c478bd9Sstevel@tonic-gate #define BMSR_LSTATUS 0x0004 /* Link status */ 1157c478bd9Sstevel@tonic-gate #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ 1167c478bd9Sstevel@tonic-gate #define BMSR_RFAULT 0x0010 /* Remote fault detected */ 1177c478bd9Sstevel@tonic-gate #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ 1187c478bd9Sstevel@tonic-gate #define BMSR_RESV 0x07c0 /* Unused... */ 1197c478bd9Sstevel@tonic-gate #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ 1207c478bd9Sstevel@tonic-gate #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ 1217c478bd9Sstevel@tonic-gate #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ 1227c478bd9Sstevel@tonic-gate #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ 1237c478bd9Sstevel@tonic-gate #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ 1247c478bd9Sstevel@tonic-gate 1257c478bd9Sstevel@tonic-gate /* Advertisement control register. */ 1267c478bd9Sstevel@tonic-gate #define ADVERTISE_SLCT 0x001f /* Selector bits */ 1277c478bd9Sstevel@tonic-gate #define ADVERTISE_CSMA 0x0001 /* Only selector supported */ 1287c478bd9Sstevel@tonic-gate #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ 1297c478bd9Sstevel@tonic-gate #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ 1307c478bd9Sstevel@tonic-gate #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ 1317c478bd9Sstevel@tonic-gate #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ 1327c478bd9Sstevel@tonic-gate #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ 1337c478bd9Sstevel@tonic-gate #define ADVERTISE_RESV 0x1c00 /* Unused... */ 1347c478bd9Sstevel@tonic-gate #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ 1357c478bd9Sstevel@tonic-gate #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ 1367c478bd9Sstevel@tonic-gate #define ADVERTISE_NPAGE 0x8000 /* Next page bit */ 1377c478bd9Sstevel@tonic-gate 1387c478bd9Sstevel@tonic-gate #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ 1397c478bd9Sstevel@tonic-gate ADVERTISE_CSMA) 1407c478bd9Sstevel@tonic-gate #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ 1417c478bd9Sstevel@tonic-gate ADVERTISE_100HALF | ADVERTISE_100FULL) 1427c478bd9Sstevel@tonic-gate 1437c478bd9Sstevel@tonic-gate /* Link partner ability register. */ 1447c478bd9Sstevel@tonic-gate #define LPA_SLCT 0x001f /* Same as advertise selector */ 1457c478bd9Sstevel@tonic-gate #define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ 1467c478bd9Sstevel@tonic-gate #define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ 1477c478bd9Sstevel@tonic-gate #define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ 1487c478bd9Sstevel@tonic-gate #define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ 1497c478bd9Sstevel@tonic-gate #define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ 1507c478bd9Sstevel@tonic-gate #define LPA_RESV 0x1c00 /* Unused... */ 1517c478bd9Sstevel@tonic-gate #define LPA_RFAULT 0x2000 /* Link partner faulted */ 1527c478bd9Sstevel@tonic-gate #define LPA_LPACK 0x4000 /* Link partner acked us */ 1537c478bd9Sstevel@tonic-gate #define LPA_NPAGE 0x8000 /* Next page bit */ 1547c478bd9Sstevel@tonic-gate 1557c478bd9Sstevel@tonic-gate #define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) 1567c478bd9Sstevel@tonic-gate #define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) 1577c478bd9Sstevel@tonic-gate 1587c478bd9Sstevel@tonic-gate /* Expansion register for auto-negotiation. */ 1597c478bd9Sstevel@tonic-gate #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ 1607c478bd9Sstevel@tonic-gate #define EXPANSION_LCWP 0x0002 /* Got new RX page code word */ 1617c478bd9Sstevel@tonic-gate #define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */ 1627c478bd9Sstevel@tonic-gate #define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */ 1637c478bd9Sstevel@tonic-gate #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ 1647c478bd9Sstevel@tonic-gate #define EXPANSION_RESV 0xffe0 /* Unused... */ 1657c478bd9Sstevel@tonic-gate 1667c478bd9Sstevel@tonic-gate /* N-way test register. */ 1677c478bd9Sstevel@tonic-gate #define NWAYTEST_RESV1 0x00ff /* Unused... */ 1687c478bd9Sstevel@tonic-gate #define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */ 1697c478bd9Sstevel@tonic-gate #define NWAYTEST_RESV2 0xfe00 /* Unused... */ 1707c478bd9Sstevel@tonic-gate 1717c478bd9Sstevel@tonic-gate 1727c478bd9Sstevel@tonic-gate /* From tg3.h */ 1737c478bd9Sstevel@tonic-gate 1747c478bd9Sstevel@tonic-gate #define TG3_64BIT_REG_HIGH 0x00UL 1757c478bd9Sstevel@tonic-gate #define TG3_64BIT_REG_LOW 0x04UL 1767c478bd9Sstevel@tonic-gate 1777c478bd9Sstevel@tonic-gate /* Descriptor block info. */ 1787c478bd9Sstevel@tonic-gate #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */ 1797c478bd9Sstevel@tonic-gate #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */ 1807c478bd9Sstevel@tonic-gate #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */ 1817c478bd9Sstevel@tonic-gate #define BDINFO_FLAGS_DISABLED 0x00000002 1827c478bd9Sstevel@tonic-gate #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000 1837c478bd9Sstevel@tonic-gate #define BDINFO_FLAGS_MAXLEN_SHIFT 16 1847c478bd9Sstevel@tonic-gate #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */ 1857c478bd9Sstevel@tonic-gate #define TG3_BDINFO_SIZE 0x10UL 1867c478bd9Sstevel@tonic-gate 1877c478bd9Sstevel@tonic-gate #define RX_COPY_THRESHOLD 256 1887c478bd9Sstevel@tonic-gate 1897c478bd9Sstevel@tonic-gate #define RX_STD_MAX_SIZE 1536 1907c478bd9Sstevel@tonic-gate #define RX_STD_MAX_SIZE_5705 512 1917c478bd9Sstevel@tonic-gate #define RX_JUMBO_MAX_SIZE 0xdeadbeef /* XXX */ 1927c478bd9Sstevel@tonic-gate 1937c478bd9Sstevel@tonic-gate /* First 256 bytes are a mirror of PCI config space. */ 1947c478bd9Sstevel@tonic-gate #define TG3PCI_VENDOR 0x00000000 1957c478bd9Sstevel@tonic-gate #define TG3PCI_VENDOR_BROADCOM 0x14e4 1967c478bd9Sstevel@tonic-gate #define TG3PCI_DEVICE 0x00000002 1977c478bd9Sstevel@tonic-gate #define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */ 1987c478bd9Sstevel@tonic-gate #define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */ 1997c478bd9Sstevel@tonic-gate #define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */ 2007c478bd9Sstevel@tonic-gate #define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */ 2017c478bd9Sstevel@tonic-gate #define TG3PCI_COMMAND 0x00000004 2027c478bd9Sstevel@tonic-gate #define TG3PCI_STATUS 0x00000006 2037c478bd9Sstevel@tonic-gate #define TG3PCI_CCREVID 0x00000008 2047c478bd9Sstevel@tonic-gate #define TG3PCI_CACHELINESZ 0x0000000c 2057c478bd9Sstevel@tonic-gate #define TG3PCI_LATTIMER 0x0000000d 2067c478bd9Sstevel@tonic-gate #define TG3PCI_HEADERTYPE 0x0000000e 2077c478bd9Sstevel@tonic-gate #define TG3PCI_BIST 0x0000000f 2087c478bd9Sstevel@tonic-gate #define TG3PCI_BASE0_LOW 0x00000010 2097c478bd9Sstevel@tonic-gate #define TG3PCI_BASE0_HIGH 0x00000014 2107c478bd9Sstevel@tonic-gate /* 0x18 --> 0x2c unused */ 2117c478bd9Sstevel@tonic-gate #define TG3PCI_SUBSYSVENID 0x0000002c 2127c478bd9Sstevel@tonic-gate #define TG3PCI_SUBSYSID 0x0000002e 2137c478bd9Sstevel@tonic-gate #define TG3PCI_ROMADDR 0x00000030 2147c478bd9Sstevel@tonic-gate #define TG3PCI_CAPLIST 0x00000034 2157c478bd9Sstevel@tonic-gate /* 0x35 --> 0x3c unused */ 2167c478bd9Sstevel@tonic-gate #define TG3PCI_IRQ_LINE 0x0000003c 2177c478bd9Sstevel@tonic-gate #define TG3PCI_IRQ_PIN 0x0000003d 2187c478bd9Sstevel@tonic-gate #define TG3PCI_MIN_GNT 0x0000003e 2197c478bd9Sstevel@tonic-gate #define TG3PCI_MAX_LAT 0x0000003f 2207c478bd9Sstevel@tonic-gate #define TG3PCI_X_CAPS 0x00000040 2217c478bd9Sstevel@tonic-gate #define PCIX_CAPS_RELAXED_ORDERING 0x00020000 2227c478bd9Sstevel@tonic-gate #define PCIX_CAPS_SPLIT_MASK 0x00700000 2237c478bd9Sstevel@tonic-gate #define PCIX_CAPS_SPLIT_SHIFT 20 2247c478bd9Sstevel@tonic-gate #define PCIX_CAPS_BURST_MASK 0x000c0000 2257c478bd9Sstevel@tonic-gate #define PCIX_CAPS_BURST_SHIFT 18 2267c478bd9Sstevel@tonic-gate #define PCIX_CAPS_MAX_BURST_CPIOB 2 2277c478bd9Sstevel@tonic-gate #define TG3PCI_PM_CAP_PTR 0x00000041 2287c478bd9Sstevel@tonic-gate #define TG3PCI_X_COMMAND 0x00000042 2297c478bd9Sstevel@tonic-gate #define TG3PCI_X_STATUS 0x00000044 2307c478bd9Sstevel@tonic-gate #define TG3PCI_PM_CAP_ID 0x00000048 2317c478bd9Sstevel@tonic-gate #define TG3PCI_VPD_CAP_PTR 0x00000049 2327c478bd9Sstevel@tonic-gate #define TG3PCI_PM_CAPS 0x0000004a 2337c478bd9Sstevel@tonic-gate #define TG3PCI_PM_CTRL_STAT 0x0000004c 2347c478bd9Sstevel@tonic-gate #define TG3PCI_BR_SUPP_EXT 0x0000004e 2357c478bd9Sstevel@tonic-gate #define TG3PCI_PM_DATA 0x0000004f 2367c478bd9Sstevel@tonic-gate #define TG3PCI_VPD_CAP_ID 0x00000050 2377c478bd9Sstevel@tonic-gate #define TG3PCI_MSI_CAP_PTR 0x00000051 2387c478bd9Sstevel@tonic-gate #define TG3PCI_VPD_ADDR_FLAG 0x00000052 2397c478bd9Sstevel@tonic-gate #define VPD_ADDR_FLAG_WRITE 0x00008000 2407c478bd9Sstevel@tonic-gate #define TG3PCI_VPD_DATA 0x00000054 2417c478bd9Sstevel@tonic-gate #define TG3PCI_MSI_CAP_ID 0x00000058 2427c478bd9Sstevel@tonic-gate #define TG3PCI_NXT_CAP_PTR 0x00000059 2437c478bd9Sstevel@tonic-gate #define TG3PCI_MSI_CTRL 0x0000005a 2447c478bd9Sstevel@tonic-gate #define TG3PCI_MSI_ADDR_LOW 0x0000005c 2457c478bd9Sstevel@tonic-gate #define TG3PCI_MSI_ADDR_HIGH 0x00000060 2467c478bd9Sstevel@tonic-gate #define TG3PCI_MSI_DATA 0x00000064 2477c478bd9Sstevel@tonic-gate /* 0x66 --> 0x68 unused */ 2487c478bd9Sstevel@tonic-gate #define TG3PCI_MISC_HOST_CTRL 0x00000068 2497c478bd9Sstevel@tonic-gate #define MISC_HOST_CTRL_CLEAR_INT 0x00000001 2507c478bd9Sstevel@tonic-gate #define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002 2517c478bd9Sstevel@tonic-gate #define MISC_HOST_CTRL_BYTE_SWAP 0x00000004 2527c478bd9Sstevel@tonic-gate #define MISC_HOST_CTRL_WORD_SWAP 0x00000008 2537c478bd9Sstevel@tonic-gate #define MISC_HOST_CTRL_PCISTATE_RW 0x00000010 2547c478bd9Sstevel@tonic-gate #define MISC_HOST_CTRL_CLKREG_RW 0x00000020 2557c478bd9Sstevel@tonic-gate #define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040 2567c478bd9Sstevel@tonic-gate #define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080 2577c478bd9Sstevel@tonic-gate #define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100 2587c478bd9Sstevel@tonic-gate #define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200 2597c478bd9Sstevel@tonic-gate #define MISC_HOST_CTRL_CHIPREV 0xffff0000 2607c478bd9Sstevel@tonic-gate #define MISC_HOST_CTRL_CHIPREV_SHIFT 16 2617c478bd9Sstevel@tonic-gate #define GET_CHIP_REV_ID(MISC_HOST_CTRL) \ 2627c478bd9Sstevel@tonic-gate (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \ 2637c478bd9Sstevel@tonic-gate MISC_HOST_CTRL_CHIPREV_SHIFT) 2647c478bd9Sstevel@tonic-gate #define CHIPREV_ID_5700_A0 0x7000 2657c478bd9Sstevel@tonic-gate #define CHIPREV_ID_5700_A1 0x7001 2667c478bd9Sstevel@tonic-gate #define CHIPREV_ID_5700_B0 0x7100 2677c478bd9Sstevel@tonic-gate #define CHIPREV_ID_5700_B1 0x7101 2687c478bd9Sstevel@tonic-gate #define CHIPREV_ID_5700_B3 0x7102 2697c478bd9Sstevel@tonic-gate #define CHIPREV_ID_5700_ALTIMA 0x7104 2707c478bd9Sstevel@tonic-gate #define CHIPREV_ID_5700_C0 0x7200 2717c478bd9Sstevel@tonic-gate #define CHIPREV_ID_5701_A0 0x0000 2727c478bd9Sstevel@tonic-gate #define CHIPREV_ID_5701_B0 0x0100 2737c478bd9Sstevel@tonic-gate #define CHIPREV_ID_5701_B2 0x0102 2747c478bd9Sstevel@tonic-gate #define CHIPREV_ID_5701_B5 0x0105 2757c478bd9Sstevel@tonic-gate #define CHIPREV_ID_5703_A0 0x1000 2767c478bd9Sstevel@tonic-gate #define CHIPREV_ID_5703_A1 0x1001 2777c478bd9Sstevel@tonic-gate #define CHIPREV_ID_5703_A2 0x1002 2787c478bd9Sstevel@tonic-gate #define CHIPREV_ID_5703_A3 0x1003 2797c478bd9Sstevel@tonic-gate #define CHIPREV_ID_5704_A0 0x2000 2807c478bd9Sstevel@tonic-gate #define CHIPREV_ID_5704_A1 0x2001 2817c478bd9Sstevel@tonic-gate #define CHIPREV_ID_5704_A2 0x2002 2827c478bd9Sstevel@tonic-gate #define CHIPREV_ID_5705_A0 0x3000 2837c478bd9Sstevel@tonic-gate #define CHIPREV_ID_5705_A1 0x3001 2847c478bd9Sstevel@tonic-gate #define CHIPREV_ID_5705_A2 0x3002 2857c478bd9Sstevel@tonic-gate #define CHIPREV_ID_5705_A3 0x3003 2867c478bd9Sstevel@tonic-gate #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) 2877c478bd9Sstevel@tonic-gate #define ASIC_REV_5700 0x07 2887c478bd9Sstevel@tonic-gate #define ASIC_REV_5701 0x00 2897c478bd9Sstevel@tonic-gate #define ASIC_REV_5703 0x01 2907c478bd9Sstevel@tonic-gate #define ASIC_REV_5704 0x02 2917c478bd9Sstevel@tonic-gate #define ASIC_REV_5705 0x03 2927c478bd9Sstevel@tonic-gate #define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8) 2937c478bd9Sstevel@tonic-gate #define CHIPREV_5700_AX 0x70 2947c478bd9Sstevel@tonic-gate #define CHIPREV_5700_BX 0x71 2957c478bd9Sstevel@tonic-gate #define CHIPREV_5700_CX 0x72 2967c478bd9Sstevel@tonic-gate #define CHIPREV_5701_AX 0x00 2977c478bd9Sstevel@tonic-gate #define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff) 2987c478bd9Sstevel@tonic-gate #define METAL_REV_A0 0x00 2997c478bd9Sstevel@tonic-gate #define METAL_REV_A1 0x01 3007c478bd9Sstevel@tonic-gate #define METAL_REV_B0 0x00 3017c478bd9Sstevel@tonic-gate #define METAL_REV_B1 0x01 3027c478bd9Sstevel@tonic-gate #define METAL_REV_B2 0x02 3037c478bd9Sstevel@tonic-gate #define TG3PCI_DMA_RW_CTRL 0x0000006c 3047c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_MIN_DMA 0x000000ff 3057c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_MIN_DMA_SHIFT 0 3067c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700 3077c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000 3087c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_READ_BNDRY_16 0x00000100 3097c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_READ_BNDRY_32 0x00000200 3107c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_READ_BNDRY_64 0x00000300 3117c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_READ_BNDRY_128 0x00000400 3127c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_READ_BNDRY_256 0x00000500 3137c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_READ_BNDRY_512 0x00000600 3147c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_READ_BNDRY_1024 0x00000700 3157c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800 3167c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000 3177c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800 3187c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000 3197c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800 3207c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000 3217c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800 3227c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000 3237c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800 3247c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_ONE_DMA 0x00004000 3257c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_READ_WATER 0x00070000 3267c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_READ_WATER_SHIFT 16 3277c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_WRITE_WATER 0x00380000 3287c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_WRITE_WATER_SHIFT 19 3297c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000 3307c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000 3317c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_PCI_READ_CMD 0x0f000000 3327c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24 3337c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000 3347c478bd9Sstevel@tonic-gate #define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28 3357c478bd9Sstevel@tonic-gate #define TG3PCI_PCISTATE 0x00000070 3367c478bd9Sstevel@tonic-gate #define PCISTATE_FORCE_RESET 0x00000001 3377c478bd9Sstevel@tonic-gate #define PCISTATE_INT_NOT_ACTIVE 0x00000002 3387c478bd9Sstevel@tonic-gate #define PCISTATE_CONV_PCI_MODE 0x00000004 3397c478bd9Sstevel@tonic-gate #define PCISTATE_BUS_SPEED_HIGH 0x00000008 3407c478bd9Sstevel@tonic-gate #define PCISTATE_BUS_32BIT 0x00000010 3417c478bd9Sstevel@tonic-gate #define PCISTATE_ROM_ENABLE 0x00000020 3427c478bd9Sstevel@tonic-gate #define PCISTATE_ROM_RETRY_ENABLE 0x00000040 3437c478bd9Sstevel@tonic-gate #define PCISTATE_FLAT_VIEW 0x00000100 3447c478bd9Sstevel@tonic-gate #define PCISTATE_RETRY_SAME_DMA 0x00002000 3457c478bd9Sstevel@tonic-gate #define TG3PCI_CLOCK_CTRL 0x00000074 3467c478bd9Sstevel@tonic-gate #define CLOCK_CTRL_CORECLK_DISABLE 0x00000200 3477c478bd9Sstevel@tonic-gate #define CLOCK_CTRL_RXCLK_DISABLE 0x00000400 3487c478bd9Sstevel@tonic-gate #define CLOCK_CTRL_TXCLK_DISABLE 0x00000800 3497c478bd9Sstevel@tonic-gate #define CLOCK_CTRL_ALTCLK 0x00001000 3507c478bd9Sstevel@tonic-gate #define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000 3517c478bd9Sstevel@tonic-gate #define CLOCK_CTRL_44MHZ_CORE 0x00040000 3527c478bd9Sstevel@tonic-gate #define CLOCK_CTRL_625_CORE 0x00100000 3537c478bd9Sstevel@tonic-gate #define CLOCK_CTRL_FORCE_CLKRUN 0x00200000 3547c478bd9Sstevel@tonic-gate #define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000 3557c478bd9Sstevel@tonic-gate #define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000 3567c478bd9Sstevel@tonic-gate #define TG3PCI_REG_BASE_ADDR 0x00000078 3577c478bd9Sstevel@tonic-gate #define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c 3587c478bd9Sstevel@tonic-gate #define TG3PCI_REG_DATA 0x00000080 3597c478bd9Sstevel@tonic-gate #define TG3PCI_MEM_WIN_DATA 0x00000084 3607c478bd9Sstevel@tonic-gate #define TG3PCI_MODE_CTRL 0x00000088 3617c478bd9Sstevel@tonic-gate #define TG3PCI_MISC_CFG 0x0000008c 3627c478bd9Sstevel@tonic-gate #define TG3PCI_MISC_LOCAL_CTRL 0x00000090 3637c478bd9Sstevel@tonic-gate /* 0x94 --> 0x98 unused */ 3647c478bd9Sstevel@tonic-gate #define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */ 3657c478bd9Sstevel@tonic-gate #define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */ 3667c478bd9Sstevel@tonic-gate #define TG3PCI_SND_PROD_IDX 0x000000a8 /* 64-bit */ 3677c478bd9Sstevel@tonic-gate /* 0xb0 --> 0x100 unused */ 3687c478bd9Sstevel@tonic-gate 3697c478bd9Sstevel@tonic-gate /* 0x100 --> 0x200 unused */ 3707c478bd9Sstevel@tonic-gate 3717c478bd9Sstevel@tonic-gate /* Mailbox registers */ 3727c478bd9Sstevel@tonic-gate #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */ 3737c478bd9Sstevel@tonic-gate #define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */ 3747c478bd9Sstevel@tonic-gate #define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */ 3757c478bd9Sstevel@tonic-gate #define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */ 3767c478bd9Sstevel@tonic-gate #define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */ 3777c478bd9Sstevel@tonic-gate #define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */ 3787c478bd9Sstevel@tonic-gate #define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */ 3797c478bd9Sstevel@tonic-gate #define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */ 3807c478bd9Sstevel@tonic-gate #define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */ 3817c478bd9Sstevel@tonic-gate #define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */ 3827c478bd9Sstevel@tonic-gate #define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */ 3837c478bd9Sstevel@tonic-gate #define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */ 3847c478bd9Sstevel@tonic-gate #define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */ 3857c478bd9Sstevel@tonic-gate #define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */ 3867c478bd9Sstevel@tonic-gate #define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */ 3877c478bd9Sstevel@tonic-gate #define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */ 3887c478bd9Sstevel@tonic-gate #define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */ 3897c478bd9Sstevel@tonic-gate #define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */ 3907c478bd9Sstevel@tonic-gate #define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */ 3917c478bd9Sstevel@tonic-gate #define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */ 3927c478bd9Sstevel@tonic-gate #define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */ 3937c478bd9Sstevel@tonic-gate #define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */ 3947c478bd9Sstevel@tonic-gate #define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */ 3957c478bd9Sstevel@tonic-gate #define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */ 3967c478bd9Sstevel@tonic-gate #define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */ 3977c478bd9Sstevel@tonic-gate #define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */ 3987c478bd9Sstevel@tonic-gate #define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */ 3997c478bd9Sstevel@tonic-gate #define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */ 4007c478bd9Sstevel@tonic-gate #define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */ 4017c478bd9Sstevel@tonic-gate #define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */ 4027c478bd9Sstevel@tonic-gate #define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */ 4037c478bd9Sstevel@tonic-gate #define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */ 4047c478bd9Sstevel@tonic-gate #define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */ 4057c478bd9Sstevel@tonic-gate #define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */ 4067c478bd9Sstevel@tonic-gate #define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */ 4077c478bd9Sstevel@tonic-gate #define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */ 4087c478bd9Sstevel@tonic-gate #define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */ 4097c478bd9Sstevel@tonic-gate #define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */ 4107c478bd9Sstevel@tonic-gate #define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */ 4117c478bd9Sstevel@tonic-gate #define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */ 4127c478bd9Sstevel@tonic-gate #define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */ 4137c478bd9Sstevel@tonic-gate #define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */ 4147c478bd9Sstevel@tonic-gate #define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */ 4157c478bd9Sstevel@tonic-gate #define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */ 4167c478bd9Sstevel@tonic-gate #define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */ 4177c478bd9Sstevel@tonic-gate #define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */ 4187c478bd9Sstevel@tonic-gate #define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */ 4197c478bd9Sstevel@tonic-gate #define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */ 4207c478bd9Sstevel@tonic-gate #define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */ 4217c478bd9Sstevel@tonic-gate #define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */ 4227c478bd9Sstevel@tonic-gate #define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */ 4237c478bd9Sstevel@tonic-gate #define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */ 4247c478bd9Sstevel@tonic-gate #define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */ 4257c478bd9Sstevel@tonic-gate #define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */ 4267c478bd9Sstevel@tonic-gate #define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */ 4277c478bd9Sstevel@tonic-gate #define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */ 4287c478bd9Sstevel@tonic-gate #define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */ 4297c478bd9Sstevel@tonic-gate #define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */ 4307c478bd9Sstevel@tonic-gate #define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */ 4317c478bd9Sstevel@tonic-gate #define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */ 4327c478bd9Sstevel@tonic-gate #define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */ 4337c478bd9Sstevel@tonic-gate #define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */ 4347c478bd9Sstevel@tonic-gate #define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */ 4357c478bd9Sstevel@tonic-gate #define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */ 4367c478bd9Sstevel@tonic-gate 4377c478bd9Sstevel@tonic-gate /* MAC control registers */ 4387c478bd9Sstevel@tonic-gate #define MAC_MODE 0x00000400 4397c478bd9Sstevel@tonic-gate #define MAC_MODE_RESET 0x00000001 4407c478bd9Sstevel@tonic-gate #define MAC_MODE_HALF_DUPLEX 0x00000002 4417c478bd9Sstevel@tonic-gate #define MAC_MODE_PORT_MODE_MASK 0x0000000c 4427c478bd9Sstevel@tonic-gate #define MAC_MODE_PORT_MODE_TBI 0x0000000c 4437c478bd9Sstevel@tonic-gate #define MAC_MODE_PORT_MODE_GMII 0x00000008 4447c478bd9Sstevel@tonic-gate #define MAC_MODE_PORT_MODE_MII 0x00000004 4457c478bd9Sstevel@tonic-gate #define MAC_MODE_PORT_MODE_NONE 0x00000000 4467c478bd9Sstevel@tonic-gate #define MAC_MODE_PORT_INT_LPBACK 0x00000010 4477c478bd9Sstevel@tonic-gate #define MAC_MODE_TAGGED_MAC_CTRL 0x00000080 4487c478bd9Sstevel@tonic-gate #define MAC_MODE_TX_BURSTING 0x00000100 4497c478bd9Sstevel@tonic-gate #define MAC_MODE_MAX_DEFER 0x00000200 4507c478bd9Sstevel@tonic-gate #define MAC_MODE_LINK_POLARITY 0x00000400 4517c478bd9Sstevel@tonic-gate #define MAC_MODE_RXSTAT_ENABLE 0x00000800 4527c478bd9Sstevel@tonic-gate #define MAC_MODE_RXSTAT_CLEAR 0x00001000 4537c478bd9Sstevel@tonic-gate #define MAC_MODE_RXSTAT_FLUSH 0x00002000 4547c478bd9Sstevel@tonic-gate #define MAC_MODE_TXSTAT_ENABLE 0x00004000 4557c478bd9Sstevel@tonic-gate #define MAC_MODE_TXSTAT_CLEAR 0x00008000 4567c478bd9Sstevel@tonic-gate #define MAC_MODE_TXSTAT_FLUSH 0x00010000 4577c478bd9Sstevel@tonic-gate #define MAC_MODE_SEND_CONFIGS 0x00020000 4587c478bd9Sstevel@tonic-gate #define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000 4597c478bd9Sstevel@tonic-gate #define MAC_MODE_ACPI_ENABLE 0x00080000 4607c478bd9Sstevel@tonic-gate #define MAC_MODE_MIP_ENABLE 0x00100000 4617c478bd9Sstevel@tonic-gate #define MAC_MODE_TDE_ENABLE 0x00200000 4627c478bd9Sstevel@tonic-gate #define MAC_MODE_RDE_ENABLE 0x00400000 4637c478bd9Sstevel@tonic-gate #define MAC_MODE_FHDE_ENABLE 0x00800000 4647c478bd9Sstevel@tonic-gate #define MAC_STATUS 0x00000404 4657c478bd9Sstevel@tonic-gate #define MAC_STATUS_PCS_SYNCED 0x00000001 4667c478bd9Sstevel@tonic-gate #define MAC_STATUS_SIGNAL_DET 0x00000002 4677c478bd9Sstevel@tonic-gate #define MAC_STATUS_RCVD_CFG 0x00000004 4687c478bd9Sstevel@tonic-gate #define MAC_STATUS_CFG_CHANGED 0x00000008 4697c478bd9Sstevel@tonic-gate #define MAC_STATUS_SYNC_CHANGED 0x00000010 4707c478bd9Sstevel@tonic-gate #define MAC_STATUS_PORT_DEC_ERR 0x00000400 4717c478bd9Sstevel@tonic-gate #define MAC_STATUS_LNKSTATE_CHANGED 0x00001000 4727c478bd9Sstevel@tonic-gate #define MAC_STATUS_MI_COMPLETION 0x00400000 4737c478bd9Sstevel@tonic-gate #define MAC_STATUS_MI_INTERRUPT 0x00800000 4747c478bd9Sstevel@tonic-gate #define MAC_STATUS_AP_ERROR 0x01000000 4757c478bd9Sstevel@tonic-gate #define MAC_STATUS_ODI_ERROR 0x02000000 4767c478bd9Sstevel@tonic-gate #define MAC_STATUS_RXSTAT_OVERRUN 0x04000000 4777c478bd9Sstevel@tonic-gate #define MAC_STATUS_TXSTAT_OVERRUN 0x08000000 4787c478bd9Sstevel@tonic-gate #define MAC_EVENT 0x00000408 4797c478bd9Sstevel@tonic-gate #define MAC_EVENT_PORT_DECODE_ERR 0x00000400 4807c478bd9Sstevel@tonic-gate #define MAC_EVENT_LNKSTATE_CHANGED 0x00001000 4817c478bd9Sstevel@tonic-gate #define MAC_EVENT_MI_COMPLETION 0x00400000 4827c478bd9Sstevel@tonic-gate #define MAC_EVENT_MI_INTERRUPT 0x00800000 4837c478bd9Sstevel@tonic-gate #define MAC_EVENT_AP_ERROR 0x01000000 4847c478bd9Sstevel@tonic-gate #define MAC_EVENT_ODI_ERROR 0x02000000 4857c478bd9Sstevel@tonic-gate #define MAC_EVENT_RXSTAT_OVERRUN 0x04000000 4867c478bd9Sstevel@tonic-gate #define MAC_EVENT_TXSTAT_OVERRUN 0x08000000 4877c478bd9Sstevel@tonic-gate #define MAC_LED_CTRL 0x0000040c 4887c478bd9Sstevel@tonic-gate #define LED_CTRL_LNKLED_OVERRIDE 0x00000001 4897c478bd9Sstevel@tonic-gate #define LED_CTRL_1000MBPS_ON 0x00000002 4907c478bd9Sstevel@tonic-gate #define LED_CTRL_100MBPS_ON 0x00000004 4917c478bd9Sstevel@tonic-gate #define LED_CTRL_10MBPS_ON 0x00000008 4927c478bd9Sstevel@tonic-gate #define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010 4937c478bd9Sstevel@tonic-gate #define LED_CTRL_TRAFFIC_BLINK 0x00000020 4947c478bd9Sstevel@tonic-gate #define LED_CTRL_TRAFFIC_LED 0x00000040 4957c478bd9Sstevel@tonic-gate #define LED_CTRL_1000MBPS_STATUS 0x00000080 4967c478bd9Sstevel@tonic-gate #define LED_CTRL_100MBPS_STATUS 0x00000100 4977c478bd9Sstevel@tonic-gate #define LED_CTRL_10MBPS_STATUS 0x00000200 4987c478bd9Sstevel@tonic-gate #define LED_CTRL_TRAFFIC_STATUS 0x00000400 4997c478bd9Sstevel@tonic-gate #define LED_CTRL_MAC_MODE 0x00000000 5007c478bd9Sstevel@tonic-gate #define LED_CTRL_PHY_MODE_1 0x00000800 5017c478bd9Sstevel@tonic-gate #define LED_CTRL_PHY_MODE_2 0x00001000 5027c478bd9Sstevel@tonic-gate #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000 5037c478bd9Sstevel@tonic-gate #define LED_CTRL_BLINK_RATE_SHIFT 19 5047c478bd9Sstevel@tonic-gate #define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000 5057c478bd9Sstevel@tonic-gate #define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000 5067c478bd9Sstevel@tonic-gate #define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */ 5077c478bd9Sstevel@tonic-gate #define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */ 5087c478bd9Sstevel@tonic-gate #define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */ 5097c478bd9Sstevel@tonic-gate #define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */ 5107c478bd9Sstevel@tonic-gate #define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */ 5117c478bd9Sstevel@tonic-gate #define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */ 5127c478bd9Sstevel@tonic-gate #define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */ 5137c478bd9Sstevel@tonic-gate #define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */ 5147c478bd9Sstevel@tonic-gate #define MAC_ACPI_MBUF_PTR 0x00000430 5157c478bd9Sstevel@tonic-gate #define MAC_ACPI_LEN_OFFSET 0x00000434 5167c478bd9Sstevel@tonic-gate #define ACPI_LENOFF_LEN_MASK 0x0000ffff 5177c478bd9Sstevel@tonic-gate #define ACPI_LENOFF_LEN_SHIFT 0 5187c478bd9Sstevel@tonic-gate #define ACPI_LENOFF_OFF_MASK 0x0fff0000 5197c478bd9Sstevel@tonic-gate #define ACPI_LENOFF_OFF_SHIFT 16 5207c478bd9Sstevel@tonic-gate #define MAC_TX_BACKOFF_SEED 0x00000438 5217c478bd9Sstevel@tonic-gate #define TX_BACKOFF_SEED_MASK 0x000003ff 5227c478bd9Sstevel@tonic-gate #define MAC_RX_MTU_SIZE 0x0000043c 5237c478bd9Sstevel@tonic-gate #define RX_MTU_SIZE_MASK 0x0000ffff 5247c478bd9Sstevel@tonic-gate #define MAC_PCS_TEST 0x00000440 5257c478bd9Sstevel@tonic-gate #define PCS_TEST_PATTERN_MASK 0x000fffff 5267c478bd9Sstevel@tonic-gate #define PCS_TEST_PATTERN_SHIFT 0 5277c478bd9Sstevel@tonic-gate #define PCS_TEST_ENABLE 0x00100000 5287c478bd9Sstevel@tonic-gate #define MAC_TX_AUTO_NEG 0x00000444 5297c478bd9Sstevel@tonic-gate #define TX_AUTO_NEG_MASK 0x0000ffff 5307c478bd9Sstevel@tonic-gate #define TX_AUTO_NEG_SHIFT 0 5317c478bd9Sstevel@tonic-gate #define MAC_RX_AUTO_NEG 0x00000448 5327c478bd9Sstevel@tonic-gate #define RX_AUTO_NEG_MASK 0x0000ffff 5337c478bd9Sstevel@tonic-gate #define RX_AUTO_NEG_SHIFT 0 5347c478bd9Sstevel@tonic-gate #define MAC_MI_COM 0x0000044c 5357c478bd9Sstevel@tonic-gate #define MI_COM_CMD_MASK 0x0c000000 5367c478bd9Sstevel@tonic-gate #define MI_COM_CMD_WRITE 0x04000000 5377c478bd9Sstevel@tonic-gate #define MI_COM_CMD_READ 0x08000000 5387c478bd9Sstevel@tonic-gate #define MI_COM_READ_FAILED 0x10000000 5397c478bd9Sstevel@tonic-gate #define MI_COM_START 0x20000000 5407c478bd9Sstevel@tonic-gate #define MI_COM_BUSY 0x20000000 5417c478bd9Sstevel@tonic-gate #define MI_COM_PHY_ADDR_MASK 0x03e00000 5427c478bd9Sstevel@tonic-gate #define MI_COM_PHY_ADDR_SHIFT 21 5437c478bd9Sstevel@tonic-gate #define MI_COM_REG_ADDR_MASK 0x001f0000 5447c478bd9Sstevel@tonic-gate #define MI_COM_REG_ADDR_SHIFT 16 5457c478bd9Sstevel@tonic-gate #define MI_COM_DATA_MASK 0x0000ffff 5467c478bd9Sstevel@tonic-gate #define MAC_MI_STAT 0x00000450 5477c478bd9Sstevel@tonic-gate #define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001 5487c478bd9Sstevel@tonic-gate #define MAC_MI_MODE 0x00000454 5497c478bd9Sstevel@tonic-gate #define MAC_MI_MODE_CLK_10MHZ 0x00000001 5507c478bd9Sstevel@tonic-gate #define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002 5517c478bd9Sstevel@tonic-gate #define MAC_MI_MODE_AUTO_POLL 0x00000010 5527c478bd9Sstevel@tonic-gate #define MAC_MI_MODE_CORE_CLK_62MHZ 0x00008000 5537c478bd9Sstevel@tonic-gate #define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */ 5547c478bd9Sstevel@tonic-gate #define MAC_AUTO_POLL_STATUS 0x00000458 5557c478bd9Sstevel@tonic-gate #define MAC_AUTO_POLL_ERROR 0x00000001 5567c478bd9Sstevel@tonic-gate #define MAC_TX_MODE 0x0000045c 5577c478bd9Sstevel@tonic-gate #define TX_MODE_RESET 0x00000001 5587c478bd9Sstevel@tonic-gate #define TX_MODE_ENABLE 0x00000002 5597c478bd9Sstevel@tonic-gate #define TX_MODE_FLOW_CTRL_ENABLE 0x00000010 5607c478bd9Sstevel@tonic-gate #define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020 5617c478bd9Sstevel@tonic-gate #define TX_MODE_LONG_PAUSE_ENABLE 0x00000040 5627c478bd9Sstevel@tonic-gate #define MAC_TX_STATUS 0x00000460 5637c478bd9Sstevel@tonic-gate #define TX_STATUS_XOFFED 0x00000001 5647c478bd9Sstevel@tonic-gate #define TX_STATUS_SENT_XOFF 0x00000002 5657c478bd9Sstevel@tonic-gate #define TX_STATUS_SENT_XON 0x00000004 5667c478bd9Sstevel@tonic-gate #define TX_STATUS_LINK_UP 0x00000008 5677c478bd9Sstevel@tonic-gate #define TX_STATUS_ODI_UNDERRUN 0x00000010 5687c478bd9Sstevel@tonic-gate #define TX_STATUS_ODI_OVERRUN 0x00000020 5697c478bd9Sstevel@tonic-gate #define MAC_TX_LENGTHS 0x00000464 5707c478bd9Sstevel@tonic-gate #define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff 5717c478bd9Sstevel@tonic-gate #define TX_LENGTHS_SLOT_TIME_SHIFT 0 5727c478bd9Sstevel@tonic-gate #define TX_LENGTHS_IPG_MASK 0x00000f00 5737c478bd9Sstevel@tonic-gate #define TX_LENGTHS_IPG_SHIFT 8 5747c478bd9Sstevel@tonic-gate #define TX_LENGTHS_IPG_CRS_MASK 0x00003000 5757c478bd9Sstevel@tonic-gate #define TX_LENGTHS_IPG_CRS_SHIFT 12 5767c478bd9Sstevel@tonic-gate #define MAC_RX_MODE 0x00000468 5777c478bd9Sstevel@tonic-gate #define RX_MODE_RESET 0x00000001 5787c478bd9Sstevel@tonic-gate #define RX_MODE_ENABLE 0x00000002 5797c478bd9Sstevel@tonic-gate #define RX_MODE_FLOW_CTRL_ENABLE 0x00000004 5807c478bd9Sstevel@tonic-gate #define RX_MODE_KEEP_MAC_CTRL 0x00000008 5817c478bd9Sstevel@tonic-gate #define RX_MODE_KEEP_PAUSE 0x00000010 5827c478bd9Sstevel@tonic-gate #define RX_MODE_ACCEPT_OVERSIZED 0x00000020 5837c478bd9Sstevel@tonic-gate #define RX_MODE_ACCEPT_RUNTS 0x00000040 5847c478bd9Sstevel@tonic-gate #define RX_MODE_LEN_CHECK 0x00000080 5857c478bd9Sstevel@tonic-gate #define RX_MODE_PROMISC 0x00000100 5867c478bd9Sstevel@tonic-gate #define RX_MODE_NO_CRC_CHECK 0x00000200 5877c478bd9Sstevel@tonic-gate #define RX_MODE_KEEP_VLAN_TAG 0x00000400 5887c478bd9Sstevel@tonic-gate #define MAC_RX_STATUS 0x0000046c 5897c478bd9Sstevel@tonic-gate #define RX_STATUS_REMOTE_TX_XOFFED 0x00000001 5907c478bd9Sstevel@tonic-gate #define RX_STATUS_XOFF_RCVD 0x00000002 5917c478bd9Sstevel@tonic-gate #define RX_STATUS_XON_RCVD 0x00000004 5927c478bd9Sstevel@tonic-gate #define MAC_HASH_REG_0 0x00000470 5937c478bd9Sstevel@tonic-gate #define MAC_HASH_REG_1 0x00000474 5947c478bd9Sstevel@tonic-gate #define MAC_HASH_REG_2 0x00000478 5957c478bd9Sstevel@tonic-gate #define MAC_HASH_REG_3 0x0000047c 5967c478bd9Sstevel@tonic-gate #define MAC_RCV_RULE_0 0x00000480 5977c478bd9Sstevel@tonic-gate #define MAC_RCV_VALUE_0 0x00000484 5987c478bd9Sstevel@tonic-gate #define MAC_RCV_RULE_1 0x00000488 5997c478bd9Sstevel@tonic-gate #define MAC_RCV_VALUE_1 0x0000048c 6007c478bd9Sstevel@tonic-gate #define MAC_RCV_RULE_2 0x00000490 6017c478bd9Sstevel@tonic-gate #define MAC_RCV_VALUE_2 0x00000494 6027c478bd9Sstevel@tonic-gate #define MAC_RCV_RULE_3 0x00000498 6037c478bd9Sstevel@tonic-gate #define MAC_RCV_VALUE_3 0x0000049c 6047c478bd9Sstevel@tonic-gate #define MAC_RCV_RULE_4 0x000004a0 6057c478bd9Sstevel@tonic-gate #define MAC_RCV_VALUE_4 0x000004a4 6067c478bd9Sstevel@tonic-gate #define MAC_RCV_RULE_5 0x000004a8 6077c478bd9Sstevel@tonic-gate #define MAC_RCV_VALUE_5 0x000004ac 6087c478bd9Sstevel@tonic-gate #define MAC_RCV_RULE_6 0x000004b0 6097c478bd9Sstevel@tonic-gate #define MAC_RCV_VALUE_6 0x000004b4 6107c478bd9Sstevel@tonic-gate #define MAC_RCV_RULE_7 0x000004b8 6117c478bd9Sstevel@tonic-gate #define MAC_RCV_VALUE_7 0x000004bc 6127c478bd9Sstevel@tonic-gate #define MAC_RCV_RULE_8 0x000004c0 6137c478bd9Sstevel@tonic-gate #define MAC_RCV_VALUE_8 0x000004c4 6147c478bd9Sstevel@tonic-gate #define MAC_RCV_RULE_9 0x000004c8 6157c478bd9Sstevel@tonic-gate #define MAC_RCV_VALUE_9 0x000004cc 6167c478bd9Sstevel@tonic-gate #define MAC_RCV_RULE_10 0x000004d0 6177c478bd9Sstevel@tonic-gate #define MAC_RCV_VALUE_10 0x000004d4 6187c478bd9Sstevel@tonic-gate #define MAC_RCV_RULE_11 0x000004d8 6197c478bd9Sstevel@tonic-gate #define MAC_RCV_VALUE_11 0x000004dc 6207c478bd9Sstevel@tonic-gate #define MAC_RCV_RULE_12 0x000004e0 6217c478bd9Sstevel@tonic-gate #define MAC_RCV_VALUE_12 0x000004e4 6227c478bd9Sstevel@tonic-gate #define MAC_RCV_RULE_13 0x000004e8 6237c478bd9Sstevel@tonic-gate #define MAC_RCV_VALUE_13 0x000004ec 6247c478bd9Sstevel@tonic-gate #define MAC_RCV_RULE_14 0x000004f0 6257c478bd9Sstevel@tonic-gate #define MAC_RCV_VALUE_14 0x000004f4 6267c478bd9Sstevel@tonic-gate #define MAC_RCV_RULE_15 0x000004f8 6277c478bd9Sstevel@tonic-gate #define MAC_RCV_VALUE_15 0x000004fc 6287c478bd9Sstevel@tonic-gate #define RCV_RULE_DISABLE_MASK 0x7fffffff 6297c478bd9Sstevel@tonic-gate #define MAC_RCV_RULE_CFG 0x00000500 6307c478bd9Sstevel@tonic-gate #define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008 6317c478bd9Sstevel@tonic-gate #define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504 6327c478bd9Sstevel@tonic-gate /* 0x508 --> 0x520 unused */ 6337c478bd9Sstevel@tonic-gate #define MAC_HASHREGU_0 0x00000520 6347c478bd9Sstevel@tonic-gate #define MAC_HASHREGU_1 0x00000524 6357c478bd9Sstevel@tonic-gate #define MAC_HASHREGU_2 0x00000528 6367c478bd9Sstevel@tonic-gate #define MAC_HASHREGU_3 0x0000052c 6377c478bd9Sstevel@tonic-gate #define MAC_EXTADDR_0_HIGH 0x00000530 6387c478bd9Sstevel@tonic-gate #define MAC_EXTADDR_0_LOW 0x00000534 6397c478bd9Sstevel@tonic-gate #define MAC_EXTADDR_1_HIGH 0x00000538 6407c478bd9Sstevel@tonic-gate #define MAC_EXTADDR_1_LOW 0x0000053c 6417c478bd9Sstevel@tonic-gate #define MAC_EXTADDR_2_HIGH 0x00000540 6427c478bd9Sstevel@tonic-gate #define MAC_EXTADDR_2_LOW 0x00000544 6437c478bd9Sstevel@tonic-gate #define MAC_EXTADDR_3_HIGH 0x00000548 6447c478bd9Sstevel@tonic-gate #define MAC_EXTADDR_3_LOW 0x0000054c 6457c478bd9Sstevel@tonic-gate #define MAC_EXTADDR_4_HIGH 0x00000550 6467c478bd9Sstevel@tonic-gate #define MAC_EXTADDR_4_LOW 0x00000554 6477c478bd9Sstevel@tonic-gate #define MAC_EXTADDR_5_HIGH 0x00000558 6487c478bd9Sstevel@tonic-gate #define MAC_EXTADDR_5_LOW 0x0000055c 6497c478bd9Sstevel@tonic-gate #define MAC_EXTADDR_6_HIGH 0x00000560 6507c478bd9Sstevel@tonic-gate #define MAC_EXTADDR_6_LOW 0x00000564 6517c478bd9Sstevel@tonic-gate #define MAC_EXTADDR_7_HIGH 0x00000568 6527c478bd9Sstevel@tonic-gate #define MAC_EXTADDR_7_LOW 0x0000056c 6537c478bd9Sstevel@tonic-gate #define MAC_EXTADDR_8_HIGH 0x00000570 6547c478bd9Sstevel@tonic-gate #define MAC_EXTADDR_8_LOW 0x00000574 6557c478bd9Sstevel@tonic-gate #define MAC_EXTADDR_9_HIGH 0x00000578 6567c478bd9Sstevel@tonic-gate #define MAC_EXTADDR_9_LOW 0x0000057c 6577c478bd9Sstevel@tonic-gate #define MAC_EXTADDR_10_HIGH 0x00000580 6587c478bd9Sstevel@tonic-gate #define MAC_EXTADDR_10_LOW 0x00000584 6597c478bd9Sstevel@tonic-gate #define MAC_EXTADDR_11_HIGH 0x00000588 6607c478bd9Sstevel@tonic-gate #define MAC_EXTADDR_11_LOW 0x0000058c 6617c478bd9Sstevel@tonic-gate #define MAC_SERDES_CFG 0x00000590 6627c478bd9Sstevel@tonic-gate #define MAC_SERDES_STAT 0x00000594 6637c478bd9Sstevel@tonic-gate /* 0x598 --> 0x600 unused */ 6647c478bd9Sstevel@tonic-gate #define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */ 6657c478bd9Sstevel@tonic-gate #define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */ 6667c478bd9Sstevel@tonic-gate /* 0x624 --> 0x800 unused */ 6677c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_OCTETS 0x00000800 6687c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_RESV1 0x00000804 6697c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_COLLISIONS 0x00000808 6707c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_XON_SENT 0x0000080c 6717c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_XOFF_SENT 0x00000810 6727c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_RESV2 0x00000814 6737c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_MAC_ERRORS 0x00000818 6747c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c 6757c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_MULT_COLLISIONS 0x00000820 6767c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_DEFERRED 0x00000824 6777c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_RESV3 0x00000828 6787c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c 6797c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_LATE_COL 0x00000830 6807c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_RESV4_1 0x00000834 6817c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_RESV4_2 0x00000838 6827c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_RESV4_3 0x0000083c 6837c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_RESV4_4 0x00000840 6847c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_RESV4_5 0x00000844 6857c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_RESV4_6 0x00000848 6867c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_RESV4_7 0x0000084c 6877c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_RESV4_8 0x00000850 6887c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_RESV4_9 0x00000854 6897c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_RESV4_10 0x00000858 6907c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_RESV4_11 0x0000085c 6917c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_RESV4_12 0x00000860 6927c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_RESV4_13 0x00000864 6937c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_RESV4_14 0x00000868 6947c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_UCAST 0x0000086c 6957c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_MCAST 0x00000870 6967c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_BCAST 0x00000874 6977c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_RESV5_1 0x00000878 6987c478bd9Sstevel@tonic-gate #define MAC_TX_STATS_RESV5_2 0x0000087c 6997c478bd9Sstevel@tonic-gate #define MAC_RX_STATS_OCTETS 0x00000880 7007c478bd9Sstevel@tonic-gate #define MAC_RX_STATS_RESV1 0x00000884 7017c478bd9Sstevel@tonic-gate #define MAC_RX_STATS_FRAGMENTS 0x00000888 7027c478bd9Sstevel@tonic-gate #define MAC_RX_STATS_UCAST 0x0000088c 7037c478bd9Sstevel@tonic-gate #define MAC_RX_STATS_MCAST 0x00000890 7047c478bd9Sstevel@tonic-gate #define MAC_RX_STATS_BCAST 0x00000894 7057c478bd9Sstevel@tonic-gate #define MAC_RX_STATS_FCS_ERRORS 0x00000898 7067c478bd9Sstevel@tonic-gate #define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c 7077c478bd9Sstevel@tonic-gate #define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0 7087c478bd9Sstevel@tonic-gate #define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4 7097c478bd9Sstevel@tonic-gate #define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8 7107c478bd9Sstevel@tonic-gate #define MAC_RX_STATS_XOFF_ENTERED 0x000008ac 7117c478bd9Sstevel@tonic-gate #define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0 7127c478bd9Sstevel@tonic-gate #define MAC_RX_STATS_JABBERS 0x000008b4 7137c478bd9Sstevel@tonic-gate #define MAC_RX_STATS_UNDERSIZE 0x000008b8 7147c478bd9Sstevel@tonic-gate /* 0x8bc --> 0xc00 unused */ 7157c478bd9Sstevel@tonic-gate 7167c478bd9Sstevel@tonic-gate /* Send data initiator control registers */ 7177c478bd9Sstevel@tonic-gate #define SNDDATAI_MODE 0x00000c00 7187c478bd9Sstevel@tonic-gate #define SNDDATAI_MODE_RESET 0x00000001 7197c478bd9Sstevel@tonic-gate #define SNDDATAI_MODE_ENABLE 0x00000002 7207c478bd9Sstevel@tonic-gate #define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004 7217c478bd9Sstevel@tonic-gate #define SNDDATAI_STATUS 0x00000c04 7227c478bd9Sstevel@tonic-gate #define SNDDATAI_STATUS_STAT_OFLOW 0x00000004 7237c478bd9Sstevel@tonic-gate #define SNDDATAI_STATSCTRL 0x00000c08 7247c478bd9Sstevel@tonic-gate #define SNDDATAI_SCTRL_ENABLE 0x00000001 7257c478bd9Sstevel@tonic-gate #define SNDDATAI_SCTRL_FASTUPD 0x00000002 7267c478bd9Sstevel@tonic-gate #define SNDDATAI_SCTRL_CLEAR 0x00000004 7277c478bd9Sstevel@tonic-gate #define SNDDATAI_SCTRL_FLUSH 0x00000008 7287c478bd9Sstevel@tonic-gate #define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010 7297c478bd9Sstevel@tonic-gate #define SNDDATAI_STATSENAB 0x00000c0c 7307c478bd9Sstevel@tonic-gate #define SNDDATAI_STATSINCMASK 0x00000c10 7317c478bd9Sstevel@tonic-gate /* 0xc14 --> 0xc80 unused */ 7327c478bd9Sstevel@tonic-gate #define SNDDATAI_COS_CNT_0 0x00000c80 7337c478bd9Sstevel@tonic-gate #define SNDDATAI_COS_CNT_1 0x00000c84 7347c478bd9Sstevel@tonic-gate #define SNDDATAI_COS_CNT_2 0x00000c88 7357c478bd9Sstevel@tonic-gate #define SNDDATAI_COS_CNT_3 0x00000c8c 7367c478bd9Sstevel@tonic-gate #define SNDDATAI_COS_CNT_4 0x00000c90 7377c478bd9Sstevel@tonic-gate #define SNDDATAI_COS_CNT_5 0x00000c94 7387c478bd9Sstevel@tonic-gate #define SNDDATAI_COS_CNT_6 0x00000c98 7397c478bd9Sstevel@tonic-gate #define SNDDATAI_COS_CNT_7 0x00000c9c 7407c478bd9Sstevel@tonic-gate #define SNDDATAI_COS_CNT_8 0x00000ca0 7417c478bd9Sstevel@tonic-gate #define SNDDATAI_COS_CNT_9 0x00000ca4 7427c478bd9Sstevel@tonic-gate #define SNDDATAI_COS_CNT_10 0x00000ca8 7437c478bd9Sstevel@tonic-gate #define SNDDATAI_COS_CNT_11 0x00000cac 7447c478bd9Sstevel@tonic-gate #define SNDDATAI_COS_CNT_12 0x00000cb0 7457c478bd9Sstevel@tonic-gate #define SNDDATAI_COS_CNT_13 0x00000cb4 7467c478bd9Sstevel@tonic-gate #define SNDDATAI_COS_CNT_14 0x00000cb8 7477c478bd9Sstevel@tonic-gate #define SNDDATAI_COS_CNT_15 0x00000cbc 7487c478bd9Sstevel@tonic-gate #define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0 7497c478bd9Sstevel@tonic-gate #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4 7507c478bd9Sstevel@tonic-gate #define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8 7517c478bd9Sstevel@tonic-gate #define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc 7527c478bd9Sstevel@tonic-gate #define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0 7537c478bd9Sstevel@tonic-gate #define SNDDATAI_INTERRUPTS_CNT 0x00000cd4 7547c478bd9Sstevel@tonic-gate #define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8 7557c478bd9Sstevel@tonic-gate #define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc 7567c478bd9Sstevel@tonic-gate /* 0xce0 --> 0x1000 unused */ 7577c478bd9Sstevel@tonic-gate 7587c478bd9Sstevel@tonic-gate /* Send data completion control registers */ 7597c478bd9Sstevel@tonic-gate #define SNDDATAC_MODE 0x00001000 7607c478bd9Sstevel@tonic-gate #define SNDDATAC_MODE_RESET 0x00000001 7617c478bd9Sstevel@tonic-gate #define SNDDATAC_MODE_ENABLE 0x00000002 7627c478bd9Sstevel@tonic-gate /* 0x1004 --> 0x1400 unused */ 7637c478bd9Sstevel@tonic-gate 7647c478bd9Sstevel@tonic-gate /* Send BD ring selector */ 7657c478bd9Sstevel@tonic-gate #define SNDBDS_MODE 0x00001400 7667c478bd9Sstevel@tonic-gate #define SNDBDS_MODE_RESET 0x00000001 7677c478bd9Sstevel@tonic-gate #define SNDBDS_MODE_ENABLE 0x00000002 7687c478bd9Sstevel@tonic-gate #define SNDBDS_MODE_ATTN_ENABLE 0x00000004 7697c478bd9Sstevel@tonic-gate #define SNDBDS_STATUS 0x00001404 7707c478bd9Sstevel@tonic-gate #define SNDBDS_STATUS_ERROR_ATTN 0x00000004 7717c478bd9Sstevel@tonic-gate #define SNDBDS_HWDIAG 0x00001408 7727c478bd9Sstevel@tonic-gate /* 0x140c --> 0x1440 */ 7737c478bd9Sstevel@tonic-gate #define SNDBDS_SEL_CON_IDX_0 0x00001440 7747c478bd9Sstevel@tonic-gate #define SNDBDS_SEL_CON_IDX_1 0x00001444 7757c478bd9Sstevel@tonic-gate #define SNDBDS_SEL_CON_IDX_2 0x00001448 7767c478bd9Sstevel@tonic-gate #define SNDBDS_SEL_CON_IDX_3 0x0000144c 7777c478bd9Sstevel@tonic-gate #define SNDBDS_SEL_CON_IDX_4 0x00001450 7787c478bd9Sstevel@tonic-gate #define SNDBDS_SEL_CON_IDX_5 0x00001454 7797c478bd9Sstevel@tonic-gate #define SNDBDS_SEL_CON_IDX_6 0x00001458 7807c478bd9Sstevel@tonic-gate #define SNDBDS_SEL_CON_IDX_7 0x0000145c 7817c478bd9Sstevel@tonic-gate #define SNDBDS_SEL_CON_IDX_8 0x00001460 7827c478bd9Sstevel@tonic-gate #define SNDBDS_SEL_CON_IDX_9 0x00001464 7837c478bd9Sstevel@tonic-gate #define SNDBDS_SEL_CON_IDX_10 0x00001468 7847c478bd9Sstevel@tonic-gate #define SNDBDS_SEL_CON_IDX_11 0x0000146c 7857c478bd9Sstevel@tonic-gate #define SNDBDS_SEL_CON_IDX_12 0x00001470 7867c478bd9Sstevel@tonic-gate #define SNDBDS_SEL_CON_IDX_13 0x00001474 7877c478bd9Sstevel@tonic-gate #define SNDBDS_SEL_CON_IDX_14 0x00001478 7887c478bd9Sstevel@tonic-gate #define SNDBDS_SEL_CON_IDX_15 0x0000147c 7897c478bd9Sstevel@tonic-gate /* 0x1480 --> 0x1800 unused */ 7907c478bd9Sstevel@tonic-gate 7917c478bd9Sstevel@tonic-gate /* Send BD initiator control registers */ 7927c478bd9Sstevel@tonic-gate #define SNDBDI_MODE 0x00001800 7937c478bd9Sstevel@tonic-gate #define SNDBDI_MODE_RESET 0x00000001 7947c478bd9Sstevel@tonic-gate #define SNDBDI_MODE_ENABLE 0x00000002 7957c478bd9Sstevel@tonic-gate #define SNDBDI_MODE_ATTN_ENABLE 0x00000004 7967c478bd9Sstevel@tonic-gate #define SNDBDI_STATUS 0x00001804 7977c478bd9Sstevel@tonic-gate #define SNDBDI_STATUS_ERROR_ATTN 0x00000004 7987c478bd9Sstevel@tonic-gate #define SNDBDI_IN_PROD_IDX_0 0x00001808 7997c478bd9Sstevel@tonic-gate #define SNDBDI_IN_PROD_IDX_1 0x0000180c 8007c478bd9Sstevel@tonic-gate #define SNDBDI_IN_PROD_IDX_2 0x00001810 8017c478bd9Sstevel@tonic-gate #define SNDBDI_IN_PROD_IDX_3 0x00001814 8027c478bd9Sstevel@tonic-gate #define SNDBDI_IN_PROD_IDX_4 0x00001818 8037c478bd9Sstevel@tonic-gate #define SNDBDI_IN_PROD_IDX_5 0x0000181c 8047c478bd9Sstevel@tonic-gate #define SNDBDI_IN_PROD_IDX_6 0x00001820 8057c478bd9Sstevel@tonic-gate #define SNDBDI_IN_PROD_IDX_7 0x00001824 8067c478bd9Sstevel@tonic-gate #define SNDBDI_IN_PROD_IDX_8 0x00001828 8077c478bd9Sstevel@tonic-gate #define SNDBDI_IN_PROD_IDX_9 0x0000182c 8087c478bd9Sstevel@tonic-gate #define SNDBDI_IN_PROD_IDX_10 0x00001830 8097c478bd9Sstevel@tonic-gate #define SNDBDI_IN_PROD_IDX_11 0x00001834 8107c478bd9Sstevel@tonic-gate #define SNDBDI_IN_PROD_IDX_12 0x00001838 8117c478bd9Sstevel@tonic-gate #define SNDBDI_IN_PROD_IDX_13 0x0000183c 8127c478bd9Sstevel@tonic-gate #define SNDBDI_IN_PROD_IDX_14 0x00001840 8137c478bd9Sstevel@tonic-gate #define SNDBDI_IN_PROD_IDX_15 0x00001844 8147c478bd9Sstevel@tonic-gate /* 0x1848 --> 0x1c00 unused */ 8157c478bd9Sstevel@tonic-gate 8167c478bd9Sstevel@tonic-gate /* Send BD completion control registers */ 8177c478bd9Sstevel@tonic-gate #define SNDBDC_MODE 0x00001c00 8187c478bd9Sstevel@tonic-gate #define SNDBDC_MODE_RESET 0x00000001 8197c478bd9Sstevel@tonic-gate #define SNDBDC_MODE_ENABLE 0x00000002 8207c478bd9Sstevel@tonic-gate #define SNDBDC_MODE_ATTN_ENABLE 0x00000004 8217c478bd9Sstevel@tonic-gate /* 0x1c04 --> 0x2000 unused */ 8227c478bd9Sstevel@tonic-gate 8237c478bd9Sstevel@tonic-gate /* Receive list placement control registers */ 8247c478bd9Sstevel@tonic-gate #define RCVLPC_MODE 0x00002000 8257c478bd9Sstevel@tonic-gate #define RCVLPC_MODE_RESET 0x00000001 8267c478bd9Sstevel@tonic-gate #define RCVLPC_MODE_ENABLE 0x00000002 8277c478bd9Sstevel@tonic-gate #define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004 8287c478bd9Sstevel@tonic-gate #define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008 8297c478bd9Sstevel@tonic-gate #define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010 8307c478bd9Sstevel@tonic-gate #define RCVLPC_STATUS 0x00002004 8317c478bd9Sstevel@tonic-gate #define RCVLPC_STATUS_CLASS0 0x00000004 8327c478bd9Sstevel@tonic-gate #define RCVLPC_STATUS_MAPOOR 0x00000008 8337c478bd9Sstevel@tonic-gate #define RCVLPC_STATUS_STAT_OFLOW 0x00000010 8347c478bd9Sstevel@tonic-gate #define RCVLPC_LOCK 0x00002008 8357c478bd9Sstevel@tonic-gate #define RCVLPC_LOCK_REQ_MASK 0x0000ffff 8367c478bd9Sstevel@tonic-gate #define RCVLPC_LOCK_REQ_SHIFT 0 8377c478bd9Sstevel@tonic-gate #define RCVLPC_LOCK_GRANT_MASK 0xffff0000 8387c478bd9Sstevel@tonic-gate #define RCVLPC_LOCK_GRANT_SHIFT 16 8397c478bd9Sstevel@tonic-gate #define RCVLPC_NON_EMPTY_BITS 0x0000200c 8407c478bd9Sstevel@tonic-gate #define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff 8417c478bd9Sstevel@tonic-gate #define RCVLPC_CONFIG 0x00002010 8427c478bd9Sstevel@tonic-gate #define RCVLPC_STATSCTRL 0x00002014 8437c478bd9Sstevel@tonic-gate #define RCVLPC_STATSCTRL_ENABLE 0x00000001 8447c478bd9Sstevel@tonic-gate #define RCVLPC_STATSCTRL_FASTUPD 0x00000002 8457c478bd9Sstevel@tonic-gate #define RCVLPC_STATS_ENABLE 0x00002018 8467c478bd9Sstevel@tonic-gate #define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000 8477c478bd9Sstevel@tonic-gate #define RCVLPC_STATS_INCMASK 0x0000201c 8487c478bd9Sstevel@tonic-gate /* 0x2020 --> 0x2100 unused */ 8497c478bd9Sstevel@tonic-gate #define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */ 8507c478bd9Sstevel@tonic-gate #define SELLST_TAIL 0x00000004 8517c478bd9Sstevel@tonic-gate #define SELLST_CONT 0x00000008 8527c478bd9Sstevel@tonic-gate #define SELLST_UNUSED 0x0000000c 8537c478bd9Sstevel@tonic-gate #define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */ 8547c478bd9Sstevel@tonic-gate #define RCVLPC_DROP_FILTER_CNT 0x00002240 8557c478bd9Sstevel@tonic-gate #define RCVLPC_DMA_WQ_FULL_CNT 0x00002244 8567c478bd9Sstevel@tonic-gate #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248 8577c478bd9Sstevel@tonic-gate #define RCVLPC_NO_RCV_BD_CNT 0x0000224c 8587c478bd9Sstevel@tonic-gate #define RCVLPC_IN_DISCARDS_CNT 0x00002250 8597c478bd9Sstevel@tonic-gate #define RCVLPC_IN_ERRORS_CNT 0x00002254 8607c478bd9Sstevel@tonic-gate #define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258 8617c478bd9Sstevel@tonic-gate /* 0x225c --> 0x2400 unused */ 8627c478bd9Sstevel@tonic-gate 8637c478bd9Sstevel@tonic-gate /* Receive Data and Receive BD Initiator Control */ 8647c478bd9Sstevel@tonic-gate #define RCVDBDI_MODE 0x00002400 8657c478bd9Sstevel@tonic-gate #define RCVDBDI_MODE_RESET 0x00000001 8667c478bd9Sstevel@tonic-gate #define RCVDBDI_MODE_ENABLE 0x00000002 8677c478bd9Sstevel@tonic-gate #define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004 8687c478bd9Sstevel@tonic-gate #define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008 8697c478bd9Sstevel@tonic-gate #define RCVDBDI_MODE_INV_RING_SZ 0x00000010 8707c478bd9Sstevel@tonic-gate #define RCVDBDI_STATUS 0x00002404 8717c478bd9Sstevel@tonic-gate #define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004 8727c478bd9Sstevel@tonic-gate #define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008 8737c478bd9Sstevel@tonic-gate #define RCVDBDI_STATUS_INV_RING_SZ 0x00000010 8747c478bd9Sstevel@tonic-gate #define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408 8757c478bd9Sstevel@tonic-gate /* 0x240c --> 0x2440 unused */ 8767c478bd9Sstevel@tonic-gate #define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */ 8777c478bd9Sstevel@tonic-gate #define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */ 8787c478bd9Sstevel@tonic-gate #define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */ 8797c478bd9Sstevel@tonic-gate #define RCVDBDI_JUMBO_CON_IDX 0x00002470 8807c478bd9Sstevel@tonic-gate #define RCVDBDI_STD_CON_IDX 0x00002474 8817c478bd9Sstevel@tonic-gate #define RCVDBDI_MINI_CON_IDX 0x00002478 8827c478bd9Sstevel@tonic-gate /* 0x247c --> 0x2480 unused */ 8837c478bd9Sstevel@tonic-gate #define RCVDBDI_BD_PROD_IDX_0 0x00002480 8847c478bd9Sstevel@tonic-gate #define RCVDBDI_BD_PROD_IDX_1 0x00002484 8857c478bd9Sstevel@tonic-gate #define RCVDBDI_BD_PROD_IDX_2 0x00002488 8867c478bd9Sstevel@tonic-gate #define RCVDBDI_BD_PROD_IDX_3 0x0000248c 8877c478bd9Sstevel@tonic-gate #define RCVDBDI_BD_PROD_IDX_4 0x00002490 8887c478bd9Sstevel@tonic-gate #define RCVDBDI_BD_PROD_IDX_5 0x00002494 8897c478bd9Sstevel@tonic-gate #define RCVDBDI_BD_PROD_IDX_6 0x00002498 8907c478bd9Sstevel@tonic-gate #define RCVDBDI_BD_PROD_IDX_7 0x0000249c 8917c478bd9Sstevel@tonic-gate #define RCVDBDI_BD_PROD_IDX_8 0x000024a0 8927c478bd9Sstevel@tonic-gate #define RCVDBDI_BD_PROD_IDX_9 0x000024a4 8937c478bd9Sstevel@tonic-gate #define RCVDBDI_BD_PROD_IDX_10 0x000024a8 8947c478bd9Sstevel@tonic-gate #define RCVDBDI_BD_PROD_IDX_11 0x000024ac 8957c478bd9Sstevel@tonic-gate #define RCVDBDI_BD_PROD_IDX_12 0x000024b0 8967c478bd9Sstevel@tonic-gate #define RCVDBDI_BD_PROD_IDX_13 0x000024b4 8977c478bd9Sstevel@tonic-gate #define RCVDBDI_BD_PROD_IDX_14 0x000024b8 8987c478bd9Sstevel@tonic-gate #define RCVDBDI_BD_PROD_IDX_15 0x000024bc 8997c478bd9Sstevel@tonic-gate #define RCVDBDI_HWDIAG 0x000024c0 9007c478bd9Sstevel@tonic-gate /* 0x24c4 --> 0x2800 unused */ 9017c478bd9Sstevel@tonic-gate 9027c478bd9Sstevel@tonic-gate /* Receive Data Completion Control */ 9037c478bd9Sstevel@tonic-gate #define RCVDCC_MODE 0x00002800 9047c478bd9Sstevel@tonic-gate #define RCVDCC_MODE_RESET 0x00000001 9057c478bd9Sstevel@tonic-gate #define RCVDCC_MODE_ENABLE 0x00000002 9067c478bd9Sstevel@tonic-gate #define RCVDCC_MODE_ATTN_ENABLE 0x00000004 9077c478bd9Sstevel@tonic-gate /* 0x2804 --> 0x2c00 unused */ 9087c478bd9Sstevel@tonic-gate 9097c478bd9Sstevel@tonic-gate /* Receive BD Initiator Control Registers */ 9107c478bd9Sstevel@tonic-gate #define RCVBDI_MODE 0x00002c00 9117c478bd9Sstevel@tonic-gate #define RCVBDI_MODE_RESET 0x00000001 9127c478bd9Sstevel@tonic-gate #define RCVBDI_MODE_ENABLE 0x00000002 9137c478bd9Sstevel@tonic-gate #define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004 9147c478bd9Sstevel@tonic-gate #define RCVBDI_STATUS 0x00002c04 9157c478bd9Sstevel@tonic-gate #define RCVBDI_STATUS_RCB_ATTN 0x00000004 9167c478bd9Sstevel@tonic-gate #define RCVBDI_JUMBO_PROD_IDX 0x00002c08 9177c478bd9Sstevel@tonic-gate #define RCVBDI_STD_PROD_IDX 0x00002c0c 9187c478bd9Sstevel@tonic-gate #define RCVBDI_MINI_PROD_IDX 0x00002c10 9197c478bd9Sstevel@tonic-gate #define RCVBDI_MINI_THRESH 0x00002c14 9207c478bd9Sstevel@tonic-gate #define RCVBDI_STD_THRESH 0x00002c18 9217c478bd9Sstevel@tonic-gate #define RCVBDI_JUMBO_THRESH 0x00002c1c 9227c478bd9Sstevel@tonic-gate /* 0x2c20 --> 0x3000 unused */ 9237c478bd9Sstevel@tonic-gate 9247c478bd9Sstevel@tonic-gate /* Receive BD Completion Control Registers */ 9257c478bd9Sstevel@tonic-gate #define RCVCC_MODE 0x00003000 9267c478bd9Sstevel@tonic-gate #define RCVCC_MODE_RESET 0x00000001 9277c478bd9Sstevel@tonic-gate #define RCVCC_MODE_ENABLE 0x00000002 9287c478bd9Sstevel@tonic-gate #define RCVCC_MODE_ATTN_ENABLE 0x00000004 9297c478bd9Sstevel@tonic-gate #define RCVCC_STATUS 0x00003004 9307c478bd9Sstevel@tonic-gate #define RCVCC_STATUS_ERROR_ATTN 0x00000004 9317c478bd9Sstevel@tonic-gate #define RCVCC_JUMP_PROD_IDX 0x00003008 9327c478bd9Sstevel@tonic-gate #define RCVCC_STD_PROD_IDX 0x0000300c 9337c478bd9Sstevel@tonic-gate #define RCVCC_MINI_PROD_IDX 0x00003010 9347c478bd9Sstevel@tonic-gate /* 0x3014 --> 0x3400 unused */ 9357c478bd9Sstevel@tonic-gate 9367c478bd9Sstevel@tonic-gate /* Receive list selector control registers */ 9377c478bd9Sstevel@tonic-gate #define RCVLSC_MODE 0x00003400 9387c478bd9Sstevel@tonic-gate #define RCVLSC_MODE_RESET 0x00000001 9397c478bd9Sstevel@tonic-gate #define RCVLSC_MODE_ENABLE 0x00000002 9407c478bd9Sstevel@tonic-gate #define RCVLSC_MODE_ATTN_ENABLE 0x00000004 9417c478bd9Sstevel@tonic-gate #define RCVLSC_STATUS 0x00003404 9427c478bd9Sstevel@tonic-gate #define RCVLSC_STATUS_ERROR_ATTN 0x00000004 9437c478bd9Sstevel@tonic-gate /* 0x3408 --> 0x3800 unused */ 9447c478bd9Sstevel@tonic-gate 9457c478bd9Sstevel@tonic-gate /* Mbuf cluster free registers */ 9467c478bd9Sstevel@tonic-gate #define MBFREE_MODE 0x00003800 9477c478bd9Sstevel@tonic-gate #define MBFREE_MODE_RESET 0x00000001 9487c478bd9Sstevel@tonic-gate #define MBFREE_MODE_ENABLE 0x00000002 9497c478bd9Sstevel@tonic-gate #define MBFREE_STATUS 0x00003804 9507c478bd9Sstevel@tonic-gate /* 0x3808 --> 0x3c00 unused */ 9517c478bd9Sstevel@tonic-gate 9527c478bd9Sstevel@tonic-gate /* Host coalescing control registers */ 9537c478bd9Sstevel@tonic-gate #define HOSTCC_MODE 0x00003c00 9547c478bd9Sstevel@tonic-gate #define HOSTCC_MODE_RESET 0x00000001 9557c478bd9Sstevel@tonic-gate #define HOSTCC_MODE_ENABLE 0x00000002 9567c478bd9Sstevel@tonic-gate #define HOSTCC_MODE_ATTN 0x00000004 9577c478bd9Sstevel@tonic-gate #define HOSTCC_MODE_NOW 0x00000008 9587c478bd9Sstevel@tonic-gate #define HOSTCC_MODE_FULL_STATUS 0x00000000 9597c478bd9Sstevel@tonic-gate #define HOSTCC_MODE_64BYTE 0x00000080 9607c478bd9Sstevel@tonic-gate #define HOSTCC_MODE_32BYTE 0x00000100 9617c478bd9Sstevel@tonic-gate #define HOSTCC_MODE_CLRTICK_RXBD 0x00000200 9627c478bd9Sstevel@tonic-gate #define HOSTCC_MODE_CLRTICK_TXBD 0x00000400 9637c478bd9Sstevel@tonic-gate #define HOSTCC_MODE_NOINT_ON_NOW 0x00000800 9647c478bd9Sstevel@tonic-gate #define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000 9657c478bd9Sstevel@tonic-gate #define HOSTCC_STATUS 0x00003c04 9667c478bd9Sstevel@tonic-gate #define HOSTCC_STATUS_ERROR_ATTN 0x00000004 9677c478bd9Sstevel@tonic-gate #define HOSTCC_RXCOL_TICKS 0x00003c08 9687c478bd9Sstevel@tonic-gate #define LOW_RXCOL_TICKS 0x00000032 9697c478bd9Sstevel@tonic-gate #define DEFAULT_RXCOL_TICKS 0x00000048 9707c478bd9Sstevel@tonic-gate #define HIGH_RXCOL_TICKS 0x00000096 9717c478bd9Sstevel@tonic-gate #define HOSTCC_TXCOL_TICKS 0x00003c0c 9727c478bd9Sstevel@tonic-gate #define LOW_TXCOL_TICKS 0x00000096 9737c478bd9Sstevel@tonic-gate #define DEFAULT_TXCOL_TICKS 0x0000012c 9747c478bd9Sstevel@tonic-gate #define HIGH_TXCOL_TICKS 0x00000145 9757c478bd9Sstevel@tonic-gate #define HOSTCC_RXMAX_FRAMES 0x00003c10 9767c478bd9Sstevel@tonic-gate #define LOW_RXMAX_FRAMES 0x00000005 9777c478bd9Sstevel@tonic-gate #define DEFAULT_RXMAX_FRAMES 0x00000008 9787c478bd9Sstevel@tonic-gate #define HIGH_RXMAX_FRAMES 0x00000012 9797c478bd9Sstevel@tonic-gate #define HOSTCC_TXMAX_FRAMES 0x00003c14 9807c478bd9Sstevel@tonic-gate #define LOW_TXMAX_FRAMES 0x00000035 9817c478bd9Sstevel@tonic-gate #define DEFAULT_TXMAX_FRAMES 0x0000004b 9827c478bd9Sstevel@tonic-gate #define HIGH_TXMAX_FRAMES 0x00000052 9837c478bd9Sstevel@tonic-gate #define HOSTCC_RXCOAL_TICK_INT 0x00003c18 9847c478bd9Sstevel@tonic-gate #define DEFAULT_RXCOAL_TICK_INT 0x00000019 9857c478bd9Sstevel@tonic-gate #define HOSTCC_TXCOAL_TICK_INT 0x00003c1c 9867c478bd9Sstevel@tonic-gate #define DEFAULT_TXCOAL_TICK_INT 0x00000019 9877c478bd9Sstevel@tonic-gate #define HOSTCC_RXCOAL_MAXF_INT 0x00003c20 9887c478bd9Sstevel@tonic-gate #define DEFAULT_RXCOAL_MAXF_INT 0x00000005 9897c478bd9Sstevel@tonic-gate #define HOSTCC_TXCOAL_MAXF_INT 0x00003c24 9907c478bd9Sstevel@tonic-gate #define DEFAULT_TXCOAL_MAXF_INT 0x00000005 9917c478bd9Sstevel@tonic-gate #define HOSTCC_STAT_COAL_TICKS 0x00003c28 9927c478bd9Sstevel@tonic-gate #define DEFAULT_STAT_COAL_TICKS 0x000f4240 9937c478bd9Sstevel@tonic-gate /* 0x3c2c --> 0x3c30 unused */ 9947c478bd9Sstevel@tonic-gate #define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */ 9957c478bd9Sstevel@tonic-gate #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */ 9967c478bd9Sstevel@tonic-gate #define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40 9977c478bd9Sstevel@tonic-gate #define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44 9987c478bd9Sstevel@tonic-gate #define HOSTCC_FLOW_ATTN 0x00003c48 9997c478bd9Sstevel@tonic-gate /* 0x3c4c --> 0x3c50 unused */ 10007c478bd9Sstevel@tonic-gate #define HOSTCC_JUMBO_CON_IDX 0x00003c50 10017c478bd9Sstevel@tonic-gate #define HOSTCC_STD_CON_IDX 0x00003c54 10027c478bd9Sstevel@tonic-gate #define HOSTCC_MINI_CON_IDX 0x00003c58 10037c478bd9Sstevel@tonic-gate /* 0x3c5c --> 0x3c80 unused */ 10047c478bd9Sstevel@tonic-gate #define HOSTCC_RET_PROD_IDX_0 0x00003c80 10057c478bd9Sstevel@tonic-gate #define HOSTCC_RET_PROD_IDX_1 0x00003c84 10067c478bd9Sstevel@tonic-gate #define HOSTCC_RET_PROD_IDX_2 0x00003c88 10077c478bd9Sstevel@tonic-gate #define HOSTCC_RET_PROD_IDX_3 0x00003c8c 10087c478bd9Sstevel@tonic-gate #define HOSTCC_RET_PROD_IDX_4 0x00003c90 10097c478bd9Sstevel@tonic-gate #define HOSTCC_RET_PROD_IDX_5 0x00003c94 10107c478bd9Sstevel@tonic-gate #define HOSTCC_RET_PROD_IDX_6 0x00003c98 10117c478bd9Sstevel@tonic-gate #define HOSTCC_RET_PROD_IDX_7 0x00003c9c 10127c478bd9Sstevel@tonic-gate #define HOSTCC_RET_PROD_IDX_8 0x00003ca0 10137c478bd9Sstevel@tonic-gate #define HOSTCC_RET_PROD_IDX_9 0x00003ca4 10147c478bd9Sstevel@tonic-gate #define HOSTCC_RET_PROD_IDX_10 0x00003ca8 10157c478bd9Sstevel@tonic-gate #define HOSTCC_RET_PROD_IDX_11 0x00003cac 10167c478bd9Sstevel@tonic-gate #define HOSTCC_RET_PROD_IDX_12 0x00003cb0 10177c478bd9Sstevel@tonic-gate #define HOSTCC_RET_PROD_IDX_13 0x00003cb4 10187c478bd9Sstevel@tonic-gate #define HOSTCC_RET_PROD_IDX_14 0x00003cb8 10197c478bd9Sstevel@tonic-gate #define HOSTCC_RET_PROD_IDX_15 0x00003cbc 10207c478bd9Sstevel@tonic-gate #define HOSTCC_SND_CON_IDX_0 0x00003cc0 10217c478bd9Sstevel@tonic-gate #define HOSTCC_SND_CON_IDX_1 0x00003cc4 10227c478bd9Sstevel@tonic-gate #define HOSTCC_SND_CON_IDX_2 0x00003cc8 10237c478bd9Sstevel@tonic-gate #define HOSTCC_SND_CON_IDX_3 0x00003ccc 10247c478bd9Sstevel@tonic-gate #define HOSTCC_SND_CON_IDX_4 0x00003cd0 10257c478bd9Sstevel@tonic-gate #define HOSTCC_SND_CON_IDX_5 0x00003cd4 10267c478bd9Sstevel@tonic-gate #define HOSTCC_SND_CON_IDX_6 0x00003cd8 10277c478bd9Sstevel@tonic-gate #define HOSTCC_SND_CON_IDX_7 0x00003cdc 10287c478bd9Sstevel@tonic-gate #define HOSTCC_SND_CON_IDX_8 0x00003ce0 10297c478bd9Sstevel@tonic-gate #define HOSTCC_SND_CON_IDX_9 0x00003ce4 10307c478bd9Sstevel@tonic-gate #define HOSTCC_SND_CON_IDX_10 0x00003ce8 10317c478bd9Sstevel@tonic-gate #define HOSTCC_SND_CON_IDX_11 0x00003cec 10327c478bd9Sstevel@tonic-gate #define HOSTCC_SND_CON_IDX_12 0x00003cf0 10337c478bd9Sstevel@tonic-gate #define HOSTCC_SND_CON_IDX_13 0x00003cf4 10347c478bd9Sstevel@tonic-gate #define HOSTCC_SND_CON_IDX_14 0x00003cf8 10357c478bd9Sstevel@tonic-gate #define HOSTCC_SND_CON_IDX_15 0x00003cfc 10367c478bd9Sstevel@tonic-gate /* 0x3d00 --> 0x4000 unused */ 10377c478bd9Sstevel@tonic-gate 10387c478bd9Sstevel@tonic-gate /* Memory arbiter control registers */ 10397c478bd9Sstevel@tonic-gate #define MEMARB_MODE 0x00004000 10407c478bd9Sstevel@tonic-gate #define MEMARB_MODE_RESET 0x00000001 10417c478bd9Sstevel@tonic-gate #define MEMARB_MODE_ENABLE 0x00000002 10427c478bd9Sstevel@tonic-gate #define MEMARB_STATUS 0x00004004 10437c478bd9Sstevel@tonic-gate #define MEMARB_TRAP_ADDR_LOW 0x00004008 10447c478bd9Sstevel@tonic-gate #define MEMARB_TRAP_ADDR_HIGH 0x0000400c 10457c478bd9Sstevel@tonic-gate /* 0x4010 --> 0x4400 unused */ 10467c478bd9Sstevel@tonic-gate 10477c478bd9Sstevel@tonic-gate /* Buffer manager control registers */ 10487c478bd9Sstevel@tonic-gate #define BUFMGR_MODE 0x00004400 10497c478bd9Sstevel@tonic-gate #define BUFMGR_MODE_RESET 0x00000001 10507c478bd9Sstevel@tonic-gate #define BUFMGR_MODE_ENABLE 0x00000002 10517c478bd9Sstevel@tonic-gate #define BUFMGR_MODE_ATTN_ENABLE 0x00000004 10527c478bd9Sstevel@tonic-gate #define BUFMGR_MODE_BM_TEST 0x00000008 10537c478bd9Sstevel@tonic-gate #define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010 10547c478bd9Sstevel@tonic-gate #define BUFMGR_STATUS 0x00004404 10557c478bd9Sstevel@tonic-gate #define BUFMGR_STATUS_ERROR 0x00000004 10567c478bd9Sstevel@tonic-gate #define BUFMGR_STATUS_MBLOW 0x00000010 10577c478bd9Sstevel@tonic-gate #define BUFMGR_MB_POOL_ADDR 0x00004408 10587c478bd9Sstevel@tonic-gate #define BUFMGR_MB_POOL_SIZE 0x0000440c 10597c478bd9Sstevel@tonic-gate #define BUFMGR_MB_RDMA_LOW_WATER 0x00004410 10607c478bd9Sstevel@tonic-gate #define DEFAULT_MB_RDMA_LOW_WATER 0x00000050 10617c478bd9Sstevel@tonic-gate #define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000 10627c478bd9Sstevel@tonic-gate #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130 10637c478bd9Sstevel@tonic-gate #define BUFMGR_MB_MACRX_LOW_WATER 0x00004414 10647c478bd9Sstevel@tonic-gate #define DEFAULT_MB_MACRX_LOW_WATER 0x00000020 10657c478bd9Sstevel@tonic-gate #define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010 10667c478bd9Sstevel@tonic-gate #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098 10677c478bd9Sstevel@tonic-gate #define BUFMGR_MB_HIGH_WATER 0x00004418 10687c478bd9Sstevel@tonic-gate #define DEFAULT_MB_HIGH_WATER 0x00000060 10697c478bd9Sstevel@tonic-gate #define DEFAULT_MB_HIGH_WATER_5705 0x00000060 10707c478bd9Sstevel@tonic-gate #define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c 10717c478bd9Sstevel@tonic-gate #define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c 10727c478bd9Sstevel@tonic-gate #define BUFMGR_MB_ALLOC_BIT 0x10000000 10737c478bd9Sstevel@tonic-gate #define BUFMGR_RX_MB_ALLOC_RESP 0x00004420 10747c478bd9Sstevel@tonic-gate #define BUFMGR_TX_MB_ALLOC_REQ 0x00004424 10757c478bd9Sstevel@tonic-gate #define BUFMGR_TX_MB_ALLOC_RESP 0x00004428 10767c478bd9Sstevel@tonic-gate #define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c 10777c478bd9Sstevel@tonic-gate #define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430 10787c478bd9Sstevel@tonic-gate #define BUFMGR_DMA_LOW_WATER 0x00004434 10797c478bd9Sstevel@tonic-gate #define DEFAULT_DMA_LOW_WATER 0x00000005 10807c478bd9Sstevel@tonic-gate #define BUFMGR_DMA_HIGH_WATER 0x00004438 10817c478bd9Sstevel@tonic-gate #define DEFAULT_DMA_HIGH_WATER 0x0000000a 10827c478bd9Sstevel@tonic-gate #define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c 10837c478bd9Sstevel@tonic-gate #define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440 10847c478bd9Sstevel@tonic-gate #define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444 10857c478bd9Sstevel@tonic-gate #define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448 10867c478bd9Sstevel@tonic-gate #define BUFMGR_HWDIAG_0 0x0000444c 10877c478bd9Sstevel@tonic-gate #define BUFMGR_HWDIAG_1 0x00004450 10887c478bd9Sstevel@tonic-gate #define BUFMGR_HWDIAG_2 0x00004454 10897c478bd9Sstevel@tonic-gate /* 0x4458 --> 0x4800 unused */ 10907c478bd9Sstevel@tonic-gate 10917c478bd9Sstevel@tonic-gate /* Read DMA control registers */ 10927c478bd9Sstevel@tonic-gate #define RDMAC_MODE 0x00004800 10937c478bd9Sstevel@tonic-gate #define RDMAC_MODE_RESET 0x00000001 10947c478bd9Sstevel@tonic-gate #define RDMAC_MODE_ENABLE 0x00000002 10957c478bd9Sstevel@tonic-gate #define RDMAC_MODE_TGTABORT_ENAB 0x00000004 10967c478bd9Sstevel@tonic-gate #define RDMAC_MODE_MSTABORT_ENAB 0x00000008 10977c478bd9Sstevel@tonic-gate #define RDMAC_MODE_PARITYERR_ENAB 0x00000010 10987c478bd9Sstevel@tonic-gate #define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020 10997c478bd9Sstevel@tonic-gate #define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040 11007c478bd9Sstevel@tonic-gate #define RDMAC_MODE_FIFOURUN_ENAB 0x00000080 11017c478bd9Sstevel@tonic-gate #define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100 11027c478bd9Sstevel@tonic-gate #define RDMAC_MODE_LNGREAD_ENAB 0x00000200 11037c478bd9Sstevel@tonic-gate #define RDMAC_MODE_SPLIT_ENABLE 0x00000800 11047c478bd9Sstevel@tonic-gate #define RDMAC_MODE_SPLIT_RESET 0x00001000 11057c478bd9Sstevel@tonic-gate #define RDMAC_MODE_FIFO_SIZE_128 0x00020000 11067c478bd9Sstevel@tonic-gate #define RDMAC_MODE_FIFO_LONG_BURST 0x00030000 11077c478bd9Sstevel@tonic-gate #define RDMAC_STATUS 0x00004804 11087c478bd9Sstevel@tonic-gate #define RDMAC_STATUS_TGTABORT 0x00000004 11097c478bd9Sstevel@tonic-gate #define RDMAC_STATUS_MSTABORT 0x00000008 11107c478bd9Sstevel@tonic-gate #define RDMAC_STATUS_PARITYERR 0x00000010 11117c478bd9Sstevel@tonic-gate #define RDMAC_STATUS_ADDROFLOW 0x00000020 11127c478bd9Sstevel@tonic-gate #define RDMAC_STATUS_FIFOOFLOW 0x00000040 11137c478bd9Sstevel@tonic-gate #define RDMAC_STATUS_FIFOURUN 0x00000080 11147c478bd9Sstevel@tonic-gate #define RDMAC_STATUS_FIFOOREAD 0x00000100 11157c478bd9Sstevel@tonic-gate #define RDMAC_STATUS_LNGREAD 0x00000200 11167c478bd9Sstevel@tonic-gate /* 0x4808 --> 0x4c00 unused */ 11177c478bd9Sstevel@tonic-gate 11187c478bd9Sstevel@tonic-gate /* Write DMA control registers */ 11197c478bd9Sstevel@tonic-gate #define WDMAC_MODE 0x00004c00 11207c478bd9Sstevel@tonic-gate #define WDMAC_MODE_RESET 0x00000001 11217c478bd9Sstevel@tonic-gate #define WDMAC_MODE_ENABLE 0x00000002 11227c478bd9Sstevel@tonic-gate #define WDMAC_MODE_TGTABORT_ENAB 0x00000004 11237c478bd9Sstevel@tonic-gate #define WDMAC_MODE_MSTABORT_ENAB 0x00000008 11247c478bd9Sstevel@tonic-gate #define WDMAC_MODE_PARITYERR_ENAB 0x00000010 11257c478bd9Sstevel@tonic-gate #define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020 11267c478bd9Sstevel@tonic-gate #define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040 11277c478bd9Sstevel@tonic-gate #define WDMAC_MODE_FIFOURUN_ENAB 0x00000080 11287c478bd9Sstevel@tonic-gate #define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100 11297c478bd9Sstevel@tonic-gate #define WDMAC_MODE_LNGREAD_ENAB 0x00000200 11307c478bd9Sstevel@tonic-gate #define WDMAC_MODE_RX_ACCEL 0x00000400 11317c478bd9Sstevel@tonic-gate #define WDMAC_STATUS 0x00004c04 11327c478bd9Sstevel@tonic-gate #define WDMAC_STATUS_TGTABORT 0x00000004 11337c478bd9Sstevel@tonic-gate #define WDMAC_STATUS_MSTABORT 0x00000008 11347c478bd9Sstevel@tonic-gate #define WDMAC_STATUS_PARITYERR 0x00000010 11357c478bd9Sstevel@tonic-gate #define WDMAC_STATUS_ADDROFLOW 0x00000020 11367c478bd9Sstevel@tonic-gate #define WDMAC_STATUS_FIFOOFLOW 0x00000040 11377c478bd9Sstevel@tonic-gate #define WDMAC_STATUS_FIFOURUN 0x00000080 11387c478bd9Sstevel@tonic-gate #define WDMAC_STATUS_FIFOOREAD 0x00000100 11397c478bd9Sstevel@tonic-gate #define WDMAC_STATUS_LNGREAD 0x00000200 11407c478bd9Sstevel@tonic-gate /* 0x4c08 --> 0x5000 unused */ 11417c478bd9Sstevel@tonic-gate 11427c478bd9Sstevel@tonic-gate /* Per-cpu register offsets (arm9) */ 11437c478bd9Sstevel@tonic-gate #define CPU_MODE 0x00000000 11447c478bd9Sstevel@tonic-gate #define CPU_MODE_RESET 0x00000001 11457c478bd9Sstevel@tonic-gate #define CPU_MODE_HALT 0x00000400 11467c478bd9Sstevel@tonic-gate #define CPU_STATE 0x00000004 11477c478bd9Sstevel@tonic-gate #define CPU_EVTMASK 0x00000008 11487c478bd9Sstevel@tonic-gate /* 0xc --> 0x1c reserved */ 11497c478bd9Sstevel@tonic-gate #define CPU_PC 0x0000001c 11507c478bd9Sstevel@tonic-gate #define CPU_INSN 0x00000020 11517c478bd9Sstevel@tonic-gate #define CPU_SPAD_UFLOW 0x00000024 11527c478bd9Sstevel@tonic-gate #define CPU_WDOG_CLEAR 0x00000028 11537c478bd9Sstevel@tonic-gate #define CPU_WDOG_VECTOR 0x0000002c 11547c478bd9Sstevel@tonic-gate #define CPU_WDOG_PC 0x00000030 11557c478bd9Sstevel@tonic-gate #define CPU_HW_BP 0x00000034 11567c478bd9Sstevel@tonic-gate /* 0x38 --> 0x44 unused */ 11577c478bd9Sstevel@tonic-gate #define CPU_WDOG_SAVED_STATE 0x00000044 11587c478bd9Sstevel@tonic-gate #define CPU_LAST_BRANCH_ADDR 0x00000048 11597c478bd9Sstevel@tonic-gate #define CPU_SPAD_UFLOW_SET 0x0000004c 11607c478bd9Sstevel@tonic-gate /* 0x50 --> 0x200 unused */ 11617c478bd9Sstevel@tonic-gate #define CPU_R0 0x00000200 11627c478bd9Sstevel@tonic-gate #define CPU_R1 0x00000204 11637c478bd9Sstevel@tonic-gate #define CPU_R2 0x00000208 11647c478bd9Sstevel@tonic-gate #define CPU_R3 0x0000020c 11657c478bd9Sstevel@tonic-gate #define CPU_R4 0x00000210 11667c478bd9Sstevel@tonic-gate #define CPU_R5 0x00000214 11677c478bd9Sstevel@tonic-gate #define CPU_R6 0x00000218 11687c478bd9Sstevel@tonic-gate #define CPU_R7 0x0000021c 11697c478bd9Sstevel@tonic-gate #define CPU_R8 0x00000220 11707c478bd9Sstevel@tonic-gate #define CPU_R9 0x00000224 11717c478bd9Sstevel@tonic-gate #define CPU_R10 0x00000228 11727c478bd9Sstevel@tonic-gate #define CPU_R11 0x0000022c 11737c478bd9Sstevel@tonic-gate #define CPU_R12 0x00000230 11747c478bd9Sstevel@tonic-gate #define CPU_R13 0x00000234 11757c478bd9Sstevel@tonic-gate #define CPU_R14 0x00000238 11767c478bd9Sstevel@tonic-gate #define CPU_R15 0x0000023c 11777c478bd9Sstevel@tonic-gate #define CPU_R16 0x00000240 11787c478bd9Sstevel@tonic-gate #define CPU_R17 0x00000244 11797c478bd9Sstevel@tonic-gate #define CPU_R18 0x00000248 11807c478bd9Sstevel@tonic-gate #define CPU_R19 0x0000024c 11817c478bd9Sstevel@tonic-gate #define CPU_R20 0x00000250 11827c478bd9Sstevel@tonic-gate #define CPU_R21 0x00000254 11837c478bd9Sstevel@tonic-gate #define CPU_R22 0x00000258 11847c478bd9Sstevel@tonic-gate #define CPU_R23 0x0000025c 11857c478bd9Sstevel@tonic-gate #define CPU_R24 0x00000260 11867c478bd9Sstevel@tonic-gate #define CPU_R25 0x00000264 11877c478bd9Sstevel@tonic-gate #define CPU_R26 0x00000268 11887c478bd9Sstevel@tonic-gate #define CPU_R27 0x0000026c 11897c478bd9Sstevel@tonic-gate #define CPU_R28 0x00000270 11907c478bd9Sstevel@tonic-gate #define CPU_R29 0x00000274 11917c478bd9Sstevel@tonic-gate #define CPU_R30 0x00000278 11927c478bd9Sstevel@tonic-gate #define CPU_R31 0x0000027c 11937c478bd9Sstevel@tonic-gate /* 0x280 --> 0x400 unused */ 11947c478bd9Sstevel@tonic-gate 11957c478bd9Sstevel@tonic-gate #define RX_CPU_BASE 0x00005000 11967c478bd9Sstevel@tonic-gate #define TX_CPU_BASE 0x00005400 11977c478bd9Sstevel@tonic-gate 11987c478bd9Sstevel@tonic-gate /* Mailboxes */ 11997c478bd9Sstevel@tonic-gate #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */ 12007c478bd9Sstevel@tonic-gate #define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */ 12017c478bd9Sstevel@tonic-gate #define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */ 12027c478bd9Sstevel@tonic-gate #define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */ 12037c478bd9Sstevel@tonic-gate #define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */ 12047c478bd9Sstevel@tonic-gate #define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */ 12057c478bd9Sstevel@tonic-gate #define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */ 12067c478bd9Sstevel@tonic-gate #define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */ 12077c478bd9Sstevel@tonic-gate #define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */ 12087c478bd9Sstevel@tonic-gate #define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */ 12097c478bd9Sstevel@tonic-gate #define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */ 12107c478bd9Sstevel@tonic-gate #define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */ 12117c478bd9Sstevel@tonic-gate #define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */ 12127c478bd9Sstevel@tonic-gate #define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */ 12137c478bd9Sstevel@tonic-gate #define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */ 12147c478bd9Sstevel@tonic-gate #define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */ 12157c478bd9Sstevel@tonic-gate #define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */ 12167c478bd9Sstevel@tonic-gate #define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */ 12177c478bd9Sstevel@tonic-gate #define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */ 12187c478bd9Sstevel@tonic-gate #define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */ 12197c478bd9Sstevel@tonic-gate #define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */ 12207c478bd9Sstevel@tonic-gate #define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */ 12217c478bd9Sstevel@tonic-gate #define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */ 12227c478bd9Sstevel@tonic-gate #define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */ 12237c478bd9Sstevel@tonic-gate #define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */ 12247c478bd9Sstevel@tonic-gate #define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */ 12257c478bd9Sstevel@tonic-gate #define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */ 12267c478bd9Sstevel@tonic-gate #define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */ 12277c478bd9Sstevel@tonic-gate #define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */ 12287c478bd9Sstevel@tonic-gate #define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */ 12297c478bd9Sstevel@tonic-gate #define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */ 12307c478bd9Sstevel@tonic-gate #define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */ 12317c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */ 12327c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */ 12337c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */ 12347c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */ 12357c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */ 12367c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */ 12377c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */ 12387c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */ 12397c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */ 12407c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */ 12417c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */ 12427c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */ 12437c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */ 12447c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */ 12457c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */ 12467c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */ 12477c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */ 12487c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */ 12497c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */ 12507c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */ 12517c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */ 12527c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */ 12537c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */ 12547c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */ 12557c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */ 12567c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */ 12577c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */ 12587c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */ 12597c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */ 12607c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */ 12617c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */ 12627c478bd9Sstevel@tonic-gate #define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */ 12637c478bd9Sstevel@tonic-gate #define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00 12647c478bd9Sstevel@tonic-gate #define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04 12657c478bd9Sstevel@tonic-gate #define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08 12667c478bd9Sstevel@tonic-gate #define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c 12677c478bd9Sstevel@tonic-gate /* 0x5a10 --> 0x5c00 */ 12687c478bd9Sstevel@tonic-gate 12697c478bd9Sstevel@tonic-gate /* Flow Through queues */ 12707c478bd9Sstevel@tonic-gate #define FTQ_RESET 0x00005c00 12717c478bd9Sstevel@tonic-gate /* 0x5c04 --> 0x5c10 unused */ 12727c478bd9Sstevel@tonic-gate #define FTQ_DMA_NORM_READ_CTL 0x00005c10 12737c478bd9Sstevel@tonic-gate #define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14 12747c478bd9Sstevel@tonic-gate #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18 12757c478bd9Sstevel@tonic-gate #define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c 12767c478bd9Sstevel@tonic-gate #define FTQ_DMA_HIGH_READ_CTL 0x00005c20 12777c478bd9Sstevel@tonic-gate #define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24 12787c478bd9Sstevel@tonic-gate #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28 12797c478bd9Sstevel@tonic-gate #define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c 12807c478bd9Sstevel@tonic-gate #define FTQ_DMA_COMP_DISC_CTL 0x00005c30 12817c478bd9Sstevel@tonic-gate #define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34 12827c478bd9Sstevel@tonic-gate #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38 12837c478bd9Sstevel@tonic-gate #define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c 12847c478bd9Sstevel@tonic-gate #define FTQ_SEND_BD_COMP_CTL 0x00005c40 12857c478bd9Sstevel@tonic-gate #define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44 12867c478bd9Sstevel@tonic-gate #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48 12877c478bd9Sstevel@tonic-gate #define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c 12887c478bd9Sstevel@tonic-gate #define FTQ_SEND_DATA_INIT_CTL 0x00005c50 12897c478bd9Sstevel@tonic-gate #define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54 12907c478bd9Sstevel@tonic-gate #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58 12917c478bd9Sstevel@tonic-gate #define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c 12927c478bd9Sstevel@tonic-gate #define FTQ_DMA_NORM_WRITE_CTL 0x00005c60 12937c478bd9Sstevel@tonic-gate #define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64 12947c478bd9Sstevel@tonic-gate #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68 12957c478bd9Sstevel@tonic-gate #define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c 12967c478bd9Sstevel@tonic-gate #define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70 12977c478bd9Sstevel@tonic-gate #define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74 12987c478bd9Sstevel@tonic-gate #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78 12997c478bd9Sstevel@tonic-gate #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c 13007c478bd9Sstevel@tonic-gate #define FTQ_SWTYPE1_CTL 0x00005c80 13017c478bd9Sstevel@tonic-gate #define FTQ_SWTYPE1_FULL_CNT 0x00005c84 13027c478bd9Sstevel@tonic-gate #define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88 13037c478bd9Sstevel@tonic-gate #define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c 13047c478bd9Sstevel@tonic-gate #define FTQ_SEND_DATA_COMP_CTL 0x00005c90 13057c478bd9Sstevel@tonic-gate #define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94 13067c478bd9Sstevel@tonic-gate #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98 13077c478bd9Sstevel@tonic-gate #define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c 13087c478bd9Sstevel@tonic-gate #define FTQ_HOST_COAL_CTL 0x00005ca0 13097c478bd9Sstevel@tonic-gate #define FTQ_HOST_COAL_FULL_CNT 0x00005ca4 13107c478bd9Sstevel@tonic-gate #define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8 13117c478bd9Sstevel@tonic-gate #define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac 13127c478bd9Sstevel@tonic-gate #define FTQ_MAC_TX_CTL 0x00005cb0 13137c478bd9Sstevel@tonic-gate #define FTQ_MAC_TX_FULL_CNT 0x00005cb4 13147c478bd9Sstevel@tonic-gate #define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8 13157c478bd9Sstevel@tonic-gate #define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc 13167c478bd9Sstevel@tonic-gate #define FTQ_MB_FREE_CTL 0x00005cc0 13177c478bd9Sstevel@tonic-gate #define FTQ_MB_FREE_FULL_CNT 0x00005cc4 13187c478bd9Sstevel@tonic-gate #define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8 13197c478bd9Sstevel@tonic-gate #define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc 13207c478bd9Sstevel@tonic-gate #define FTQ_RCVBD_COMP_CTL 0x00005cd0 13217c478bd9Sstevel@tonic-gate #define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4 13227c478bd9Sstevel@tonic-gate #define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8 13237c478bd9Sstevel@tonic-gate #define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc 13247c478bd9Sstevel@tonic-gate #define FTQ_RCVLST_PLMT_CTL 0x00005ce0 13257c478bd9Sstevel@tonic-gate #define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4 13267c478bd9Sstevel@tonic-gate #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8 13277c478bd9Sstevel@tonic-gate #define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec 13287c478bd9Sstevel@tonic-gate #define FTQ_RCVDATA_INI_CTL 0x00005cf0 13297c478bd9Sstevel@tonic-gate #define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4 13307c478bd9Sstevel@tonic-gate #define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8 13317c478bd9Sstevel@tonic-gate #define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc 13327c478bd9Sstevel@tonic-gate #define FTQ_RCVDATA_COMP_CTL 0x00005d00 13337c478bd9Sstevel@tonic-gate #define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04 13347c478bd9Sstevel@tonic-gate #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08 13357c478bd9Sstevel@tonic-gate #define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c 13367c478bd9Sstevel@tonic-gate #define FTQ_SWTYPE2_CTL 0x00005d10 13377c478bd9Sstevel@tonic-gate #define FTQ_SWTYPE2_FULL_CNT 0x00005d14 13387c478bd9Sstevel@tonic-gate #define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18 13397c478bd9Sstevel@tonic-gate #define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c 13407c478bd9Sstevel@tonic-gate /* 0x5d20 --> 0x6000 unused */ 13417c478bd9Sstevel@tonic-gate 13427c478bd9Sstevel@tonic-gate /* Message signaled interrupt registers */ 13437c478bd9Sstevel@tonic-gate #define MSGINT_MODE 0x00006000 13447c478bd9Sstevel@tonic-gate #define MSGINT_MODE_RESET 0x00000001 13457c478bd9Sstevel@tonic-gate #define MSGINT_MODE_ENABLE 0x00000002 13467c478bd9Sstevel@tonic-gate #define MSGINT_STATUS 0x00006004 13477c478bd9Sstevel@tonic-gate #define MSGINT_FIFO 0x00006008 13487c478bd9Sstevel@tonic-gate /* 0x600c --> 0x6400 unused */ 13497c478bd9Sstevel@tonic-gate 13507c478bd9Sstevel@tonic-gate /* DMA completion registers */ 13517c478bd9Sstevel@tonic-gate #define DMAC_MODE 0x00006400 13527c478bd9Sstevel@tonic-gate #define DMAC_MODE_RESET 0x00000001 13537c478bd9Sstevel@tonic-gate #define DMAC_MODE_ENABLE 0x00000002 13547c478bd9Sstevel@tonic-gate /* 0x6404 --> 0x6800 unused */ 13557c478bd9Sstevel@tonic-gate 13567c478bd9Sstevel@tonic-gate /* GRC registers */ 13577c478bd9Sstevel@tonic-gate #define GRC_MODE 0x00006800 13587c478bd9Sstevel@tonic-gate #define GRC_MODE_UPD_ON_COAL 0x00000001 13597c478bd9Sstevel@tonic-gate #define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002 13607c478bd9Sstevel@tonic-gate #define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004 13617c478bd9Sstevel@tonic-gate #define GRC_MODE_BSWAP_DATA 0x00000010 13627c478bd9Sstevel@tonic-gate #define GRC_MODE_WSWAP_DATA 0x00000020 13637c478bd9Sstevel@tonic-gate #define GRC_MODE_SPLITHDR 0x00000100 13647c478bd9Sstevel@tonic-gate #define GRC_MODE_NOFRM_CRACKING 0x00000200 13657c478bd9Sstevel@tonic-gate #define GRC_MODE_INCL_CRC 0x00000400 13667c478bd9Sstevel@tonic-gate #define GRC_MODE_ALLOW_BAD_FRMS 0x00000800 13677c478bd9Sstevel@tonic-gate #define GRC_MODE_NOIRQ_ON_SENDS 0x00002000 13687c478bd9Sstevel@tonic-gate #define GRC_MODE_NOIRQ_ON_RCV 0x00004000 13697c478bd9Sstevel@tonic-gate #define GRC_MODE_FORCE_PCI32BIT 0x00008000 13707c478bd9Sstevel@tonic-gate #define GRC_MODE_HOST_STACKUP 0x00010000 13717c478bd9Sstevel@tonic-gate #define GRC_MODE_HOST_SENDBDS 0x00020000 13727c478bd9Sstevel@tonic-gate #define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000 13737c478bd9Sstevel@tonic-gate #define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000 13747c478bd9Sstevel@tonic-gate #define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000 13757c478bd9Sstevel@tonic-gate #define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000 13767c478bd9Sstevel@tonic-gate #define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000 13777c478bd9Sstevel@tonic-gate #define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000 13787c478bd9Sstevel@tonic-gate #define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000 13797c478bd9Sstevel@tonic-gate #define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000 13807c478bd9Sstevel@tonic-gate #define GRC_MODE_MCAST_FRM_ENABLE 0x40000000 13817c478bd9Sstevel@tonic-gate #define GRC_MISC_CFG 0x00006804 13827c478bd9Sstevel@tonic-gate #define GRC_MISC_CFG_CORECLK_RESET 0x00000001 13837c478bd9Sstevel@tonic-gate #define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe 13847c478bd9Sstevel@tonic-gate #define GRC_MISC_CFG_PRESCALAR_SHIFT 1 13857c478bd9Sstevel@tonic-gate #define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000 13867c478bd9Sstevel@tonic-gate #define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000 13877c478bd9Sstevel@tonic-gate #define GRC_MISC_CFG_BOARD_ID_5701 0x00000000 13887c478bd9Sstevel@tonic-gate #define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000 13897c478bd9Sstevel@tonic-gate #define GRC_MISC_CFG_BOARD_ID_5703 0x00000000 13907c478bd9Sstevel@tonic-gate #define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000 13917c478bd9Sstevel@tonic-gate #define GRC_MISC_CFG_BOARD_ID_5704 0x00000000 13927c478bd9Sstevel@tonic-gate #define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000 13937c478bd9Sstevel@tonic-gate #define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000 13947c478bd9Sstevel@tonic-gate #define GRC_MISC_CFG_BOARD_ID_5788 0x00010000 13957c478bd9Sstevel@tonic-gate #define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000 13967c478bd9Sstevel@tonic-gate #define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000 13977c478bd9Sstevel@tonic-gate #define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000 13987c478bd9Sstevel@tonic-gate #define GRC_LOCAL_CTRL 0x00006808 13997c478bd9Sstevel@tonic-gate #define GRC_LCLCTRL_INT_ACTIVE 0x00000001 14007c478bd9Sstevel@tonic-gate #define GRC_LCLCTRL_CLEARINT 0x00000002 14017c478bd9Sstevel@tonic-gate #define GRC_LCLCTRL_SETINT 0x00000004 14027c478bd9Sstevel@tonic-gate #define GRC_LCLCTRL_INT_ON_ATTN 0x00000008 14037c478bd9Sstevel@tonic-gate #define GRC_LCLCTRL_GPIO_INPUT0 0x00000100 14047c478bd9Sstevel@tonic-gate #define GRC_LCLCTRL_GPIO_INPUT1 0x00000200 14057c478bd9Sstevel@tonic-gate #define GRC_LCLCTRL_GPIO_INPUT2 0x00000400 14067c478bd9Sstevel@tonic-gate #define GRC_LCLCTRL_GPIO_OE0 0x00000800 14077c478bd9Sstevel@tonic-gate #define GRC_LCLCTRL_GPIO_OE1 0x00001000 14087c478bd9Sstevel@tonic-gate #define GRC_LCLCTRL_GPIO_OE2 0x00002000 14097c478bd9Sstevel@tonic-gate #define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000 14107c478bd9Sstevel@tonic-gate #define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000 14117c478bd9Sstevel@tonic-gate #define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000 14127c478bd9Sstevel@tonic-gate #define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000 14137c478bd9Sstevel@tonic-gate #define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000 14147c478bd9Sstevel@tonic-gate #define GRC_LCLCTRL_MEMSZ_256K 0x00000000 14157c478bd9Sstevel@tonic-gate #define GRC_LCLCTRL_MEMSZ_512K 0x00040000 14167c478bd9Sstevel@tonic-gate #define GRC_LCLCTRL_MEMSZ_1M 0x00080000 14177c478bd9Sstevel@tonic-gate #define GRC_LCLCTRL_MEMSZ_2M 0x000c0000 14187c478bd9Sstevel@tonic-gate #define GRC_LCLCTRL_MEMSZ_4M 0x00100000 14197c478bd9Sstevel@tonic-gate #define GRC_LCLCTRL_MEMSZ_8M 0x00140000 14207c478bd9Sstevel@tonic-gate #define GRC_LCLCTRL_MEMSZ_16M 0x00180000 14217c478bd9Sstevel@tonic-gate #define GRC_LCLCTRL_BANK_SELECT 0x00200000 14227c478bd9Sstevel@tonic-gate #define GRC_LCLCTRL_SSRAM_TYPE 0x00400000 14237c478bd9Sstevel@tonic-gate #define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000 14247c478bd9Sstevel@tonic-gate #define GRC_TIMER 0x0000680c 14257c478bd9Sstevel@tonic-gate #define GRC_RX_CPU_EVENT 0x00006810 14267c478bd9Sstevel@tonic-gate #define GRC_RX_TIMER_REF 0x00006814 14277c478bd9Sstevel@tonic-gate #define GRC_RX_CPU_SEM 0x00006818 14287c478bd9Sstevel@tonic-gate #define GRC_REMOTE_RX_CPU_ATTN 0x0000681c 14297c478bd9Sstevel@tonic-gate #define GRC_TX_CPU_EVENT 0x00006820 14307c478bd9Sstevel@tonic-gate #define GRC_TX_TIMER_REF 0x00006824 14317c478bd9Sstevel@tonic-gate #define GRC_TX_CPU_SEM 0x00006828 14327c478bd9Sstevel@tonic-gate #define GRC_REMOTE_TX_CPU_ATTN 0x0000682c 14337c478bd9Sstevel@tonic-gate #define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */ 14347c478bd9Sstevel@tonic-gate #define GRC_EEPROM_ADDR 0x00006838 14357c478bd9Sstevel@tonic-gate #define EEPROM_ADDR_WRITE 0x00000000 14367c478bd9Sstevel@tonic-gate #define EEPROM_ADDR_READ 0x80000000 14377c478bd9Sstevel@tonic-gate #define EEPROM_ADDR_COMPLETE 0x40000000 14387c478bd9Sstevel@tonic-gate #define EEPROM_ADDR_FSM_RESET 0x20000000 14397c478bd9Sstevel@tonic-gate #define EEPROM_ADDR_DEVID_MASK 0x1c000000 14407c478bd9Sstevel@tonic-gate #define EEPROM_ADDR_DEVID_SHIFT 26 14417c478bd9Sstevel@tonic-gate #define EEPROM_ADDR_START 0x02000000 14427c478bd9Sstevel@tonic-gate #define EEPROM_ADDR_CLKPERD_SHIFT 16 14437c478bd9Sstevel@tonic-gate #define EEPROM_ADDR_ADDR_MASK 0x0000ffff 14447c478bd9Sstevel@tonic-gate #define EEPROM_ADDR_ADDR_SHIFT 0 14457c478bd9Sstevel@tonic-gate #define EEPROM_DEFAULT_CLOCK_PERIOD 0x60 14467c478bd9Sstevel@tonic-gate #define EEPROM_CHIP_SIZE (64 * 1024) 14477c478bd9Sstevel@tonic-gate #define GRC_EEPROM_DATA 0x0000683c 14487c478bd9Sstevel@tonic-gate #define GRC_EEPROM_CTRL 0x00006840 14497c478bd9Sstevel@tonic-gate #define GRC_MDI_CTRL 0x00006844 14507c478bd9Sstevel@tonic-gate #define GRC_SEEPROM_DELAY 0x00006848 14517c478bd9Sstevel@tonic-gate /* 0x684c --> 0x6c00 unused */ 14527c478bd9Sstevel@tonic-gate 14537c478bd9Sstevel@tonic-gate /* 0x6c00 --> 0x7000 unused */ 14547c478bd9Sstevel@tonic-gate 14557c478bd9Sstevel@tonic-gate /* NVRAM Control registers */ 14567c478bd9Sstevel@tonic-gate #define NVRAM_CMD 0x00007000 14577c478bd9Sstevel@tonic-gate #define NVRAM_CMD_RESET 0x00000001 14587c478bd9Sstevel@tonic-gate #define NVRAM_CMD_DONE 0x00000008 14597c478bd9Sstevel@tonic-gate #define NVRAM_CMD_GO 0x00000010 14607c478bd9Sstevel@tonic-gate #define NVRAM_CMD_WR 0x00000020 14617c478bd9Sstevel@tonic-gate #define NVRAM_CMD_RD 0x00000000 14627c478bd9Sstevel@tonic-gate #define NVRAM_CMD_ERASE 0x00000040 14637c478bd9Sstevel@tonic-gate #define NVRAM_CMD_FIRST 0x00000080 14647c478bd9Sstevel@tonic-gate #define NVRAM_CMD_LAST 0x00000100 14657c478bd9Sstevel@tonic-gate #define NVRAM_STAT 0x00007004 14667c478bd9Sstevel@tonic-gate #define NVRAM_WRDATA 0x00007008 14677c478bd9Sstevel@tonic-gate #define NVRAM_ADDR 0x0000700c 14687c478bd9Sstevel@tonic-gate #define NVRAM_ADDR_MSK 0x00ffffff 14697c478bd9Sstevel@tonic-gate #define NVRAM_RDDATA 0x00007010 14707c478bd9Sstevel@tonic-gate #define NVRAM_CFG1 0x00007014 14717c478bd9Sstevel@tonic-gate #define NVRAM_CFG1_FLASHIF_ENAB 0x00000001 14727c478bd9Sstevel@tonic-gate #define NVRAM_CFG1_BUFFERED_MODE 0x00000002 14737c478bd9Sstevel@tonic-gate #define NVRAM_CFG1_PASS_THRU 0x00000004 14747c478bd9Sstevel@tonic-gate #define NVRAM_CFG1_BIT_BANG 0x00000008 14757c478bd9Sstevel@tonic-gate #define NVRAM_CFG1_COMPAT_BYPASS 0x80000000 14767c478bd9Sstevel@tonic-gate #define NVRAM_CFG2 0x00007018 14777c478bd9Sstevel@tonic-gate #define NVRAM_CFG3 0x0000701c 14787c478bd9Sstevel@tonic-gate #define NVRAM_SWARB 0x00007020 14797c478bd9Sstevel@tonic-gate #define SWARB_REQ_SET0 0x00000001 14807c478bd9Sstevel@tonic-gate #define SWARB_REQ_SET1 0x00000002 14817c478bd9Sstevel@tonic-gate #define SWARB_REQ_SET2 0x00000004 14827c478bd9Sstevel@tonic-gate #define SWARB_REQ_SET3 0x00000008 14837c478bd9Sstevel@tonic-gate #define SWARB_REQ_CLR0 0x00000010 14847c478bd9Sstevel@tonic-gate #define SWARB_REQ_CLR1 0x00000020 14857c478bd9Sstevel@tonic-gate #define SWARB_REQ_CLR2 0x00000040 14867c478bd9Sstevel@tonic-gate #define SWARB_REQ_CLR3 0x00000080 14877c478bd9Sstevel@tonic-gate #define SWARB_GNT0 0x00000100 14887c478bd9Sstevel@tonic-gate #define SWARB_GNT1 0x00000200 14897c478bd9Sstevel@tonic-gate #define SWARB_GNT2 0x00000400 14907c478bd9Sstevel@tonic-gate #define SWARB_GNT3 0x00000800 14917c478bd9Sstevel@tonic-gate #define SWARB_REQ0 0x00001000 14927c478bd9Sstevel@tonic-gate #define SWARB_REQ1 0x00002000 14937c478bd9Sstevel@tonic-gate #define SWARB_REQ2 0x00004000 14947c478bd9Sstevel@tonic-gate #define SWARB_REQ3 0x00008000 14957c478bd9Sstevel@tonic-gate #define NVRAM_BUFFERED_PAGE_SIZE 264 14967c478bd9Sstevel@tonic-gate #define NVRAM_BUFFERED_PAGE_POS 9 14977c478bd9Sstevel@tonic-gate /* 0x7024 --> 0x7400 unused */ 14987c478bd9Sstevel@tonic-gate 14997c478bd9Sstevel@tonic-gate /* 0x7400 --> 0x8000 unused */ 15007c478bd9Sstevel@tonic-gate 15017c478bd9Sstevel@tonic-gate /* 32K Window into NIC internal memory */ 15027c478bd9Sstevel@tonic-gate #define NIC_SRAM_WIN_BASE 0x00008000 15037c478bd9Sstevel@tonic-gate 15047c478bd9Sstevel@tonic-gate /* Offsets into first 32k of NIC internal memory. */ 15057c478bd9Sstevel@tonic-gate #define NIC_SRAM_PAGE_ZERO 0x00000000 15067c478bd9Sstevel@tonic-gate #define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */ 15077c478bd9Sstevel@tonic-gate #define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */ 15087c478bd9Sstevel@tonic-gate #define NIC_SRAM_STATS_BLK 0x00000300 15097c478bd9Sstevel@tonic-gate #define NIC_SRAM_STATUS_BLK 0x00000b00 15107c478bd9Sstevel@tonic-gate 15117c478bd9Sstevel@tonic-gate #define NIC_SRAM_FIRMWARE_MBOX 0x00000b50 15127c478bd9Sstevel@tonic-gate #define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654 15137c478bd9Sstevel@tonic-gate #define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */ 15147c478bd9Sstevel@tonic-gate 15157c478bd9Sstevel@tonic-gate #define NIC_SRAM_DATA_SIG 0x00000b54 15167c478bd9Sstevel@tonic-gate #define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */ 15177c478bd9Sstevel@tonic-gate 15187c478bd9Sstevel@tonic-gate #define NIC_SRAM_DATA_CFG 0x00000b58 15197c478bd9Sstevel@tonic-gate #define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c 15207c478bd9Sstevel@tonic-gate #define NIC_SRAM_DATA_CFG_LED_MODE_UNKNOWN 0x00000000 15217c478bd9Sstevel@tonic-gate #define NIC_SRAM_DATA_CFG_LED_TRIPLE_SPD 0x00000004 15227c478bd9Sstevel@tonic-gate #define NIC_SRAM_DATA_CFG_LED_OPEN_DRAIN 0x00000004 15237c478bd9Sstevel@tonic-gate #define NIC_SRAM_DATA_CFG_LED_LINK_SPD 0x00000008 15247c478bd9Sstevel@tonic-gate #define NIC_SRAM_DATA_CFG_LED_OUTPUT 0x00000008 15257c478bd9Sstevel@tonic-gate #define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030 15267c478bd9Sstevel@tonic-gate #define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000 15277c478bd9Sstevel@tonic-gate #define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010 15287c478bd9Sstevel@tonic-gate #define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020 15297c478bd9Sstevel@tonic-gate #define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040 15307c478bd9Sstevel@tonic-gate #define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080 15317c478bd9Sstevel@tonic-gate #define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100 15327c478bd9Sstevel@tonic-gate #define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000 15337c478bd9Sstevel@tonic-gate #define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000 15347c478bd9Sstevel@tonic-gate 15357c478bd9Sstevel@tonic-gate #define NIC_SRAM_DATA_PHY_ID 0x00000b74 15367c478bd9Sstevel@tonic-gate #define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000 15377c478bd9Sstevel@tonic-gate #define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff 15387c478bd9Sstevel@tonic-gate 15397c478bd9Sstevel@tonic-gate #define NIC_SRAM_FW_CMD_MBOX 0x00000b78 15407c478bd9Sstevel@tonic-gate #define FWCMD_NICDRV_ALIVE 0x00000001 15417c478bd9Sstevel@tonic-gate #define FWCMD_NICDRV_PAUSE_FW 0x00000002 15427c478bd9Sstevel@tonic-gate #define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003 15437c478bd9Sstevel@tonic-gate #define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004 15447c478bd9Sstevel@tonic-gate #define FWCMD_NICDRV_FIX_DMAR 0x00000005 15457c478bd9Sstevel@tonic-gate #define FWCMD_NICDRV_FIX_DMAW 0x00000006 15467c478bd9Sstevel@tonic-gate #define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c 15477c478bd9Sstevel@tonic-gate #define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80 15487c478bd9Sstevel@tonic-gate #define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00 15497c478bd9Sstevel@tonic-gate #define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04 15507c478bd9Sstevel@tonic-gate #define DRV_STATE_START 0x00000001 15517c478bd9Sstevel@tonic-gate #define DRV_STATE_UNLOAD 0x00000002 15527c478bd9Sstevel@tonic-gate #define DRV_STATE_WOL 0x00000003 15537c478bd9Sstevel@tonic-gate #define DRV_STATE_SUSPEND 0x00000004 15547c478bd9Sstevel@tonic-gate 15557c478bd9Sstevel@tonic-gate #define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08 15567c478bd9Sstevel@tonic-gate 15577c478bd9Sstevel@tonic-gate #define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14 15587c478bd9Sstevel@tonic-gate #define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18 15597c478bd9Sstevel@tonic-gate 15607c478bd9Sstevel@tonic-gate #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000 15617c478bd9Sstevel@tonic-gate 15627c478bd9Sstevel@tonic-gate #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000 15637c478bd9Sstevel@tonic-gate #define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000 15647c478bd9Sstevel@tonic-gate #define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */ 15657c478bd9Sstevel@tonic-gate #define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */ 15667c478bd9Sstevel@tonic-gate #define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */ 15677c478bd9Sstevel@tonic-gate #define NIC_SRAM_MBUF_POOL_BASE 0x00008000 15687c478bd9Sstevel@tonic-gate #define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000 15697c478bd9Sstevel@tonic-gate #define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000 15707c478bd9Sstevel@tonic-gate #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000 15717c478bd9Sstevel@tonic-gate #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000 15727c478bd9Sstevel@tonic-gate 15737c478bd9Sstevel@tonic-gate /* Currently this is fixed. */ 15747c478bd9Sstevel@tonic-gate #define PHY_ADDR 0x01 15757c478bd9Sstevel@tonic-gate 15767c478bd9Sstevel@tonic-gate /* Tigon3 specific PHY MII registers. */ 15777c478bd9Sstevel@tonic-gate #define TG3_BMCR_SPEED1000 0x0040 15787c478bd9Sstevel@tonic-gate 15797c478bd9Sstevel@tonic-gate #define MII_TG3_CTRL 0x09 /* 1000-baseT control register */ 15807c478bd9Sstevel@tonic-gate #define MII_TG3_CTRL_ADV_1000_HALF 0x0100 15817c478bd9Sstevel@tonic-gate #define MII_TG3_CTRL_ADV_1000_FULL 0x0200 15827c478bd9Sstevel@tonic-gate #define MII_TG3_CTRL_AS_MASTER 0x0800 15837c478bd9Sstevel@tonic-gate #define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000 15847c478bd9Sstevel@tonic-gate 15857c478bd9Sstevel@tonic-gate #define MII_TG3_EXT_CTRL 0x10 /* Extended control register */ 15867c478bd9Sstevel@tonic-gate #define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002 15877c478bd9Sstevel@tonic-gate #define MII_TG3_EXT_CTRL_TBI 0x8000 15887c478bd9Sstevel@tonic-gate 15897c478bd9Sstevel@tonic-gate #define MII_TG3_EXT_STAT 0x11 /* Extended status register */ 15907c478bd9Sstevel@tonic-gate #define MII_TG3_EXT_STAT_LPASS 0x0100 15917c478bd9Sstevel@tonic-gate 15927c478bd9Sstevel@tonic-gate #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */ 15937c478bd9Sstevel@tonic-gate 15947c478bd9Sstevel@tonic-gate #define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */ 15957c478bd9Sstevel@tonic-gate 15967c478bd9Sstevel@tonic-gate #define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */ 15977c478bd9Sstevel@tonic-gate 15987c478bd9Sstevel@tonic-gate #define MII_TG3_AUX_STAT 0x19 /* auxilliary status register */ 15997c478bd9Sstevel@tonic-gate #define MII_TG3_AUX_STAT_LPASS 0x0004 16007c478bd9Sstevel@tonic-gate #define MII_TG3_AUX_STAT_SPDMASK 0x0700 16017c478bd9Sstevel@tonic-gate #define MII_TG3_AUX_STAT_10HALF 0x0100 16027c478bd9Sstevel@tonic-gate #define MII_TG3_AUX_STAT_10FULL 0x0200 16037c478bd9Sstevel@tonic-gate #define MII_TG3_AUX_STAT_100HALF 0x0300 16047c478bd9Sstevel@tonic-gate #define MII_TG3_AUX_STAT_100_4 0x0400 16057c478bd9Sstevel@tonic-gate #define MII_TG3_AUX_STAT_100FULL 0x0500 16067c478bd9Sstevel@tonic-gate #define MII_TG3_AUX_STAT_1000HALF 0x0600 16077c478bd9Sstevel@tonic-gate #define MII_TG3_AUX_STAT_1000FULL 0x0700 16087c478bd9Sstevel@tonic-gate 16097c478bd9Sstevel@tonic-gate #define MII_TG3_ISTAT 0x1a /* IRQ status register */ 16107c478bd9Sstevel@tonic-gate #define MII_TG3_IMASK 0x1b /* IRQ mask register */ 16117c478bd9Sstevel@tonic-gate 16127c478bd9Sstevel@tonic-gate /* ISTAT/IMASK event bits */ 16137c478bd9Sstevel@tonic-gate #define MII_TG3_INT_LINKCHG 0x0002 16147c478bd9Sstevel@tonic-gate #define MII_TG3_INT_SPEEDCHG 0x0004 16157c478bd9Sstevel@tonic-gate #define MII_TG3_INT_DUPLEXCHG 0x0008 16167c478bd9Sstevel@tonic-gate #define MII_TG3_INT_ANEG_PAGE_RX 0x0400 16177c478bd9Sstevel@tonic-gate 16187c478bd9Sstevel@tonic-gate /* XXX Add this to mii.h */ 16197c478bd9Sstevel@tonic-gate #ifndef ADVERTISE_PAUSE 16207c478bd9Sstevel@tonic-gate #define ADVERTISE_PAUSE_CAP 0x0400 16217c478bd9Sstevel@tonic-gate #endif 16227c478bd9Sstevel@tonic-gate #ifndef ADVERTISE_PAUSE_ASYM 16237c478bd9Sstevel@tonic-gate #define ADVERTISE_PAUSE_ASYM 0x0800 16247c478bd9Sstevel@tonic-gate #endif 16257c478bd9Sstevel@tonic-gate #ifndef LPA_PAUSE 16267c478bd9Sstevel@tonic-gate #define LPA_PAUSE_CAP 0x0400 16277c478bd9Sstevel@tonic-gate #endif 16287c478bd9Sstevel@tonic-gate #ifndef LPA_PAUSE_ASYM 16297c478bd9Sstevel@tonic-gate #define LPA_PAUSE_ASYM 0x0800 16307c478bd9Sstevel@tonic-gate #endif 16317c478bd9Sstevel@tonic-gate 16327c478bd9Sstevel@tonic-gate /* There are two ways to manage the TX descriptors on the tigon3. 16337c478bd9Sstevel@tonic-gate * Either the descriptors are in host DMA'able memory, or they 16347c478bd9Sstevel@tonic-gate * exist only in the cards on-chip SRAM. All 16 send bds are under 16357c478bd9Sstevel@tonic-gate * the same mode, they may not be configured individually. 16367c478bd9Sstevel@tonic-gate * 16377c478bd9Sstevel@tonic-gate * The mode we use is controlled by TG3_FLAG_HOST_TXDS in tp->tg3_flags. 16387c478bd9Sstevel@tonic-gate * 16397c478bd9Sstevel@tonic-gate * To use host memory TX descriptors: 16407c478bd9Sstevel@tonic-gate * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register. 16417c478bd9Sstevel@tonic-gate * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear. 16427c478bd9Sstevel@tonic-gate * 2) Allocate DMA'able memory. 16437c478bd9Sstevel@tonic-gate * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM: 16447c478bd9Sstevel@tonic-gate * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory 16457c478bd9Sstevel@tonic-gate * obtained in step 2 16467c478bd9Sstevel@tonic-gate * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC. 16477c478bd9Sstevel@tonic-gate * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number 16487c478bd9Sstevel@tonic-gate * of TX descriptors. Leave flags field clear. 16497c478bd9Sstevel@tonic-gate * 4) Access TX descriptors via host memory. The chip 16507c478bd9Sstevel@tonic-gate * will refetch into local SRAM as needed when producer 16517c478bd9Sstevel@tonic-gate * index mailboxes are updated. 16527c478bd9Sstevel@tonic-gate * 16537c478bd9Sstevel@tonic-gate * To use on-chip TX descriptors: 16547c478bd9Sstevel@tonic-gate * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register. 16557c478bd9Sstevel@tonic-gate * Make sure GRC_MODE_HOST_SENDBDS is clear. 16567c478bd9Sstevel@tonic-gate * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM: 16577c478bd9Sstevel@tonic-gate * a) Set TG3_BDINFO_HOST_ADDR to zero. 16587c478bd9Sstevel@tonic-gate * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC 16597c478bd9Sstevel@tonic-gate * c) TG3_BDINFO_MAXLEN_FLAGS is don't care. 16607c478bd9Sstevel@tonic-gate * 3) Access TX descriptors directly in on-chip SRAM 16617c478bd9Sstevel@tonic-gate * using normal {read,write}l(). (and not using 16627c478bd9Sstevel@tonic-gate * pointer dereferencing of ioremap()'d memory like 16637c478bd9Sstevel@tonic-gate * the broken Broadcom driver does) 16647c478bd9Sstevel@tonic-gate * 16657c478bd9Sstevel@tonic-gate * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of 16667c478bd9Sstevel@tonic-gate * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices. 16677c478bd9Sstevel@tonic-gate */ 16687c478bd9Sstevel@tonic-gate struct tg3_tx_buffer_desc { 16697c478bd9Sstevel@tonic-gate uint32_t addr_hi; 16707c478bd9Sstevel@tonic-gate uint32_t addr_lo; 16717c478bd9Sstevel@tonic-gate 16727c478bd9Sstevel@tonic-gate uint32_t len_flags; 16737c478bd9Sstevel@tonic-gate #define TXD_FLAG_TCPUDP_CSUM 0x0001 16747c478bd9Sstevel@tonic-gate #define TXD_FLAG_IP_CSUM 0x0002 16757c478bd9Sstevel@tonic-gate #define TXD_FLAG_END 0x0004 16767c478bd9Sstevel@tonic-gate #define TXD_FLAG_IP_FRAG 0x0008 16777c478bd9Sstevel@tonic-gate #define TXD_FLAG_IP_FRAG_END 0x0010 16787c478bd9Sstevel@tonic-gate #define TXD_FLAG_VLAN 0x0040 16797c478bd9Sstevel@tonic-gate #define TXD_FLAG_COAL_NOW 0x0080 16807c478bd9Sstevel@tonic-gate #define TXD_FLAG_CPU_PRE_DMA 0x0100 16817c478bd9Sstevel@tonic-gate #define TXD_FLAG_CPU_POST_DMA 0x0200 16827c478bd9Sstevel@tonic-gate #define TXD_FLAG_ADD_SRC_ADDR 0x1000 16837c478bd9Sstevel@tonic-gate #define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000 16847c478bd9Sstevel@tonic-gate #define TXD_FLAG_NO_CRC 0x8000 16857c478bd9Sstevel@tonic-gate #define TXD_LEN_SHIFT 16 16867c478bd9Sstevel@tonic-gate 16877c478bd9Sstevel@tonic-gate uint32_t vlan_tag; 16887c478bd9Sstevel@tonic-gate #define TXD_VLAN_TAG_SHIFT 0 16897c478bd9Sstevel@tonic-gate #define TXD_MSS_SHIFT 16 16907c478bd9Sstevel@tonic-gate }; 16917c478bd9Sstevel@tonic-gate 16927c478bd9Sstevel@tonic-gate #define TXD_ADDR 0x00UL /* 64-bit */ 16937c478bd9Sstevel@tonic-gate #define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */ 16947c478bd9Sstevel@tonic-gate #define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */ 16957c478bd9Sstevel@tonic-gate #define TXD_SIZE 0x10UL 16967c478bd9Sstevel@tonic-gate 16977c478bd9Sstevel@tonic-gate struct tg3_rx_buffer_desc { 16987c478bd9Sstevel@tonic-gate uint32_t addr_hi; 16997c478bd9Sstevel@tonic-gate uint32_t addr_lo; 17007c478bd9Sstevel@tonic-gate 17017c478bd9Sstevel@tonic-gate uint32_t idx_len; 17027c478bd9Sstevel@tonic-gate #define RXD_IDX_MASK 0xffff0000 17037c478bd9Sstevel@tonic-gate #define RXD_IDX_SHIFT 16 17047c478bd9Sstevel@tonic-gate #define RXD_LEN_MASK 0x0000ffff 17057c478bd9Sstevel@tonic-gate #define RXD_LEN_SHIFT 0 17067c478bd9Sstevel@tonic-gate 17077c478bd9Sstevel@tonic-gate uint32_t type_flags; 17087c478bd9Sstevel@tonic-gate #define RXD_TYPE_SHIFT 16 17097c478bd9Sstevel@tonic-gate #define RXD_FLAGS_SHIFT 0 17107c478bd9Sstevel@tonic-gate 17117c478bd9Sstevel@tonic-gate #define RXD_FLAG_END 0x0004 17127c478bd9Sstevel@tonic-gate #define RXD_FLAG_MINI 0x0800 17137c478bd9Sstevel@tonic-gate #define RXD_FLAG_JUMBO 0x0020 17147c478bd9Sstevel@tonic-gate #define RXD_FLAG_VLAN 0x0040 17157c478bd9Sstevel@tonic-gate #define RXD_FLAG_ERROR 0x0400 17167c478bd9Sstevel@tonic-gate #define RXD_FLAG_IP_CSUM 0x1000 17177c478bd9Sstevel@tonic-gate #define RXD_FLAG_TCPUDP_CSUM 0x2000 17187c478bd9Sstevel@tonic-gate #define RXD_FLAG_IS_TCP 0x4000 17197c478bd9Sstevel@tonic-gate 17207c478bd9Sstevel@tonic-gate uint32_t ip_tcp_csum; 17217c478bd9Sstevel@tonic-gate #define RXD_IPCSUM_MASK 0xffff0000 17227c478bd9Sstevel@tonic-gate #define RXD_IPCSUM_SHIFT 16 17237c478bd9Sstevel@tonic-gate #define RXD_TCPCSUM_MASK 0x0000ffff 17247c478bd9Sstevel@tonic-gate #define RXD_TCPCSUM_SHIFT 0 17257c478bd9Sstevel@tonic-gate 17267c478bd9Sstevel@tonic-gate uint32_t err_vlan; 17277c478bd9Sstevel@tonic-gate 17287c478bd9Sstevel@tonic-gate #define RXD_VLAN_MASK 0x0000ffff 17297c478bd9Sstevel@tonic-gate 17307c478bd9Sstevel@tonic-gate #define RXD_ERR_BAD_CRC 0x00010000 17317c478bd9Sstevel@tonic-gate #define RXD_ERR_COLLISION 0x00020000 17327c478bd9Sstevel@tonic-gate #define RXD_ERR_LINK_LOST 0x00040000 17337c478bd9Sstevel@tonic-gate #define RXD_ERR_PHY_DECODE 0x00080000 17347c478bd9Sstevel@tonic-gate #define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000 17357c478bd9Sstevel@tonic-gate #define RXD_ERR_MAC_ABRT 0x00200000 17367c478bd9Sstevel@tonic-gate #define RXD_ERR_TOO_SMALL 0x00400000 17377c478bd9Sstevel@tonic-gate #define RXD_ERR_NO_RESOURCES 0x00800000 17387c478bd9Sstevel@tonic-gate #define RXD_ERR_HUGE_FRAME 0x01000000 17397c478bd9Sstevel@tonic-gate #define RXD_ERR_MASK 0xffff0000 17407c478bd9Sstevel@tonic-gate 17417c478bd9Sstevel@tonic-gate uint32_t reserved; 17427c478bd9Sstevel@tonic-gate uint32_t opaque; 17437c478bd9Sstevel@tonic-gate #define RXD_OPAQUE_INDEX_MASK 0x0000ffff 17447c478bd9Sstevel@tonic-gate #define RXD_OPAQUE_INDEX_SHIFT 0 17457c478bd9Sstevel@tonic-gate #define RXD_OPAQUE_RING_STD 0x00010000 17467c478bd9Sstevel@tonic-gate #define RXD_OPAQUE_RING_JUMBO 0x00020000 17477c478bd9Sstevel@tonic-gate #define RXD_OPAQUE_RING_MINI 0x00040000 17487c478bd9Sstevel@tonic-gate #define RXD_OPAQUE_RING_MASK 0x00070000 17497c478bd9Sstevel@tonic-gate }; 17507c478bd9Sstevel@tonic-gate 17517c478bd9Sstevel@tonic-gate struct tg3_ext_rx_buffer_desc { 17527c478bd9Sstevel@tonic-gate struct { 17537c478bd9Sstevel@tonic-gate uint32_t addr_hi; 17547c478bd9Sstevel@tonic-gate uint32_t addr_lo; 17557c478bd9Sstevel@tonic-gate } addrlist[3]; 17567c478bd9Sstevel@tonic-gate uint32_t len2_len1; 17577c478bd9Sstevel@tonic-gate uint32_t resv_len3; 17587c478bd9Sstevel@tonic-gate struct tg3_rx_buffer_desc std; 17597c478bd9Sstevel@tonic-gate }; 17607c478bd9Sstevel@tonic-gate 17617c478bd9Sstevel@tonic-gate /* We only use this when testing out the DMA engine 17627c478bd9Sstevel@tonic-gate * at probe time. This is the internal format of buffer 17637c478bd9Sstevel@tonic-gate * descriptors used by the chip at NIC_SRAM_DMA_DESCS. 17647c478bd9Sstevel@tonic-gate */ 17657c478bd9Sstevel@tonic-gate struct tg3_internal_buffer_desc { 17667c478bd9Sstevel@tonic-gate uint32_t addr_hi; 17677c478bd9Sstevel@tonic-gate uint32_t addr_lo; 17687c478bd9Sstevel@tonic-gate uint32_t nic_mbuf; 17697c478bd9Sstevel@tonic-gate /* XXX FIX THIS */ 17707c478bd9Sstevel@tonic-gate #if __BYTE_ORDER == __BIG_ENDIAN 17717c478bd9Sstevel@tonic-gate uint16_t cqid_sqid; 17727c478bd9Sstevel@tonic-gate uint16_t len; 17737c478bd9Sstevel@tonic-gate #else 17747c478bd9Sstevel@tonic-gate uint16_t len; 17757c478bd9Sstevel@tonic-gate uint16_t cqid_sqid; 17767c478bd9Sstevel@tonic-gate #endif 17777c478bd9Sstevel@tonic-gate uint32_t flags; 17787c478bd9Sstevel@tonic-gate uint32_t __cookie1; 17797c478bd9Sstevel@tonic-gate uint32_t __cookie2; 17807c478bd9Sstevel@tonic-gate uint32_t __cookie3; 17817c478bd9Sstevel@tonic-gate }; 17827c478bd9Sstevel@tonic-gate 17837c478bd9Sstevel@tonic-gate #define TG3_HW_STATUS_SIZE 0x50 17847c478bd9Sstevel@tonic-gate struct tg3_hw_status { 17857c478bd9Sstevel@tonic-gate uint32_t status; 17867c478bd9Sstevel@tonic-gate #define SD_STATUS_UPDATED 0x00000001 17877c478bd9Sstevel@tonic-gate #define SD_STATUS_LINK_CHG 0x00000002 17887c478bd9Sstevel@tonic-gate #define SD_STATUS_ERROR 0x00000004 17897c478bd9Sstevel@tonic-gate 17907c478bd9Sstevel@tonic-gate uint32_t status_tag; 17917c478bd9Sstevel@tonic-gate 17927c478bd9Sstevel@tonic-gate #if __BYTE_ORDER == __BIG_ENDIAN 17937c478bd9Sstevel@tonic-gate uint16_t rx_consumer; 17947c478bd9Sstevel@tonic-gate uint16_t rx_jumbo_consumer; 17957c478bd9Sstevel@tonic-gate #else 17967c478bd9Sstevel@tonic-gate uint16_t rx_jumbo_consumer; 17977c478bd9Sstevel@tonic-gate uint16_t rx_consumer; 17987c478bd9Sstevel@tonic-gate #endif 17997c478bd9Sstevel@tonic-gate 18007c478bd9Sstevel@tonic-gate #if __BYTE_ORDER == __BIG_ENDIAN 18017c478bd9Sstevel@tonic-gate uint16_t reserved; 18027c478bd9Sstevel@tonic-gate uint16_t rx_mini_consumer; 18037c478bd9Sstevel@tonic-gate #else 18047c478bd9Sstevel@tonic-gate uint16_t rx_mini_consumer; 18057c478bd9Sstevel@tonic-gate uint16_t reserved; 18067c478bd9Sstevel@tonic-gate #endif 18077c478bd9Sstevel@tonic-gate struct { 18087c478bd9Sstevel@tonic-gate #if __BYTE_ORDER == __BIG_ENDIAN 18097c478bd9Sstevel@tonic-gate uint16_t tx_consumer; 18107c478bd9Sstevel@tonic-gate uint16_t rx_producer; 18117c478bd9Sstevel@tonic-gate #else 18127c478bd9Sstevel@tonic-gate uint16_t rx_producer; 18137c478bd9Sstevel@tonic-gate uint16_t tx_consumer; 18147c478bd9Sstevel@tonic-gate #endif 18157c478bd9Sstevel@tonic-gate } idx[16]; 18167c478bd9Sstevel@tonic-gate }; 18177c478bd9Sstevel@tonic-gate 18187c478bd9Sstevel@tonic-gate typedef struct { 18197c478bd9Sstevel@tonic-gate uint32_t high, low; 18207c478bd9Sstevel@tonic-gate } tg3_stat64_t; 18217c478bd9Sstevel@tonic-gate 18227c478bd9Sstevel@tonic-gate struct tg3_hw_stats { 18237c478bd9Sstevel@tonic-gate uint8_t __reserved0[0x400-0x300]; 18247c478bd9Sstevel@tonic-gate 18257c478bd9Sstevel@tonic-gate /* Statistics maintained by Receive MAC. */ 18267c478bd9Sstevel@tonic-gate tg3_stat64_t rx_octets; 18277c478bd9Sstevel@tonic-gate uint64_t __reserved1; 18287c478bd9Sstevel@tonic-gate tg3_stat64_t rx_fragments; 18297c478bd9Sstevel@tonic-gate tg3_stat64_t rx_ucast_packets; 18307c478bd9Sstevel@tonic-gate tg3_stat64_t rx_mcast_packets; 18317c478bd9Sstevel@tonic-gate tg3_stat64_t rx_bcast_packets; 18327c478bd9Sstevel@tonic-gate tg3_stat64_t rx_fcs_errors; 18337c478bd9Sstevel@tonic-gate tg3_stat64_t rx_align_errors; 18347c478bd9Sstevel@tonic-gate tg3_stat64_t rx_xon_pause_rcvd; 18357c478bd9Sstevel@tonic-gate tg3_stat64_t rx_xoff_pause_rcvd; 18367c478bd9Sstevel@tonic-gate tg3_stat64_t rx_mac_ctrl_rcvd; 18377c478bd9Sstevel@tonic-gate tg3_stat64_t rx_xoff_entered; 18387c478bd9Sstevel@tonic-gate tg3_stat64_t rx_frame_too_long_errors; 18397c478bd9Sstevel@tonic-gate tg3_stat64_t rx_jabbers; 18407c478bd9Sstevel@tonic-gate tg3_stat64_t rx_undersize_packets; 18417c478bd9Sstevel@tonic-gate tg3_stat64_t rx_in_length_errors; 18427c478bd9Sstevel@tonic-gate tg3_stat64_t rx_out_length_errors; 18437c478bd9Sstevel@tonic-gate tg3_stat64_t rx_64_or_less_octet_packets; 18447c478bd9Sstevel@tonic-gate tg3_stat64_t rx_65_to_127_octet_packets; 18457c478bd9Sstevel@tonic-gate tg3_stat64_t rx_128_to_255_octet_packets; 18467c478bd9Sstevel@tonic-gate tg3_stat64_t rx_256_to_511_octet_packets; 18477c478bd9Sstevel@tonic-gate tg3_stat64_t rx_512_to_1023_octet_packets; 18487c478bd9Sstevel@tonic-gate tg3_stat64_t rx_1024_to_1522_octet_packets; 18497c478bd9Sstevel@tonic-gate tg3_stat64_t rx_1523_to_2047_octet_packets; 18507c478bd9Sstevel@tonic-gate tg3_stat64_t rx_2048_to_4095_octet_packets; 18517c478bd9Sstevel@tonic-gate tg3_stat64_t rx_4096_to_8191_octet_packets; 18527c478bd9Sstevel@tonic-gate tg3_stat64_t rx_8192_to_9022_octet_packets; 18537c478bd9Sstevel@tonic-gate 18547c478bd9Sstevel@tonic-gate uint64_t __unused0[37]; 18557c478bd9Sstevel@tonic-gate 18567c478bd9Sstevel@tonic-gate /* Statistics maintained by Transmit MAC. */ 18577c478bd9Sstevel@tonic-gate tg3_stat64_t tx_octets; 18587c478bd9Sstevel@tonic-gate uint64_t __reserved2; 18597c478bd9Sstevel@tonic-gate tg3_stat64_t tx_collisions; 18607c478bd9Sstevel@tonic-gate tg3_stat64_t tx_xon_sent; 18617c478bd9Sstevel@tonic-gate tg3_stat64_t tx_xoff_sent; 18627c478bd9Sstevel@tonic-gate tg3_stat64_t tx_flow_control; 18637c478bd9Sstevel@tonic-gate tg3_stat64_t tx_mac_errors; 18647c478bd9Sstevel@tonic-gate tg3_stat64_t tx_single_collisions; 18657c478bd9Sstevel@tonic-gate tg3_stat64_t tx_mult_collisions; 18667c478bd9Sstevel@tonic-gate tg3_stat64_t tx_deferred; 18677c478bd9Sstevel@tonic-gate uint64_t __reserved3; 18687c478bd9Sstevel@tonic-gate tg3_stat64_t tx_excessive_collisions; 18697c478bd9Sstevel@tonic-gate tg3_stat64_t tx_late_collisions; 18707c478bd9Sstevel@tonic-gate tg3_stat64_t tx_collide_2times; 18717c478bd9Sstevel@tonic-gate tg3_stat64_t tx_collide_3times; 18727c478bd9Sstevel@tonic-gate tg3_stat64_t tx_collide_4times; 18737c478bd9Sstevel@tonic-gate tg3_stat64_t tx_collide_5times; 18747c478bd9Sstevel@tonic-gate tg3_stat64_t tx_collide_6times; 18757c478bd9Sstevel@tonic-gate tg3_stat64_t tx_collide_7times; 18767c478bd9Sstevel@tonic-gate tg3_stat64_t tx_collide_8times; 18777c478bd9Sstevel@tonic-gate tg3_stat64_t tx_collide_9times; 18787c478bd9Sstevel@tonic-gate tg3_stat64_t tx_collide_10times; 18797c478bd9Sstevel@tonic-gate tg3_stat64_t tx_collide_11times; 18807c478bd9Sstevel@tonic-gate tg3_stat64_t tx_collide_12times; 18817c478bd9Sstevel@tonic-gate tg3_stat64_t tx_collide_13times; 18827c478bd9Sstevel@tonic-gate tg3_stat64_t tx_collide_14times; 18837c478bd9Sstevel@tonic-gate tg3_stat64_t tx_collide_15times; 18847c478bd9Sstevel@tonic-gate tg3_stat64_t tx_ucast_packets; 18857c478bd9Sstevel@tonic-gate tg3_stat64_t tx_mcast_packets; 18867c478bd9Sstevel@tonic-gate tg3_stat64_t tx_bcast_packets; 18877c478bd9Sstevel@tonic-gate tg3_stat64_t tx_carrier_sense_errors; 18887c478bd9Sstevel@tonic-gate tg3_stat64_t tx_discards; 18897c478bd9Sstevel@tonic-gate tg3_stat64_t tx_errors; 18907c478bd9Sstevel@tonic-gate 18917c478bd9Sstevel@tonic-gate uint64_t __unused1[31]; 18927c478bd9Sstevel@tonic-gate 18937c478bd9Sstevel@tonic-gate /* Statistics maintained by Receive List Placement. */ 18947c478bd9Sstevel@tonic-gate tg3_stat64_t COS_rx_packets[16]; 18957c478bd9Sstevel@tonic-gate tg3_stat64_t COS_rx_filter_dropped; 18967c478bd9Sstevel@tonic-gate tg3_stat64_t dma_writeq_full; 18977c478bd9Sstevel@tonic-gate tg3_stat64_t dma_write_prioq_full; 18987c478bd9Sstevel@tonic-gate tg3_stat64_t rxbds_empty; 18997c478bd9Sstevel@tonic-gate tg3_stat64_t rx_discards; 19007c478bd9Sstevel@tonic-gate tg3_stat64_t rx_errors; 19017c478bd9Sstevel@tonic-gate tg3_stat64_t rx_threshold_hit; 19027c478bd9Sstevel@tonic-gate 19037c478bd9Sstevel@tonic-gate uint64_t __unused2[9]; 19047c478bd9Sstevel@tonic-gate 19057c478bd9Sstevel@tonic-gate /* Statistics maintained by Send Data Initiator. */ 19067c478bd9Sstevel@tonic-gate tg3_stat64_t COS_out_packets[16]; 19077c478bd9Sstevel@tonic-gate tg3_stat64_t dma_readq_full; 19087c478bd9Sstevel@tonic-gate tg3_stat64_t dma_read_prioq_full; 19097c478bd9Sstevel@tonic-gate tg3_stat64_t tx_comp_queue_full; 19107c478bd9Sstevel@tonic-gate 19117c478bd9Sstevel@tonic-gate /* Statistics maintained by Host Coalescing. */ 19127c478bd9Sstevel@tonic-gate tg3_stat64_t ring_set_send_prod_index; 19137c478bd9Sstevel@tonic-gate tg3_stat64_t ring_status_update; 19147c478bd9Sstevel@tonic-gate tg3_stat64_t nic_irqs; 19157c478bd9Sstevel@tonic-gate tg3_stat64_t nic_avoided_irqs; 19167c478bd9Sstevel@tonic-gate tg3_stat64_t nic_tx_threshold_hit; 19177c478bd9Sstevel@tonic-gate 19187c478bd9Sstevel@tonic-gate uint8_t __reserved4[0xb00-0x9c0]; 19197c478bd9Sstevel@tonic-gate }; 19207c478bd9Sstevel@tonic-gate 19217c478bd9Sstevel@tonic-gate enum phy_led_mode { 19227c478bd9Sstevel@tonic-gate led_mode_auto, 19237c478bd9Sstevel@tonic-gate led_mode_three_link, 19247c478bd9Sstevel@tonic-gate led_mode_link10 19257c478bd9Sstevel@tonic-gate }; 19267c478bd9Sstevel@tonic-gate 19277c478bd9Sstevel@tonic-gate #if 0 19287c478bd9Sstevel@tonic-gate /* 'mapping' is superfluous as the chip does not write into 19297c478bd9Sstevel@tonic-gate * the tx/rx post rings so we could just fetch it from there. 19307c478bd9Sstevel@tonic-gate * But the cache behavior is better how we are doing it now. 19317c478bd9Sstevel@tonic-gate */ 19327c478bd9Sstevel@tonic-gate struct ring_info { 19337c478bd9Sstevel@tonic-gate struct sk_buff *skb; 19347c478bd9Sstevel@tonic-gate DECLARE_PCI_UNMAP_ADDR(mapping) 19357c478bd9Sstevel@tonic-gate }; 19367c478bd9Sstevel@tonic-gate 19377c478bd9Sstevel@tonic-gate struct tx_ring_info { 19387c478bd9Sstevel@tonic-gate struct sk_buff *skb; 19397c478bd9Sstevel@tonic-gate DECLARE_PCI_UNMAP_ADDR(mapping) 19407c478bd9Sstevel@tonic-gate uint32_t prev_vlan_tag; 19417c478bd9Sstevel@tonic-gate }; 19427c478bd9Sstevel@tonic-gate #endif 19437c478bd9Sstevel@tonic-gate 19447c478bd9Sstevel@tonic-gate struct tg3_config_info { 19457c478bd9Sstevel@tonic-gate uint32_t flags; 19467c478bd9Sstevel@tonic-gate }; 19477c478bd9Sstevel@tonic-gate 19487c478bd9Sstevel@tonic-gate struct tg3_link_config { 19497c478bd9Sstevel@tonic-gate /* Describes what we're trying to get. */ 19507c478bd9Sstevel@tonic-gate uint32_t advertising; 19517c478bd9Sstevel@tonic-gate #if 0 19527c478bd9Sstevel@tonic-gate uint16_t speed; 19537c478bd9Sstevel@tonic-gate uint8_t duplex; 19547c478bd9Sstevel@tonic-gate uint8_t autoneg; 19557c478bd9Sstevel@tonic-gate #define SPEED_INVALID 0xffff 19567c478bd9Sstevel@tonic-gate #define DUPLEX_INVALID 0xff 19577c478bd9Sstevel@tonic-gate #define AUTONEG_INVALID 0xff 19587c478bd9Sstevel@tonic-gate #endif 19597c478bd9Sstevel@tonic-gate 19607c478bd9Sstevel@tonic-gate /* Describes what we actually have. */ 19617c478bd9Sstevel@tonic-gate uint8_t active_speed; 19627c478bd9Sstevel@tonic-gate uint8_t active_duplex; 19637c478bd9Sstevel@tonic-gate 19647c478bd9Sstevel@tonic-gate /* When we go in and out of low power mode we need 19657c478bd9Sstevel@tonic-gate * to swap with this state. 19667c478bd9Sstevel@tonic-gate */ 19677c478bd9Sstevel@tonic-gate #if 0 19687c478bd9Sstevel@tonic-gate int phy_is_low_power; 19697c478bd9Sstevel@tonic-gate uint16_t orig_speed; 19707c478bd9Sstevel@tonic-gate uint8_t orig_duplex; 19717c478bd9Sstevel@tonic-gate uint8_t orig_autoneg; 19727c478bd9Sstevel@tonic-gate #endif 19737c478bd9Sstevel@tonic-gate }; 19747c478bd9Sstevel@tonic-gate 19757c478bd9Sstevel@tonic-gate struct tg3_bufmgr_config { 19767c478bd9Sstevel@tonic-gate uint32_t mbuf_read_dma_low_water; 19777c478bd9Sstevel@tonic-gate uint32_t mbuf_mac_rx_low_water; 19787c478bd9Sstevel@tonic-gate uint32_t mbuf_high_water; 19797c478bd9Sstevel@tonic-gate 19807c478bd9Sstevel@tonic-gate uint32_t mbuf_read_dma_low_water_jumbo; 19817c478bd9Sstevel@tonic-gate uint32_t mbuf_mac_rx_low_water_jumbo; 19827c478bd9Sstevel@tonic-gate uint32_t mbuf_high_water_jumbo; 19837c478bd9Sstevel@tonic-gate 19847c478bd9Sstevel@tonic-gate uint32_t dma_low_water; 19857c478bd9Sstevel@tonic-gate uint32_t dma_high_water; 19867c478bd9Sstevel@tonic-gate }; 19877c478bd9Sstevel@tonic-gate 19887c478bd9Sstevel@tonic-gate struct tg3 { 19897c478bd9Sstevel@tonic-gate #if 0 19907c478bd9Sstevel@tonic-gate /* SMP locking strategy: 19917c478bd9Sstevel@tonic-gate * 19927c478bd9Sstevel@tonic-gate * lock: Held during all operations except TX packet 19937c478bd9Sstevel@tonic-gate * processing. 19947c478bd9Sstevel@tonic-gate * 19957c478bd9Sstevel@tonic-gate * tx_lock: Held during tg3_start_xmit{,_4gbug} and tg3_tx 19967c478bd9Sstevel@tonic-gate * 19977c478bd9Sstevel@tonic-gate * If you want to shut up all asynchronous processing you must 19987c478bd9Sstevel@tonic-gate * acquire both locks, 'lock' taken before 'tx_lock'. IRQs must 19997c478bd9Sstevel@tonic-gate * be disabled to take 'lock' but only softirq disabling is 20007c478bd9Sstevel@tonic-gate * necessary for acquisition of 'tx_lock'. 20017c478bd9Sstevel@tonic-gate */ 20027c478bd9Sstevel@tonic-gate spinlock_t lock; 20037c478bd9Sstevel@tonic-gate spinlock_t tx_lock; 20047c478bd9Sstevel@tonic-gate #endif 20057c478bd9Sstevel@tonic-gate 20067c478bd9Sstevel@tonic-gate uint32_t tx_prod; 20077c478bd9Sstevel@tonic-gate #if 0 20087c478bd9Sstevel@tonic-gate uint32_t tx_cons; 20097c478bd9Sstevel@tonic-gate #endif 20107c478bd9Sstevel@tonic-gate uint32_t rx_rcb_ptr; 20117c478bd9Sstevel@tonic-gate uint32_t rx_std_ptr; 20127c478bd9Sstevel@tonic-gate #if 0 20137c478bd9Sstevel@tonic-gate uint32_t rx_jumbo_ptr; 20147c478bd9Sstevel@tonic-gate spinlock_t indirect_lock; 20157c478bd9Sstevel@tonic-gate 20167c478bd9Sstevel@tonic-gate struct net_device_stats net_stats; 20177c478bd9Sstevel@tonic-gate struct net_device_stats net_stats_prev; 20187c478bd9Sstevel@tonic-gate #endif 20197c478bd9Sstevel@tonic-gate unsigned long phy_crc_errors; 20207c478bd9Sstevel@tonic-gate 20217c478bd9Sstevel@tonic-gate #if 0 20227c478bd9Sstevel@tonic-gate uint32_t rx_offset; 20237c478bd9Sstevel@tonic-gate #endif 20247c478bd9Sstevel@tonic-gate uint32_t tg3_flags; 20257c478bd9Sstevel@tonic-gate #if 0 20267c478bd9Sstevel@tonic-gate #define TG3_FLAG_HOST_TXDS 0x00000001 20277c478bd9Sstevel@tonic-gate #endif 20287c478bd9Sstevel@tonic-gate #define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002 20297c478bd9Sstevel@tonic-gate #define TG3_FLAG_RX_CHECKSUMS 0x00000004 20307c478bd9Sstevel@tonic-gate #define TG3_FLAG_USE_LINKCHG_REG 0x00000008 20317c478bd9Sstevel@tonic-gate #define TG3_FLAG_USE_MI_INTERRUPT 0x00000010 20327c478bd9Sstevel@tonic-gate #define TG3_FLAG_ENABLE_ASF 0x00000020 20337c478bd9Sstevel@tonic-gate #define TG3_FLAG_5701_REG_WRITE_BUG 0x00000040 20347c478bd9Sstevel@tonic-gate #define TG3_FLAG_POLL_SERDES 0x00000080 20357c478bd9Sstevel@tonic-gate #define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100 20367c478bd9Sstevel@tonic-gate #define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200 20377c478bd9Sstevel@tonic-gate #define TG3_FLAG_WOL_SPEED_100MB 0x00000400 20387c478bd9Sstevel@tonic-gate #define TG3_FLAG_WOL_ENABLE 0x00000800 20397c478bd9Sstevel@tonic-gate #define TG3_FLAG_EEPROM_WRITE_PROT 0x00001000 20407c478bd9Sstevel@tonic-gate #define TG3_FLAG_NVRAM 0x00002000 20417c478bd9Sstevel@tonic-gate #define TG3_FLAG_NVRAM_BUFFERED 0x00004000 20427c478bd9Sstevel@tonic-gate #define TG3_FLAG_RX_PAUSE 0x00008000 20437c478bd9Sstevel@tonic-gate #define TG3_FLAG_TX_PAUSE 0x00010000 20447c478bd9Sstevel@tonic-gate #define TG3_FLAG_PCIX_MODE 0x00020000 20457c478bd9Sstevel@tonic-gate #define TG3_FLAG_PCI_HIGH_SPEED 0x00040000 20467c478bd9Sstevel@tonic-gate #define TG3_FLAG_PCI_32BIT 0x00080000 20477c478bd9Sstevel@tonic-gate #define TG3_FLAG_NO_TX_PSEUDO_CSUM 0x00100000 20487c478bd9Sstevel@tonic-gate #define TG3_FLAG_NO_RX_PSEUDO_CSUM 0x00200000 20497c478bd9Sstevel@tonic-gate #define TG3_FLAG_SERDES_WOL_CAP 0x00400000 20507c478bd9Sstevel@tonic-gate #define TG3_FLAG_JUMBO_ENABLE 0x00800000 20517c478bd9Sstevel@tonic-gate #define TG3_FLAG_10_100_ONLY 0x01000000 20527c478bd9Sstevel@tonic-gate #define TG3_FLAG_PAUSE_AUTONEG 0x02000000 20537c478bd9Sstevel@tonic-gate #define TG3_FLAG_PAUSE_RX 0x04000000 20547c478bd9Sstevel@tonic-gate #define TG3_FLAG_PAUSE_TX 0x08000000 20557c478bd9Sstevel@tonic-gate #define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000 20567c478bd9Sstevel@tonic-gate #define TG3_FLAG_GOT_SERDES_FLOWCTL 0x20000000 20577c478bd9Sstevel@tonic-gate #define TG3_FLAG_SPLIT_MODE 0x40000000 20587c478bd9Sstevel@tonic-gate #define TG3_FLAG_INIT_COMPLETE 0x80000000 20597c478bd9Sstevel@tonic-gate 20607c478bd9Sstevel@tonic-gate uint32_t tg3_flags2; 20617c478bd9Sstevel@tonic-gate #define TG3_FLG2_RESTART_TIMER 0x00000001 20627c478bd9Sstevel@tonic-gate #define TG3_FLG2_SUN_5704 0x00000002 20637c478bd9Sstevel@tonic-gate #define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004 20647c478bd9Sstevel@tonic-gate #define TG3_FLG2_IS_5788 0x00000008 20657c478bd9Sstevel@tonic-gate #define TG3_FLG2_MAX_RXPEND_64 0x00000010 20667c478bd9Sstevel@tonic-gate #define TG3_FLG2_TSO_CAPABLE 0x00000020 20677c478bd9Sstevel@tonic-gate 20687c478bd9Sstevel@tonic-gate 20697c478bd9Sstevel@tonic-gate 20707c478bd9Sstevel@tonic-gate uint32_t split_mode_max_reqs; 20717c478bd9Sstevel@tonic-gate #define SPLIT_MODE_5704_MAX_REQ 3 20727c478bd9Sstevel@tonic-gate 20737c478bd9Sstevel@tonic-gate #if 0 20747c478bd9Sstevel@tonic-gate struct timer_list timer; 20757c478bd9Sstevel@tonic-gate uint16_t timer_counter; 20767c478bd9Sstevel@tonic-gate uint16_t timer_multiplier; 20777c478bd9Sstevel@tonic-gate uint32_t timer_offset; 20787c478bd9Sstevel@tonic-gate uint16_t asf_counter; 20797c478bd9Sstevel@tonic-gate uint16_t asf_multiplier; 20807c478bd9Sstevel@tonic-gate #endif 20817c478bd9Sstevel@tonic-gate 20827c478bd9Sstevel@tonic-gate struct tg3_link_config link_config; 20837c478bd9Sstevel@tonic-gate struct tg3_bufmgr_config bufmgr_config; 20847c478bd9Sstevel@tonic-gate 20857c478bd9Sstevel@tonic-gate #if 0 20867c478bd9Sstevel@tonic-gate uint32_t rx_pending; 20877c478bd9Sstevel@tonic-gate uint32_t rx_jumbo_pending; 20887c478bd9Sstevel@tonic-gate uint32_t tx_pending; 20897c478bd9Sstevel@tonic-gate #endif 20907c478bd9Sstevel@tonic-gate 20917c478bd9Sstevel@tonic-gate /* cache h/w values, often passed straight to h/w */ 20927c478bd9Sstevel@tonic-gate uint32_t rx_mode; 20937c478bd9Sstevel@tonic-gate uint32_t tx_mode; 20947c478bd9Sstevel@tonic-gate uint32_t mac_mode; 20957c478bd9Sstevel@tonic-gate uint32_t mi_mode; 20967c478bd9Sstevel@tonic-gate uint32_t misc_host_ctrl; 20977c478bd9Sstevel@tonic-gate uint32_t grc_mode; 20987c478bd9Sstevel@tonic-gate uint32_t grc_local_ctrl; 20997c478bd9Sstevel@tonic-gate uint32_t dma_rwctrl; 21007c478bd9Sstevel@tonic-gate #if 0 21017c478bd9Sstevel@tonic-gate uint32_t coalesce_mode; 21027c478bd9Sstevel@tonic-gate #endif 21037c478bd9Sstevel@tonic-gate 21047c478bd9Sstevel@tonic-gate /* PCI block */ 21057c478bd9Sstevel@tonic-gate uint16_t pci_chip_rev_id; 21067c478bd9Sstevel@tonic-gate #if 0 21077c478bd9Sstevel@tonic-gate uint8_t pci_cacheline_sz; 21087c478bd9Sstevel@tonic-gate uint8_t pci_lat_timer; 21097c478bd9Sstevel@tonic-gate uint8_t pci_hdr_type; 21107c478bd9Sstevel@tonic-gate uint8_t pci_bist; 21117c478bd9Sstevel@tonic-gate #endif 21127c478bd9Sstevel@tonic-gate uint32_t pci_cfg_state[64 / sizeof(uint32_t)]; 21137c478bd9Sstevel@tonic-gate 21147c478bd9Sstevel@tonic-gate int pm_cap; 21157c478bd9Sstevel@tonic-gate 21167c478bd9Sstevel@tonic-gate /* PHY info */ 21177c478bd9Sstevel@tonic-gate uint32_t phy_id; 21187c478bd9Sstevel@tonic-gate #define PHY_ID_MASK 0xfffffff0 21197c478bd9Sstevel@tonic-gate #define PHY_ID_BCM5400 0x60008040 21207c478bd9Sstevel@tonic-gate #define PHY_ID_BCM5401 0x60008050 21217c478bd9Sstevel@tonic-gate #define PHY_ID_BCM5411 0x60008070 21227c478bd9Sstevel@tonic-gate #define PHY_ID_BCM5701 0x60008110 21237c478bd9Sstevel@tonic-gate #define PHY_ID_BCM5703 0x60008160 21247c478bd9Sstevel@tonic-gate #define PHY_ID_BCM5704 0x60008190 21257c478bd9Sstevel@tonic-gate #define PHY_ID_BCM5705 0x600081a0 21267c478bd9Sstevel@tonic-gate #define PHY_ID_BCM8002 0x60010140 21277c478bd9Sstevel@tonic-gate #define PHY_ID_SERDES 0xfeedbee0 21287c478bd9Sstevel@tonic-gate #define PHY_ID_INVALID 0xffffffff 21297c478bd9Sstevel@tonic-gate #define PHY_ID_REV_MASK 0x0000000f 21307c478bd9Sstevel@tonic-gate #define PHY_REV_BCM5401_B0 0x1 21317c478bd9Sstevel@tonic-gate #define PHY_REV_BCM5401_B2 0x3 21327c478bd9Sstevel@tonic-gate #define PHY_REV_BCM5401_C0 0x6 21337c478bd9Sstevel@tonic-gate #define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */ 21347c478bd9Sstevel@tonic-gate 21357c478bd9Sstevel@tonic-gate enum phy_led_mode led_mode; 21367c478bd9Sstevel@tonic-gate 21377c478bd9Sstevel@tonic-gate char board_part_number[24]; 21387c478bd9Sstevel@tonic-gate uint32_t nic_sram_data_cfg; 21397c478bd9Sstevel@tonic-gate uint32_t pci_clock_ctrl; 21407c478bd9Sstevel@tonic-gate #if 0 21417c478bd9Sstevel@tonic-gate struct pci_device *pdev_peer; 21427c478bd9Sstevel@tonic-gate #endif 21437c478bd9Sstevel@tonic-gate 21447c478bd9Sstevel@tonic-gate /* This macro assumes the passed PHY ID is already masked 21457c478bd9Sstevel@tonic-gate * with PHY_ID_MASK. 21467c478bd9Sstevel@tonic-gate */ 21477c478bd9Sstevel@tonic-gate #define KNOWN_PHY_ID(X) \ 21487c478bd9Sstevel@tonic-gate ((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \ 21497c478bd9Sstevel@tonic-gate (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \ 21507c478bd9Sstevel@tonic-gate (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \ 21517c478bd9Sstevel@tonic-gate (X) == PHY_ID_BCM5705 || \ 21527c478bd9Sstevel@tonic-gate (X) == PHY_ID_BCM8002 || (X) == PHY_ID_SERDES) 21537c478bd9Sstevel@tonic-gate 21547c478bd9Sstevel@tonic-gate unsigned long regs; 21557c478bd9Sstevel@tonic-gate struct pci_device *pdev; 21567c478bd9Sstevel@tonic-gate struct nic *nic; 21577c478bd9Sstevel@tonic-gate #if 0 21587c478bd9Sstevel@tonic-gate struct net_device *dev; 21597c478bd9Sstevel@tonic-gate #endif 21607c478bd9Sstevel@tonic-gate #if TG3_VLAN_TAG_USED 21617c478bd9Sstevel@tonic-gate struct vlan_group *vlgrp; 21627c478bd9Sstevel@tonic-gate #endif 21637c478bd9Sstevel@tonic-gate 21647c478bd9Sstevel@tonic-gate struct tg3_rx_buffer_desc *rx_std; 21657c478bd9Sstevel@tonic-gate #if 0 21667c478bd9Sstevel@tonic-gate struct ring_info *rx_std_buffers; 21677c478bd9Sstevel@tonic-gate dma_addr_t rx_std_mapping; 21687c478bd9Sstevel@tonic-gate struct tg3_rx_buffer_desc *rx_jumbo; 21697c478bd9Sstevel@tonic-gate struct ring_info *rx_jumbo_buffers; 21707c478bd9Sstevel@tonic-gate dma_addr_t rx_jumbo_mapping; 21717c478bd9Sstevel@tonic-gate #endif 21727c478bd9Sstevel@tonic-gate 21737c478bd9Sstevel@tonic-gate struct tg3_rx_buffer_desc *rx_rcb; 21747c478bd9Sstevel@tonic-gate #if 0 21757c478bd9Sstevel@tonic-gate dma_addr_t rx_rcb_mapping; 21767c478bd9Sstevel@tonic-gate #endif 21777c478bd9Sstevel@tonic-gate 21787c478bd9Sstevel@tonic-gate /* TX descs are only used if TG3_FLAG_HOST_TXDS is set. */ 21797c478bd9Sstevel@tonic-gate struct tg3_tx_buffer_desc *tx_ring; 21807c478bd9Sstevel@tonic-gate #if 0 21817c478bd9Sstevel@tonic-gate struct tx_ring_info *tx_buffers; 21827c478bd9Sstevel@tonic-gate dma_addr_t tx_desc_mapping; 21837c478bd9Sstevel@tonic-gate #endif 21847c478bd9Sstevel@tonic-gate 21857c478bd9Sstevel@tonic-gate struct tg3_hw_status *hw_status; 21867c478bd9Sstevel@tonic-gate #if 0 21877c478bd9Sstevel@tonic-gate dma_addr_t status_mapping; 21887c478bd9Sstevel@tonic-gate #endif 21897c478bd9Sstevel@tonic-gate #if 0 21907c478bd9Sstevel@tonic-gate uint32_t msg_enable; 21917c478bd9Sstevel@tonic-gate #endif 21927c478bd9Sstevel@tonic-gate 21937c478bd9Sstevel@tonic-gate struct tg3_hw_stats *hw_stats; 21947c478bd9Sstevel@tonic-gate #if 0 21957c478bd9Sstevel@tonic-gate dma_addr_t stats_mapping; 21967c478bd9Sstevel@tonic-gate #endif 21977c478bd9Sstevel@tonic-gate 21987c478bd9Sstevel@tonic-gate int carrier_ok; 21997c478bd9Sstevel@tonic-gate uint16_t subsystem_vendor; 22007c478bd9Sstevel@tonic-gate uint16_t subsystem_device; 22017c478bd9Sstevel@tonic-gate }; 22027c478bd9Sstevel@tonic-gate 22037c478bd9Sstevel@tonic-gate #endif /* !(_T3_H) */ 2204