17c478bd9Sstevel@tonic-gate #if !defined(PCI_H) && defined(CONFIG_PCI)
27c478bd9Sstevel@tonic-gate #define PCI_H
37c478bd9Sstevel@tonic-gate
47c478bd9Sstevel@tonic-gate /*
57c478bd9Sstevel@tonic-gate ** Support for NE2000 PCI clones added David Monro June 1997
67c478bd9Sstevel@tonic-gate ** Generalised for other PCI NICs by Ken Yap July 1997
77c478bd9Sstevel@tonic-gate **
87c478bd9Sstevel@tonic-gate ** Most of this is taken from:
97c478bd9Sstevel@tonic-gate **
107c478bd9Sstevel@tonic-gate ** /usr/src/linux/drivers/pci/pci.c
117c478bd9Sstevel@tonic-gate ** /usr/src/linux/include/linux/pci.h
127c478bd9Sstevel@tonic-gate ** /usr/src/linux/arch/i386/bios32.c
137c478bd9Sstevel@tonic-gate ** /usr/src/linux/include/linux/bios32.h
147c478bd9Sstevel@tonic-gate ** /usr/src/linux/drivers/net/ne.c
157c478bd9Sstevel@tonic-gate */
167c478bd9Sstevel@tonic-gate
177c478bd9Sstevel@tonic-gate /*
187c478bd9Sstevel@tonic-gate * This program is free software; you can redistribute it and/or
197c478bd9Sstevel@tonic-gate * modify it under the terms of the GNU General Public License as
207c478bd9Sstevel@tonic-gate * published by the Free Software Foundation; either version 2, or (at
217c478bd9Sstevel@tonic-gate * your option) any later version.
227c478bd9Sstevel@tonic-gate */
237c478bd9Sstevel@tonic-gate
247c478bd9Sstevel@tonic-gate #include "pci_ids.h"
257c478bd9Sstevel@tonic-gate
267c478bd9Sstevel@tonic-gate #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
277c478bd9Sstevel@tonic-gate #define PCI_COMMAND_MEM 0x2 /* Enable response in mem space */
287c478bd9Sstevel@tonic-gate #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
297c478bd9Sstevel@tonic-gate #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
307c478bd9Sstevel@tonic-gate #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
317c478bd9Sstevel@tonic-gate #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
327c478bd9Sstevel@tonic-gate #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
337c478bd9Sstevel@tonic-gate #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
347c478bd9Sstevel@tonic-gate #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
357c478bd9Sstevel@tonic-gate #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
367c478bd9Sstevel@tonic-gate #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
377c478bd9Sstevel@tonic-gate
387c478bd9Sstevel@tonic-gate #define PCIBIOS_PCI_FUNCTION_ID 0xb1XX
397c478bd9Sstevel@tonic-gate #define PCIBIOS_PCI_BIOS_PRESENT 0xb101
407c478bd9Sstevel@tonic-gate #define PCIBIOS_FIND_PCI_DEVICE 0xb102
417c478bd9Sstevel@tonic-gate #define PCIBIOS_FIND_PCI_CLASS_CODE 0xb103
427c478bd9Sstevel@tonic-gate #define PCIBIOS_GENERATE_SPECIAL_CYCLE 0xb106
437c478bd9Sstevel@tonic-gate #define PCIBIOS_READ_CONFIG_BYTE 0xb108
447c478bd9Sstevel@tonic-gate #define PCIBIOS_READ_CONFIG_WORD 0xb109
457c478bd9Sstevel@tonic-gate #define PCIBIOS_READ_CONFIG_DWORD 0xb10a
467c478bd9Sstevel@tonic-gate #define PCIBIOS_WRITE_CONFIG_BYTE 0xb10b
477c478bd9Sstevel@tonic-gate #define PCIBIOS_WRITE_CONFIG_WORD 0xb10c
487c478bd9Sstevel@tonic-gate #define PCIBIOS_WRITE_CONFIG_DWORD 0xb10d
497c478bd9Sstevel@tonic-gate
507c478bd9Sstevel@tonic-gate #define PCI_VENDOR_ID 0x00 /* 16 bits */
517c478bd9Sstevel@tonic-gate #define PCI_DEVICE_ID 0x02 /* 16 bits */
527c478bd9Sstevel@tonic-gate #define PCI_COMMAND 0x04 /* 16 bits */
537c478bd9Sstevel@tonic-gate
547c478bd9Sstevel@tonic-gate #define PCI_STATUS 0x06 /* 16 bits */
557c478bd9Sstevel@tonic-gate #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
567c478bd9Sstevel@tonic-gate #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
577c478bd9Sstevel@tonic-gate #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
587c478bd9Sstevel@tonic-gate #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
597c478bd9Sstevel@tonic-gate #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
607c478bd9Sstevel@tonic-gate #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
617c478bd9Sstevel@tonic-gate #define PCI_STATUS_DEVSEL_FAST 0x000
627c478bd9Sstevel@tonic-gate #define PCI_STATUS_DEVSEL_MEDIUM 0x200
637c478bd9Sstevel@tonic-gate #define PCI_STATUS_DEVSEL_SLOW 0x400
647c478bd9Sstevel@tonic-gate #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
657c478bd9Sstevel@tonic-gate #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
667c478bd9Sstevel@tonic-gate #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
677c478bd9Sstevel@tonic-gate #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
687c478bd9Sstevel@tonic-gate #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
697c478bd9Sstevel@tonic-gate
707c478bd9Sstevel@tonic-gate #define PCI_REVISION 0x08 /* 8 bits */
717c478bd9Sstevel@tonic-gate #define PCI_REVISION_ID 0x08 /* 8 bits */
727c478bd9Sstevel@tonic-gate #define PCI_CLASS_REVISION 0x08 /* 32 bits */
737c478bd9Sstevel@tonic-gate #define PCI_CLASS_CODE 0x0b /* 8 bits */
747c478bd9Sstevel@tonic-gate #define PCI_SUBCLASS_CODE 0x0a /* 8 bits */
757c478bd9Sstevel@tonic-gate #define PCI_HEADER_TYPE 0x0e /* 8 bits */
767c478bd9Sstevel@tonic-gate #define PCI_HEADER_TYPE_NORMAL 0
777c478bd9Sstevel@tonic-gate #define PCI_HEADER_TYPE_BRIDGE 1
787c478bd9Sstevel@tonic-gate #define PCI_HEADER_TYPE_CARDBUS 2
797c478bd9Sstevel@tonic-gate
807c478bd9Sstevel@tonic-gate
817c478bd9Sstevel@tonic-gate /* Header type 0 (normal devices) */
827c478bd9Sstevel@tonic-gate #define PCI_CARDBUS_CIS 0x28
837c478bd9Sstevel@tonic-gate #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
847c478bd9Sstevel@tonic-gate #define PCI_SUBSYSTEM_ID 0x2e
857c478bd9Sstevel@tonic-gate
867c478bd9Sstevel@tonic-gate #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
877c478bd9Sstevel@tonic-gate #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits */
887c478bd9Sstevel@tonic-gate #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits */
897c478bd9Sstevel@tonic-gate #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
907c478bd9Sstevel@tonic-gate #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
917c478bd9Sstevel@tonic-gate #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
927c478bd9Sstevel@tonic-gate
937c478bd9Sstevel@tonic-gate #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
947c478bd9Sstevel@tonic-gate #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
957c478bd9Sstevel@tonic-gate #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
967c478bd9Sstevel@tonic-gate #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
977c478bd9Sstevel@tonic-gate
987c478bd9Sstevel@tonic-gate #ifndef PCI_BASE_ADDRESS_IO_MASK
997c478bd9Sstevel@tonic-gate #define PCI_BASE_ADDRESS_IO_MASK (~0x03)
1007c478bd9Sstevel@tonic-gate #endif
1017c478bd9Sstevel@tonic-gate #ifndef PCI_BASE_ADDRESS_MEM_MASK
1027c478bd9Sstevel@tonic-gate #define PCI_BASE_ADDRESS_MEM_MASK (~0x0f)
1037c478bd9Sstevel@tonic-gate #endif
1047c478bd9Sstevel@tonic-gate #define PCI_BASE_ADDRESS_SPACE_IO 0x01
1057c478bd9Sstevel@tonic-gate #define PCI_ROM_ADDRESS 0x30 /* 32 bits */
1067c478bd9Sstevel@tonic-gate #define PCI_ROM_ADDRESS_ENABLE 0x01 /* Write 1 to enable ROM,
1077c478bd9Sstevel@tonic-gate bits 31..11 are address,
1087c478bd9Sstevel@tonic-gate 10..2 are reserved */
1097c478bd9Sstevel@tonic-gate
1107c478bd9Sstevel@tonic-gate #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
1117c478bd9Sstevel@tonic-gate
1127c478bd9Sstevel@tonic-gate #define PCI_INTERRUPT_LINE 0x3c /* IRQ number (0-15) */
1137c478bd9Sstevel@tonic-gate #define PCI_INTERRUPT_PIN 0x3d /* IRQ pin on PCI bus (A-D) */
1147c478bd9Sstevel@tonic-gate
1157c478bd9Sstevel@tonic-gate /* Header type 1 (PCI-to-PCI bridges) */
1167c478bd9Sstevel@tonic-gate #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
1177c478bd9Sstevel@tonic-gate #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
1187c478bd9Sstevel@tonic-gate #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
1197c478bd9Sstevel@tonic-gate #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
1207c478bd9Sstevel@tonic-gate #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
1217c478bd9Sstevel@tonic-gate #define PCI_IO_LIMIT 0x1d
1227c478bd9Sstevel@tonic-gate #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
1237c478bd9Sstevel@tonic-gate #define PCI_IO_RANGE_TYPE_16 0x00
1247c478bd9Sstevel@tonic-gate #define PCI_IO_RANGE_TYPE_32 0x01
1257c478bd9Sstevel@tonic-gate #define PCI_IO_RANGE_MASK ~0x0f
1267c478bd9Sstevel@tonic-gate #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
1277c478bd9Sstevel@tonic-gate #define PCI_MEMORY_BASE 0x20 /* Memory range behind */
1287c478bd9Sstevel@tonic-gate #define PCI_MEMORY_LIMIT 0x22
1297c478bd9Sstevel@tonic-gate #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
1307c478bd9Sstevel@tonic-gate #define PCI_MEMORY_RANGE_MASK ~0x0f
1317c478bd9Sstevel@tonic-gate #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
1327c478bd9Sstevel@tonic-gate #define PCI_PREF_MEMORY_LIMIT 0x26
1337c478bd9Sstevel@tonic-gate #define PCI_PREF_RANGE_TYPE_MASK 0x0f
1347c478bd9Sstevel@tonic-gate #define PCI_PREF_RANGE_TYPE_32 0x00
1357c478bd9Sstevel@tonic-gate #define PCI_PREF_RANGE_TYPE_64 0x01
1367c478bd9Sstevel@tonic-gate #define PCI_PREF_RANGE_MASK ~0x0f
1377c478bd9Sstevel@tonic-gate #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
1387c478bd9Sstevel@tonic-gate #define PCI_PREF_LIMIT_UPPER32 0x2c
1397c478bd9Sstevel@tonic-gate #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
1407c478bd9Sstevel@tonic-gate #define PCI_IO_LIMIT_UPPER16 0x32
1417c478bd9Sstevel@tonic-gate /* 0x34 same as for htype 0 */
1427c478bd9Sstevel@tonic-gate /* 0x35-0x3b is reserved */
1437c478bd9Sstevel@tonic-gate #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
1447c478bd9Sstevel@tonic-gate /* 0x3c-0x3d are same as for htype 0 */
1457c478bd9Sstevel@tonic-gate #define PCI_BRIDGE_CONTROL 0x3e
1467c478bd9Sstevel@tonic-gate #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
1477c478bd9Sstevel@tonic-gate #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
1487c478bd9Sstevel@tonic-gate #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
1497c478bd9Sstevel@tonic-gate #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
1507c478bd9Sstevel@tonic-gate #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
1517c478bd9Sstevel@tonic-gate #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
1527c478bd9Sstevel@tonic-gate #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
1537c478bd9Sstevel@tonic-gate
1547c478bd9Sstevel@tonic-gate #define PCI_CB_CAPABILITY_LIST 0x14
1557c478bd9Sstevel@tonic-gate
1567c478bd9Sstevel@tonic-gate /* Capability lists */
1577c478bd9Sstevel@tonic-gate
1587c478bd9Sstevel@tonic-gate #define PCI_CAP_LIST_ID 0 /* Capability ID */
1597c478bd9Sstevel@tonic-gate #define PCI_CAP_ID_PM 0x01 /* Power Management */
1607c478bd9Sstevel@tonic-gate #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
1617c478bd9Sstevel@tonic-gate #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
1627c478bd9Sstevel@tonic-gate #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
1637c478bd9Sstevel@tonic-gate #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
1647c478bd9Sstevel@tonic-gate #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
1657c478bd9Sstevel@tonic-gate #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
1667c478bd9Sstevel@tonic-gate #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
1677c478bd9Sstevel@tonic-gate #define PCI_CAP_SIZEOF 4
1687c478bd9Sstevel@tonic-gate
1697c478bd9Sstevel@tonic-gate /* Power Management Registers */
1707c478bd9Sstevel@tonic-gate
1717c478bd9Sstevel@tonic-gate #define PCI_PM_PMC 2 /* PM Capabilities Register */
1727c478bd9Sstevel@tonic-gate #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
1737c478bd9Sstevel@tonic-gate #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
1747c478bd9Sstevel@tonic-gate #define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
1757c478bd9Sstevel@tonic-gate #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
1767c478bd9Sstevel@tonic-gate #define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
1777c478bd9Sstevel@tonic-gate #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
1787c478bd9Sstevel@tonic-gate #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
1797c478bd9Sstevel@tonic-gate #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
1807c478bd9Sstevel@tonic-gate #define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
1817c478bd9Sstevel@tonic-gate #define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
1827c478bd9Sstevel@tonic-gate #define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
1837c478bd9Sstevel@tonic-gate #define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
1847c478bd9Sstevel@tonic-gate #define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
1857c478bd9Sstevel@tonic-gate #define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
1867c478bd9Sstevel@tonic-gate #define PCI_PM_CTRL 4 /* PM control and status register */
1877c478bd9Sstevel@tonic-gate #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
1887c478bd9Sstevel@tonic-gate #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
1897c478bd9Sstevel@tonic-gate #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
1907c478bd9Sstevel@tonic-gate #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
1917c478bd9Sstevel@tonic-gate #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
1927c478bd9Sstevel@tonic-gate #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
1937c478bd9Sstevel@tonic-gate #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
1947c478bd9Sstevel@tonic-gate #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
1957c478bd9Sstevel@tonic-gate #define PCI_PM_DATA_REGISTER 7 /* (??) */
1967c478bd9Sstevel@tonic-gate #define PCI_PM_SIZEOF 8
1977c478bd9Sstevel@tonic-gate
1987c478bd9Sstevel@tonic-gate /* AGP registers */
1997c478bd9Sstevel@tonic-gate
2007c478bd9Sstevel@tonic-gate #define PCI_AGP_VERSION 2 /* BCD version number */
2017c478bd9Sstevel@tonic-gate #define PCI_AGP_RFU 3 /* Rest of capability flags */
2027c478bd9Sstevel@tonic-gate #define PCI_AGP_STATUS 4 /* Status register */
2037c478bd9Sstevel@tonic-gate #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
2047c478bd9Sstevel@tonic-gate #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
2057c478bd9Sstevel@tonic-gate #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
2067c478bd9Sstevel@tonic-gate #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
2077c478bd9Sstevel@tonic-gate #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
2087c478bd9Sstevel@tonic-gate #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
2097c478bd9Sstevel@tonic-gate #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
2107c478bd9Sstevel@tonic-gate #define PCI_AGP_COMMAND 8 /* Control register */
2117c478bd9Sstevel@tonic-gate #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
2127c478bd9Sstevel@tonic-gate #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
2137c478bd9Sstevel@tonic-gate #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
2147c478bd9Sstevel@tonic-gate #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
2157c478bd9Sstevel@tonic-gate #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
2167c478bd9Sstevel@tonic-gate #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
2177c478bd9Sstevel@tonic-gate #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */
2187c478bd9Sstevel@tonic-gate #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */
2197c478bd9Sstevel@tonic-gate #define PCI_AGP_SIZEOF 12
2207c478bd9Sstevel@tonic-gate
2217c478bd9Sstevel@tonic-gate /* Slot Identification */
2227c478bd9Sstevel@tonic-gate
2237c478bd9Sstevel@tonic-gate #define PCI_SID_ESR 2 /* Expansion Slot Register */
2247c478bd9Sstevel@tonic-gate #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
2257c478bd9Sstevel@tonic-gate #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
2267c478bd9Sstevel@tonic-gate #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
2277c478bd9Sstevel@tonic-gate
2287c478bd9Sstevel@tonic-gate /* Message Signalled Interrupts registers */
2297c478bd9Sstevel@tonic-gate
2307c478bd9Sstevel@tonic-gate #define PCI_MSI_FLAGS 2 /* Various flags */
2317c478bd9Sstevel@tonic-gate #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
2327c478bd9Sstevel@tonic-gate #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
2337c478bd9Sstevel@tonic-gate #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
2347c478bd9Sstevel@tonic-gate #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
2357c478bd9Sstevel@tonic-gate #define PCI_MSI_RFU 3 /* Rest of capability flags */
2367c478bd9Sstevel@tonic-gate #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
2377c478bd9Sstevel@tonic-gate #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
2387c478bd9Sstevel@tonic-gate #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
2397c478bd9Sstevel@tonic-gate #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
2407c478bd9Sstevel@tonic-gate
2417c478bd9Sstevel@tonic-gate #define PCI_SLOT(devfn) ((devfn) >> 3)
2427c478bd9Sstevel@tonic-gate #define PCI_FUNC(devfn) ((devfn) & 0x07)
2437c478bd9Sstevel@tonic-gate
2447c478bd9Sstevel@tonic-gate #define BIOS32_SIGNATURE (('_' << 0) + ('3' << 8) + ('2' << 16) + ('_' << 24))
2457c478bd9Sstevel@tonic-gate
2467c478bd9Sstevel@tonic-gate /* PCI signature: "PCI " */
2477c478bd9Sstevel@tonic-gate #define PCI_SIGNATURE (('P' << 0) + ('C' << 8) + ('I' << 16) + (' ' << 24))
2487c478bd9Sstevel@tonic-gate
2497c478bd9Sstevel@tonic-gate /* PCI service signature: "$PCI" */
2507c478bd9Sstevel@tonic-gate #define PCI_SERVICE (('$' << 0) + ('P' << 8) + ('C' << 16) + ('I' << 24))
2517c478bd9Sstevel@tonic-gate
2527c478bd9Sstevel@tonic-gate union bios32 {
2537c478bd9Sstevel@tonic-gate struct {
2547c478bd9Sstevel@tonic-gate unsigned long signature; /* _32_ */
2557c478bd9Sstevel@tonic-gate unsigned long entry; /* 32 bit physical address */
2567c478bd9Sstevel@tonic-gate unsigned char revision; /* Revision level, 0 */
2577c478bd9Sstevel@tonic-gate unsigned char length; /* Length in paragraphs should be 01 */
2587c478bd9Sstevel@tonic-gate unsigned char checksum; /* All bytes must add up to zero */
2597c478bd9Sstevel@tonic-gate unsigned char reserved[5]; /* Must be zero */
2607c478bd9Sstevel@tonic-gate } fields;
2617c478bd9Sstevel@tonic-gate char chars[16];
2627c478bd9Sstevel@tonic-gate };
2637c478bd9Sstevel@tonic-gate
2647c478bd9Sstevel@tonic-gate struct pci_device;
2657c478bd9Sstevel@tonic-gate struct dev;
2667c478bd9Sstevel@tonic-gate typedef int (*pci_probe_t)(struct dev *, struct pci_device *);
2677c478bd9Sstevel@tonic-gate
2687c478bd9Sstevel@tonic-gate struct pci_device {
2697c478bd9Sstevel@tonic-gate uint32_t class;
2707c478bd9Sstevel@tonic-gate uint16_t vendor, dev_id;
2717c478bd9Sstevel@tonic-gate const char *name;
2727c478bd9Sstevel@tonic-gate /* membase and ioaddr are silly and depricated */
2737c478bd9Sstevel@tonic-gate unsigned int membase;
2747c478bd9Sstevel@tonic-gate unsigned int ioaddr;
2757c478bd9Sstevel@tonic-gate unsigned int romaddr;
2767c478bd9Sstevel@tonic-gate unsigned char irq;
2777c478bd9Sstevel@tonic-gate unsigned char devfn;
2787c478bd9Sstevel@tonic-gate unsigned char bus;
2797c478bd9Sstevel@tonic-gate unsigned char use_specified;
2807c478bd9Sstevel@tonic-gate const struct pci_driver *driver;
2817c478bd9Sstevel@tonic-gate };
2827c478bd9Sstevel@tonic-gate
2837c478bd9Sstevel@tonic-gate extern void scan_pci_bus(int type, struct pci_device *dev);
2847c478bd9Sstevel@tonic-gate extern void find_pci(int type, struct pci_device *dev);
2857c478bd9Sstevel@tonic-gate
2867c478bd9Sstevel@tonic-gate extern int pcibios_read_config_byte(unsigned int bus, unsigned int device_fn, unsigned int where, uint8_t *value);
2877c478bd9Sstevel@tonic-gate extern int pcibios_write_config_byte (unsigned int bus, unsigned int device_fn, unsigned int where, uint8_t value);
2887c478bd9Sstevel@tonic-gate extern int pcibios_read_config_word(unsigned int bus, unsigned int device_fn, unsigned int where, uint16_t *value);
2897c478bd9Sstevel@tonic-gate extern int pcibios_write_config_word (unsigned int bus, unsigned int device_fn, unsigned int where, uint16_t value);
2907c478bd9Sstevel@tonic-gate extern int pcibios_read_config_dword(unsigned int bus, unsigned int device_fn, unsigned int where, uint32_t *value);
2917c478bd9Sstevel@tonic-gate extern int pcibios_write_config_dword(unsigned int bus, unsigned int device_fn, unsigned int where, uint32_t value);
2927c478bd9Sstevel@tonic-gate extern unsigned long pcibios_bus_base(unsigned int bus);
2937c478bd9Sstevel@tonic-gate extern void adjust_pci_device(struct pci_device *p);
2947c478bd9Sstevel@tonic-gate
2957c478bd9Sstevel@tonic-gate
2967c478bd9Sstevel@tonic-gate static inline int
pci_read_config_byte(struct pci_device * dev,unsigned int where,uint8_t * value)2977c478bd9Sstevel@tonic-gate pci_read_config_byte(struct pci_device *dev, unsigned int where, uint8_t *value)
2987c478bd9Sstevel@tonic-gate {
2997c478bd9Sstevel@tonic-gate return pcibios_read_config_byte(dev->bus, dev->devfn, where, value);
3007c478bd9Sstevel@tonic-gate }
3017c478bd9Sstevel@tonic-gate static inline int
pci_write_config_byte(struct pci_device * dev,unsigned int where,uint8_t value)3027c478bd9Sstevel@tonic-gate pci_write_config_byte(struct pci_device *dev, unsigned int where, uint8_t value)
3037c478bd9Sstevel@tonic-gate {
3047c478bd9Sstevel@tonic-gate return pcibios_write_config_byte(dev->bus, dev->devfn, where, value);
3057c478bd9Sstevel@tonic-gate }
3067c478bd9Sstevel@tonic-gate static inline int
pci_read_config_word(struct pci_device * dev,unsigned int where,uint16_t * value)3077c478bd9Sstevel@tonic-gate pci_read_config_word(struct pci_device *dev, unsigned int where, uint16_t *value)
3087c478bd9Sstevel@tonic-gate {
3097c478bd9Sstevel@tonic-gate return pcibios_read_config_word(dev->bus, dev->devfn, where, value);
3107c478bd9Sstevel@tonic-gate }
3117c478bd9Sstevel@tonic-gate static inline int
pci_write_config_word(struct pci_device * dev,unsigned int where,uint16_t value)3127c478bd9Sstevel@tonic-gate pci_write_config_word(struct pci_device *dev, unsigned int where, uint16_t value)
3137c478bd9Sstevel@tonic-gate {
3147c478bd9Sstevel@tonic-gate return pcibios_write_config_word(dev->bus, dev->devfn, where, value);
3157c478bd9Sstevel@tonic-gate }
3167c478bd9Sstevel@tonic-gate static inline int
pci_read_config_dword(struct pci_device * dev,unsigned int where,uint32_t * value)3177c478bd9Sstevel@tonic-gate pci_read_config_dword(struct pci_device *dev, unsigned int where, uint32_t *value)
3187c478bd9Sstevel@tonic-gate {
3197c478bd9Sstevel@tonic-gate return pcibios_read_config_dword(dev->bus, dev->devfn, where, value);
3207c478bd9Sstevel@tonic-gate }
3217c478bd9Sstevel@tonic-gate static inline int
pci_write_config_dword(struct pci_device * dev,unsigned int where,uint32_t value)3227c478bd9Sstevel@tonic-gate pci_write_config_dword(struct pci_device *dev, unsigned int where, uint32_t value)
3237c478bd9Sstevel@tonic-gate {
3247c478bd9Sstevel@tonic-gate return pcibios_write_config_dword(dev->bus, dev->devfn, where, value);
3257c478bd9Sstevel@tonic-gate }
3267c478bd9Sstevel@tonic-gate
3277c478bd9Sstevel@tonic-gate /* Helper functions to find the size of a pci bar */
3287c478bd9Sstevel@tonic-gate extern unsigned long pci_bar_start(struct pci_device *dev, unsigned int bar);
3297c478bd9Sstevel@tonic-gate extern unsigned long pci_bar_size(struct pci_device *dev, unsigned int bar);
3307c478bd9Sstevel@tonic-gate /* Helper function to find pci capabilities */
3317c478bd9Sstevel@tonic-gate extern int pci_find_capability(struct pci_device *dev, int cap);
3327c478bd9Sstevel@tonic-gate struct pci_id {
3337c478bd9Sstevel@tonic-gate unsigned short vendor, dev_id;
3347c478bd9Sstevel@tonic-gate const char *name;
3357c478bd9Sstevel@tonic-gate };
3367c478bd9Sstevel@tonic-gate
3377c478bd9Sstevel@tonic-gate struct dev;
3387c478bd9Sstevel@tonic-gate /* Most pci drivers will use this */
3397c478bd9Sstevel@tonic-gate struct pci_driver {
3407c478bd9Sstevel@tonic-gate int type;
3417c478bd9Sstevel@tonic-gate const char *name;
3427c478bd9Sstevel@tonic-gate pci_probe_t probe;
3437c478bd9Sstevel@tonic-gate struct pci_id *ids;
3447c478bd9Sstevel@tonic-gate int id_count;
3457c478bd9Sstevel@tonic-gate
3467c478bd9Sstevel@tonic-gate /* On a few occasions the hardware is standardized enough that
3477c478bd9Sstevel@tonic-gate * we only need to know the class of the device and not the exact
3487c478bd9Sstevel@tonic-gate * type to drive the device correctly. If this is the case
3497c478bd9Sstevel@tonic-gate * set a class value other than 0.
3507c478bd9Sstevel@tonic-gate */
3517c478bd9Sstevel@tonic-gate unsigned short class;
3527c478bd9Sstevel@tonic-gate };
3537c478bd9Sstevel@tonic-gate
3547c478bd9Sstevel@tonic-gate #define PCI_ROM(VENDOR_ID, DEVICE_ID, IMAGE, DESCRIPTION) \
3557c478bd9Sstevel@tonic-gate { VENDOR_ID, DEVICE_ID, IMAGE, }
3567c478bd9Sstevel@tonic-gate
3577c478bd9Sstevel@tonic-gate #endif /* PCI_H */
358