17c478bd9Sstevel@tonic-gate #ifndef _EPIC100_H_ 27c478bd9Sstevel@tonic-gate # define _EPIC100_H_ 37c478bd9Sstevel@tonic-gate 47c478bd9Sstevel@tonic-gate #ifndef PCI_VENDOR_SMC 57c478bd9Sstevel@tonic-gate # define PCI_VENDOR_SMC 0x10B8 67c478bd9Sstevel@tonic-gate #endif 77c478bd9Sstevel@tonic-gate 87c478bd9Sstevel@tonic-gate #ifndef PCI_DEVICE_SMC_EPIC100 97c478bd9Sstevel@tonic-gate # define PCI_DEVICE_SMC_EPIC100 0x0005 107c478bd9Sstevel@tonic-gate #endif 117c478bd9Sstevel@tonic-gate 127c478bd9Sstevel@tonic-gate #define PCI_DEVICE_ID_NONE 0xFFFF 137c478bd9Sstevel@tonic-gate 147c478bd9Sstevel@tonic-gate /* Offsets to registers (using SMC names). */ 157c478bd9Sstevel@tonic-gate enum epic100_registers { 167c478bd9Sstevel@tonic-gate COMMAND= 0, /* Control Register */ 177c478bd9Sstevel@tonic-gate INTSTAT= 4, /* Interrupt Status */ 187c478bd9Sstevel@tonic-gate INTMASK= 8, /* Interrupt Mask */ 197c478bd9Sstevel@tonic-gate GENCTL = 0x0C, /* General Control */ 207c478bd9Sstevel@tonic-gate NVCTL = 0x10, /* Non Volatile Control */ 217c478bd9Sstevel@tonic-gate EECTL = 0x14, /* EEPROM Control */ 227c478bd9Sstevel@tonic-gate TEST = 0x1C, /* Test register: marked as reserved (see in source code) */ 237c478bd9Sstevel@tonic-gate CRCCNT = 0x20, /* CRC Error Counter */ 247c478bd9Sstevel@tonic-gate ALICNT = 0x24, /* Frame Alignment Error Counter */ 257c478bd9Sstevel@tonic-gate MPCNT = 0x28, /* Missed Packet Counter */ 267c478bd9Sstevel@tonic-gate MMCTL = 0x30, /* MII Management Interface Control */ 277c478bd9Sstevel@tonic-gate MMDATA = 0x34, /* MII Management Interface Data */ 287c478bd9Sstevel@tonic-gate MIICFG = 0x38, /* MII Configuration */ 297c478bd9Sstevel@tonic-gate IPG = 0x3C, /* InterPacket Gap */ 307c478bd9Sstevel@tonic-gate LAN0 = 0x40, /* MAC address. (0x40-0x48) */ 317c478bd9Sstevel@tonic-gate IDCHK = 0x4C, /* BoardID/ Checksum */ 327c478bd9Sstevel@tonic-gate MC0 = 0x50, /* Multicast filter table. (0x50-0x5c) */ 337c478bd9Sstevel@tonic-gate RXCON = 0x60, /* Receive Control */ 347c478bd9Sstevel@tonic-gate TXCON = 0x70, /* Transmit Control */ 357c478bd9Sstevel@tonic-gate TXSTAT = 0x74, /* Transmit Status */ 367c478bd9Sstevel@tonic-gate PRCDAR = 0x84, /* PCI Receive Current Descriptor Address */ 377c478bd9Sstevel@tonic-gate PRSTAT = 0xA4, /* PCI Receive DMA Status */ 387c478bd9Sstevel@tonic-gate PRCPTHR= 0xB0, /* PCI Receive Copy Threshold */ 397c478bd9Sstevel@tonic-gate PTCDAR = 0xC4, /* PCI Transmit Current Descriptor Address */ 407c478bd9Sstevel@tonic-gate ETHTHR = 0xDC /* Early Transmit Threshold */ 417c478bd9Sstevel@tonic-gate }; 427c478bd9Sstevel@tonic-gate 437c478bd9Sstevel@tonic-gate /* Command register (CR_) bits */ 447c478bd9Sstevel@tonic-gate #define CR_STOP_RX (0x00000001) 457c478bd9Sstevel@tonic-gate #define CR_START_RX (0x00000002) 467c478bd9Sstevel@tonic-gate #define CR_QUEUE_TX (0x00000004) 477c478bd9Sstevel@tonic-gate #define CR_QUEUE_RX (0x00000008) 487c478bd9Sstevel@tonic-gate #define CR_NEXTFRAME (0x00000010) 497c478bd9Sstevel@tonic-gate #define CR_STOP_TX_DMA (0x00000020) 507c478bd9Sstevel@tonic-gate #define CR_STOP_RX_DMA (0x00000040) 517c478bd9Sstevel@tonic-gate #define CR_TX_UGO (0x00000080) 527c478bd9Sstevel@tonic-gate 537c478bd9Sstevel@tonic-gate /* Interrupt register bits. NI means No Interrupt generated */ 547c478bd9Sstevel@tonic-gate 557c478bd9Sstevel@tonic-gate #define INTR_RX_THR_STA (0x00400000) /* rx copy threshold status NI */ 567c478bd9Sstevel@tonic-gate #define INTR_RX_BUFF_EMPTY (0x00200000) /* rx buffers empty. NI */ 577c478bd9Sstevel@tonic-gate #define INTR_TX_IN_PROG (0x00100000) /* tx copy in progess. NI */ 587c478bd9Sstevel@tonic-gate #define INTR_RX_IN_PROG (0x00080000) /* rx copy in progress. NI */ 597c478bd9Sstevel@tonic-gate #define INTR_TXIDLE (0x00040000) /* tx idle. NI */ 607c478bd9Sstevel@tonic-gate #define INTR_RXIDLE (0x00020000) /* rx idle. NI */ 617c478bd9Sstevel@tonic-gate #define INTR_INTR_ACTIVE (0x00010000) /* Interrupt active. NI */ 627c478bd9Sstevel@tonic-gate #define INTR_RX_STATUS_OK (0x00008000) /* rx status valid. NI */ 637c478bd9Sstevel@tonic-gate #define INTR_PCI_TGT_ABT (0x00004000) /* PCI Target abort */ 647c478bd9Sstevel@tonic-gate #define INTR_PCI_MASTER_ABT (0x00002000) /* PCI Master abort */ 657c478bd9Sstevel@tonic-gate #define INTR_PCI_PARITY_ERR (0x00001000) /* PCI adress parity error */ 667c478bd9Sstevel@tonic-gate #define INTR_PCI_DATA_ERR (0x00000800) /* PCI data parity error */ 677c478bd9Sstevel@tonic-gate #define INTR_RX_THR_CROSSED (0x00000400) /* rx copy threshold crossed */ 687c478bd9Sstevel@tonic-gate #define INTR_CNTFULL (0x00000200) /* Counter overflow */ 697c478bd9Sstevel@tonic-gate #define INTR_TXUNDERRUN (0x00000100) /* tx underrun. */ 707c478bd9Sstevel@tonic-gate #define INTR_TXEMPTY (0x00000080) /* tx queue empty */ 717c478bd9Sstevel@tonic-gate #define INTR_TX_CH_COMPLETE (0x00000040) /* tx chain complete */ 727c478bd9Sstevel@tonic-gate #define INTR_TXDONE (0x00000020) /* tx complete (w or w/o err) */ 737c478bd9Sstevel@tonic-gate #define INTR_RXERROR (0x00000010) /* rx error (CRC) */ 747c478bd9Sstevel@tonic-gate #define INTR_RXOVERFLOW (0x00000008) /* rx buffer overflow */ 757c478bd9Sstevel@tonic-gate #define INTR_RX_QUEUE_EMPTY (0x00000004) /* rx queue empty. */ 767c478bd9Sstevel@tonic-gate #define INTR_RXHEADER (0x00000002) /* header copy complete */ 777c478bd9Sstevel@tonic-gate #define INTR_RXDONE (0x00000001) /* Receive copy complete */ 787c478bd9Sstevel@tonic-gate 797c478bd9Sstevel@tonic-gate #define INTR_CLEARINTR (0x00007FFF) 807c478bd9Sstevel@tonic-gate #define INTR_VALIDBITS (0x007FFFFF) 817c478bd9Sstevel@tonic-gate #define INTR_DISABLE (0x00000000) 827c478bd9Sstevel@tonic-gate #define INTR_CLEARERRS (0x00007F18) 837c478bd9Sstevel@tonic-gate #define INTR_ABNINTR (INTR_CNTFULL | INTR_TXUNDERRUN | INTR_RXOVERFLOW) 847c478bd9Sstevel@tonic-gate 857c478bd9Sstevel@tonic-gate /* General Control (GC_) bits */ 867c478bd9Sstevel@tonic-gate 877c478bd9Sstevel@tonic-gate #define GC_SOFT_RESET (0x00000001) 887c478bd9Sstevel@tonic-gate #define GC_INTR_ENABLE (0x00000002) 897c478bd9Sstevel@tonic-gate #define GC_SOFT_INTR (0x00000004) 907c478bd9Sstevel@tonic-gate #define GC_POWER_DOWN (0x00000008) 917c478bd9Sstevel@tonic-gate #define GC_ONE_COPY (0x00000010) 927c478bd9Sstevel@tonic-gate #define GC_BIG_ENDIAN (0x00000020) 937c478bd9Sstevel@tonic-gate #define GC_RX_PREEMPT_TX (0x00000040) 947c478bd9Sstevel@tonic-gate #define GC_TX_PREEMPT_RX (0x00000080) 957c478bd9Sstevel@tonic-gate 967c478bd9Sstevel@tonic-gate /* 977c478bd9Sstevel@tonic-gate * Receive FIFO Threshold values 987c478bd9Sstevel@tonic-gate * Control the level at which the PCI burst state machine 997c478bd9Sstevel@tonic-gate * begins to empty the receive FIFO. Possible values: 0-3 1007c478bd9Sstevel@tonic-gate * 1017c478bd9Sstevel@tonic-gate * 0 => 32, 1 => 64, 2 => 96 3 => 128 bytes. 1027c478bd9Sstevel@tonic-gate */ 1037c478bd9Sstevel@tonic-gate #define GC_RX_FIFO_THR_32 (0x00000000) 1047c478bd9Sstevel@tonic-gate #define GC_RX_FIFO_THR_64 (0x00000100) 1057c478bd9Sstevel@tonic-gate #define GC_RX_FIFO_THR_96 (0x00000200) 1067c478bd9Sstevel@tonic-gate #define GC_RX_FIFO_THR_128 (0x00000300) 1077c478bd9Sstevel@tonic-gate 1087c478bd9Sstevel@tonic-gate /* Memory Read Control (MRC_) values */ 1097c478bd9Sstevel@tonic-gate #define GC_MRC_MEM_READ (0x00000000) 1107c478bd9Sstevel@tonic-gate #define GC_MRC_READ_MULT (0x00000400) 1117c478bd9Sstevel@tonic-gate #define GC_MRC_READ_LINE (0x00000800) 1127c478bd9Sstevel@tonic-gate 1137c478bd9Sstevel@tonic-gate #define GC_SOFTBIT0 (0x00001000) 1147c478bd9Sstevel@tonic-gate #define GC_SOFTBIT1 (0x00002000) 1157c478bd9Sstevel@tonic-gate #define GC_RESET_PHY (0x00004000) 1167c478bd9Sstevel@tonic-gate 1177c478bd9Sstevel@tonic-gate /* Definitions of the Receive Control (RC_) register bits */ 1187c478bd9Sstevel@tonic-gate 1197c478bd9Sstevel@tonic-gate #define RC_SAVE_ERRORED_PKT (0x00000001) 1207c478bd9Sstevel@tonic-gate #define RC_SAVE_RUNT_FRAMES (0x00000002) 1217c478bd9Sstevel@tonic-gate #define RC_RCV_BROADCAST (0x00000004) 1227c478bd9Sstevel@tonic-gate #define RC_RCV_MULTICAST (0x00000008) 1237c478bd9Sstevel@tonic-gate #define RC_RCV_INVERSE_PKT (0x00000010) 1247c478bd9Sstevel@tonic-gate #define RC_PROMISCUOUS_MODE (0x00000020) 1257c478bd9Sstevel@tonic-gate #define RC_MONITOR_MODE (0x00000040) 1267c478bd9Sstevel@tonic-gate #define RC_EARLY_RCV_ENABLE (0x00000080) 1277c478bd9Sstevel@tonic-gate 1287c478bd9Sstevel@tonic-gate /* description of the rx descriptors control bits */ 1297c478bd9Sstevel@tonic-gate #define RD_FRAGLIST (0x0001) /* Desc points to a fragment list */ 1307c478bd9Sstevel@tonic-gate #define RD_LLFORM (0x0002) /* Frag list format */ 1317c478bd9Sstevel@tonic-gate #define RD_HDR_CPY (0x0004) /* Desc used for header copy */ 1327c478bd9Sstevel@tonic-gate 1337c478bd9Sstevel@tonic-gate /* Definition of the Transmit CONTROL (TC) register bits */ 1347c478bd9Sstevel@tonic-gate 1357c478bd9Sstevel@tonic-gate #define TC_EARLY_TX_ENABLE (0x00000001) 1367c478bd9Sstevel@tonic-gate 1377c478bd9Sstevel@tonic-gate /* Loopback Mode (LM_) Select valuesbits */ 1387c478bd9Sstevel@tonic-gate #define TC_LM_NORMAL (0x00000000) 1397c478bd9Sstevel@tonic-gate #define TC_LM_INTERNAL (0x00000002) 1407c478bd9Sstevel@tonic-gate #define TC_LM_EXTERNAL (0x00000004) 1417c478bd9Sstevel@tonic-gate #define TC_LM_FULL_DPX (0x00000006) 1427c478bd9Sstevel@tonic-gate 1437c478bd9Sstevel@tonic-gate #define TX_SLOT_TIME (0x00000078) 1447c478bd9Sstevel@tonic-gate 1457c478bd9Sstevel@tonic-gate /* Bytes transferred to chip before transmission starts. */ 1467c478bd9Sstevel@tonic-gate #define TX_FIFO_THRESH 128 /* Rounded down to 4 byte units. */ 1477c478bd9Sstevel@tonic-gate 1487c478bd9Sstevel@tonic-gate /* description of rx descriptors status bits */ 1497c478bd9Sstevel@tonic-gate #define RRING_PKT_INTACT (0x0001) 1507c478bd9Sstevel@tonic-gate #define RRING_ALIGN_ERR (0x0002) 1517c478bd9Sstevel@tonic-gate #define RRING_CRC_ERR (0x0004) 1527c478bd9Sstevel@tonic-gate #define RRING_MISSED_PKT (0x0008) 1537c478bd9Sstevel@tonic-gate #define RRING_MULTICAST (0x0010) 1547c478bd9Sstevel@tonic-gate #define RRING_BROADCAST (0x0020) 1557c478bd9Sstevel@tonic-gate #define RRING_RECEIVER_DISABLE (0x0040) 1567c478bd9Sstevel@tonic-gate #define RRING_STATUS_VALID (0x1000) 1577c478bd9Sstevel@tonic-gate #define RRING_FRAGLIST_ERR (0x2000) 1587c478bd9Sstevel@tonic-gate #define RRING_HDR_COPIED (0x4000) 1597c478bd9Sstevel@tonic-gate #define RRING_OWN (0x8000) 1607c478bd9Sstevel@tonic-gate 1617c478bd9Sstevel@tonic-gate /* error summary */ 1627c478bd9Sstevel@tonic-gate #define RRING_ERROR (RRING_ALIGN_ERR|RRING_CRC_ERR) 1637c478bd9Sstevel@tonic-gate 1647c478bd9Sstevel@tonic-gate /* description of tx descriptors status bits */ 1657c478bd9Sstevel@tonic-gate #define TRING_PKT_INTACT (0x0001) /* pkt transmitted. */ 1667c478bd9Sstevel@tonic-gate #define TRING_PKT_NONDEFER (0x0002) /* pkt xmitted w/o deferring */ 1677c478bd9Sstevel@tonic-gate #define TRING_COLL (0x0004) /* pkt xmitted w collisions */ 1687c478bd9Sstevel@tonic-gate #define TRING_CARR (0x0008) /* carrier sense lost */ 1697c478bd9Sstevel@tonic-gate #define TRING_UNDERRUN (0x0010) /* DMA underrun */ 1707c478bd9Sstevel@tonic-gate #define TRING_HB_COLL (0x0020) /* Collision detect Heartbeat */ 1717c478bd9Sstevel@tonic-gate #define TRING_WIN_COLL (0x0040) /* out of window collision */ 1727c478bd9Sstevel@tonic-gate #define TRING_DEFERRED (0x0080) /* Deferring */ 1737c478bd9Sstevel@tonic-gate #define TRING_COLL_COUNT (0x0F00) /* collision counter (mask) */ 1747c478bd9Sstevel@tonic-gate #define TRING_COLL_EXCESS (0x1000) /* tx aborted: excessive colls */ 1757c478bd9Sstevel@tonic-gate #define TRING_OWN (0x8000) /* desc ownership bit */ 1767c478bd9Sstevel@tonic-gate 1777c478bd9Sstevel@tonic-gate /* error summary */ 1787c478bd9Sstevel@tonic-gate #define TRING_ABORT (TRING_COLL_EXCESS|TRING_WIN_COLL|TRING_UNDERRUN) 1797c478bd9Sstevel@tonic-gate #define TRING_ERROR (TRING_DEFERRED|TRING_WIN_COLL|TRING_UNDERRUN|TRING_CARR/*|TRING_COLL*/ ) 1807c478bd9Sstevel@tonic-gate 1817c478bd9Sstevel@tonic-gate /* description of the tx descriptors control bits */ 1827c478bd9Sstevel@tonic-gate #define TD_FRAGLIST (0x0001) /* Desc points to a fragment list */ 1837c478bd9Sstevel@tonic-gate #define TD_LLFORM (0x0002) /* Frag list format */ 1847c478bd9Sstevel@tonic-gate #define TD_IAF (0x0004) /* Generate Interrupt after tx */ 1857c478bd9Sstevel@tonic-gate #define TD_NOCRC (0x0008) /* No CRC generated */ 1867c478bd9Sstevel@tonic-gate #define TD_LASTDESC (0x0010) /* Last desc for this frame */ 1877c478bd9Sstevel@tonic-gate 1887c478bd9Sstevel@tonic-gate #endif /* _EPIC100_H_ */ 189