17c478bd9Sstevel@tonic-gate /**************************************************************************
27c478bd9Sstevel@tonic-gate Etherboot -  BOOTP/TFTP Bootstrap Program
37c478bd9Sstevel@tonic-gate Inter Pro 1000 for Etherboot
47c478bd9Sstevel@tonic-gate Drivers are port from Intel's Linux driver e1000-4.3.15
57c478bd9Sstevel@tonic-gate 
67c478bd9Sstevel@tonic-gate ***************************************************************************/
77c478bd9Sstevel@tonic-gate /*******************************************************************************
87c478bd9Sstevel@tonic-gate 
97c478bd9Sstevel@tonic-gate 
107c478bd9Sstevel@tonic-gate   Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
117c478bd9Sstevel@tonic-gate 
127c478bd9Sstevel@tonic-gate   This program is free software; you can redistribute it and/or modify it
137c478bd9Sstevel@tonic-gate   under the terms of the GNU General Public License as published by the Free
147c478bd9Sstevel@tonic-gate   Software Foundation; either version 2 of the License, or (at your option)
157c478bd9Sstevel@tonic-gate   any later version.
167c478bd9Sstevel@tonic-gate 
177c478bd9Sstevel@tonic-gate   This program is distributed in the hope that it will be useful, but WITHOUT
187c478bd9Sstevel@tonic-gate   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
197c478bd9Sstevel@tonic-gate   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
207c478bd9Sstevel@tonic-gate   more details.
217c478bd9Sstevel@tonic-gate 
227c478bd9Sstevel@tonic-gate   You should have received a copy of the GNU General Public License along with
237c478bd9Sstevel@tonic-gate   this program; if not, write to the Free Software Foundation, Inc., 59
247c478bd9Sstevel@tonic-gate   Temple Place - Suite 330, Boston, MA  02111-1307, USA.
257c478bd9Sstevel@tonic-gate 
267c478bd9Sstevel@tonic-gate   The full GNU General Public License is included in this distribution in the
277c478bd9Sstevel@tonic-gate   file called LICENSE.
287c478bd9Sstevel@tonic-gate 
297c478bd9Sstevel@tonic-gate   Contact Information:
307c478bd9Sstevel@tonic-gate   Linux NICS <linux.nics@intel.com>
317c478bd9Sstevel@tonic-gate   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
327c478bd9Sstevel@tonic-gate 
337c478bd9Sstevel@tonic-gate *******************************************************************************/
347c478bd9Sstevel@tonic-gate /*
357c478bd9Sstevel@tonic-gate  *  Copyright (C) Archway Digital Solutions.
367c478bd9Sstevel@tonic-gate  *
377c478bd9Sstevel@tonic-gate  *  written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
387c478bd9Sstevel@tonic-gate  *  2/9/2002
397c478bd9Sstevel@tonic-gate  *
407c478bd9Sstevel@tonic-gate  *  Copyright (C) Linux Networx.
417c478bd9Sstevel@tonic-gate  *  Massive upgrade to work with the new intel gigabit NICs.
427c478bd9Sstevel@tonic-gate  *  <ebiederman at lnxi dot com>
437c478bd9Sstevel@tonic-gate  *
447c478bd9Sstevel@tonic-gate  *  Support for 82541ei & 82547ei chips from Intel's Linux driver 5.1.13 added by
457c478bd9Sstevel@tonic-gate  *  Georg Baum <gbaum@users.sf.net>, sponsored by PetaMem GmbH and linkLINE Communications, Inc.
467c478bd9Sstevel@tonic-gate  *
477c478bd9Sstevel@tonic-gate  *  01/2004: Updated to Linux driver 5.2.22 by Georg Baum <gbaum@users.sf.net>
487c478bd9Sstevel@tonic-gate  */
497c478bd9Sstevel@tonic-gate 
507c478bd9Sstevel@tonic-gate /* to get some global routines like printf */
517c478bd9Sstevel@tonic-gate #include "etherboot.h"
527c478bd9Sstevel@tonic-gate /* to get the interface to the body of the program */
537c478bd9Sstevel@tonic-gate #include "nic.h"
547c478bd9Sstevel@tonic-gate /* to get the PCI support functions, if this is a PCI NIC */
557c478bd9Sstevel@tonic-gate #include "pci.h"
567c478bd9Sstevel@tonic-gate #include "timer.h"
577c478bd9Sstevel@tonic-gate 
587c478bd9Sstevel@tonic-gate typedef unsigned char *dma_addr_t;
597c478bd9Sstevel@tonic-gate 
607c478bd9Sstevel@tonic-gate typedef enum {
617c478bd9Sstevel@tonic-gate 	FALSE = 0,
627c478bd9Sstevel@tonic-gate 	TRUE = 1
637c478bd9Sstevel@tonic-gate } boolean_t;
647c478bd9Sstevel@tonic-gate 
657c478bd9Sstevel@tonic-gate #define DEBUG 0
667c478bd9Sstevel@tonic-gate 
677c478bd9Sstevel@tonic-gate 
687c478bd9Sstevel@tonic-gate /* Some pieces of code are disabled with #if 0 ... #endif.
697c478bd9Sstevel@tonic-gate  * They are not deleted to show where the etherboot driver differs
707c478bd9Sstevel@tonic-gate  * from the linux driver below the function level.
717c478bd9Sstevel@tonic-gate  * Some member variables of the hw struct have been eliminated
727c478bd9Sstevel@tonic-gate  * and the corresponding inplace checks inserted instead.
737c478bd9Sstevel@tonic-gate  * Pieces such as LED handling that we definitely don't need are deleted.
747c478bd9Sstevel@tonic-gate  *
757c478bd9Sstevel@tonic-gate  * The following defines should not be needed normally,
767c478bd9Sstevel@tonic-gate  * but may be helpful for debugging purposes. */
777c478bd9Sstevel@tonic-gate 
787c478bd9Sstevel@tonic-gate /* Define this if you want to program the transmission control register
797c478bd9Sstevel@tonic-gate  * the way the Linux driver does it. */
807c478bd9Sstevel@tonic-gate #undef LINUX_DRIVER_TCTL
817c478bd9Sstevel@tonic-gate 
827c478bd9Sstevel@tonic-gate /* Define this to behave more like the Linux driver. */
837c478bd9Sstevel@tonic-gate #undef LINUX_DRIVER
847c478bd9Sstevel@tonic-gate 
857c478bd9Sstevel@tonic-gate #include "e1000_hw.h"
867c478bd9Sstevel@tonic-gate 
877c478bd9Sstevel@tonic-gate /* NIC specific static variables go here */
887c478bd9Sstevel@tonic-gate static struct e1000_hw hw;
897c478bd9Sstevel@tonic-gate static char tx_pool[128 + 16];
907c478bd9Sstevel@tonic-gate static char rx_pool[128 + 16];
917c478bd9Sstevel@tonic-gate static char packet[2096];
927c478bd9Sstevel@tonic-gate 
937c478bd9Sstevel@tonic-gate static struct e1000_tx_desc *tx_base;
947c478bd9Sstevel@tonic-gate static struct e1000_rx_desc *rx_base;
957c478bd9Sstevel@tonic-gate 
967c478bd9Sstevel@tonic-gate static int tx_tail;
977c478bd9Sstevel@tonic-gate static int rx_tail, rx_last;
987c478bd9Sstevel@tonic-gate 
997c478bd9Sstevel@tonic-gate /* Function forward declarations */
1007c478bd9Sstevel@tonic-gate static int e1000_setup_link(struct e1000_hw *hw);
1017c478bd9Sstevel@tonic-gate static int e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
1027c478bd9Sstevel@tonic-gate static int e1000_setup_copper_link(struct e1000_hw *hw);
1037c478bd9Sstevel@tonic-gate static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
1047c478bd9Sstevel@tonic-gate static void e1000_config_collision_dist(struct e1000_hw *hw);
1057c478bd9Sstevel@tonic-gate static int e1000_config_mac_to_phy(struct e1000_hw *hw);
1067c478bd9Sstevel@tonic-gate static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
1077c478bd9Sstevel@tonic-gate static int e1000_check_for_link(struct e1000_hw *hw);
1087c478bd9Sstevel@tonic-gate static int e1000_wait_autoneg(struct e1000_hw *hw);
1097c478bd9Sstevel@tonic-gate static void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, uint16_t *duplex);
1107c478bd9Sstevel@tonic-gate static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
1117c478bd9Sstevel@tonic-gate static int e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
1127c478bd9Sstevel@tonic-gate static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
1137c478bd9Sstevel@tonic-gate static int e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
1147c478bd9Sstevel@tonic-gate static void e1000_phy_hw_reset(struct e1000_hw *hw);
1157c478bd9Sstevel@tonic-gate static int e1000_phy_reset(struct e1000_hw *hw);
1167c478bd9Sstevel@tonic-gate static int e1000_detect_gig_phy(struct e1000_hw *hw);
1177c478bd9Sstevel@tonic-gate 
1187c478bd9Sstevel@tonic-gate /* Printing macros... */
1197c478bd9Sstevel@tonic-gate 
1207c478bd9Sstevel@tonic-gate #define E1000_ERR(args...) printf("e1000: " args)
1217c478bd9Sstevel@tonic-gate 
1227c478bd9Sstevel@tonic-gate #if DEBUG >= 3
1237c478bd9Sstevel@tonic-gate #define E1000_DBG(args...) printf("e1000: " args)
1247c478bd9Sstevel@tonic-gate #else
1257c478bd9Sstevel@tonic-gate #define E1000_DBG(args...)
1267c478bd9Sstevel@tonic-gate #endif
1277c478bd9Sstevel@tonic-gate 
1287c478bd9Sstevel@tonic-gate #define MSGOUT(S, A, B)     printk(S "\n", A, B)
1297c478bd9Sstevel@tonic-gate #if DEBUG >= 2
1307c478bd9Sstevel@tonic-gate #define DEBUGFUNC(F)        DEBUGOUT(F "\n");
1317c478bd9Sstevel@tonic-gate #else
1327c478bd9Sstevel@tonic-gate #define DEBUGFUNC(F)
1337c478bd9Sstevel@tonic-gate #endif
1347c478bd9Sstevel@tonic-gate #if DEBUG >= 1
1357c478bd9Sstevel@tonic-gate #define DEBUGOUT(S) printf(S)
1367c478bd9Sstevel@tonic-gate #define DEBUGOUT1(S,A) printf(S,A)
1377c478bd9Sstevel@tonic-gate #define DEBUGOUT2(S,A,B) printf(S,A,B)
1387c478bd9Sstevel@tonic-gate #define DEBUGOUT3(S,A,B,C) printf(S,A,B,C)
1397c478bd9Sstevel@tonic-gate #define DEBUGOUT7(S,A,B,C,D,E,F,G) printf(S,A,B,C,D,E,F,G)
1407c478bd9Sstevel@tonic-gate #else
1417c478bd9Sstevel@tonic-gate #define DEBUGOUT(S)
1427c478bd9Sstevel@tonic-gate #define DEBUGOUT1(S,A)
1437c478bd9Sstevel@tonic-gate #define DEBUGOUT2(S,A,B)
1447c478bd9Sstevel@tonic-gate #define DEBUGOUT3(S,A,B,C)
1457c478bd9Sstevel@tonic-gate #define DEBUGOUT7(S,A,B,C,D,E,F,G)
1467c478bd9Sstevel@tonic-gate #endif
1477c478bd9Sstevel@tonic-gate 
1487c478bd9Sstevel@tonic-gate #define E1000_WRITE_REG(a, reg, value) ( \
1497c478bd9Sstevel@tonic-gate     ((a)->mac_type >= e1000_82543) ? \
1507c478bd9Sstevel@tonic-gate         (writel((value), ((a)->hw_addr + E1000_##reg))) : \
1517c478bd9Sstevel@tonic-gate         (writel((value), ((a)->hw_addr + E1000_82542_##reg))))
1527c478bd9Sstevel@tonic-gate 
1537c478bd9Sstevel@tonic-gate #define E1000_READ_REG(a, reg) ( \
1547c478bd9Sstevel@tonic-gate     ((a)->mac_type >= e1000_82543) ? \
1557c478bd9Sstevel@tonic-gate         readl((a)->hw_addr + E1000_##reg) : \
1567c478bd9Sstevel@tonic-gate         readl((a)->hw_addr + E1000_82542_##reg))
1577c478bd9Sstevel@tonic-gate 
1587c478bd9Sstevel@tonic-gate #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
1597c478bd9Sstevel@tonic-gate     ((a)->mac_type >= e1000_82543) ? \
1607c478bd9Sstevel@tonic-gate         writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))) : \
1617c478bd9Sstevel@tonic-gate         writel((value), ((a)->hw_addr + E1000_82542_##reg + ((offset) << 2))))
1627c478bd9Sstevel@tonic-gate 
1637c478bd9Sstevel@tonic-gate #define E1000_READ_REG_ARRAY(a, reg, offset) ( \
1647c478bd9Sstevel@tonic-gate     ((a)->mac_type >= e1000_82543) ? \
1657c478bd9Sstevel@tonic-gate         readl((a)->hw_addr + E1000_##reg + ((offset) << 2)) : \
1667c478bd9Sstevel@tonic-gate         readl((a)->hw_addr + E1000_82542_##reg + ((offset) << 2)))
1677c478bd9Sstevel@tonic-gate 
1687c478bd9Sstevel@tonic-gate #define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);}
1697c478bd9Sstevel@tonic-gate 
1707c478bd9Sstevel@tonic-gate uint32_t
e1000_io_read(struct e1000_hw * hw __unused,uint32_t port)1717c478bd9Sstevel@tonic-gate e1000_io_read(struct e1000_hw *hw __unused, uint32_t port)
1727c478bd9Sstevel@tonic-gate {
1737c478bd9Sstevel@tonic-gate         return inl(port);
1747c478bd9Sstevel@tonic-gate }
1757c478bd9Sstevel@tonic-gate 
1767c478bd9Sstevel@tonic-gate void
e1000_io_write(struct e1000_hw * hw __unused,uint32_t port,uint32_t value)1777c478bd9Sstevel@tonic-gate e1000_io_write(struct e1000_hw *hw __unused, uint32_t port, uint32_t value)
1787c478bd9Sstevel@tonic-gate {
1797c478bd9Sstevel@tonic-gate         outl(value, port);
1807c478bd9Sstevel@tonic-gate }
1817c478bd9Sstevel@tonic-gate 
e1000_pci_set_mwi(struct e1000_hw * hw)1827c478bd9Sstevel@tonic-gate static inline void e1000_pci_set_mwi(struct e1000_hw *hw)
1837c478bd9Sstevel@tonic-gate {
1847c478bd9Sstevel@tonic-gate 	pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1857c478bd9Sstevel@tonic-gate }
1867c478bd9Sstevel@tonic-gate 
e1000_pci_clear_mwi(struct e1000_hw * hw)1877c478bd9Sstevel@tonic-gate static inline void e1000_pci_clear_mwi(struct e1000_hw *hw)
1887c478bd9Sstevel@tonic-gate {
1897c478bd9Sstevel@tonic-gate 	pci_write_config_word(hw->pdev, PCI_COMMAND,
1907c478bd9Sstevel@tonic-gate 			      hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1917c478bd9Sstevel@tonic-gate }
1927c478bd9Sstevel@tonic-gate 
1937c478bd9Sstevel@tonic-gate /******************************************************************************
1947c478bd9Sstevel@tonic-gate  * Raises the EEPROM's clock input.
1957c478bd9Sstevel@tonic-gate  *
1967c478bd9Sstevel@tonic-gate  * hw - Struct containing variables accessed by shared code
1977c478bd9Sstevel@tonic-gate  * eecd - EECD's current value
1987c478bd9Sstevel@tonic-gate  *****************************************************************************/
1997c478bd9Sstevel@tonic-gate static void
e1000_raise_ee_clk(struct e1000_hw * hw,uint32_t * eecd)2007c478bd9Sstevel@tonic-gate e1000_raise_ee_clk(struct e1000_hw *hw,
2017c478bd9Sstevel@tonic-gate                    uint32_t *eecd)
2027c478bd9Sstevel@tonic-gate {
2037c478bd9Sstevel@tonic-gate 	/* Raise the clock input to the EEPROM (by setting the SK bit), and then
2047c478bd9Sstevel@tonic-gate 	 * wait <delay> microseconds.
2057c478bd9Sstevel@tonic-gate 	 */
2067c478bd9Sstevel@tonic-gate 	*eecd = *eecd | E1000_EECD_SK;
2077c478bd9Sstevel@tonic-gate 	E1000_WRITE_REG(hw, EECD, *eecd);
2087c478bd9Sstevel@tonic-gate 	E1000_WRITE_FLUSH(hw);
2097c478bd9Sstevel@tonic-gate 	udelay(hw->eeprom.delay_usec);
2107c478bd9Sstevel@tonic-gate }
2117c478bd9Sstevel@tonic-gate 
2127c478bd9Sstevel@tonic-gate /******************************************************************************
2137c478bd9Sstevel@tonic-gate  * Lowers the EEPROM's clock input.
2147c478bd9Sstevel@tonic-gate  *
2157c478bd9Sstevel@tonic-gate  * hw - Struct containing variables accessed by shared code
2167c478bd9Sstevel@tonic-gate  * eecd - EECD's current value
2177c478bd9Sstevel@tonic-gate  *****************************************************************************/
2187c478bd9Sstevel@tonic-gate static void
e1000_lower_ee_clk(struct e1000_hw * hw,uint32_t * eecd)2197c478bd9Sstevel@tonic-gate e1000_lower_ee_clk(struct e1000_hw *hw,
2207c478bd9Sstevel@tonic-gate                    uint32_t *eecd)
2217c478bd9Sstevel@tonic-gate {
2227c478bd9Sstevel@tonic-gate 	/* Lower the clock input to the EEPROM (by clearing the SK bit), and then
2237c478bd9Sstevel@tonic-gate 	 * wait 50 microseconds.
2247c478bd9Sstevel@tonic-gate 	 */
2257c478bd9Sstevel@tonic-gate 	*eecd = *eecd & ~E1000_EECD_SK;
2267c478bd9Sstevel@tonic-gate 	E1000_WRITE_REG(hw, EECD, *eecd);
2277c478bd9Sstevel@tonic-gate 	E1000_WRITE_FLUSH(hw);
2287c478bd9Sstevel@tonic-gate 	udelay(hw->eeprom.delay_usec);
2297c478bd9Sstevel@tonic-gate }
2307c478bd9Sstevel@tonic-gate 
2317c478bd9Sstevel@tonic-gate /******************************************************************************
2327c478bd9Sstevel@tonic-gate  * Shift data bits out to the EEPROM.
2337c478bd9Sstevel@tonic-gate  *
2347c478bd9Sstevel@tonic-gate  * hw - Struct containing variables accessed by shared code
2357c478bd9Sstevel@tonic-gate  * data - data to send to the EEPROM
2367c478bd9Sstevel@tonic-gate  * count - number of bits to shift out
2377c478bd9Sstevel@tonic-gate  *****************************************************************************/
2387c478bd9Sstevel@tonic-gate static void
e1000_shift_out_ee_bits(struct e1000_hw * hw,uint16_t data,uint16_t count)2397c478bd9Sstevel@tonic-gate e1000_shift_out_ee_bits(struct e1000_hw *hw,
2407c478bd9Sstevel@tonic-gate                         uint16_t data,
2417c478bd9Sstevel@tonic-gate                         uint16_t count)
2427c478bd9Sstevel@tonic-gate {
2437c478bd9Sstevel@tonic-gate 	struct e1000_eeprom_info *eeprom = &hw->eeprom;
2447c478bd9Sstevel@tonic-gate 	uint32_t eecd;
2457c478bd9Sstevel@tonic-gate 	uint32_t mask;
2467c478bd9Sstevel@tonic-gate 
2477c478bd9Sstevel@tonic-gate 	/* We need to shift "count" bits out to the EEPROM. So, value in the
2487c478bd9Sstevel@tonic-gate 	 * "data" parameter will be shifted out to the EEPROM one bit at a time.
2497c478bd9Sstevel@tonic-gate 	 * In order to do this, "data" must be broken down into bits.
2507c478bd9Sstevel@tonic-gate 	 */
2517c478bd9Sstevel@tonic-gate 	mask = 0x01 << (count - 1);
2527c478bd9Sstevel@tonic-gate 	eecd = E1000_READ_REG(hw, EECD);
2537c478bd9Sstevel@tonic-gate 	if (eeprom->type == e1000_eeprom_microwire) {
2547c478bd9Sstevel@tonic-gate 		eecd &= ~E1000_EECD_DO;
2557c478bd9Sstevel@tonic-gate 	} else if (eeprom->type == e1000_eeprom_spi) {
2567c478bd9Sstevel@tonic-gate 		eecd |= E1000_EECD_DO;
2577c478bd9Sstevel@tonic-gate 	}
2587c478bd9Sstevel@tonic-gate 	do {
2597c478bd9Sstevel@tonic-gate 		/* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
2607c478bd9Sstevel@tonic-gate 		 * and then raising and then lowering the clock (the SK bit controls
2617c478bd9Sstevel@tonic-gate 		 * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
2627c478bd9Sstevel@tonic-gate 		 * by setting "DI" to "0" and then raising and then lowering the clock.
2637c478bd9Sstevel@tonic-gate 		 */
2647c478bd9Sstevel@tonic-gate 		eecd &= ~E1000_EECD_DI;
2657c478bd9Sstevel@tonic-gate 
2667c478bd9Sstevel@tonic-gate 		if(data & mask)
2677c478bd9Sstevel@tonic-gate 			eecd |= E1000_EECD_DI;
2687c478bd9Sstevel@tonic-gate 
2697c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, EECD, eecd);
2707c478bd9Sstevel@tonic-gate 		E1000_WRITE_FLUSH(hw);
2717c478bd9Sstevel@tonic-gate 
2727c478bd9Sstevel@tonic-gate 		udelay(eeprom->delay_usec);
2737c478bd9Sstevel@tonic-gate 
2747c478bd9Sstevel@tonic-gate 		e1000_raise_ee_clk(hw, &eecd);
2757c478bd9Sstevel@tonic-gate 		e1000_lower_ee_clk(hw, &eecd);
2767c478bd9Sstevel@tonic-gate 
2777c478bd9Sstevel@tonic-gate 		mask = mask >> 1;
2787c478bd9Sstevel@tonic-gate 
2797c478bd9Sstevel@tonic-gate 	} while(mask);
2807c478bd9Sstevel@tonic-gate 
2817c478bd9Sstevel@tonic-gate 	/* We leave the "DI" bit set to "0" when we leave this routine. */
2827c478bd9Sstevel@tonic-gate 	eecd &= ~E1000_EECD_DI;
2837c478bd9Sstevel@tonic-gate 	E1000_WRITE_REG(hw, EECD, eecd);
2847c478bd9Sstevel@tonic-gate }
2857c478bd9Sstevel@tonic-gate 
2867c478bd9Sstevel@tonic-gate /******************************************************************************
2877c478bd9Sstevel@tonic-gate  * Shift data bits in from the EEPROM
2887c478bd9Sstevel@tonic-gate  *
2897c478bd9Sstevel@tonic-gate  * hw - Struct containing variables accessed by shared code
2907c478bd9Sstevel@tonic-gate  *****************************************************************************/
2917c478bd9Sstevel@tonic-gate static uint16_t
e1000_shift_in_ee_bits(struct e1000_hw * hw,uint16_t count)2927c478bd9Sstevel@tonic-gate e1000_shift_in_ee_bits(struct e1000_hw *hw,
2937c478bd9Sstevel@tonic-gate                        uint16_t count)
2947c478bd9Sstevel@tonic-gate {
2957c478bd9Sstevel@tonic-gate 	uint32_t eecd;
2967c478bd9Sstevel@tonic-gate 	uint32_t i;
2977c478bd9Sstevel@tonic-gate 	uint16_t data;
2987c478bd9Sstevel@tonic-gate 
2997c478bd9Sstevel@tonic-gate 	/* In order to read a register from the EEPROM, we need to shift 'count'
3007c478bd9Sstevel@tonic-gate 	 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
3017c478bd9Sstevel@tonic-gate 	 * input to the EEPROM (setting the SK bit), and then reading the value of
3027c478bd9Sstevel@tonic-gate 	 * the "DO" bit.  During this "shifting in" process the "DI" bit should
3037c478bd9Sstevel@tonic-gate 	 * always be clear.
3047c478bd9Sstevel@tonic-gate 	 */
3057c478bd9Sstevel@tonic-gate 
3067c478bd9Sstevel@tonic-gate 	eecd = E1000_READ_REG(hw, EECD);
3077c478bd9Sstevel@tonic-gate 
3087c478bd9Sstevel@tonic-gate 	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
3097c478bd9Sstevel@tonic-gate 	data = 0;
3107c478bd9Sstevel@tonic-gate 
3117c478bd9Sstevel@tonic-gate 	for(i = 0; i < count; i++) {
3127c478bd9Sstevel@tonic-gate 		data = data << 1;
3137c478bd9Sstevel@tonic-gate 		e1000_raise_ee_clk(hw, &eecd);
3147c478bd9Sstevel@tonic-gate 
3157c478bd9Sstevel@tonic-gate 		eecd = E1000_READ_REG(hw, EECD);
3167c478bd9Sstevel@tonic-gate 
3177c478bd9Sstevel@tonic-gate 		eecd &= ~(E1000_EECD_DI);
3187c478bd9Sstevel@tonic-gate 		if(eecd & E1000_EECD_DO)
3197c478bd9Sstevel@tonic-gate 			data |= 1;
3207c478bd9Sstevel@tonic-gate 
3217c478bd9Sstevel@tonic-gate 		e1000_lower_ee_clk(hw, &eecd);
3227c478bd9Sstevel@tonic-gate 	}
3237c478bd9Sstevel@tonic-gate 
3247c478bd9Sstevel@tonic-gate 	return data;
3257c478bd9Sstevel@tonic-gate }
3267c478bd9Sstevel@tonic-gate 
3277c478bd9Sstevel@tonic-gate /******************************************************************************
3287c478bd9Sstevel@tonic-gate  * Prepares EEPROM for access
3297c478bd9Sstevel@tonic-gate  *
3307c478bd9Sstevel@tonic-gate  * hw - Struct containing variables accessed by shared code
3317c478bd9Sstevel@tonic-gate  *
3327c478bd9Sstevel@tonic-gate  * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3337c478bd9Sstevel@tonic-gate  * function should be called before issuing a command to the EEPROM.
3347c478bd9Sstevel@tonic-gate  *****************************************************************************/
3357c478bd9Sstevel@tonic-gate static int32_t
e1000_acquire_eeprom(struct e1000_hw * hw)3367c478bd9Sstevel@tonic-gate e1000_acquire_eeprom(struct e1000_hw *hw)
3377c478bd9Sstevel@tonic-gate {
3387c478bd9Sstevel@tonic-gate 	struct e1000_eeprom_info *eeprom = &hw->eeprom;
3397c478bd9Sstevel@tonic-gate 	uint32_t eecd, i=0;
3407c478bd9Sstevel@tonic-gate 
3417c478bd9Sstevel@tonic-gate 	eecd = E1000_READ_REG(hw, EECD);
3427c478bd9Sstevel@tonic-gate 
3437c478bd9Sstevel@tonic-gate 	/* Request EEPROM Access */
3447c478bd9Sstevel@tonic-gate 	if(hw->mac_type > e1000_82544) {
3457c478bd9Sstevel@tonic-gate 		eecd |= E1000_EECD_REQ;
3467c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, EECD, eecd);
3477c478bd9Sstevel@tonic-gate 		eecd = E1000_READ_REG(hw, EECD);
3487c478bd9Sstevel@tonic-gate 		while((!(eecd & E1000_EECD_GNT)) &&
3497c478bd9Sstevel@tonic-gate 		      (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3507c478bd9Sstevel@tonic-gate 			i++;
3517c478bd9Sstevel@tonic-gate 			udelay(5);
3527c478bd9Sstevel@tonic-gate 			eecd = E1000_READ_REG(hw, EECD);
3537c478bd9Sstevel@tonic-gate 		}
3547c478bd9Sstevel@tonic-gate 		if(!(eecd & E1000_EECD_GNT)) {
3557c478bd9Sstevel@tonic-gate 			eecd &= ~E1000_EECD_REQ;
3567c478bd9Sstevel@tonic-gate 			E1000_WRITE_REG(hw, EECD, eecd);
3577c478bd9Sstevel@tonic-gate 			DEBUGOUT("Could not acquire EEPROM grant\n");
3587c478bd9Sstevel@tonic-gate 			return -E1000_ERR_EEPROM;
3597c478bd9Sstevel@tonic-gate 		}
3607c478bd9Sstevel@tonic-gate 	}
3617c478bd9Sstevel@tonic-gate 
3627c478bd9Sstevel@tonic-gate 	/* Setup EEPROM for Read/Write */
3637c478bd9Sstevel@tonic-gate 
3647c478bd9Sstevel@tonic-gate 	if (eeprom->type == e1000_eeprom_microwire) {
3657c478bd9Sstevel@tonic-gate 		/* Clear SK and DI */
3667c478bd9Sstevel@tonic-gate 		eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
3677c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, EECD, eecd);
3687c478bd9Sstevel@tonic-gate 
3697c478bd9Sstevel@tonic-gate 		/* Set CS */
3707c478bd9Sstevel@tonic-gate 		eecd |= E1000_EECD_CS;
3717c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, EECD, eecd);
3727c478bd9Sstevel@tonic-gate 	} else if (eeprom->type == e1000_eeprom_spi) {
3737c478bd9Sstevel@tonic-gate 		/* Clear SK and CS */
3747c478bd9Sstevel@tonic-gate 		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3757c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, EECD, eecd);
3767c478bd9Sstevel@tonic-gate 		udelay(1);
3777c478bd9Sstevel@tonic-gate 	}
3787c478bd9Sstevel@tonic-gate 
3797c478bd9Sstevel@tonic-gate 	return E1000_SUCCESS;
3807c478bd9Sstevel@tonic-gate }
3817c478bd9Sstevel@tonic-gate 
3827c478bd9Sstevel@tonic-gate /******************************************************************************
3837c478bd9Sstevel@tonic-gate  * Returns EEPROM to a "standby" state
3847c478bd9Sstevel@tonic-gate  *
3857c478bd9Sstevel@tonic-gate  * hw - Struct containing variables accessed by shared code
3867c478bd9Sstevel@tonic-gate  *****************************************************************************/
3877c478bd9Sstevel@tonic-gate static void
e1000_standby_eeprom(struct e1000_hw * hw)3887c478bd9Sstevel@tonic-gate e1000_standby_eeprom(struct e1000_hw *hw)
3897c478bd9Sstevel@tonic-gate {
3907c478bd9Sstevel@tonic-gate 	struct e1000_eeprom_info *eeprom = &hw->eeprom;
3917c478bd9Sstevel@tonic-gate 	uint32_t eecd;
3927c478bd9Sstevel@tonic-gate 
3937c478bd9Sstevel@tonic-gate 	eecd = E1000_READ_REG(hw, EECD);
3947c478bd9Sstevel@tonic-gate 
3957c478bd9Sstevel@tonic-gate 	if(eeprom->type == e1000_eeprom_microwire) {
3967c478bd9Sstevel@tonic-gate 
3977c478bd9Sstevel@tonic-gate 		/* Deselect EEPROM */
3987c478bd9Sstevel@tonic-gate 		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3997c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, EECD, eecd);
4007c478bd9Sstevel@tonic-gate 		E1000_WRITE_FLUSH(hw);
4017c478bd9Sstevel@tonic-gate 		udelay(eeprom->delay_usec);
4027c478bd9Sstevel@tonic-gate 
4037c478bd9Sstevel@tonic-gate 		/* Clock high */
4047c478bd9Sstevel@tonic-gate 		eecd |= E1000_EECD_SK;
4057c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, EECD, eecd);
4067c478bd9Sstevel@tonic-gate 		E1000_WRITE_FLUSH(hw);
4077c478bd9Sstevel@tonic-gate 		udelay(eeprom->delay_usec);
4087c478bd9Sstevel@tonic-gate 
4097c478bd9Sstevel@tonic-gate 		/* Select EEPROM */
4107c478bd9Sstevel@tonic-gate 		eecd |= E1000_EECD_CS;
4117c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, EECD, eecd);
4127c478bd9Sstevel@tonic-gate 		E1000_WRITE_FLUSH(hw);
4137c478bd9Sstevel@tonic-gate 		udelay(eeprom->delay_usec);
4147c478bd9Sstevel@tonic-gate 
4157c478bd9Sstevel@tonic-gate 		/* Clock low */
4167c478bd9Sstevel@tonic-gate 		eecd &= ~E1000_EECD_SK;
4177c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, EECD, eecd);
4187c478bd9Sstevel@tonic-gate 		E1000_WRITE_FLUSH(hw);
4197c478bd9Sstevel@tonic-gate 		udelay(eeprom->delay_usec);
4207c478bd9Sstevel@tonic-gate 	} else if(eeprom->type == e1000_eeprom_spi) {
4217c478bd9Sstevel@tonic-gate 		/* Toggle CS to flush commands */
4227c478bd9Sstevel@tonic-gate 		eecd |= E1000_EECD_CS;
4237c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, EECD, eecd);
4247c478bd9Sstevel@tonic-gate 		E1000_WRITE_FLUSH(hw);
4257c478bd9Sstevel@tonic-gate 		udelay(eeprom->delay_usec);
4267c478bd9Sstevel@tonic-gate 		eecd &= ~E1000_EECD_CS;
4277c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, EECD, eecd);
4287c478bd9Sstevel@tonic-gate 		E1000_WRITE_FLUSH(hw);
4297c478bd9Sstevel@tonic-gate 		udelay(eeprom->delay_usec);
4307c478bd9Sstevel@tonic-gate 	}
4317c478bd9Sstevel@tonic-gate }
4327c478bd9Sstevel@tonic-gate 
4337c478bd9Sstevel@tonic-gate /******************************************************************************
4347c478bd9Sstevel@tonic-gate  * Terminates a command by inverting the EEPROM's chip select pin
4357c478bd9Sstevel@tonic-gate  *
4367c478bd9Sstevel@tonic-gate  * hw - Struct containing variables accessed by shared code
4377c478bd9Sstevel@tonic-gate  *****************************************************************************/
4387c478bd9Sstevel@tonic-gate static void
e1000_release_eeprom(struct e1000_hw * hw)4397c478bd9Sstevel@tonic-gate e1000_release_eeprom(struct e1000_hw *hw)
4407c478bd9Sstevel@tonic-gate {
4417c478bd9Sstevel@tonic-gate 	uint32_t eecd;
4427c478bd9Sstevel@tonic-gate 
4437c478bd9Sstevel@tonic-gate 	eecd = E1000_READ_REG(hw, EECD);
4447c478bd9Sstevel@tonic-gate 
4457c478bd9Sstevel@tonic-gate 	if (hw->eeprom.type == e1000_eeprom_spi) {
4467c478bd9Sstevel@tonic-gate 		eecd |= E1000_EECD_CS;  /* Pull CS high */
4477c478bd9Sstevel@tonic-gate 		eecd &= ~E1000_EECD_SK; /* Lower SCK */
4487c478bd9Sstevel@tonic-gate 
4497c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, EECD, eecd);
4507c478bd9Sstevel@tonic-gate 
4517c478bd9Sstevel@tonic-gate 		udelay(hw->eeprom.delay_usec);
4527c478bd9Sstevel@tonic-gate 	} else if(hw->eeprom.type == e1000_eeprom_microwire) {
4537c478bd9Sstevel@tonic-gate 		/* cleanup eeprom */
4547c478bd9Sstevel@tonic-gate 
4557c478bd9Sstevel@tonic-gate 		/* CS on Microwire is active-high */
4567c478bd9Sstevel@tonic-gate 		eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
4577c478bd9Sstevel@tonic-gate 
4587c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, EECD, eecd);
4597c478bd9Sstevel@tonic-gate 
4607c478bd9Sstevel@tonic-gate 		/* Rising edge of clock */
4617c478bd9Sstevel@tonic-gate 		eecd |= E1000_EECD_SK;
4627c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, EECD, eecd);
4637c478bd9Sstevel@tonic-gate 		E1000_WRITE_FLUSH(hw);
4647c478bd9Sstevel@tonic-gate 		udelay(hw->eeprom.delay_usec);
4657c478bd9Sstevel@tonic-gate 
4667c478bd9Sstevel@tonic-gate 		/* Falling edge of clock */
4677c478bd9Sstevel@tonic-gate 		eecd &= ~E1000_EECD_SK;
4687c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, EECD, eecd);
4697c478bd9Sstevel@tonic-gate 		E1000_WRITE_FLUSH(hw);
4707c478bd9Sstevel@tonic-gate 		udelay(hw->eeprom.delay_usec);
4717c478bd9Sstevel@tonic-gate 	}
4727c478bd9Sstevel@tonic-gate 
4737c478bd9Sstevel@tonic-gate 	/* Stop requesting EEPROM access */
4747c478bd9Sstevel@tonic-gate 	if(hw->mac_type > e1000_82544) {
4757c478bd9Sstevel@tonic-gate 		eecd &= ~E1000_EECD_REQ;
4767c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, EECD, eecd);
4777c478bd9Sstevel@tonic-gate 	}
4787c478bd9Sstevel@tonic-gate }
4797c478bd9Sstevel@tonic-gate 
4807c478bd9Sstevel@tonic-gate /******************************************************************************
4817c478bd9Sstevel@tonic-gate  * Reads a 16 bit word from the EEPROM.
4827c478bd9Sstevel@tonic-gate  *
4837c478bd9Sstevel@tonic-gate  * hw - Struct containing variables accessed by shared code
4847c478bd9Sstevel@tonic-gate  *****************************************************************************/
4857c478bd9Sstevel@tonic-gate static int32_t
e1000_spi_eeprom_ready(struct e1000_hw * hw)4867c478bd9Sstevel@tonic-gate e1000_spi_eeprom_ready(struct e1000_hw *hw)
4877c478bd9Sstevel@tonic-gate {
4887c478bd9Sstevel@tonic-gate 	uint16_t retry_count = 0;
4897c478bd9Sstevel@tonic-gate 	uint8_t spi_stat_reg;
4907c478bd9Sstevel@tonic-gate 
4917c478bd9Sstevel@tonic-gate 	/* Read "Status Register" repeatedly until the LSB is cleared.  The
4927c478bd9Sstevel@tonic-gate 	 * EEPROM will signal that the command has been completed by clearing
4937c478bd9Sstevel@tonic-gate 	 * bit 0 of the internal status register.  If it's not cleared within
4947c478bd9Sstevel@tonic-gate 	 * 5 milliseconds, then error out.
4957c478bd9Sstevel@tonic-gate 	 */
4967c478bd9Sstevel@tonic-gate 	retry_count = 0;
4977c478bd9Sstevel@tonic-gate 	do {
4987c478bd9Sstevel@tonic-gate 		e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
4997c478bd9Sstevel@tonic-gate 		hw->eeprom.opcode_bits);
5007c478bd9Sstevel@tonic-gate 		spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
5017c478bd9Sstevel@tonic-gate 		if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
5027c478bd9Sstevel@tonic-gate 			break;
5037c478bd9Sstevel@tonic-gate 
5047c478bd9Sstevel@tonic-gate 		udelay(5);
5057c478bd9Sstevel@tonic-gate 		retry_count += 5;
5067c478bd9Sstevel@tonic-gate 
5077c478bd9Sstevel@tonic-gate 	} while(retry_count < EEPROM_MAX_RETRY_SPI);
5087c478bd9Sstevel@tonic-gate 
5097c478bd9Sstevel@tonic-gate 	/* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
5107c478bd9Sstevel@tonic-gate 	 * only 0-5mSec on 5V devices)
5117c478bd9Sstevel@tonic-gate 	 */
5127c478bd9Sstevel@tonic-gate 	if(retry_count >= EEPROM_MAX_RETRY_SPI) {
5137c478bd9Sstevel@tonic-gate 		DEBUGOUT("SPI EEPROM Status error\n");
5147c478bd9Sstevel@tonic-gate 		return -E1000_ERR_EEPROM;
5157c478bd9Sstevel@tonic-gate 	}
5167c478bd9Sstevel@tonic-gate 
5177c478bd9Sstevel@tonic-gate 	return E1000_SUCCESS;
5187c478bd9Sstevel@tonic-gate }
5197c478bd9Sstevel@tonic-gate 
5207c478bd9Sstevel@tonic-gate /******************************************************************************
5217c478bd9Sstevel@tonic-gate  * Reads a 16 bit word from the EEPROM.
5227c478bd9Sstevel@tonic-gate  *
5237c478bd9Sstevel@tonic-gate  * hw - Struct containing variables accessed by shared code
5247c478bd9Sstevel@tonic-gate  * offset - offset of  word in the EEPROM to read
5257c478bd9Sstevel@tonic-gate  * data - word read from the EEPROM
5267c478bd9Sstevel@tonic-gate  * words - number of words to read
5277c478bd9Sstevel@tonic-gate  *****************************************************************************/
5287c478bd9Sstevel@tonic-gate static int
e1000_read_eeprom(struct e1000_hw * hw,uint16_t offset,uint16_t words,uint16_t * data)5297c478bd9Sstevel@tonic-gate e1000_read_eeprom(struct e1000_hw *hw,
5307c478bd9Sstevel@tonic-gate                   uint16_t offset,
5317c478bd9Sstevel@tonic-gate 		  uint16_t words,
5327c478bd9Sstevel@tonic-gate                   uint16_t *data)
5337c478bd9Sstevel@tonic-gate {
5347c478bd9Sstevel@tonic-gate 	struct e1000_eeprom_info *eeprom = &hw->eeprom;
5357c478bd9Sstevel@tonic-gate 	uint32_t i = 0;
5367c478bd9Sstevel@tonic-gate 
5377c478bd9Sstevel@tonic-gate 	DEBUGFUNC("e1000_read_eeprom");
5387c478bd9Sstevel@tonic-gate 
5397c478bd9Sstevel@tonic-gate 	/* A check for invalid values:  offset too large, too many words, and not
5407c478bd9Sstevel@tonic-gate 	 * enough words.
5417c478bd9Sstevel@tonic-gate 	 */
5427c478bd9Sstevel@tonic-gate 	if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
5437c478bd9Sstevel@tonic-gate 	   (words == 0)) {
5447c478bd9Sstevel@tonic-gate 		DEBUGOUT("\"words\" parameter out of bounds\n");
5457c478bd9Sstevel@tonic-gate 		return -E1000_ERR_EEPROM;
5467c478bd9Sstevel@tonic-gate 	}
5477c478bd9Sstevel@tonic-gate 
5487c478bd9Sstevel@tonic-gate 	/*  Prepare the EEPROM for reading  */
5497c478bd9Sstevel@tonic-gate 	if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5507c478bd9Sstevel@tonic-gate 		return -E1000_ERR_EEPROM;
5517c478bd9Sstevel@tonic-gate 
5527c478bd9Sstevel@tonic-gate 	if(eeprom->type == e1000_eeprom_spi) {
5537c478bd9Sstevel@tonic-gate 		uint16_t word_in;
5547c478bd9Sstevel@tonic-gate 		uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
5557c478bd9Sstevel@tonic-gate 
5567c478bd9Sstevel@tonic-gate 		if(e1000_spi_eeprom_ready(hw)) {
5577c478bd9Sstevel@tonic-gate 			e1000_release_eeprom(hw);
5587c478bd9Sstevel@tonic-gate 			return -E1000_ERR_EEPROM;
5597c478bd9Sstevel@tonic-gate 		}
5607c478bd9Sstevel@tonic-gate 
5617c478bd9Sstevel@tonic-gate 		e1000_standby_eeprom(hw);
5627c478bd9Sstevel@tonic-gate 
5637c478bd9Sstevel@tonic-gate 		/* Some SPI eeproms use the 8th address bit embedded in the opcode */
5647c478bd9Sstevel@tonic-gate 		if((eeprom->address_bits == 8) && (offset >= 128))
5657c478bd9Sstevel@tonic-gate 			read_opcode |= EEPROM_A8_OPCODE_SPI;
5667c478bd9Sstevel@tonic-gate 
5677c478bd9Sstevel@tonic-gate 		/* Send the READ command (opcode + addr)  */
5687c478bd9Sstevel@tonic-gate 		e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
5697c478bd9Sstevel@tonic-gate 		e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
5707c478bd9Sstevel@tonic-gate 
5717c478bd9Sstevel@tonic-gate 		/* Read the data.  The address of the eeprom internally increments with
5727c478bd9Sstevel@tonic-gate 		 * each byte (spi) being read, saving on the overhead of eeprom setup
5737c478bd9Sstevel@tonic-gate 		 * and tear-down.  The address counter will roll over if reading beyond
5747c478bd9Sstevel@tonic-gate 		 * the size of the eeprom, thus allowing the entire memory to be read
5757c478bd9Sstevel@tonic-gate 		 * starting from any offset. */
5767c478bd9Sstevel@tonic-gate 		for (i = 0; i < words; i++) {
5777c478bd9Sstevel@tonic-gate 			word_in = e1000_shift_in_ee_bits(hw, 16);
5787c478bd9Sstevel@tonic-gate 			data[i] = (word_in >> 8) | (word_in << 8);
5797c478bd9Sstevel@tonic-gate 		}
5807c478bd9Sstevel@tonic-gate 	} else if(eeprom->type == e1000_eeprom_microwire) {
5817c478bd9Sstevel@tonic-gate 		for (i = 0; i < words; i++) {
5827c478bd9Sstevel@tonic-gate 			/*  Send the READ command (opcode + addr)  */
5837c478bd9Sstevel@tonic-gate 			e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
5847c478bd9Sstevel@tonic-gate 						eeprom->opcode_bits);
5857c478bd9Sstevel@tonic-gate 			e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
5867c478bd9Sstevel@tonic-gate 			                        eeprom->address_bits);
5877c478bd9Sstevel@tonic-gate 
5887c478bd9Sstevel@tonic-gate 			/* Read the data.  For microwire, each word requires the overhead
5897c478bd9Sstevel@tonic-gate 			 * of eeprom setup and tear-down. */
5907c478bd9Sstevel@tonic-gate 			data[i] = e1000_shift_in_ee_bits(hw, 16);
5917c478bd9Sstevel@tonic-gate 			e1000_standby_eeprom(hw);
5927c478bd9Sstevel@tonic-gate 		}
5937c478bd9Sstevel@tonic-gate 	}
5947c478bd9Sstevel@tonic-gate 
5957c478bd9Sstevel@tonic-gate 	/* End this read operation */
5967c478bd9Sstevel@tonic-gate 	e1000_release_eeprom(hw);
5977c478bd9Sstevel@tonic-gate 
5987c478bd9Sstevel@tonic-gate 	return E1000_SUCCESS;
5997c478bd9Sstevel@tonic-gate }
6007c478bd9Sstevel@tonic-gate 
6017c478bd9Sstevel@tonic-gate /******************************************************************************
6027c478bd9Sstevel@tonic-gate  * Verifies that the EEPROM has a valid checksum
6037c478bd9Sstevel@tonic-gate  *
6047c478bd9Sstevel@tonic-gate  * hw - Struct containing variables accessed by shared code
6057c478bd9Sstevel@tonic-gate  *
6067c478bd9Sstevel@tonic-gate  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
6077c478bd9Sstevel@tonic-gate  * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
6087c478bd9Sstevel@tonic-gate  * valid.
6097c478bd9Sstevel@tonic-gate  *****************************************************************************/
6107c478bd9Sstevel@tonic-gate static int
e1000_validate_eeprom_checksum(struct e1000_hw * hw)6117c478bd9Sstevel@tonic-gate e1000_validate_eeprom_checksum(struct e1000_hw *hw)
6127c478bd9Sstevel@tonic-gate {
6137c478bd9Sstevel@tonic-gate 	uint16_t checksum = 0;
6147c478bd9Sstevel@tonic-gate 	uint16_t i, eeprom_data;
6157c478bd9Sstevel@tonic-gate 
6167c478bd9Sstevel@tonic-gate 	DEBUGFUNC("e1000_validate_eeprom_checksum");
6177c478bd9Sstevel@tonic-gate 
6187c478bd9Sstevel@tonic-gate 	for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
6197c478bd9Sstevel@tonic-gate 		if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
6207c478bd9Sstevel@tonic-gate 			DEBUGOUT("EEPROM Read Error\n");
6217c478bd9Sstevel@tonic-gate 			return -E1000_ERR_EEPROM;
6227c478bd9Sstevel@tonic-gate 		}
6237c478bd9Sstevel@tonic-gate 		checksum += eeprom_data;
6247c478bd9Sstevel@tonic-gate 	}
6257c478bd9Sstevel@tonic-gate 
6267c478bd9Sstevel@tonic-gate 	if(checksum == (uint16_t) EEPROM_SUM)
6277c478bd9Sstevel@tonic-gate 		return E1000_SUCCESS;
6287c478bd9Sstevel@tonic-gate 	else {
6297c478bd9Sstevel@tonic-gate 		DEBUGOUT("EEPROM Checksum Invalid\n");
6307c478bd9Sstevel@tonic-gate 		return -E1000_ERR_EEPROM;
6317c478bd9Sstevel@tonic-gate 	}
6327c478bd9Sstevel@tonic-gate }
6337c478bd9Sstevel@tonic-gate 
6347c478bd9Sstevel@tonic-gate /******************************************************************************
6357c478bd9Sstevel@tonic-gate  * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
6367c478bd9Sstevel@tonic-gate  * second function of dual function devices
6377c478bd9Sstevel@tonic-gate  *
6387c478bd9Sstevel@tonic-gate  * hw - Struct containing variables accessed by shared code
6397c478bd9Sstevel@tonic-gate  *****************************************************************************/
6407c478bd9Sstevel@tonic-gate static int
e1000_read_mac_addr(struct e1000_hw * hw)6417c478bd9Sstevel@tonic-gate e1000_read_mac_addr(struct e1000_hw *hw)
6427c478bd9Sstevel@tonic-gate {
6437c478bd9Sstevel@tonic-gate 	uint16_t offset;
6447c478bd9Sstevel@tonic-gate 	uint16_t eeprom_data;
6457c478bd9Sstevel@tonic-gate 	int i;
6467c478bd9Sstevel@tonic-gate 
6477c478bd9Sstevel@tonic-gate 	DEBUGFUNC("e1000_read_mac_addr");
6487c478bd9Sstevel@tonic-gate 
6497c478bd9Sstevel@tonic-gate 	for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
6507c478bd9Sstevel@tonic-gate 		offset = i >> 1;
6517c478bd9Sstevel@tonic-gate 		if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
6527c478bd9Sstevel@tonic-gate 			DEBUGOUT("EEPROM Read Error\n");
6537c478bd9Sstevel@tonic-gate 			return -E1000_ERR_EEPROM;
6547c478bd9Sstevel@tonic-gate 		}
6557c478bd9Sstevel@tonic-gate 		hw->mac_addr[i] = eeprom_data & 0xff;
6567c478bd9Sstevel@tonic-gate 		hw->mac_addr[i+1] = (eeprom_data >> 8) & 0xff;
6577c478bd9Sstevel@tonic-gate 	}
6587c478bd9Sstevel@tonic-gate 	if(((hw->mac_type == e1000_82546) || (hw->mac_type == e1000_82546_rev_3)) &&
6597c478bd9Sstevel@tonic-gate 		(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1))
6607c478bd9Sstevel@tonic-gate 		/* Invert the last bit if this is the second device */
6617c478bd9Sstevel@tonic-gate 		hw->mac_addr[5] ^= 1;
6627c478bd9Sstevel@tonic-gate 	return E1000_SUCCESS;
6637c478bd9Sstevel@tonic-gate }
6647c478bd9Sstevel@tonic-gate 
6657c478bd9Sstevel@tonic-gate /******************************************************************************
6667c478bd9Sstevel@tonic-gate  * Initializes receive address filters.
6677c478bd9Sstevel@tonic-gate  *
6687c478bd9Sstevel@tonic-gate  * hw - Struct containing variables accessed by shared code
6697c478bd9Sstevel@tonic-gate  *
6707c478bd9Sstevel@tonic-gate  * Places the MAC address in receive address register 0 and clears the rest
6717c478bd9Sstevel@tonic-gate  * of the receive addresss registers. Clears the multicast table. Assumes
6727c478bd9Sstevel@tonic-gate  * the receiver is in reset when the routine is called.
6737c478bd9Sstevel@tonic-gate  *****************************************************************************/
6747c478bd9Sstevel@tonic-gate static void
e1000_init_rx_addrs(struct e1000_hw * hw)6757c478bd9Sstevel@tonic-gate e1000_init_rx_addrs(struct e1000_hw *hw)
6767c478bd9Sstevel@tonic-gate {
6777c478bd9Sstevel@tonic-gate 	uint32_t i;
6787c478bd9Sstevel@tonic-gate 	uint32_t addr_low;
6797c478bd9Sstevel@tonic-gate 	uint32_t addr_high;
6807c478bd9Sstevel@tonic-gate 
6817c478bd9Sstevel@tonic-gate 	DEBUGFUNC("e1000_init_rx_addrs");
6827c478bd9Sstevel@tonic-gate 
6837c478bd9Sstevel@tonic-gate 	/* Setup the receive address. */
6847c478bd9Sstevel@tonic-gate 	DEBUGOUT("Programming MAC Address into RAR[0]\n");
6857c478bd9Sstevel@tonic-gate 	addr_low = (hw->mac_addr[0] |
6867c478bd9Sstevel@tonic-gate 		(hw->mac_addr[1] << 8) |
6877c478bd9Sstevel@tonic-gate 		(hw->mac_addr[2] << 16) | (hw->mac_addr[3] << 24));
6887c478bd9Sstevel@tonic-gate 
6897c478bd9Sstevel@tonic-gate 	addr_high = (hw->mac_addr[4] |
6907c478bd9Sstevel@tonic-gate 		(hw->mac_addr[5] << 8) | E1000_RAH_AV);
6917c478bd9Sstevel@tonic-gate 
6927c478bd9Sstevel@tonic-gate 	E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
6937c478bd9Sstevel@tonic-gate 	E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
6947c478bd9Sstevel@tonic-gate 
6957c478bd9Sstevel@tonic-gate 	/* Zero out the other 15 receive addresses. */
6967c478bd9Sstevel@tonic-gate 	DEBUGOUT("Clearing RAR[1-15]\n");
6977c478bd9Sstevel@tonic-gate 	for(i = 1; i < E1000_RAR_ENTRIES; i++) {
6987c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
6997c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
7007c478bd9Sstevel@tonic-gate 	}
7017c478bd9Sstevel@tonic-gate }
7027c478bd9Sstevel@tonic-gate 
7037c478bd9Sstevel@tonic-gate /******************************************************************************
7047c478bd9Sstevel@tonic-gate  * Clears the VLAN filer table
7057c478bd9Sstevel@tonic-gate  *
7067c478bd9Sstevel@tonic-gate  * hw - Struct containing variables accessed by shared code
7077c478bd9Sstevel@tonic-gate  *****************************************************************************/
7087c478bd9Sstevel@tonic-gate static void
e1000_clear_vfta(struct e1000_hw * hw)7097c478bd9Sstevel@tonic-gate e1000_clear_vfta(struct e1000_hw *hw)
7107c478bd9Sstevel@tonic-gate {
7117c478bd9Sstevel@tonic-gate 	uint32_t offset;
7127c478bd9Sstevel@tonic-gate 
7137c478bd9Sstevel@tonic-gate 	for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
7147c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
7157c478bd9Sstevel@tonic-gate }
7167c478bd9Sstevel@tonic-gate 
7177c478bd9Sstevel@tonic-gate /******************************************************************************
7187c478bd9Sstevel@tonic-gate * Writes a value to one of the devices registers using port I/O (as opposed to
7197c478bd9Sstevel@tonic-gate * memory mapped I/O). Only 82544 and newer devices support port I/O. *
7207c478bd9Sstevel@tonic-gate * hw - Struct containing variables accessed by shared code
7217c478bd9Sstevel@tonic-gate * offset - offset to write to * value - value to write
7227c478bd9Sstevel@tonic-gate *****************************************************************************/
e1000_write_reg_io(struct e1000_hw * hw,uint32_t offset,uint32_t value)7237c478bd9Sstevel@tonic-gate void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value){
7247c478bd9Sstevel@tonic-gate 	uint32_t io_addr = hw->io_base;
7257c478bd9Sstevel@tonic-gate 	uint32_t io_data = hw->io_base + 4;
7267c478bd9Sstevel@tonic-gate 	e1000_io_write(hw, io_addr, offset);
7277c478bd9Sstevel@tonic-gate 	e1000_io_write(hw, io_data, value);
7287c478bd9Sstevel@tonic-gate }
7297c478bd9Sstevel@tonic-gate 
7307c478bd9Sstevel@tonic-gate /******************************************************************************
7317c478bd9Sstevel@tonic-gate  * Set the phy type member in the hw struct.
7327c478bd9Sstevel@tonic-gate  *
7337c478bd9Sstevel@tonic-gate  * hw - Struct containing variables accessed by shared code
7347c478bd9Sstevel@tonic-gate  *****************************************************************************/
7357c478bd9Sstevel@tonic-gate static int32_t
e1000_set_phy_type(struct e1000_hw * hw)7367c478bd9Sstevel@tonic-gate e1000_set_phy_type(struct e1000_hw *hw)
7377c478bd9Sstevel@tonic-gate {
7387c478bd9Sstevel@tonic-gate 	DEBUGFUNC("e1000_set_phy_type");
7397c478bd9Sstevel@tonic-gate 
7407c478bd9Sstevel@tonic-gate 	switch(hw->phy_id) {
7417c478bd9Sstevel@tonic-gate 	case M88E1000_E_PHY_ID:
7427c478bd9Sstevel@tonic-gate 	case M88E1000_I_PHY_ID:
7437c478bd9Sstevel@tonic-gate 	case M88E1011_I_PHY_ID:
7447c478bd9Sstevel@tonic-gate 		hw->phy_type = e1000_phy_m88;
7457c478bd9Sstevel@tonic-gate 		break;
7467c478bd9Sstevel@tonic-gate 	case IGP01E1000_I_PHY_ID:
7477c478bd9Sstevel@tonic-gate 		hw->phy_type = e1000_phy_igp;
7487c478bd9Sstevel@tonic-gate 		break;
7497c478bd9Sstevel@tonic-gate 	default:
7507c478bd9Sstevel@tonic-gate 		/* Should never have loaded on this device */
7517c478bd9Sstevel@tonic-gate 		hw->phy_type = e1000_phy_undefined;
7527c478bd9Sstevel@tonic-gate 		return -E1000_ERR_PHY_TYPE;
7537c478bd9Sstevel@tonic-gate 	}
7547c478bd9Sstevel@tonic-gate 
7557c478bd9Sstevel@tonic-gate 	return E1000_SUCCESS;
7567c478bd9Sstevel@tonic-gate }
7577c478bd9Sstevel@tonic-gate 
7587c478bd9Sstevel@tonic-gate /******************************************************************************
7597c478bd9Sstevel@tonic-gate  * IGP phy init script - initializes the GbE PHY
7607c478bd9Sstevel@tonic-gate  *
7617c478bd9Sstevel@tonic-gate  * hw - Struct containing variables accessed by shared code
7627c478bd9Sstevel@tonic-gate  *****************************************************************************/
7637c478bd9Sstevel@tonic-gate static void
e1000_phy_init_script(struct e1000_hw * hw)7647c478bd9Sstevel@tonic-gate e1000_phy_init_script(struct e1000_hw *hw)
7657c478bd9Sstevel@tonic-gate {
7667c478bd9Sstevel@tonic-gate 	DEBUGFUNC("e1000_phy_init_script");
7677c478bd9Sstevel@tonic-gate 
7687c478bd9Sstevel@tonic-gate #if 0
7697c478bd9Sstevel@tonic-gate 	/* See e1000_sw_init() of the Linux driver */
7707c478bd9Sstevel@tonic-gate 	if(hw->phy_init_script) {
7717c478bd9Sstevel@tonic-gate #else
7727c478bd9Sstevel@tonic-gate 	if((hw->mac_type == e1000_82541) ||
7737c478bd9Sstevel@tonic-gate 	   (hw->mac_type == e1000_82547) ||
7747c478bd9Sstevel@tonic-gate 	   (hw->mac_type == e1000_82541_rev_2) ||
7757c478bd9Sstevel@tonic-gate 	   (hw->mac_type == e1000_82547_rev_2)) {
7767c478bd9Sstevel@tonic-gate #endif
7777c478bd9Sstevel@tonic-gate 		mdelay(20);
7787c478bd9Sstevel@tonic-gate 
7797c478bd9Sstevel@tonic-gate 		e1000_write_phy_reg(hw,0x0000,0x0140);
7807c478bd9Sstevel@tonic-gate 
7817c478bd9Sstevel@tonic-gate 		mdelay(5);
7827c478bd9Sstevel@tonic-gate 
7837c478bd9Sstevel@tonic-gate 		if(hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547) {
7847c478bd9Sstevel@tonic-gate 			e1000_write_phy_reg(hw, 0x1F95, 0x0001);
7857c478bd9Sstevel@tonic-gate 
7867c478bd9Sstevel@tonic-gate 			e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
7877c478bd9Sstevel@tonic-gate 
7887c478bd9Sstevel@tonic-gate 			e1000_write_phy_reg(hw, 0x1F79, 0x0018);
7897c478bd9Sstevel@tonic-gate 
7907c478bd9Sstevel@tonic-gate 			e1000_write_phy_reg(hw, 0x1F30, 0x1600);
7917c478bd9Sstevel@tonic-gate 
7927c478bd9Sstevel@tonic-gate 			e1000_write_phy_reg(hw, 0x1F31, 0x0014);
7937c478bd9Sstevel@tonic-gate 
7947c478bd9Sstevel@tonic-gate 			e1000_write_phy_reg(hw, 0x1F32, 0x161C);
7957c478bd9Sstevel@tonic-gate 
7967c478bd9Sstevel@tonic-gate 			e1000_write_phy_reg(hw, 0x1F94, 0x0003);
7977c478bd9Sstevel@tonic-gate 
7987c478bd9Sstevel@tonic-gate 			e1000_write_phy_reg(hw, 0x1F96, 0x003F);
7997c478bd9Sstevel@tonic-gate 
8007c478bd9Sstevel@tonic-gate 			e1000_write_phy_reg(hw, 0x2010, 0x0008);
8017c478bd9Sstevel@tonic-gate 		} else {
8027c478bd9Sstevel@tonic-gate 			e1000_write_phy_reg(hw, 0x1F73, 0x0099);
8037c478bd9Sstevel@tonic-gate 		}
8047c478bd9Sstevel@tonic-gate 
8057c478bd9Sstevel@tonic-gate 		e1000_write_phy_reg(hw, 0x0000, 0x3300);
8067c478bd9Sstevel@tonic-gate 
8077c478bd9Sstevel@tonic-gate 
8087c478bd9Sstevel@tonic-gate 		if(hw->mac_type == e1000_82547) {
8097c478bd9Sstevel@tonic-gate 			uint16_t fused, fine, coarse;
8107c478bd9Sstevel@tonic-gate 
8117c478bd9Sstevel@tonic-gate 			/* Move to analog registers page */
8127c478bd9Sstevel@tonic-gate 			e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
8137c478bd9Sstevel@tonic-gate 
8147c478bd9Sstevel@tonic-gate 			if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
8157c478bd9Sstevel@tonic-gate 				e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
8167c478bd9Sstevel@tonic-gate 
8177c478bd9Sstevel@tonic-gate 				fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
8187c478bd9Sstevel@tonic-gate 				coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
8197c478bd9Sstevel@tonic-gate 
8207c478bd9Sstevel@tonic-gate 				if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
8217c478bd9Sstevel@tonic-gate 					coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
8227c478bd9Sstevel@tonic-gate 					fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
8237c478bd9Sstevel@tonic-gate 				} else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
8247c478bd9Sstevel@tonic-gate 					fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
8257c478bd9Sstevel@tonic-gate 
8267c478bd9Sstevel@tonic-gate 				fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
8277c478bd9Sstevel@tonic-gate 					(fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
8287c478bd9Sstevel@tonic-gate 					(coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
8297c478bd9Sstevel@tonic-gate 
8307c478bd9Sstevel@tonic-gate 				e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
8317c478bd9Sstevel@tonic-gate 				e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
8327c478bd9Sstevel@tonic-gate 						IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
8337c478bd9Sstevel@tonic-gate 			}
8347c478bd9Sstevel@tonic-gate 		}
8357c478bd9Sstevel@tonic-gate 	}
8367c478bd9Sstevel@tonic-gate }
8377c478bd9Sstevel@tonic-gate 
8387c478bd9Sstevel@tonic-gate /******************************************************************************
8397c478bd9Sstevel@tonic-gate  * Set the mac type member in the hw struct.
8407c478bd9Sstevel@tonic-gate  *
8417c478bd9Sstevel@tonic-gate  * hw - Struct containing variables accessed by shared code
8427c478bd9Sstevel@tonic-gate  *****************************************************************************/
8437c478bd9Sstevel@tonic-gate static int
8447c478bd9Sstevel@tonic-gate e1000_set_mac_type(struct e1000_hw *hw)
8457c478bd9Sstevel@tonic-gate {
8467c478bd9Sstevel@tonic-gate 	DEBUGFUNC("e1000_set_mac_type");
8477c478bd9Sstevel@tonic-gate 
8487c478bd9Sstevel@tonic-gate 	switch (hw->device_id) {
8497c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82542:
8507c478bd9Sstevel@tonic-gate 		switch (hw->revision_id) {
8517c478bd9Sstevel@tonic-gate 		case E1000_82542_2_0_REV_ID:
8527c478bd9Sstevel@tonic-gate 			hw->mac_type = e1000_82542_rev2_0;
8537c478bd9Sstevel@tonic-gate 			break;
8547c478bd9Sstevel@tonic-gate 		case E1000_82542_2_1_REV_ID:
8557c478bd9Sstevel@tonic-gate 			hw->mac_type = e1000_82542_rev2_1;
8567c478bd9Sstevel@tonic-gate 			break;
8577c478bd9Sstevel@tonic-gate 		default:
8587c478bd9Sstevel@tonic-gate 			/* Invalid 82542 revision ID */
8597c478bd9Sstevel@tonic-gate 			return -E1000_ERR_MAC_TYPE;
8607c478bd9Sstevel@tonic-gate 		}
8617c478bd9Sstevel@tonic-gate 		break;
8627c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82543GC_FIBER:
8637c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82543GC_COPPER:
8647c478bd9Sstevel@tonic-gate 		hw->mac_type = e1000_82543;
8657c478bd9Sstevel@tonic-gate 		break;
8667c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82544EI_COPPER:
8677c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82544EI_FIBER:
8687c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82544GC_COPPER:
8697c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82544GC_LOM:
8707c478bd9Sstevel@tonic-gate 		hw->mac_type = e1000_82544;
8717c478bd9Sstevel@tonic-gate 		break;
8727c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82540EM:
8737c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82540EM_LOM:
8747c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82540EP:
8757c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82540EP_LOM:
8767c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82540EP_LP:
8777c478bd9Sstevel@tonic-gate 		hw->mac_type = e1000_82540;
8787c478bd9Sstevel@tonic-gate 		break;
8797c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82545EM_COPPER:
8807c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82545EM_FIBER:
8817c478bd9Sstevel@tonic-gate 		hw->mac_type = e1000_82545;
8827c478bd9Sstevel@tonic-gate 		break;
8837c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82545GM_COPPER:
8847c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82545GM_FIBER:
8857c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82545GM_SERDES:
8867c478bd9Sstevel@tonic-gate 		hw->mac_type = e1000_82545_rev_3;
8877c478bd9Sstevel@tonic-gate 		break;
8887c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82546EB_COPPER:
8897c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82546EB_FIBER:
8907c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82546EB_QUAD_COPPER:
8917c478bd9Sstevel@tonic-gate 		hw->mac_type = e1000_82546;
8927c478bd9Sstevel@tonic-gate 		break;
8937c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82546GB_COPPER:
8947c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82546GB_FIBER:
8957c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82546GB_SERDES:
8967c478bd9Sstevel@tonic-gate 		hw->mac_type = e1000_82546_rev_3;
8977c478bd9Sstevel@tonic-gate 		break;
8987c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82541EI:
8997c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82541EI_MOBILE:
9007c478bd9Sstevel@tonic-gate 		hw->mac_type = e1000_82541;
9017c478bd9Sstevel@tonic-gate 		break;
9027c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82541ER:
9037c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82541GI:
9047c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82541GI_MOBILE:
9057c478bd9Sstevel@tonic-gate 		hw->mac_type = e1000_82541_rev_2;
9067c478bd9Sstevel@tonic-gate 		break;
9077c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82547EI:
9087c478bd9Sstevel@tonic-gate 		hw->mac_type = e1000_82547;
9097c478bd9Sstevel@tonic-gate 		break;
9107c478bd9Sstevel@tonic-gate 	case E1000_DEV_ID_82547GI:
9117c478bd9Sstevel@tonic-gate 		hw->mac_type = e1000_82547_rev_2;
9127c478bd9Sstevel@tonic-gate 		break;
9137c478bd9Sstevel@tonic-gate 	default:
9147c478bd9Sstevel@tonic-gate 		/* Should never have loaded on this device */
9157c478bd9Sstevel@tonic-gate 		return -E1000_ERR_MAC_TYPE;
9167c478bd9Sstevel@tonic-gate 	}
9177c478bd9Sstevel@tonic-gate 
9187c478bd9Sstevel@tonic-gate 	return E1000_SUCCESS;
9197c478bd9Sstevel@tonic-gate }
9207c478bd9Sstevel@tonic-gate 
9217c478bd9Sstevel@tonic-gate /*****************************************************************************
9227c478bd9Sstevel@tonic-gate  * Set media type and TBI compatibility.
9237c478bd9Sstevel@tonic-gate  *
9247c478bd9Sstevel@tonic-gate  * hw - Struct containing variables accessed by shared code
9257c478bd9Sstevel@tonic-gate  * **************************************************************************/
9267c478bd9Sstevel@tonic-gate static void
9277c478bd9Sstevel@tonic-gate e1000_set_media_type(struct e1000_hw *hw)
9287c478bd9Sstevel@tonic-gate {
9297c478bd9Sstevel@tonic-gate 	uint32_t status;
9307c478bd9Sstevel@tonic-gate 
9317c478bd9Sstevel@tonic-gate 	DEBUGFUNC("e1000_set_media_type");
9327c478bd9Sstevel@tonic-gate 
9337c478bd9Sstevel@tonic-gate 	if(hw->mac_type != e1000_82543) {
9347c478bd9Sstevel@tonic-gate 		/* tbi_compatibility is only valid on 82543 */
9357c478bd9Sstevel@tonic-gate 		hw->tbi_compatibility_en = FALSE;
9367c478bd9Sstevel@tonic-gate 	}
9377c478bd9Sstevel@tonic-gate 
9387c478bd9Sstevel@tonic-gate 	switch (hw->device_id) {
9397c478bd9Sstevel@tonic-gate 		case E1000_DEV_ID_82545GM_SERDES:
9407c478bd9Sstevel@tonic-gate 		case E1000_DEV_ID_82546GB_SERDES:
9417c478bd9Sstevel@tonic-gate 			hw->media_type = e1000_media_type_internal_serdes;
9427c478bd9Sstevel@tonic-gate 			break;
9437c478bd9Sstevel@tonic-gate 		default:
9447c478bd9Sstevel@tonic-gate 			if(hw->mac_type >= e1000_82543) {
9457c478bd9Sstevel@tonic-gate 				status = E1000_READ_REG(hw, STATUS);
9467c478bd9Sstevel@tonic-gate 				if(status & E1000_STATUS_TBIMODE) {
9477c478bd9Sstevel@tonic-gate 					hw->media_type = e1000_media_type_fiber;
9487c478bd9Sstevel@tonic-gate 					/* tbi_compatibility not valid on fiber */
9497c478bd9Sstevel@tonic-gate 					hw->tbi_compatibility_en = FALSE;
9507c478bd9Sstevel@tonic-gate 				} else {
9517c478bd9Sstevel@tonic-gate 					hw->media_type = e1000_media_type_copper;
9527c478bd9Sstevel@tonic-gate 				}
9537c478bd9Sstevel@tonic-gate 			} else {
9547c478bd9Sstevel@tonic-gate 				/* This is an 82542 (fiber only) */
9557c478bd9Sstevel@tonic-gate 				hw->media_type = e1000_media_type_fiber;
9567c478bd9Sstevel@tonic-gate 			}
9577c478bd9Sstevel@tonic-gate 	}
9587c478bd9Sstevel@tonic-gate }
9597c478bd9Sstevel@tonic-gate 
9607c478bd9Sstevel@tonic-gate /******************************************************************************
9617c478bd9Sstevel@tonic-gate  * Reset the transmit and receive units; mask and clear all interrupts.
9627c478bd9Sstevel@tonic-gate  *
9637c478bd9Sstevel@tonic-gate  * hw - Struct containing variables accessed by shared code
9647c478bd9Sstevel@tonic-gate  *****************************************************************************/
9657c478bd9Sstevel@tonic-gate static void
9667c478bd9Sstevel@tonic-gate e1000_reset_hw(struct e1000_hw *hw)
9677c478bd9Sstevel@tonic-gate {
9687c478bd9Sstevel@tonic-gate 	uint32_t ctrl;
9697c478bd9Sstevel@tonic-gate 	uint32_t ctrl_ext;
9707c478bd9Sstevel@tonic-gate 	uint32_t icr;
9717c478bd9Sstevel@tonic-gate 	uint32_t manc;
9727c478bd9Sstevel@tonic-gate 
9737c478bd9Sstevel@tonic-gate 	DEBUGFUNC("e1000_reset_hw");
9747c478bd9Sstevel@tonic-gate 
9757c478bd9Sstevel@tonic-gate 	/* For 82542 (rev 2.0), disable MWI before issuing a device reset */
9767c478bd9Sstevel@tonic-gate 	if(hw->mac_type == e1000_82542_rev2_0) {
9777c478bd9Sstevel@tonic-gate 		DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
9787c478bd9Sstevel@tonic-gate 		e1000_pci_clear_mwi(hw);
9797c478bd9Sstevel@tonic-gate 	}
9807c478bd9Sstevel@tonic-gate 
9817c478bd9Sstevel@tonic-gate 	/* Clear interrupt mask to stop board from generating interrupts */
9827c478bd9Sstevel@tonic-gate 	DEBUGOUT("Masking off all interrupts\n");
9837c478bd9Sstevel@tonic-gate 	E1000_WRITE_REG(hw, IMC, 0xffffffff);
9847c478bd9Sstevel@tonic-gate 
9857c478bd9Sstevel@tonic-gate 	/* Disable the Transmit and Receive units.  Then delay to allow
9867c478bd9Sstevel@tonic-gate 	 * any pending transactions to complete before we hit the MAC with
9877c478bd9Sstevel@tonic-gate 	 * the global reset.
9887c478bd9Sstevel@tonic-gate 	 */
9897c478bd9Sstevel@tonic-gate 	E1000_WRITE_REG(hw, RCTL, 0);
9907c478bd9Sstevel@tonic-gate 	E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
9917c478bd9Sstevel@tonic-gate 	E1000_WRITE_FLUSH(hw);
9927c478bd9Sstevel@tonic-gate 
9937c478bd9Sstevel@tonic-gate 	/* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
9947c478bd9Sstevel@tonic-gate 	hw->tbi_compatibility_on = FALSE;
9957c478bd9Sstevel@tonic-gate 
9967c478bd9Sstevel@tonic-gate 	/* Delay to allow any outstanding PCI transactions to complete before
9977c478bd9Sstevel@tonic-gate 	 * resetting the device
9987c478bd9Sstevel@tonic-gate 	 */
9997c478bd9Sstevel@tonic-gate 	mdelay(10);
10007c478bd9Sstevel@tonic-gate 
10017c478bd9Sstevel@tonic-gate 	ctrl = E1000_READ_REG(hw, CTRL);
10027c478bd9Sstevel@tonic-gate 
10037c478bd9Sstevel@tonic-gate 	/* Must reset the PHY before resetting the MAC */
10047c478bd9Sstevel@tonic-gate 	if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
10057c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
10067c478bd9Sstevel@tonic-gate 		mdelay(5);
10077c478bd9Sstevel@tonic-gate 	}
10087c478bd9Sstevel@tonic-gate 
10097c478bd9Sstevel@tonic-gate 	/* Issue a global reset to the MAC.  This will reset the chip's
10107c478bd9Sstevel@tonic-gate 	 * transmit, receive, DMA, and link units.  It will not effect
10117c478bd9Sstevel@tonic-gate 	 * the current PCI configuration.  The global reset bit is self-
10127c478bd9Sstevel@tonic-gate 	 * clearing, and should clear within a microsecond.
10137c478bd9Sstevel@tonic-gate 	 */
10147c478bd9Sstevel@tonic-gate 	DEBUGOUT("Issuing a global reset to MAC\n");
10157c478bd9Sstevel@tonic-gate 
10167c478bd9Sstevel@tonic-gate 	switch(hw->mac_type) {
10177c478bd9Sstevel@tonic-gate 		case e1000_82544:
10187c478bd9Sstevel@tonic-gate 		case e1000_82540:
10197c478bd9Sstevel@tonic-gate 		case e1000_82545:
10207c478bd9Sstevel@tonic-gate 		case e1000_82546:
10217c478bd9Sstevel@tonic-gate 		case e1000_82541:
10227c478bd9Sstevel@tonic-gate 		case e1000_82541_rev_2:
10237c478bd9Sstevel@tonic-gate 			/* These controllers can't ack the 64-bit write when issuing the
10247c478bd9Sstevel@tonic-gate 			 * reset, so use IO-mapping as a workaround to issue the reset */
10257c478bd9Sstevel@tonic-gate 			E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
10267c478bd9Sstevel@tonic-gate 			break;
10277c478bd9Sstevel@tonic-gate 		case e1000_82545_rev_3:
10287c478bd9Sstevel@tonic-gate 		case e1000_82546_rev_3:
10297c478bd9Sstevel@tonic-gate 			/* Reset is performed on a shadow of the control register */
10307c478bd9Sstevel@tonic-gate 			E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
10317c478bd9Sstevel@tonic-gate 			break;
10327c478bd9Sstevel@tonic-gate 		default:
10337c478bd9Sstevel@tonic-gate 			E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
10347c478bd9Sstevel@tonic-gate 			break;
10357c478bd9Sstevel@tonic-gate 	}
10367c478bd9Sstevel@tonic-gate 
10377c478bd9Sstevel@tonic-gate 	/* After MAC reset, force reload of EEPROM to restore power-on settings to
10387c478bd9Sstevel@tonic-gate 	 * device.  Later controllers reload the EEPROM automatically, so just wait
10397c478bd9Sstevel@tonic-gate 	 * for reload to complete.
10407c478bd9Sstevel@tonic-gate 	 */
10417c478bd9Sstevel@tonic-gate 	switch(hw->mac_type) {
10427c478bd9Sstevel@tonic-gate 		case e1000_82542_rev2_0:
10437c478bd9Sstevel@tonic-gate 		case e1000_82542_rev2_1:
10447c478bd9Sstevel@tonic-gate 		case e1000_82543:
10457c478bd9Sstevel@tonic-gate 		case e1000_82544:
10467c478bd9Sstevel@tonic-gate 			/* Wait for reset to complete */
10477c478bd9Sstevel@tonic-gate 			udelay(10);
10487c478bd9Sstevel@tonic-gate 			ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
10497c478bd9Sstevel@tonic-gate 			ctrl_ext |= E1000_CTRL_EXT_EE_RST;
10507c478bd9Sstevel@tonic-gate 			E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
10517c478bd9Sstevel@tonic-gate 			E1000_WRITE_FLUSH(hw);
10527c478bd9Sstevel@tonic-gate 			/* Wait for EEPROM reload */
10537c478bd9Sstevel@tonic-gate 			mdelay(2);
10547c478bd9Sstevel@tonic-gate 			break;
10557c478bd9Sstevel@tonic-gate 		case e1000_82541:
10567c478bd9Sstevel@tonic-gate 		case e1000_82541_rev_2:
10577c478bd9Sstevel@tonic-gate 		case e1000_82547:
10587c478bd9Sstevel@tonic-gate 		case e1000_82547_rev_2:
10597c478bd9Sstevel@tonic-gate 			/* Wait for EEPROM reload */
10607c478bd9Sstevel@tonic-gate 			mdelay(20);
10617c478bd9Sstevel@tonic-gate 			break;
10627c478bd9Sstevel@tonic-gate 		default:
10637c478bd9Sstevel@tonic-gate 			/* Wait for EEPROM reload (it happens automatically) */
10647c478bd9Sstevel@tonic-gate 			mdelay(5);
10657c478bd9Sstevel@tonic-gate 			break;
10667c478bd9Sstevel@tonic-gate 	}
10677c478bd9Sstevel@tonic-gate 
10687c478bd9Sstevel@tonic-gate 	/* Disable HW ARPs on ASF enabled adapters */
10697c478bd9Sstevel@tonic-gate 	if(hw->mac_type >= e1000_82540) {
10707c478bd9Sstevel@tonic-gate 		manc = E1000_READ_REG(hw, MANC);
10717c478bd9Sstevel@tonic-gate 		manc &= ~(E1000_MANC_ARP_EN);
10727c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, MANC, manc);
10737c478bd9Sstevel@tonic-gate 	}
10747c478bd9Sstevel@tonic-gate 
10757c478bd9Sstevel@tonic-gate 	if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
10767c478bd9Sstevel@tonic-gate 		e1000_phy_init_script(hw);
10777c478bd9Sstevel@tonic-gate 	}
10787c478bd9Sstevel@tonic-gate 
10797c478bd9Sstevel@tonic-gate 	/* Clear interrupt mask to stop board from generating interrupts */
10807c478bd9Sstevel@tonic-gate 	DEBUGOUT("Masking off all interrupts\n");
10817c478bd9Sstevel@tonic-gate 	E1000_WRITE_REG(hw, IMC, 0xffffffff);
10827c478bd9Sstevel@tonic-gate 
10837c478bd9Sstevel@tonic-gate 	/* Clear any pending interrupt events. */
10847c478bd9Sstevel@tonic-gate 	icr = E1000_READ_REG(hw, ICR);
10857c478bd9Sstevel@tonic-gate 
10867c478bd9Sstevel@tonic-gate 	/* If MWI was previously enabled, reenable it. */
10877c478bd9Sstevel@tonic-gate 	if(hw->mac_type == e1000_82542_rev2_0) {
10887c478bd9Sstevel@tonic-gate #ifdef LINUX_DRIVER
10897c478bd9Sstevel@tonic-gate 		if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
10907c478bd9Sstevel@tonic-gate #endif
10917c478bd9Sstevel@tonic-gate 			e1000_pci_set_mwi(hw);
10927c478bd9Sstevel@tonic-gate 	}
10937c478bd9Sstevel@tonic-gate }
10947c478bd9Sstevel@tonic-gate 
10957c478bd9Sstevel@tonic-gate /******************************************************************************
10967c478bd9Sstevel@tonic-gate  * Performs basic configuration of the adapter.
10977c478bd9Sstevel@tonic-gate  *
10987c478bd9Sstevel@tonic-gate  * hw - Struct containing variables accessed by shared code
10997c478bd9Sstevel@tonic-gate  *
11007c478bd9Sstevel@tonic-gate  * Assumes that the controller has previously been reset and is in a
11017c478bd9Sstevel@tonic-gate  * post-reset uninitialized state. Initializes the receive address registers,
11027c478bd9Sstevel@tonic-gate  * multicast table, and VLAN filter table. Calls routines to setup link
11037c478bd9Sstevel@tonic-gate  * configuration and flow control settings. Clears all on-chip counters. Leaves
11047c478bd9Sstevel@tonic-gate  * the transmit and receive units disabled and uninitialized.
11057c478bd9Sstevel@tonic-gate  *****************************************************************************/
11067c478bd9Sstevel@tonic-gate static int
11077c478bd9Sstevel@tonic-gate e1000_init_hw(struct e1000_hw *hw)
11087c478bd9Sstevel@tonic-gate {
11097c478bd9Sstevel@tonic-gate 	uint32_t ctrl, status;
11107c478bd9Sstevel@tonic-gate 	uint32_t i;
11117c478bd9Sstevel@tonic-gate 	int32_t ret_val;
11127c478bd9Sstevel@tonic-gate 	uint16_t pcix_cmd_word;
11137c478bd9Sstevel@tonic-gate 	uint16_t pcix_stat_hi_word;
11147c478bd9Sstevel@tonic-gate 	uint16_t cmd_mmrbc;
11157c478bd9Sstevel@tonic-gate 	uint16_t stat_mmrbc;
11167c478bd9Sstevel@tonic-gate 	e1000_bus_type bus_type = e1000_bus_type_unknown;
11177c478bd9Sstevel@tonic-gate 
11187c478bd9Sstevel@tonic-gate 	DEBUGFUNC("e1000_init_hw");
11197c478bd9Sstevel@tonic-gate 
11207c478bd9Sstevel@tonic-gate 	/* Set the media type and TBI compatibility */
11217c478bd9Sstevel@tonic-gate 	e1000_set_media_type(hw);
11227c478bd9Sstevel@tonic-gate 
11237c478bd9Sstevel@tonic-gate 	/* Disabling VLAN filtering. */
11247c478bd9Sstevel@tonic-gate 	DEBUGOUT("Initializing the IEEE VLAN\n");
11257c478bd9Sstevel@tonic-gate 	E1000_WRITE_REG(hw, VET, 0);
11267c478bd9Sstevel@tonic-gate 
11277c478bd9Sstevel@tonic-gate 	e1000_clear_vfta(hw);
11287c478bd9Sstevel@tonic-gate 
11297c478bd9Sstevel@tonic-gate 	/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
11307c478bd9Sstevel@tonic-gate 	if(hw->mac_type == e1000_82542_rev2_0) {
11317c478bd9Sstevel@tonic-gate 		DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
11327c478bd9Sstevel@tonic-gate 		e1000_pci_clear_mwi(hw);
11337c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
11347c478bd9Sstevel@tonic-gate 		E1000_WRITE_FLUSH(hw);
11357c478bd9Sstevel@tonic-gate 		mdelay(5);
11367c478bd9Sstevel@tonic-gate 	}
11377c478bd9Sstevel@tonic-gate 
11387c478bd9Sstevel@tonic-gate 	/* Setup the receive address. This involves initializing all of the Receive
11397c478bd9Sstevel@tonic-gate 	 * Address Registers (RARs 0 - 15).
11407c478bd9Sstevel@tonic-gate 	 */
11417c478bd9Sstevel@tonic-gate 	e1000_init_rx_addrs(hw);
11427c478bd9Sstevel@tonic-gate 
11437c478bd9Sstevel@tonic-gate 	/* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
11447c478bd9Sstevel@tonic-gate 	if(hw->mac_type == e1000_82542_rev2_0) {
11457c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, RCTL, 0);
11467c478bd9Sstevel@tonic-gate 		E1000_WRITE_FLUSH(hw);
11477c478bd9Sstevel@tonic-gate 		mdelay(1);
11487c478bd9Sstevel@tonic-gate #ifdef LINUX_DRIVER
11497c478bd9Sstevel@tonic-gate 		if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
11507c478bd9Sstevel@tonic-gate #endif
11517c478bd9Sstevel@tonic-gate 			e1000_pci_set_mwi(hw);
11527c478bd9Sstevel@tonic-gate 	}
11537c478bd9Sstevel@tonic-gate 
11547c478bd9Sstevel@tonic-gate 	/* Zero out the Multicast HASH table */
11557c478bd9Sstevel@tonic-gate 	DEBUGOUT("Zeroing the MTA\n");
11567c478bd9Sstevel@tonic-gate 	for(i = 0; i < E1000_MC_TBL_SIZE; i++)
11577c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
11587c478bd9Sstevel@tonic-gate 
11597c478bd9Sstevel@tonic-gate #if 0
11607c478bd9Sstevel@tonic-gate 	/* Set the PCI priority bit correctly in the CTRL register.  This
11617c478bd9Sstevel@tonic-gate 	 * determines if the adapter gives priority to receives, or if it
11627c478bd9Sstevel@tonic-gate 	 * gives equal priority to transmits and receives.
11637c478bd9Sstevel@tonic-gate 	 */
11647c478bd9Sstevel@tonic-gate 	if(hw->dma_fairness) {
11657c478bd9Sstevel@tonic-gate 		ctrl = E1000_READ_REG(hw, CTRL);
11667c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
11677c478bd9Sstevel@tonic-gate 	}
11687c478bd9Sstevel@tonic-gate #endif
11697c478bd9Sstevel@tonic-gate 
11707c478bd9Sstevel@tonic-gate 	switch(hw->mac_type) {
11717c478bd9Sstevel@tonic-gate 		case e1000_82545_rev_3:
11727c478bd9Sstevel@tonic-gate 		case e1000_82546_rev_3:
11737c478bd9Sstevel@tonic-gate 			break;
11747c478bd9Sstevel@tonic-gate 		default:
11757c478bd9Sstevel@tonic-gate 			if (hw->mac_type >= e1000_82543) {
11767c478bd9Sstevel@tonic-gate 				/* See e1000_get_bus_info() of the Linux driver */
11777c478bd9Sstevel@tonic-gate 				status = E1000_READ_REG(hw, STATUS);
11787c478bd9Sstevel@tonic-gate 				bus_type = (status & E1000_STATUS_PCIX_MODE) ?
11797c478bd9Sstevel@tonic-gate 					e1000_bus_type_pcix : e1000_bus_type_pci;
11807c478bd9Sstevel@tonic-gate 			}
11817c478bd9Sstevel@tonic-gate 
11827c478bd9Sstevel@tonic-gate 			/* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
11837c478bd9Sstevel@tonic-gate 			if(bus_type == e1000_bus_type_pcix) {
11847c478bd9Sstevel@tonic-gate 				pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
11857c478bd9Sstevel@tonic-gate 				pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
11867c478bd9Sstevel@tonic-gate 				cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
11877c478bd9Sstevel@tonic-gate 					PCIX_COMMAND_MMRBC_SHIFT;
11887c478bd9Sstevel@tonic-gate 				stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
11897c478bd9Sstevel@tonic-gate 					PCIX_STATUS_HI_MMRBC_SHIFT;
11907c478bd9Sstevel@tonic-gate 				if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
11917c478bd9Sstevel@tonic-gate 					stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
11927c478bd9Sstevel@tonic-gate 				if(cmd_mmrbc > stat_mmrbc) {
11937c478bd9Sstevel@tonic-gate 					pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
11947c478bd9Sstevel@tonic-gate 					pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
11957c478bd9Sstevel@tonic-gate 					pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, pcix_cmd_word);
11967c478bd9Sstevel@tonic-gate 				}
11977c478bd9Sstevel@tonic-gate 			}
11987c478bd9Sstevel@tonic-gate 			break;
11997c478bd9Sstevel@tonic-gate 	}
12007c478bd9Sstevel@tonic-gate 
12017c478bd9Sstevel@tonic-gate 	/* Call a subroutine to configure the link and setup flow control. */
12027c478bd9Sstevel@tonic-gate 	ret_val = e1000_setup_link(hw);
12037c478bd9Sstevel@tonic-gate 
12047c478bd9Sstevel@tonic-gate 	/* Set the transmit descriptor write-back policy */
12057c478bd9Sstevel@tonic-gate 	if(hw->mac_type > e1000_82544) {
12067c478bd9Sstevel@tonic-gate 		ctrl = E1000_READ_REG(hw, TXDCTL);
12077c478bd9Sstevel@tonic-gate 		ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
12087c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, TXDCTL, ctrl);
12097c478bd9Sstevel@tonic-gate 	}
12107c478bd9Sstevel@tonic-gate 
12117c478bd9Sstevel@tonic-gate #if 0
12127c478bd9Sstevel@tonic-gate 	/* Clear all of the statistics registers (clear on read).  It is
12137c478bd9Sstevel@tonic-gate 	 * important that we do this after we have tried to establish link
12147c478bd9Sstevel@tonic-gate 	 * because the symbol error count will increment wildly if there
12157c478bd9Sstevel@tonic-gate 	 * is no link.
12167c478bd9Sstevel@tonic-gate 	 */
12177c478bd9Sstevel@tonic-gate 	e1000_clear_hw_cntrs(hw);
12187c478bd9Sstevel@tonic-gate #endif
12197c478bd9Sstevel@tonic-gate 
12207c478bd9Sstevel@tonic-gate 	return ret_val;
12217c478bd9Sstevel@tonic-gate }
12227c478bd9Sstevel@tonic-gate 
12237c478bd9Sstevel@tonic-gate /******************************************************************************
12247c478bd9Sstevel@tonic-gate  * Adjust SERDES output amplitude based on EEPROM setting.
12257c478bd9Sstevel@tonic-gate  *
12267c478bd9Sstevel@tonic-gate  * hw - Struct containing variables accessed by shared code.
12277c478bd9Sstevel@tonic-gate  *****************************************************************************/
12287c478bd9Sstevel@tonic-gate static int32_t
12297c478bd9Sstevel@tonic-gate e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
12307c478bd9Sstevel@tonic-gate {
12317c478bd9Sstevel@tonic-gate 	uint16_t eeprom_data;
12327c478bd9Sstevel@tonic-gate 	int32_t  ret_val;
12337c478bd9Sstevel@tonic-gate 
12347c478bd9Sstevel@tonic-gate 	DEBUGFUNC("e1000_adjust_serdes_amplitude");
12357c478bd9Sstevel@tonic-gate 
12367c478bd9Sstevel@tonic-gate 	if(hw->media_type != e1000_media_type_internal_serdes)
12377c478bd9Sstevel@tonic-gate 		return E1000_SUCCESS;
12387c478bd9Sstevel@tonic-gate 
12397c478bd9Sstevel@tonic-gate 	switch(hw->mac_type) {
12407c478bd9Sstevel@tonic-gate 		case e1000_82545_rev_3:
12417c478bd9Sstevel@tonic-gate 		case e1000_82546_rev_3:
12427c478bd9Sstevel@tonic-gate 			break;
12437c478bd9Sstevel@tonic-gate 		default:
12447c478bd9Sstevel@tonic-gate 			return E1000_SUCCESS;
12457c478bd9Sstevel@tonic-gate 	}
12467c478bd9Sstevel@tonic-gate 
12477c478bd9Sstevel@tonic-gate 	if ((ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
12487c478bd9Sstevel@tonic-gate 					&eeprom_data))) {
12497c478bd9Sstevel@tonic-gate 		return ret_val;
12507c478bd9Sstevel@tonic-gate 	}
12517c478bd9Sstevel@tonic-gate 
12527c478bd9Sstevel@tonic-gate 	if(eeprom_data != EEPROM_RESERVED_WORD) {
12537c478bd9Sstevel@tonic-gate 		/* Adjust SERDES output amplitude only. */
12547c478bd9Sstevel@tonic-gate 		eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
12557c478bd9Sstevel@tonic-gate 		if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL,
12567c478bd9Sstevel@tonic-gate 		                                  eeprom_data)))
12577c478bd9Sstevel@tonic-gate 			return ret_val;
12587c478bd9Sstevel@tonic-gate 	}
12597c478bd9Sstevel@tonic-gate 
12607c478bd9Sstevel@tonic-gate 	return E1000_SUCCESS;
12617c478bd9Sstevel@tonic-gate }
12627c478bd9Sstevel@tonic-gate 
12637c478bd9Sstevel@tonic-gate /******************************************************************************
12647c478bd9Sstevel@tonic-gate  * Configures flow control and link settings.
12657c478bd9Sstevel@tonic-gate  *
12667c478bd9Sstevel@tonic-gate  * hw - Struct containing variables accessed by shared code
12677c478bd9Sstevel@tonic-gate  *
12687c478bd9Sstevel@tonic-gate  * Determines which flow control settings to use. Calls the apropriate media-
12697c478bd9Sstevel@tonic-gate  * specific link configuration function. Configures the flow control settings.
12707c478bd9Sstevel@tonic-gate  * Assuming the adapter has a valid link partner, a valid link should be
12717c478bd9Sstevel@tonic-gate  * established. Assumes the hardware has previously been reset and the
12727c478bd9Sstevel@tonic-gate  * transmitter and receiver are not enabled.
12737c478bd9Sstevel@tonic-gate  *****************************************************************************/
12747c478bd9Sstevel@tonic-gate static int
12757c478bd9Sstevel@tonic-gate e1000_setup_link(struct e1000_hw *hw)
12767c478bd9Sstevel@tonic-gate {
12777c478bd9Sstevel@tonic-gate 	uint32_t ctrl_ext;
12787c478bd9Sstevel@tonic-gate 	int32_t ret_val;
12797c478bd9Sstevel@tonic-gate 	uint16_t eeprom_data;
12807c478bd9Sstevel@tonic-gate 
12817c478bd9Sstevel@tonic-gate 	DEBUGFUNC("e1000_setup_link");
12827c478bd9Sstevel@tonic-gate 
12837c478bd9Sstevel@tonic-gate 	/* Read and store word 0x0F of the EEPROM. This word contains bits
12847c478bd9Sstevel@tonic-gate 	 * that determine the hardware's default PAUSE (flow control) mode,
12857c478bd9Sstevel@tonic-gate 	 * a bit that determines whether the HW defaults to enabling or
12867c478bd9Sstevel@tonic-gate 	 * disabling auto-negotiation, and the direction of the
12877c478bd9Sstevel@tonic-gate 	 * SW defined pins. If there is no SW over-ride of the flow
12887c478bd9Sstevel@tonic-gate 	 * control setting, then the variable hw->fc will
12897c478bd9Sstevel@tonic-gate 	 * be initialized based on a value in the EEPROM.
12907c478bd9Sstevel@tonic-gate 	 */
12917c478bd9Sstevel@tonic-gate 	if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
12927c478bd9Sstevel@tonic-gate 		DEBUGOUT("EEPROM Read Error\n");
12937c478bd9Sstevel@tonic-gate 		return -E1000_ERR_EEPROM;
12947c478bd9Sstevel@tonic-gate 	}
12957c478bd9Sstevel@tonic-gate 
12967c478bd9Sstevel@tonic-gate 	if(hw->fc == e1000_fc_default) {
12977c478bd9Sstevel@tonic-gate 		if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
12987c478bd9Sstevel@tonic-gate 			hw->fc = e1000_fc_none;
12997c478bd9Sstevel@tonic-gate 		else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
13007c478bd9Sstevel@tonic-gate 			EEPROM_WORD0F_ASM_DIR)
13017c478bd9Sstevel@tonic-gate 			hw->fc = e1000_fc_tx_pause;
13027c478bd9Sstevel@tonic-gate 		else
13037c478bd9Sstevel@tonic-gate 			hw->fc = e1000_fc_full;
13047c478bd9Sstevel@tonic-gate 	}
13057c478bd9Sstevel@tonic-gate 
13067c478bd9Sstevel@tonic-gate 	/* We want to save off the original Flow Control configuration just
13077c478bd9Sstevel@tonic-gate 	 * in case we get disconnected and then reconnected into a different
13087c478bd9Sstevel@tonic-gate 	 * hub or switch with different Flow Control capabilities.
13097c478bd9Sstevel@tonic-gate 	 */
13107c478bd9Sstevel@tonic-gate 	if(hw->mac_type == e1000_82542_rev2_0)
13117c478bd9Sstevel@tonic-gate 		hw->fc &= (~e1000_fc_tx_pause);
13127c478bd9Sstevel@tonic-gate 
13137c478bd9Sstevel@tonic-gate #if 0
13147c478bd9Sstevel@tonic-gate 	/* See e1000_sw_init() of the Linux driver */
13157c478bd9Sstevel@tonic-gate 	if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
13167c478bd9Sstevel@tonic-gate #else
13177c478bd9Sstevel@tonic-gate 	if((hw->mac_type < e1000_82543) && (hw->mac_type >= e1000_82543))
13187c478bd9Sstevel@tonic-gate #endif
13197c478bd9Sstevel@tonic-gate 		hw->fc &= (~e1000_fc_rx_pause);
13207c478bd9Sstevel@tonic-gate 
13217c478bd9Sstevel@tonic-gate #if 0
13227c478bd9Sstevel@tonic-gate 	hw->original_fc = hw->fc;
13237c478bd9Sstevel@tonic-gate #endif
13247c478bd9Sstevel@tonic-gate 
13257c478bd9Sstevel@tonic-gate 	DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
13267c478bd9Sstevel@tonic-gate 
13277c478bd9Sstevel@tonic-gate 	/* Take the 4 bits from EEPROM word 0x0F that determine the initial
13287c478bd9Sstevel@tonic-gate 	 * polarity value for the SW controlled pins, and setup the
13297c478bd9Sstevel@tonic-gate 	 * Extended Device Control reg with that info.
13307c478bd9Sstevel@tonic-gate 	 * This is needed because one of the SW controlled pins is used for
13317c478bd9Sstevel@tonic-gate 	 * signal detection.  So this should be done before e1000_setup_pcs_link()
13327c478bd9Sstevel@tonic-gate 	 * or e1000_phy_setup() is called.
13337c478bd9Sstevel@tonic-gate 	 */
13347c478bd9Sstevel@tonic-gate 	if(hw->mac_type == e1000_82543) {
13357c478bd9Sstevel@tonic-gate 		ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
13367c478bd9Sstevel@tonic-gate 			SWDPIO__EXT_SHIFT);
13377c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
13387c478bd9Sstevel@tonic-gate 	}
13397c478bd9Sstevel@tonic-gate 
13407c478bd9Sstevel@tonic-gate 	/* Call the necessary subroutine to configure the link. */
13417c478bd9Sstevel@tonic-gate 	ret_val = (hw->media_type == e1000_media_type_copper) ?
13427c478bd9Sstevel@tonic-gate 		e1000_setup_copper_link(hw) :
13437c478bd9Sstevel@tonic-gate 		e1000_setup_fiber_serdes_link(hw);
13447c478bd9Sstevel@tonic-gate 	if (ret_val < 0) {
13457c478bd9Sstevel@tonic-gate 		return ret_val;
13467c478bd9Sstevel@tonic-gate 	}
13477c478bd9Sstevel@tonic-gate 
13487c478bd9Sstevel@tonic-gate 	/* Initialize the flow control address, type, and PAUSE timer
13497c478bd9Sstevel@tonic-gate 	 * registers to their default values.  This is done even if flow
13507c478bd9Sstevel@tonic-gate 	 * control is disabled, because it does not hurt anything to
13517c478bd9Sstevel@tonic-gate 	 * initialize these registers.
13527c478bd9Sstevel@tonic-gate 	 */
13537c478bd9Sstevel@tonic-gate 	DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
13547c478bd9Sstevel@tonic-gate 
13557c478bd9Sstevel@tonic-gate 	E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
13567c478bd9Sstevel@tonic-gate 	E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
13577c478bd9Sstevel@tonic-gate 	E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
13587c478bd9Sstevel@tonic-gate #if 0
13597c478bd9Sstevel@tonic-gate 	E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
13607c478bd9Sstevel@tonic-gate #else
13617c478bd9Sstevel@tonic-gate 	E1000_WRITE_REG(hw, FCTTV, FC_DEFAULT_TX_TIMER);
13627c478bd9Sstevel@tonic-gate #endif
13637c478bd9Sstevel@tonic-gate 
13647c478bd9Sstevel@tonic-gate 	/* Set the flow control receive threshold registers.  Normally,
13657c478bd9Sstevel@tonic-gate 	 * these registers will be set to a default threshold that may be
13667c478bd9Sstevel@tonic-gate 	 * adjusted later by the driver's runtime code.  However, if the
13677c478bd9Sstevel@tonic-gate 	 * ability to transmit pause frames in not enabled, then these
13687c478bd9Sstevel@tonic-gate 	 * registers will be set to 0.
13697c478bd9Sstevel@tonic-gate 	 */
13707c478bd9Sstevel@tonic-gate 	if(!(hw->fc & e1000_fc_tx_pause)) {
13717c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, FCRTL, 0);
13727c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, FCRTH, 0);
13737c478bd9Sstevel@tonic-gate 	} else {
13747c478bd9Sstevel@tonic-gate 		/* We need to set up the Receive Threshold high and low water marks
13757c478bd9Sstevel@tonic-gate 		 * as well as (optionally) enabling the transmission of XON frames.
13767c478bd9Sstevel@tonic-gate 		 */
13777c478bd9Sstevel@tonic-gate #if 0
13787c478bd9Sstevel@tonic-gate 		if(hw->fc_send_xon) {
13797c478bd9Sstevel@tonic-gate 			E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
13807c478bd9Sstevel@tonic-gate 			E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
13817c478bd9Sstevel@tonic-gate 		} else {
13827c478bd9Sstevel@tonic-gate 			E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
13837c478bd9Sstevel@tonic-gate 			E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
13847c478bd9Sstevel@tonic-gate 		}
13857c478bd9Sstevel@tonic-gate #else
13867c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, FCRTL, (FC_DEFAULT_LO_THRESH | E1000_FCRTL_XONE));
13877c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, FCRTH, FC_DEFAULT_HI_THRESH);
13887c478bd9Sstevel@tonic-gate #endif
13897c478bd9Sstevel@tonic-gate 	}
13907c478bd9Sstevel@tonic-gate 	return ret_val;
13917c478bd9Sstevel@tonic-gate }
13927c478bd9Sstevel@tonic-gate 
13937c478bd9Sstevel@tonic-gate /******************************************************************************
13947c478bd9Sstevel@tonic-gate  * Sets up link for a fiber based or serdes based adapter
13957c478bd9Sstevel@tonic-gate  *
13967c478bd9Sstevel@tonic-gate  * hw - Struct containing variables accessed by shared code
13977c478bd9Sstevel@tonic-gate  *
13987c478bd9Sstevel@tonic-gate  * Manipulates Physical Coding Sublayer functions in order to configure
13997c478bd9Sstevel@tonic-gate  * link. Assumes the hardware has been previously reset and the transmitter
14007c478bd9Sstevel@tonic-gate  * and receiver are not enabled.
14017c478bd9Sstevel@tonic-gate  *****************************************************************************/
14027c478bd9Sstevel@tonic-gate static int
14037c478bd9Sstevel@tonic-gate e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
14047c478bd9Sstevel@tonic-gate {
14057c478bd9Sstevel@tonic-gate 	uint32_t ctrl;
14067c478bd9Sstevel@tonic-gate 	uint32_t status;
14077c478bd9Sstevel@tonic-gate 	uint32_t txcw = 0;
14087c478bd9Sstevel@tonic-gate 	uint32_t i;
14097c478bd9Sstevel@tonic-gate 	uint32_t signal = 0;
14107c478bd9Sstevel@tonic-gate 	int32_t ret_val;
14117c478bd9Sstevel@tonic-gate 
14127c478bd9Sstevel@tonic-gate 	DEBUGFUNC("e1000_setup_fiber_serdes_link");
14137c478bd9Sstevel@tonic-gate 
14147c478bd9Sstevel@tonic-gate 	/* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
14157c478bd9Sstevel@tonic-gate 	 * set when the optics detect a signal. On older adapters, it will be
14167c478bd9Sstevel@tonic-gate 	 * cleared when there is a signal.  This applies to fiber media only.
14177c478bd9Sstevel@tonic-gate 	 * If we're on serdes media, adjust the output amplitude to value set in
14187c478bd9Sstevel@tonic-gate 	 * the EEPROM.
14197c478bd9Sstevel@tonic-gate 	 */
14207c478bd9Sstevel@tonic-gate 	ctrl = E1000_READ_REG(hw, CTRL);
14217c478bd9Sstevel@tonic-gate 	if(hw->media_type == e1000_media_type_fiber)
14227c478bd9Sstevel@tonic-gate 		signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
14237c478bd9Sstevel@tonic-gate 
14247c478bd9Sstevel@tonic-gate 	if((ret_val = e1000_adjust_serdes_amplitude(hw)))
14257c478bd9Sstevel@tonic-gate 		return ret_val;
14267c478bd9Sstevel@tonic-gate 
14277c478bd9Sstevel@tonic-gate 	/* Take the link out of reset */
14287c478bd9Sstevel@tonic-gate 	ctrl &= ~(E1000_CTRL_LRST);
14297c478bd9Sstevel@tonic-gate 
14307c478bd9Sstevel@tonic-gate #if 0
14317c478bd9Sstevel@tonic-gate 	/* Adjust VCO speed to improve BER performance */
14327c478bd9Sstevel@tonic-gate 	if((ret_val = e1000_set_vco_speed(hw)))
14337c478bd9Sstevel@tonic-gate 		return ret_val;
14347c478bd9Sstevel@tonic-gate #endif
14357c478bd9Sstevel@tonic-gate 
14367c478bd9Sstevel@tonic-gate 	e1000_config_collision_dist(hw);
14377c478bd9Sstevel@tonic-gate 
14387c478bd9Sstevel@tonic-gate 	/* Check for a software override of the flow control settings, and setup
14397c478bd9Sstevel@tonic-gate 	 * the device accordingly.  If auto-negotiation is enabled, then software
14407c478bd9Sstevel@tonic-gate 	 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
14417c478bd9Sstevel@tonic-gate 	 * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
14427c478bd9Sstevel@tonic-gate 	 * auto-negotiation is disabled, then software will have to manually
14437c478bd9Sstevel@tonic-gate 	 * configure the two flow control enable bits in the CTRL register.
14447c478bd9Sstevel@tonic-gate 	 *
14457c478bd9Sstevel@tonic-gate 	 * The possible values of the "fc" parameter are:
14467c478bd9Sstevel@tonic-gate 	 *      0:  Flow control is completely disabled
14477c478bd9Sstevel@tonic-gate 	 *      1:  Rx flow control is enabled (we can receive pause frames, but
14487c478bd9Sstevel@tonic-gate 	 *          not send pause frames).
14497c478bd9Sstevel@tonic-gate 	 *      2:  Tx flow control is enabled (we can send pause frames but we do
14507c478bd9Sstevel@tonic-gate 	 *          not support receiving pause frames).
14517c478bd9Sstevel@tonic-gate 	 *      3:  Both Rx and TX flow control (symmetric) are enabled.
14527c478bd9Sstevel@tonic-gate 	 */
14537c478bd9Sstevel@tonic-gate 	switch (hw->fc) {
14547c478bd9Sstevel@tonic-gate 	case e1000_fc_none:
14557c478bd9Sstevel@tonic-gate 		/* Flow control is completely disabled by a software over-ride. */
14567c478bd9Sstevel@tonic-gate 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
14577c478bd9Sstevel@tonic-gate 		break;
14587c478bd9Sstevel@tonic-gate 	case e1000_fc_rx_pause:
14597c478bd9Sstevel@tonic-gate 		/* RX Flow control is enabled and TX Flow control is disabled by a
14607c478bd9Sstevel@tonic-gate 		 * software over-ride. Since there really isn't a way to advertise
14617c478bd9Sstevel@tonic-gate 		 * that we are capable of RX Pause ONLY, we will advertise that we
14627c478bd9Sstevel@tonic-gate 		 * support both symmetric and asymmetric RX PAUSE. Later, we will
14637c478bd9Sstevel@tonic-gate 		 *  disable the adapter's ability to send PAUSE frames.
14647c478bd9Sstevel@tonic-gate 		 */
14657c478bd9Sstevel@tonic-gate 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
14667c478bd9Sstevel@tonic-gate 		break;
14677c478bd9Sstevel@tonic-gate 	case e1000_fc_tx_pause:
14687c478bd9Sstevel@tonic-gate 		/* TX Flow control is enabled, and RX Flow control is disabled, by a
14697c478bd9Sstevel@tonic-gate 		 * software over-ride.
14707c478bd9Sstevel@tonic-gate 		 */
14717c478bd9Sstevel@tonic-gate 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
14727c478bd9Sstevel@tonic-gate 		break;
14737c478bd9Sstevel@tonic-gate 	case e1000_fc_full:
14747c478bd9Sstevel@tonic-gate 		/* Flow control (both RX and TX) is enabled by a software over-ride. */
14757c478bd9Sstevel@tonic-gate 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
14767c478bd9Sstevel@tonic-gate 		break;
14777c478bd9Sstevel@tonic-gate 	default:
14787c478bd9Sstevel@tonic-gate 		DEBUGOUT("Flow control param set incorrectly\n");
14797c478bd9Sstevel@tonic-gate 		return -E1000_ERR_CONFIG;
14807c478bd9Sstevel@tonic-gate 		break;
14817c478bd9Sstevel@tonic-gate 	}
14827c478bd9Sstevel@tonic-gate 
14837c478bd9Sstevel@tonic-gate 	/* Since auto-negotiation is enabled, take the link out of reset (the link
14847c478bd9Sstevel@tonic-gate 	 * will be in reset, because we previously reset the chip). This will
14857c478bd9Sstevel@tonic-gate 	 * restart auto-negotiation.  If auto-neogtiation is successful then the
14867c478bd9Sstevel@tonic-gate 	 * link-up status bit will be set and the flow control enable bits (RFCE
14877c478bd9Sstevel@tonic-gate 	 * and TFCE) will be set according to their negotiated value.
14887c478bd9Sstevel@tonic-gate 	 */
14897c478bd9Sstevel@tonic-gate 	DEBUGOUT("Auto-negotiation enabled\n");
14907c478bd9Sstevel@tonic-gate 
14917c478bd9Sstevel@tonic-gate 	E1000_WRITE_REG(hw, TXCW, txcw);
14927c478bd9Sstevel@tonic-gate 	E1000_WRITE_REG(hw, CTRL, ctrl);
14937c478bd9Sstevel@tonic-gate 	E1000_WRITE_FLUSH(hw);
14947c478bd9Sstevel@tonic-gate 
14957c478bd9Sstevel@tonic-gate 	hw->txcw = txcw;
14967c478bd9Sstevel@tonic-gate 	mdelay(1);
14977c478bd9Sstevel@tonic-gate 
14987c478bd9Sstevel@tonic-gate 	/* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
14997c478bd9Sstevel@tonic-gate 	 * indication in the Device Status Register.  Time-out if a link isn't
15007c478bd9Sstevel@tonic-gate 	 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
15017c478bd9Sstevel@tonic-gate 	 * less than 500 milliseconds even if the other end is doing it in SW).
15027c478bd9Sstevel@tonic-gate 	 * For internal serdes, we just assume a signal is present, then poll.
15037c478bd9Sstevel@tonic-gate 	 */
15047c478bd9Sstevel@tonic-gate 	if(hw->media_type == e1000_media_type_internal_serdes ||
15057c478bd9Sstevel@tonic-gate 	   (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
15067c478bd9Sstevel@tonic-gate 		DEBUGOUT("Looking for Link\n");
15077c478bd9Sstevel@tonic-gate 		for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
15087c478bd9Sstevel@tonic-gate 			mdelay(10);
15097c478bd9Sstevel@tonic-gate 			status = E1000_READ_REG(hw, STATUS);
15107c478bd9Sstevel@tonic-gate 			if(status & E1000_STATUS_LU) break;
15117c478bd9Sstevel@tonic-gate 		}
15127c478bd9Sstevel@tonic-gate 		if(i == (LINK_UP_TIMEOUT / 10)) {
15137c478bd9Sstevel@tonic-gate 			DEBUGOUT("Never got a valid link from auto-neg!!!\n");
15147c478bd9Sstevel@tonic-gate 			hw->autoneg_failed = 1;
15157c478bd9Sstevel@tonic-gate 			/* AutoNeg failed to achieve a link, so we'll call
15167c478bd9Sstevel@tonic-gate 			 * e1000_check_for_link. This routine will force the link up if
15177c478bd9Sstevel@tonic-gate 			 * we detect a signal. This will allow us to communicate with
15187c478bd9Sstevel@tonic-gate 			 * non-autonegotiating link partners.
15197c478bd9Sstevel@tonic-gate 			 */
15207c478bd9Sstevel@tonic-gate 			if((ret_val = e1000_check_for_link(hw))) {
15217c478bd9Sstevel@tonic-gate 				DEBUGOUT("Error while checking for link\n");
15227c478bd9Sstevel@tonic-gate 				return ret_val;
15237c478bd9Sstevel@tonic-gate 			}
15247c478bd9Sstevel@tonic-gate 			hw->autoneg_failed = 0;
15257c478bd9Sstevel@tonic-gate 		} else {
15267c478bd9Sstevel@tonic-gate 			hw->autoneg_failed = 0;
15277c478bd9Sstevel@tonic-gate 			DEBUGOUT("Valid Link Found\n");
15287c478bd9Sstevel@tonic-gate 		}
15297c478bd9Sstevel@tonic-gate 	} else {
15307c478bd9Sstevel@tonic-gate 		DEBUGOUT("No Signal Detected\n");
15317c478bd9Sstevel@tonic-gate 	}
15327c478bd9Sstevel@tonic-gate 	return E1000_SUCCESS;
15337c478bd9Sstevel@tonic-gate }
15347c478bd9Sstevel@tonic-gate 
15357c478bd9Sstevel@tonic-gate /******************************************************************************
15367c478bd9Sstevel@tonic-gate * Detects which PHY is present and the speed and duplex
15377c478bd9Sstevel@tonic-gate *
15387c478bd9Sstevel@tonic-gate * hw - Struct containing variables accessed by shared code
15397c478bd9Sstevel@tonic-gate ******************************************************************************/
15407c478bd9Sstevel@tonic-gate static int
15417c478bd9Sstevel@tonic-gate e1000_setup_copper_link(struct e1000_hw *hw)
15427c478bd9Sstevel@tonic-gate {
15437c478bd9Sstevel@tonic-gate 	uint32_t ctrl;
15447c478bd9Sstevel@tonic-gate 	int32_t ret_val;
15457c478bd9Sstevel@tonic-gate 	uint16_t i;
15467c478bd9Sstevel@tonic-gate 	uint16_t phy_data;
15477c478bd9Sstevel@tonic-gate 
15487c478bd9Sstevel@tonic-gate 	DEBUGFUNC("e1000_setup_copper_link");
15497c478bd9Sstevel@tonic-gate 
15507c478bd9Sstevel@tonic-gate 	ctrl = E1000_READ_REG(hw, CTRL);
15517c478bd9Sstevel@tonic-gate 	/* With 82543, we need to force speed and duplex on the MAC equal to what
15527c478bd9Sstevel@tonic-gate 	 * the PHY speed and duplex configuration is. In addition, we need to
15537c478bd9Sstevel@tonic-gate 	 * perform a hardware reset on the PHY to take it out of reset.
15547c478bd9Sstevel@tonic-gate 	 */
15557c478bd9Sstevel@tonic-gate 	if(hw->mac_type > e1000_82543) {
15567c478bd9Sstevel@tonic-gate 		ctrl |= E1000_CTRL_SLU;
15577c478bd9Sstevel@tonic-gate 		ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
15587c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, CTRL, ctrl);
15597c478bd9Sstevel@tonic-gate 	} else {
15607c478bd9Sstevel@tonic-gate 		ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
15617c478bd9Sstevel@tonic-gate 		E1000_WRITE_REG(hw, CTRL, ctrl);
15627c478bd9Sstevel@tonic-gate 		e1000_phy_hw_reset(hw);
15637c478bd9Sstevel@tonic-gate 	}
15647c478bd9Sstevel@tonic-gate 
15657c478bd9Sstevel@tonic-gate 	/* Make sure we have a valid PHY */
15667c478bd9Sstevel@tonic-gate 	if((ret_val = e1000_detect_gig_phy(hw))) {
15677c478bd9Sstevel@tonic-gate 		DEBUGOUT("Error, did not detect valid phy.\n");
15687c478bd9Sstevel@tonic-gate 		return ret_val;
15697c478bd9Sstevel@tonic-gate 	}
15707c478bd9Sstevel@tonic-gate 	DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
15717c478bd9Sstevel@tonic-gate 
15727c478bd9Sstevel@tonic-gate 	if(hw->mac_type <= e1000_82543 ||
15737c478bd9Sstevel@tonic-gate 	   hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
15747c478bd9Sstevel@tonic-gate #if 0
15757c478bd9Sstevel@tonic-gate 	   hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
15767c478bd9Sstevel@tonic-gate 		hw->phy_reset_disable = FALSE;
15777c478bd9Sstevel@tonic-gate 
15787c478bd9Sstevel@tonic-gate 	if(!hw->phy_reset_disable) {
15797c478bd9Sstevel@tonic-gate #else
15807c478bd9Sstevel@tonic-gate 	   hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
15817c478bd9Sstevel@tonic-gate #endif
15827c478bd9Sstevel@tonic-gate 	if (hw->phy_type == e1000_phy_igp) {
15837c478bd9Sstevel@tonic-gate 
15847c478bd9Sstevel@tonic-gate 		if((ret_val = e1000_phy_reset(hw))) {
15857c478bd9Sstevel@tonic-gate 			DEBUGOUT("Error Resetting the PHY\n");
15867c478bd9Sstevel@tonic-gate 			return ret_val;
15877c478bd9Sstevel@tonic-gate 		}
15887c478bd9Sstevel@tonic-gate 
15897c478bd9Sstevel@tonic-gate 		/* Wait 10ms for MAC to configure PHY from eeprom settings */
15907c478bd9Sstevel@tonic-gate 		mdelay(15);
15917c478bd9Sstevel@tonic-gate 
15927c478bd9Sstevel@tonic-gate #if 0
15937c478bd9Sstevel@tonic-gate 		/* disable lplu d3 during driver init */
15947c478bd9Sstevel@tonic-gate 		if((ret_val = e1000_set_d3_lplu_state(hw, FALSE))) {
15957c478bd9Sstevel@tonic-gate 			DEBUGOUT("Error Disabling LPLU D3\n");
15967c478bd9Sstevel@tonic-gate 			return ret_val;
15977c478bd9Sstevel@tonic-gate 		}
15987c478bd9Sstevel@tonic-gate 
15997c478bd9Sstevel@tonic-gate 		/* Configure mdi-mdix settings */
16007c478bd9Sstevel@tonic-gate 		if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
16017c478bd9Sstevel@tonic-gate 		                                 &phy_data)))
16027c478bd9Sstevel@tonic-gate 			return ret_val;
16037c478bd9Sstevel@tonic-gate 
16047c478bd9Sstevel@tonic-gate 		if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
16057c478bd9Sstevel@tonic-gate 			hw->dsp_config_state = e1000_dsp_config_disabled;
16067c478bd9Sstevel@tonic-gate 			/* Force MDI for IGP B-0 PHY */
16077c478bd9Sstevel@tonic-gate 			phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
16087c478bd9Sstevel@tonic-gate 			              IGP01E1000_PSCR_FORCE_MDI_MDIX);
16097c478bd9Sstevel@tonic-gate 			hw->mdix = 1;
16107c478bd9Sstevel@tonic-gate 
16117c478bd9Sstevel@tonic-gate 		} else {
16127c478bd9Sstevel@tonic-gate 			hw->dsp_config_state = e1000_dsp_config_enabled;
16137c478bd9Sstevel@tonic-gate 			phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
16147c478bd9Sstevel@tonic-gate 
16157c478bd9Sstevel@tonic-gate 			switch (hw->mdix) {
16167c478bd9Sstevel@tonic-gate 			case 1:
16177c478bd9Sstevel@tonic-gate 				phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
16187c478bd9Sstevel@tonic-gate 				break;
16197c478bd9Sstevel@tonic-gate 			case 2:
16207c478bd9Sstevel@tonic-gate 				phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
16217c478bd9Sstevel@tonic-gate 				break;
16227c478bd9Sstevel@tonic-gate 			case 0:
16237c478bd9Sstevel@tonic-gate 			default:
16247c478bd9Sstevel@tonic-gate 				phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
16257c478bd9Sstevel@tonic-gate 				break;
16267c478bd9Sstevel@tonic-gate 			}
16277c478bd9Sstevel@tonic-gate 		}
16287c478bd9Sstevel@tonic-gate 		if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
16297c478bd9Sstevel@tonic-gate 		                                  phy_data)))
16307c478bd9Sstevel@tonic-gate 			return ret_val;
16317c478bd9Sstevel@tonic-gate 
16327c478bd9Sstevel@tonic-gate 		/* set auto-master slave resolution settings */
16337c478bd9Sstevel@tonic-gate 		e1000_ms_type phy_ms_setting = hw->master_slave;
16347c478bd9Sstevel@tonic-gate 
1635