1[
2  {
3    "EventCode": "0x00",
4    "UMask": "0x01",
5    "EventName": "INST_RETIRED.ANY",
6    "BriefDescription": "Instructions retired from execution.",
7    "PublicDescription": "Counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
8    "Counter": "Fixed counter 0",
9    "CounterHTOff": "Fixed counter 0",
10    "SampleAfterValue": "2000003",
11    "MSRIndex": "0",
12    "MSRValue": "0",
13    "TakenAlone": "0",
14    "CounterMask": "0",
15    "Invert": "0",
16    "AnyThread": "0",
17    "EdgeDetect": "0",
18    "PEBS": "0",
19    "Data_LA": "0",
20    "L1_Hit_Indication": "0",
21    "Errata": "0",
22    "Offcore": "0"
23  },
24  {
25    "EventCode": "0x00",
26    "UMask": "0x02",
27    "EventName": "CPU_CLK_UNHALTED.THREAD",
28    "BriefDescription": "Core cycles when the thread is not in halt state",
29    "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
30    "Counter": "Fixed counter 1",
31    "CounterHTOff": "Fixed counter 1",
32    "SampleAfterValue": "2000003",
33    "MSRIndex": "0",
34    "MSRValue": "0",
35    "TakenAlone": "0",
36    "CounterMask": "0",
37    "Invert": "0",
38    "AnyThread": "0",
39    "EdgeDetect": "0",
40    "PEBS": "0",
41    "Data_LA": "0",
42    "L1_Hit_Indication": "0",
43    "Errata": "0",
44    "Offcore": "0"
45  },
46  {
47    "EventCode": "0x00",
48    "UMask": "0x02",
49    "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
50    "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
51    "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
52    "Counter": "Fixed counter 1",
53    "CounterHTOff": "Fixed counter 1",
54    "SampleAfterValue": "2000003",
55    "MSRIndex": "0",
56    "MSRValue": "0",
57    "TakenAlone": "0",
58    "CounterMask": "0",
59    "Invert": "0",
60    "AnyThread": "1",
61    "EdgeDetect": "0",
62    "PEBS": "0",
63    "Data_LA": "0",
64    "L1_Hit_Indication": "0",
65    "Errata": "0",
66    "Offcore": "0"
67  },
68  {
69    "EventCode": "0x00",
70    "UMask": "0x03",
71    "EventName": "CPU_CLK_UNHALTED.REF_TSC",
72    "BriefDescription": "Reference cycles when the core is not in halt state.",
73    "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
74    "Counter": "Fixed counter 2",
75    "CounterHTOff": "Fixed counter 2",
76    "SampleAfterValue": "2000003",
77    "MSRIndex": "0",
78    "MSRValue": "0",
79    "TakenAlone": "0",
80    "CounterMask": "0",
81    "Invert": "0",
82    "AnyThread": "0",
83    "EdgeDetect": "0",
84    "PEBS": "0",
85    "Data_LA": "0",
86    "L1_Hit_Indication": "0",
87    "Errata": "0",
88    "Offcore": "0"
89  },
90  {
91    "EventCode": "0x03",
92    "UMask": "0x02",
93    "EventName": "LD_BLOCKS.STORE_FORWARD",
94    "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
95    "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
96    "Counter": "0,1,2,3",
97    "CounterHTOff": "0,1,2,3,4,5,6,7",
98    "SampleAfterValue": "100003",
99    "MSRIndex": "0",
100    "MSRValue": "0",
101    "TakenAlone": "0",
102    "CounterMask": "0",
103    "Invert": "0",
104    "AnyThread": "0",
105    "EdgeDetect": "0",
106    "PEBS": "0",
107    "Data_LA": "0",
108    "L1_Hit_Indication": "0",
109    "Errata": "0",
110    "Offcore": "0"
111  },
112  {
113    "EventCode": "0x03",
114    "UMask": "0x08",
115    "EventName": "LD_BLOCKS.NO_SR",
116    "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use",
117    "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
118    "Counter": "0,1,2,3",
119    "CounterHTOff": "0,1,2,3,4,5,6,7",
120    "SampleAfterValue": "100003",
121    "MSRIndex": "0",
122    "MSRValue": "0",
123    "TakenAlone": "0",
124    "CounterMask": "0",
125    "Invert": "0",
126    "AnyThread": "0",
127    "EdgeDetect": "0",
128    "PEBS": "0",
129    "Data_LA": "0",
130    "L1_Hit_Indication": "0",
131    "Errata": "0",
132    "Offcore": "0"
133  },
134  {
135    "EventCode": "0x07",
136    "UMask": "0x01",
137    "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
138    "BriefDescription": "False dependencies in MOB due to partial compare on address.",
139    "PublicDescription": "Counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.",
140    "Counter": "0,1,2,3",
141    "CounterHTOff": "0,1,2,3,4,5,6,7",
142    "SampleAfterValue": "100003",
143    "MSRIndex": "0",
144    "MSRValue": "0",
145    "TakenAlone": "0",
146    "CounterMask": "0",
147    "Invert": "0",
148    "AnyThread": "0",
149    "EdgeDetect": "0",
150    "PEBS": "0",
151    "Data_LA": "0",
152    "L1_Hit_Indication": "0",
153    "Errata": "0",
154    "Offcore": "0"
155  },
156  {
157    "EventCode": "0x08",
158    "UMask": "0x01",
159    "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
160    "BriefDescription": "Load misses in all DTLB levels that cause page walks",
161    "PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
162    "Counter": "0,1,2,3",
163    "CounterHTOff": "0,1,2,3,4,5,6,7",
164    "SampleAfterValue": "100003",
165    "MSRIndex": "0",
166    "MSRValue": "0",
167    "TakenAlone": "0",
168    "CounterMask": "0",
169    "Invert": "0",
170    "AnyThread": "0",
171    "EdgeDetect": "0",
172    "PEBS": "0",
173    "Data_LA": "0",
174    "L1_Hit_Indication": "0",
175    "Errata": "0",
176    "Offcore": "0"
177  },
178  {
179    "EventCode": "0x08",
180    "UMask": "0x02",
181    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
182    "BriefDescription": "Page walk completed due to a demand data load to a 4K page",
183    "PublicDescription": "Counts completed page walks  (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
184    "Counter": "0,1,2,3",
185    "CounterHTOff": "0,1,2,3,4,5,6,7",
186    "SampleAfterValue": "2000003",
187    "MSRIndex": "0",
188    "MSRValue": "0",
189    "TakenAlone": "0",
190    "CounterMask": "0",
191    "Invert": "0",
192    "AnyThread": "0",
193    "EdgeDetect": "0",
194    "PEBS": "0",
195    "Data_LA": "0",
196    "L1_Hit_Indication": "0",
197    "Errata": "0",
198    "Offcore": "0"
199  },
200  {
201    "EventCode": "0x08",
202    "UMask": "0x04",
203    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
204    "BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page",
205    "PublicDescription": "Counts completed page walks  (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
206    "Counter": "0,1,2,3",
207    "CounterHTOff": "0,1,2,3,4,5,6,7",
208    "SampleAfterValue": "2000003",
209    "MSRIndex": "0",
210    "MSRValue": "0",
211    "TakenAlone": "0",
212    "CounterMask": "0",
213    "Invert": "0",
214    "AnyThread": "0",
215    "EdgeDetect": "0",
216    "PEBS": "0",
217    "Data_LA": "0",
218    "L1_Hit_Indication": "0",
219    "Errata": "0",
220    "Offcore": "0"
221  },
222  {
223    "EventCode": "0x08",
224    "UMask": "0x08",
225    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
226    "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
227    "PublicDescription": "Counts completed page walks  (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
228    "Counter": "0,1,2,3",
229    "CounterHTOff": "0,1,2,3,4,5,6,7",
230    "SampleAfterValue": "2000003",
231    "MSRIndex": "0",
232    "MSRValue": "0",
233    "TakenAlone": "0",
234    "CounterMask": "0",
235    "Invert": "0",
236    "AnyThread": "0",
237    "EdgeDetect": "0",
238    "PEBS": "0",
239    "Data_LA": "0",
240    "L1_Hit_Indication": "0",
241    "Errata": "0",
242    "Offcore": "0"
243  },
244  {
245    "EventCode": "0x08",
246    "UMask": "0x0e",
247    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
248    "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
249    "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
250    "Counter": "0,1,2,3",
251    "CounterHTOff": "0,1,2,3,4,5,6,7",
252    "SampleAfterValue": "100003",
253    "MSRIndex": "0",
254    "MSRValue": "0",
255    "TakenAlone": "0",
256    "CounterMask": "0",
257    "Invert": "0",
258    "AnyThread": "0",
259    "EdgeDetect": "0",
260    "PEBS": "0",
261    "Data_LA": "0",
262    "L1_Hit_Indication": "0",
263    "Errata": "0",
264    "Offcore": "0"
265  },
266  {
267    "EventCode": "0x08",
268    "UMask": "0x10",
269    "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
270    "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
271    "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture.",
272    "Counter": "0,1,2,3",
273    "CounterHTOff": "0,1,2,3,4,5,6,7",
274    "SampleAfterValue": "2000003",
275    "MSRIndex": "0",
276    "MSRValue": "0",
277    "TakenAlone": "0",
278    "CounterMask": "0",
279    "Invert": "0",
280    "AnyThread": "0",
281    "EdgeDetect": "0",
282    "PEBS": "0",
283    "Data_LA": "0",
284    "L1_Hit_Indication": "0",
285    "Errata": "0",
286    "Offcore": "0"
287  },
288  {
289    "EventCode": "0x08",
290    "UMask": "0x10",
291    "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
292    "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
293    "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
294    "Counter": "0,1,2,3",
295    "CounterHTOff": "0,1,2,3,4,5,6,7",
296    "SampleAfterValue": "100003",
297    "MSRIndex": "0x00",
298    "MSRValue": "0x00",
299    "TakenAlone": "0",
300    "CounterMask": "1",
301    "Invert": "0",
302    "AnyThread": "0",
303    "EdgeDetect": "0",
304    "PEBS": "0",
305    "Data_LA": "0",
306    "L1_Hit_Indication": "0",
307    "Errata": "0",
308    "Offcore": "0"
309  },
310  {
311    "EventCode": "0x08",
312    "UMask": "0x20",
313    "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
314    "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
315    "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
316    "Counter": "0,1,2,3",
317    "CounterHTOff": "0,1,2,3,4,5,6,7",
318    "SampleAfterValue": "2000003",
319    "MSRIndex": "0",
320    "MSRValue": "0",
321    "TakenAlone": "0",
322    "CounterMask": "0",
323    "Invert": "0",
324    "AnyThread": "0",
325    "EdgeDetect": "0",
326    "PEBS": "0",
327    "Data_LA": "0",
328    "L1_Hit_Indication": "0",
329    "Errata": "0",
330    "Offcore": "0"
331  },
332  {
333    "EventCode": "0x09",
334    "UMask": "0x01",
335    "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
336    "BriefDescription": "tbd",
337    "PublicDescription": "tbd",
338    "Counter": "0,1,2,3",
339    "CounterHTOff": "0,1,2,3,4,5,6,7",
340    "SampleAfterValue": "2000003",
341    "MSRIndex": "0",
342    "MSRValue": "0",
343    "TakenAlone": "0",
344    "CounterMask": "0",
345    "Invert": "0",
346    "AnyThread": "0",
347    "EdgeDetect": "0",
348    "PEBS": "0",
349    "Data_LA": "0",
350    "L1_Hit_Indication": "0",
351    "Errata": "0",
352    "Offcore": "0"
353  },
354  {
355    "EventCode": "0x0D",
356    "UMask": "0x01",
357    "EventName": "INT_MISC.RECOVERY_CYCLES",
358    "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
359    "PublicDescription": "Core cycles the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
360    "Counter": "0,1,2,3",
361    "CounterHTOff": "0,1,2,3,4,5,6,7",
362    "SampleAfterValue": "2000003",
363    "MSRIndex": "0",
364    "MSRValue": "0",
365    "TakenAlone": "0",
366    "CounterMask": "0",
367    "Invert": "0",
368    "AnyThread": "0",
369    "EdgeDetect": "0",
370    "PEBS": "0",
371    "Data_LA": "0",
372    "L1_Hit_Indication": "0",
373    "Errata": "0",
374    "Offcore": "0"
375  },
376  {
377    "EventCode": "0x0D",
378    "UMask": "0x01",
379    "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
380    "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
381    "PublicDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
382    "Counter": "0,1,2,3",
383    "CounterHTOff": "0,1,2,3,4,5,6,7",
384    "SampleAfterValue": "2000003",
385    "MSRIndex": "0",
386    "MSRValue": "0",
387    "TakenAlone": "0",
388    "CounterMask": "0",
389    "Invert": "0",
390    "AnyThread": "1",
391    "EdgeDetect": "0",
392    "PEBS": "0",
393    "Data_LA": "0",
394    "L1_Hit_Indication": "0",
395    "Errata": "0",
396    "Offcore": "0"
397  },
398  {
399    "EventCode": "0x0D",
400    "UMask": "0x80",
401    "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
402    "BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events.",
403    "PublicDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events.",
404    "Counter": "0,1,2,3",
405    "CounterHTOff": "0,1,2,3,4,5,6,7",
406    "SampleAfterValue": "2000003",
407    "MSRIndex": "0",
408    "MSRValue": "0",
409    "TakenAlone": "0",
410    "CounterMask": "0",
411    "Invert": "0",
412    "AnyThread": "0",
413    "EdgeDetect": "0",
414    "PEBS": "0",
415    "Data_LA": "0",
416    "L1_Hit_Indication": "0",
417    "Errata": "0",
418    "Offcore": "0"
419  },
420  {
421    "EventCode": "0x0E",
422    "UMask": "0x01",
423    "EventName": "UOPS_ISSUED.ANY",
424    "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
425    "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
426    "Counter": "0,1,2,3",
427    "CounterHTOff": "0,1,2,3,4,5,6,7",
428    "SampleAfterValue": "2000003",
429    "MSRIndex": "0",
430    "MSRValue": "0",
431    "TakenAlone": "0",
432    "CounterMask": "0",
433    "Invert": "0",
434    "AnyThread": "0",
435    "EdgeDetect": "0",
436    "PEBS": "0",
437    "Data_LA": "0",
438    "L1_Hit_Indication": "0",
439    "Errata": "0",
440    "Offcore": "0"
441  },
442  {
443    "EventCode": "0x0E",
444    "UMask": "0x01",
445    "EventName": "UOPS_ISSUED.STALL_CYCLES",
446    "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
447    "PublicDescription": "Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.",
448    "Counter": "0,1,2,3",
449    "CounterHTOff": "0,1,2,3,4,5,6,7",
450    "SampleAfterValue": "2000003",
451    "MSRIndex": "0",
452    "MSRValue": "0",
453    "TakenAlone": "0",
454    "CounterMask": "1",
455    "Invert": "1",
456    "AnyThread": "0",
457    "EdgeDetect": "0",
458    "PEBS": "0",
459    "Data_LA": "0",
460    "L1_Hit_Indication": "0",
461    "Errata": "0",
462    "Offcore": "0"
463  },
464  {
465    "EventCode": "0x0E",
466    "UMask": "0x02",
467    "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH",
468    "BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.",
469    "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.",
470    "Counter": "0,1,2,3",
471    "CounterHTOff": "0,1,2,3,4,5,6,7",
472    "SampleAfterValue": "2000003",
473    "MSRIndex": "0x00",
474    "MSRValue": "0x00",
475    "TakenAlone": "0",
476    "CounterMask": "0",
477    "Invert": "0",
478    "AnyThread": "0",
479    "EdgeDetect": "0",
480    "PEBS": "0",
481    "Data_LA": "0",
482    "L1_Hit_Indication": "0",
483    "Errata": "0",
484    "Offcore": "0"
485  },
486  {
487    "EventCode": "0x0E",
488    "UMask": "0x20",
489    "EventName": "UOPS_ISSUED.SLOW_LEA",
490    "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
491    "PublicDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
492    "Counter": "0,1,2,3",
493    "CounterHTOff": "0,1,2,3,4,5,6,7",
494    "SampleAfterValue": "2000003",
495    "MSRIndex": "0",
496    "MSRValue": "0",
497    "TakenAlone": "0",
498    "CounterMask": "0",
499    "Invert": "0",
500    "AnyThread": "0",
501    "EdgeDetect": "0",
502    "PEBS": "0",
503    "Data_LA": "0",
504    "L1_Hit_Indication": "0",
505    "Errata": "0",
506    "Offcore": "0"
507  },
508  {
509    "EventCode": "0x14",
510    "UMask": "0x01",
511    "EventName": "ARITH.DIVIDER_ACTIVE",
512    "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
513    "PublicDescription": "Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
514    "Counter": "0,1,2,3",
515    "CounterHTOff": "0,1,2,3,4,5,6,7",
516    "SampleAfterValue": "2000003",
517    "MSRIndex": "0",
518    "MSRValue": "0",
519    "TakenAlone": "0",
520    "CounterMask": "1",
521    "Invert": "0",
522    "AnyThread": "0",
523    "EdgeDetect": "0",
524    "PEBS": "0",
525    "Data_LA": "0",
526    "L1_Hit_Indication": "0",
527    "Errata": "0",
528    "Offcore": "0"
529  },
530  {
531    "EventCode": "0x24",
532    "UMask": "0x21",
533    "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
534    "BriefDescription": "Demand Data Read miss L2, no rejects",
535    "PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
536    "Counter": "0,1,2,3",
537    "CounterHTOff": "0,1,2,3,4,5,6,7",
538    "SampleAfterValue": "200003",
539    "MSRIndex": "0",
540    "MSRValue": "0",
541    "TakenAlone": "0",
542    "CounterMask": "0",
543    "Invert": "0",
544    "AnyThread": "0",
545    "EdgeDetect": "0",
546    "PEBS": "0",
547    "Data_LA": "0",
548    "L1_Hit_Indication": "0",
549    "Errata": "0",
550    "Offcore": "0"
551  },
552  {
553    "EventCode": "0x24",
554    "UMask": "0x22",
555    "EventName": "L2_RQSTS.RFO_MISS",
556    "BriefDescription": "RFO requests that miss L2 cache",
557    "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
558    "Counter": "0,1,2,3",
559    "CounterHTOff": "0,1,2,3,4,5,6,7",
560    "SampleAfterValue": "200003",
561    "MSRIndex": "0",
562    "MSRValue": "0",
563    "TakenAlone": "0",
564    "CounterMask": "0",
565    "Invert": "0",
566    "AnyThread": "0",
567    "EdgeDetect": "0",
568    "PEBS": "0",
569    "Data_LA": "0",
570    "L1_Hit_Indication": "0",
571    "Errata": "0",
572    "Offcore": "0"
573  },
574  {
575    "EventCode": "0x24",
576    "UMask": "0x24",
577    "EventName": "L2_RQSTS.CODE_RD_MISS",
578    "BriefDescription": "L2 cache misses when fetching instructions",
579    "PublicDescription": "Counts L2 cache misses when fetching instructions.",
580    "Counter": "0,1,2,3",
581    "CounterHTOff": "0,1,2,3,4,5,6,7",
582    "SampleAfterValue": "200003",
583    "MSRIndex": "0",
584    "MSRValue": "0",
585    "TakenAlone": "0",
586    "CounterMask": "0",
587    "Invert": "0",
588    "AnyThread": "0",
589    "EdgeDetect": "0",
590    "PEBS": "0",
591    "Data_LA": "0",
592    "L1_Hit_Indication": "0",
593    "Errata": "0",
594    "Offcore": "0"
595  },
596  {
597    "EventCode": "0x24",
598    "UMask": "0x27",
599    "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
600    "BriefDescription": "Demand requests that miss L2 cache",
601    "PublicDescription": "Demand requests that miss L2 cache.",
602    "Counter": "0,1,2,3",
603    "CounterHTOff": "0,1,2,3,4,5,6,7",
604    "SampleAfterValue": "200003",
605    "MSRIndex": "0",
606    "MSRValue": "0",
607    "TakenAlone": "0",
608    "CounterMask": "0",
609    "Invert": "0",
610    "AnyThread": "0",
611    "EdgeDetect": "0",
612    "PEBS": "0",
613    "Data_LA": "0",
614    "L1_Hit_Indication": "0",
615    "Errata": "0",
616    "Offcore": "0"
617  },
618  {
619    "EventCode": "0x24",
620    "UMask": "0x38",
621    "EventName": "L2_RQSTS.PF_MISS",
622    "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache",
623    "PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache.",
624    "Counter": "0,1,2,3",
625    "CounterHTOff": "0,1,2,3,4,5,6,7",
626    "SampleAfterValue": "200003",
627    "MSRIndex": "0",
628    "MSRValue": "0",
629    "TakenAlone": "0",
630    "CounterMask": "0",
631    "Invert": "0",
632    "AnyThread": "0",
633    "EdgeDetect": "0",
634    "PEBS": "0",
635    "Data_LA": "0",
636    "L1_Hit_Indication": "0",
637    "Errata": "0",
638    "Offcore": "0"
639  },
640  {
641    "EventCode": "0x24",
642    "UMask": "0x3F",
643    "EventName": "L2_RQSTS.MISS",
644    "BriefDescription": "All requests that miss L2 cache",
645    "PublicDescription": "All requests that miss L2 cache.",
646    "Counter": "0,1,2,3",
647    "CounterHTOff": "0,1,2,3,4,5,6,7",
648    "SampleAfterValue": "200003",
649    "MSRIndex": "0",
650    "MSRValue": "0",
651    "TakenAlone": "0",
652    "CounterMask": "0",
653    "Invert": "0",
654    "AnyThread": "0",
655    "EdgeDetect": "0",
656    "PEBS": "0",
657    "Data_LA": "0",
658    "L1_Hit_Indication": "0",
659    "Errata": "0",
660    "Offcore": "0"
661  },
662  {
663    "EventCode": "0x24",
664    "UMask": "0xc1",
665    "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
666    "BriefDescription": "Demand Data Read requests that hit L2 cache",
667    "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache",
668    "Counter": "0,1,2,3",
669    "CounterHTOff": "0,1,2,3,4,5,6,7",
670    "SampleAfterValue": "200003",
671    "MSRIndex": "0",
672    "MSRValue": "0",
673    "TakenAlone": "0",
674    "CounterMask": "0",
675    "Invert": "0",
676    "AnyThread": "0",
677    "EdgeDetect": "0",
678    "PEBS": "0",
679    "Data_LA": "0",
680    "L1_Hit_Indication": "0",
681    "Errata": "0",
682    "Offcore": "0"
683  },
684  {
685    "EventCode": "0x24",
686    "UMask": "0xc2",
687    "EventName": "L2_RQSTS.RFO_HIT",
688    "BriefDescription": "RFO requests that hit L2 cache",
689    "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
690    "Counter": "0,1,2,3",
691    "CounterHTOff": "0,1,2,3,4,5,6,7",
692    "SampleAfterValue": "200003",
693    "MSRIndex": "0",
694    "MSRValue": "0",
695    "TakenAlone": "0",
696    "CounterMask": "0",
697    "Invert": "0",
698    "AnyThread": "0",
699    "EdgeDetect": "0",
700    "PEBS": "0",
701    "Data_LA": "0",
702    "L1_Hit_Indication": "0",
703    "Errata": "0",
704    "Offcore": "0"
705  },
706  {
707    "EventCode": "0x24",
708    "UMask": "0xc4",
709    "EventName": "L2_RQSTS.CODE_RD_HIT",
710    "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
711    "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
712    "Counter": "0,1,2,3",
713    "CounterHTOff": "0,1,2,3,4,5,6,7",
714    "SampleAfterValue": "200003",
715    "MSRIndex": "0",
716    "MSRValue": "0",
717    "TakenAlone": "0",
718    "CounterMask": "0",
719    "Invert": "0",
720    "AnyThread": "0",
721    "EdgeDetect": "0",
722    "PEBS": "0",
723    "Data_LA": "0",
724    "L1_Hit_Indication": "0",
725    "Errata": "0",
726    "Offcore": "0"
727  },
728  {
729    "EventCode": "0x24",
730    "UMask": "0xd8",
731    "EventName": "L2_RQSTS.PF_HIT",
732    "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache",
733    "PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache.",
734    "Counter": "0,1,2,3",
735    "CounterHTOff": "0,1,2,3,4,5,6,7",
736    "SampleAfterValue": "200003",
737    "MSRIndex": "0",
738    "MSRValue": "0",
739    "TakenAlone": "0",
740    "CounterMask": "0",
741    "Invert": "0",
742    "AnyThread": "0",
743    "EdgeDetect": "0",
744    "PEBS": "0",
745    "Data_LA": "0",
746    "L1_Hit_Indication": "0",
747    "Errata": "0",
748    "Offcore": "0"
749  },
750  {
751    "EventCode": "0x24",
752    "UMask": "0xE1",
753    "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
754    "BriefDescription": "Demand Data Read requests",
755    "PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
756    "Counter": "0,1,2,3",
757    "CounterHTOff": "0,1,2,3,4,5,6,7",
758    "SampleAfterValue": "200003",
759    "MSRIndex": "0",
760    "MSRValue": "0",
761    "TakenAlone": "0",
762    "CounterMask": "0",
763    "Invert": "0",
764    "AnyThread": "0",
765    "EdgeDetect": "0",
766    "PEBS": "0",
767    "Data_LA": "0",
768    "L1_Hit_Indication": "0",
769    "Errata": "0",
770    "Offcore": "0"
771  },
772  {
773    "EventCode": "0x24",
774    "UMask": "0xE2",
775    "EventName": "L2_RQSTS.ALL_RFO",
776    "BriefDescription": "RFO requests to L2 cache",
777    "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
778    "Counter": "0,1,2,3",
779    "CounterHTOff": "0,1,2,3,4,5,6,7",
780    "SampleAfterValue": "200003",
781    "MSRIndex": "0",
782    "MSRValue": "0",
783    "TakenAlone": "0",
784    "CounterMask": "0",
785    "Invert": "0",
786    "AnyThread": "0",
787    "EdgeDetect": "0",
788    "PEBS": "0",
789    "Data_LA": "0",
790    "L1_Hit_Indication": "0",
791    "Errata": "0",
792    "Offcore": "0"
793  },
794  {
795    "EventCode": "0x24",
796    "UMask": "0xE4",
797    "EventName": "L2_RQSTS.ALL_CODE_RD",
798    "BriefDescription": "L2 code requests",
799    "PublicDescription": "Counts the total number of L2 code requests.",
800    "Counter": "0,1,2,3",
801    "CounterHTOff": "0,1,2,3,4,5,6,7",
802    "SampleAfterValue": "200003",
803    "MSRIndex": "0",
804    "MSRValue": "0",
805    "TakenAlone": "0",
806    "CounterMask": "0",
807    "Invert": "0",
808    "AnyThread": "0",
809    "EdgeDetect": "0",
810    "PEBS": "0",
811    "Data_LA": "0",
812    "L1_Hit_Indication": "0",
813    "Errata": "0",
814    "Offcore": "0"
815  },
816  {
817    "EventCode": "0x24",
818    "UMask": "0xe7",
819    "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
820    "BriefDescription": "Demand requests to L2 cache",
821    "PublicDescription": "Demand requests to L2 cache.",
822    "Counter": "0,1,2,3",
823    "CounterHTOff": "0,1,2,3,4,5,6,7",
824    "SampleAfterValue": "200003",
825    "MSRIndex": "0",
826    "MSRValue": "0",
827    "TakenAlone": "0",
828    "CounterMask": "0",
829    "Invert": "0",
830    "AnyThread": "0",
831    "EdgeDetect": "0",
832    "PEBS": "0",
833    "Data_LA": "0",
834    "L1_Hit_Indication": "0",
835    "Errata": "0",
836    "Offcore": "0"
837  },
838  {
839    "EventCode": "0x24",
840    "UMask": "0xF8",
841    "EventName": "L2_RQSTS.ALL_PF",
842    "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches",
843    "PublicDescription": "Counts the total number of requests from the L2 hardware prefetchers.",
844    "Counter": "0,1,2,3",
845    "CounterHTOff": "0,1,2,3,4,5,6,7",
846    "SampleAfterValue": "200003",
847    "MSRIndex": "0",
848    "MSRValue": "0",
849    "TakenAlone": "0",
850    "CounterMask": "0",
851    "Invert": "0",
852    "AnyThread": "0",
853    "EdgeDetect": "0",
854    "PEBS": "0",
855    "Data_LA": "0",
856    "L1_Hit_Indication": "0",
857    "Errata": "0",
858    "Offcore": "0"
859  },
860  {
861    "EventCode": "0x24",
862    "UMask": "0xFF",
863    "EventName": "L2_RQSTS.REFERENCES",
864    "BriefDescription": "All L2 requests",
865    "PublicDescription": "All L2 requests.",
866    "Counter": "0,1,2,3",
867    "CounterHTOff": "0,1,2,3,4,5,6,7",
868    "SampleAfterValue": "200003",
869    "MSRIndex": "0",
870    "MSRValue": "0",
871    "TakenAlone": "0",
872    "CounterMask": "0",
873    "Invert": "0",
874    "AnyThread": "0",
875    "EdgeDetect": "0",
876    "PEBS": "0",
877    "Data_LA": "0",
878    "L1_Hit_Indication": "0",
879    "Errata": "0",
880    "Offcore": "0"
881  },
882  {
883    "EventCode": "0x2E",
884    "UMask": "0x41",
885    "EventName": "LONGEST_LAT_CACHE.MISS",
886    "BriefDescription": "Core-originated cacheable demand requests missed L3",
887    "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all misses to the L3.",
888    "Counter": "0,1,2,3",
889    "CounterHTOff": "0,1,2,3,4,5,6,7",
890    "SampleAfterValue": "100003",
891    "MSRIndex": "0",
892    "MSRValue": "0",
893    "TakenAlone": "0",
894    "CounterMask": "0",
895    "Invert": "0",
896    "AnyThread": "0",
897    "EdgeDetect": "0",
898    "PEBS": "0",
899    "Data_LA": "0",
900    "L1_Hit_Indication": "0",
901    "Errata": "SKL057",
902    "Offcore": "0"
903  },
904  {
905    "EventCode": "0x2E",
906    "UMask": "0x4F",
907    "EventName": "LONGEST_LAT_CACHE.REFERENCE",
908    "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
909    "PublicDescription": "Counts core-originated cacheable requests to the  L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2.  It does not include all accesses to the L3.",
910    "Counter": "0,1,2,3",
911    "CounterHTOff": "0,1,2,3,4,5,6,7",
912    "SampleAfterValue": "100003",
913    "MSRIndex": "0",
914    "MSRValue": "0",
915    "TakenAlone": "0",
916    "CounterMask": "0",
917    "Invert": "0",
918    "AnyThread": "0",
919    "EdgeDetect": "0",
920    "PEBS": "0",
921    "Data_LA": "0",
922    "L1_Hit_Indication": "0",
923    "Errata": "SKL057",
924    "Offcore": "0"
925  },
926  {
927    "EventCode": "0x32",
928    "UMask": "0x01",
929    "EventName": "SW_PREFETCH_ACCESS.NTA",
930    "BriefDescription": "Number of PREFETCHNTA instructions executed.",
931    "PublicDescription": "Number of PREFETCHNTA instructions executed.",
932    "Counter": "0,1,2,3",
933    "CounterHTOff": "0,1,2,3,4,5,6,7",
934    "SampleAfterValue": "2000003",
935    "MSRIndex": "0",
936    "MSRValue": "0",
937    "TakenAlone": "0",
938    "CounterMask": "0",
939    "Invert": "0",
940    "AnyThread": "0",
941    "EdgeDetect": "0",
942    "PEBS": "0",
943    "Data_LA": "0",
944    "L1_Hit_Indication": "0",
945    "Errata": "0",
946    "Offcore": "0"
947  },
948  {
949    "EventCode": "0x32",
950    "UMask": "0x02",
951    "EventName": "SW_PREFETCH_ACCESS.T0",
952    "BriefDescription": "Number of PREFETCHT0 instructions executed.",
953    "PublicDescription": "Number of PREFETCHT0 instructions executed.",
954    "Counter": "0,1,2,3",
955    "CounterHTOff": "0,1,2,3,4,5,6,7",
956    "SampleAfterValue": "2000003",
957    "MSRIndex": "0",
958    "MSRValue": "0",
959    "TakenAlone": "0",
960    "CounterMask": "0",
961    "Invert": "0",
962    "AnyThread": "0",
963    "EdgeDetect": "0",
964    "PEBS": "0",
965    "Data_LA": "0",
966    "L1_Hit_Indication": "0",
967    "Errata": "0",
968    "Offcore": "0"
969  },
970  {
971    "EventCode": "0x32",
972    "UMask": "0x04",
973    "EventName": "SW_PREFETCH_ACCESS.T1_T2",
974    "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
975    "PublicDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
976    "Counter": "0,1,2,3",
977    "CounterHTOff": "0,1,2,3,4,5,6,7",
978    "SampleAfterValue": "2000003",
979    "MSRIndex": "0",
980    "MSRValue": "0",
981    "TakenAlone": "0",
982    "CounterMask": "0",
983    "Invert": "0",
984    "AnyThread": "0",
985    "EdgeDetect": "0",
986    "PEBS": "0",
987    "Data_LA": "0",
988    "L1_Hit_Indication": "0",
989    "Errata": "0",
990    "Offcore": "0"
991  },
992  {
993    "EventCode": "0x32",
994    "UMask": "0x08",
995    "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
996    "BriefDescription": "Number of PREFETCHW instructions executed.",
997    "PublicDescription": "Number of PREFETCHW instructions executed.",
998    "Counter": "0,1,2,3",
999    "CounterHTOff": "0,1,2,3,4,5,6,7",
1000    "SampleAfterValue": "2000003",
1001    "MSRIndex": "0",
1002    "MSRValue": "0",
1003    "TakenAlone": "0",
1004    "CounterMask": "0",
1005    "Invert": "0",
1006    "AnyThread": "0",
1007    "EdgeDetect": "0",
1008    "PEBS": "0",
1009    "Data_LA": "0",
1010    "L1_Hit_Indication": "0",
1011    "Errata": "0",
1012    "Offcore": "0"
1013  },
1014  {
1015    "EventCode": "0x3C",
1016    "UMask": "0x00",
1017    "EventName": "CPU_CLK_UNHALTED.THREAD_P",
1018    "BriefDescription": "Thread cycles when thread is not in halt state",
1019    "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
1020    "Counter": "0,1,2,3",
1021    "CounterHTOff": "0,1,2,3,4,5,6,7",
1022    "SampleAfterValue": "2000003",
1023    "MSRIndex": "0",
1024    "MSRValue": "0",
1025    "TakenAlone": "0",
1026    "CounterMask": "0",
1027    "Invert": "0",
1028    "AnyThread": "0",
1029    "EdgeDetect": "0",
1030    "PEBS": "0",
1031    "Data_LA": "0",
1032    "L1_Hit_Indication": "0",
1033    "Errata": "0",
1034    "Offcore": "0"
1035  },
1036  {
1037    "EventCode": "0x3C",
1038    "UMask": "0x00",
1039    "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
1040    "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
1041    "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
1042    "Counter": "0,1,2,3",
1043    "CounterHTOff": "0,1,2,3,4,5,6,7",
1044    "SampleAfterValue": "2000003",
1045    "MSRIndex": "0",
1046    "MSRValue": "0",
1047    "TakenAlone": "0",
1048    "CounterMask": "0",
1049    "Invert": "0",
1050    "AnyThread": "1",
1051    "EdgeDetect": "0",
1052    "PEBS": "0",
1053    "Data_LA": "0",
1054    "L1_Hit_Indication": "0",
1055    "Errata": "0",
1056    "Offcore": "0"
1057  },
1058  {
1059    "EventCode": "0x3C",
1060    "UMask": "0x00",
1061    "EventName": "CPU_CLK_UNHALTED.RING0_TRANS",
1062    "BriefDescription": "Counts when there is a transition from ring 1, 2 or 3 to ring 0.",
1063    "PublicDescription": "Counts when the Current Privilege Level (CPL) transitions from ring 1, 2 or 3 to ring 0 (Kernel).",
1064    "Counter": "0,1,2,3",
1065    "CounterHTOff": "0,1,2,3,4,5,6,7",
1066    "SampleAfterValue": "100007",
1067    "MSRIndex": "0",
1068    "MSRValue": "0",
1069    "TakenAlone": "0",
1070    "CounterMask": "1",
1071    "Invert": "0",
1072    "AnyThread": "0",
1073    "EdgeDetect": "1",
1074    "PEBS": "0",
1075    "Data_LA": "0",
1076    "L1_Hit_Indication": "0",
1077    "Errata": "0",
1078    "Offcore": "0"
1079  },
1080  {
1081    "EventCode": "0x3C",
1082    "UMask": "0x01",
1083    "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
1084    "BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
1085    "PublicDescription": "Core crystal clock cycles when the thread is unhalted.",
1086    "Counter": "0,1,2,3",
1087    "CounterHTOff": "0,1,2,3,4,5,6,7",
1088    "SampleAfterValue": "25003",
1089    "MSRIndex": "0",
1090    "MSRValue": "0",
1091    "TakenAlone": "0",
1092    "CounterMask": "0",
1093    "Invert": "0",
1094    "AnyThread": "0",
1095    "EdgeDetect": "0",
1096    "PEBS": "0",
1097    "Data_LA": "0",
1098    "L1_Hit_Indication": "0",
1099    "Errata": "0",
1100    "Offcore": "0"
1101  },
1102  {
1103    "EventCode": "0x3C",
1104    "UMask": "0x01",
1105    "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
1106    "BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
1107    "PublicDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
1108    "Counter": "0,1,2,3",
1109    "CounterHTOff": "0,1,2,3,4,5,6,7",
1110    "SampleAfterValue": "25003",
1111    "MSRIndex": "0",
1112    "MSRValue": "0",
1113    "TakenAlone": "0",
1114    "CounterMask": "0",
1115    "Invert": "0",
1116    "AnyThread": "1",
1117    "EdgeDetect": "0",
1118    "PEBS": "0",
1119    "Data_LA": "0",
1120    "L1_Hit_Indication": "0",
1121    "Errata": "0",
1122    "Offcore": "0"
1123  },
1124  {
1125    "EventCode": "0x3C",
1126    "UMask": "0x01",
1127    "EventName": "CPU_CLK_UNHALTED.REF_XCLK",
1128    "BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
1129    "PublicDescription": "Core crystal clock cycles when the thread is unhalted.",
1130    "Counter": "0,1,2,3",
1131    "CounterHTOff": "0,1,2,3,4,5,6,7",
1132    "SampleAfterValue": "25003",
1133    "MSRIndex": "0",
1134    "MSRValue": "0",
1135    "TakenAlone": "0",
1136    "CounterMask": "0",
1137    "Invert": "0",
1138    "AnyThread": "0",
1139    "EdgeDetect": "0",
1140    "PEBS": "0",
1141    "Data_LA": "0",
1142    "L1_Hit_Indication": "0",
1143    "Errata": "0",
1144    "Offcore": "0"
1145  },
1146  {
1147    "EventCode": "0x3C",
1148    "UMask": "0x01",
1149    "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
1150    "BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
1151    "PublicDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
1152    "Counter": "0,1,2,3",
1153    "CounterHTOff": "0,1,2,3,4,5,6,7",
1154    "SampleAfterValue": "25003",
1155    "MSRIndex": "0",
1156    "MSRValue": "0",
1157    "TakenAlone": "0",
1158    "CounterMask": "0",
1159    "Invert": "0",
1160    "AnyThread": "1",
1161    "EdgeDetect": "0",
1162    "PEBS": "0",
1163    "Data_LA": "0",
1164    "L1_Hit_Indication": "0",
1165    "Errata": "0",
1166    "Offcore": "0"
1167  },
1168  {
1169    "EventCode": "0x3C",
1170    "UMask": "0x02",
1171    "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
1172    "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
1173    "PublicDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
1174    "Counter": "0,1,2,3",
1175    "CounterHTOff": "0,1,2,3,4,5,6,7",
1176    "SampleAfterValue": "25003",
1177    "MSRIndex": "0",
1178    "MSRValue": "0",
1179    "TakenAlone": "0",
1180    "CounterMask": "0",
1181    "Invert": "0",
1182    "AnyThread": "0",
1183    "EdgeDetect": "0",
1184    "PEBS": "0",
1185    "Data_LA": "0",
1186    "L1_Hit_Indication": "0",
1187    "Errata": "0",
1188    "Offcore": "0"
1189  },
1190  {
1191    "EventCode": "0x3C",
1192    "UMask": "0x02",
1193    "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
1194    "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
1195    "PublicDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
1196    "Counter": "0,1,2,3",
1197    "CounterHTOff": "0,1,2,3,4,5,6,7",
1198    "SampleAfterValue": "25003",
1199    "MSRIndex": "0x00",
1200    "MSRValue": "0x00",
1201    "TakenAlone": "0",
1202    "CounterMask": "0",
1203    "Invert": "0",
1204    "AnyThread": "0",
1205    "EdgeDetect": "0",
1206    "PEBS": "0",
1207    "Data_LA": "0",
1208    "L1_Hit_Indication": "0",
1209    "Errata": "0",
1210    "Offcore": "0"
1211  },
1212  {
1213    "EventCode": "0x48",
1214    "UMask": "0x01",
1215    "EventName": "L1D_PEND_MISS.PENDING",
1216    "BriefDescription": "L1D miss outstandings duration in cycles",
1217    "PublicDescription": "Counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch.Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
1218    "Counter": "0,1,2,3",
1219    "CounterHTOff": "0,1,2,3,4,5,6,7",
1220    "SampleAfterValue": "2000003",
1221    "MSRIndex": "0",
1222    "MSRValue": "0",
1223    "TakenAlone": "0",
1224    "CounterMask": "0",
1225    "Invert": "0",
1226    "AnyThread": "0",
1227    "EdgeDetect": "0",
1228    "PEBS": "0",
1229    "Data_LA": "0",
1230    "L1_Hit_Indication": "0",
1231    "Errata": "0",
1232    "Offcore": "0"
1233  },
1234  {
1235    "EventCode": "0x48",
1236    "UMask": "0x01",
1237    "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
1238    "BriefDescription": "Cycles with L1D load Misses outstanding.",
1239    "PublicDescription": "Counts duration of L1D miss outstanding in cycles.",
1240    "Counter": "0,1,2,3",
1241    "CounterHTOff": "0,1,2,3,4,5,6,7",
1242    "SampleAfterValue": "2000003",
1243    "MSRIndex": "0",
1244    "MSRValue": "0",
1245    "TakenAlone": "0",
1246    "CounterMask": "1",
1247    "Invert": "0",
1248    "AnyThread": "0",
1249    "EdgeDetect": "0",
1250    "PEBS": "0",
1251    "Data_LA": "0",
1252    "L1_Hit_Indication": "0",
1253    "Errata": "0",
1254    "Offcore": "0"
1255  },
1256  {
1257    "EventCode": "0x48",
1258    "UMask": "0x01",
1259    "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
1260    "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
1261    "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
1262    "Counter": "0,1,2,3",
1263    "CounterHTOff": "0,1,2,3,4,5,6,7",
1264    "SampleAfterValue": "2000003",
1265    "MSRIndex": "0x00",
1266    "MSRValue": "0x00",
1267    "TakenAlone": "0",
1268    "CounterMask": "1",
1269    "Invert": "0",
1270    "AnyThread": "1",
1271    "EdgeDetect": "0",
1272    "PEBS": "0",
1273    "Data_LA": "0",
1274    "L1_Hit_Indication": "0",
1275    "Errata": "0",
1276    "Offcore": "0"
1277  },
1278  {
1279    "EventCode": "0x48",
1280    "UMask": "0x02",
1281    "EventName": "L1D_PEND_MISS.FB_FULL",
1282    "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch.",
1283    "PublicDescription": "Number of times a request needed a FB (Fill Buffer) entry but there was no entry available for it. A request includes cacheable/uncacheable demands that are load, store or SW prefetch instructions.",
1284    "Counter": "0,1,2,3",
1285    "CounterHTOff": "0,1,2,3,4,5,6,7",
1286    "SampleAfterValue": "2000003",
1287    "MSRIndex": "0",
1288    "MSRValue": "0",
1289    "TakenAlone": "0",
1290    "CounterMask": "0",
1291    "Invert": "0",
1292    "AnyThread": "0",
1293    "EdgeDetect": "0",
1294    "PEBS": "0",
1295    "Data_LA": "0",
1296    "L1_Hit_Indication": "0",
1297    "Errata": "0",
1298    "Offcore": "0"
1299  },
1300  {
1301    "EventCode": "0x49",
1302    "UMask": "0x01",
1303    "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
1304    "BriefDescription": "Store misses in all DTLB levels that cause page walks",
1305    "PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
1306    "Counter": "0,1,2,3",
1307    "CounterHTOff": "0,1,2,3,4,5,6,7",
1308    "SampleAfterValue": "100003",
1309    "MSRIndex": "0",
1310    "MSRValue": "0",
1311    "TakenAlone": "0",
1312    "CounterMask": "0",
1313    "Invert": "0",
1314    "AnyThread": "0",
1315    "EdgeDetect": "0",
1316    "PEBS": "0",
1317    "Data_LA": "0",
1318    "L1_Hit_Indication": "0",
1319    "Errata": "0",
1320    "Offcore": "0"
1321  },
1322  {
1323    "EventCode": "0x49",
1324    "UMask": "0x02",
1325    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
1326    "BriefDescription": "Page walk completed due to a demand data store to a 4K page",
1327    "PublicDescription": "Counts completed page walks  (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
1328    "Counter": "0,1,2,3",
1329    "CounterHTOff": "0,1,2,3,4,5,6,7",
1330    "SampleAfterValue": "100003",
1331    "MSRIndex": "0",
1332    "MSRValue": "0",
1333    "TakenAlone": "0",
1334    "CounterMask": "0",
1335    "Invert": "0",
1336    "AnyThread": "0",
1337    "EdgeDetect": "0",
1338    "PEBS": "0",
1339    "Data_LA": "0",
1340    "L1_Hit_Indication": "0",
1341    "Errata": "0",
1342    "Offcore": "0"
1343  },
1344  {
1345    "EventCode": "0x49",
1346    "UMask": "0x04",
1347    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
1348    "BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page",
1349    "PublicDescription": "Counts completed page walks  (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
1350    "Counter": "0,1,2,3",
1351    "CounterHTOff": "0,1,2,3,4,5,6,7",
1352    "SampleAfterValue": "100003",
1353    "MSRIndex": "0",
1354    "MSRValue": "0",
1355    "TakenAlone": "0",
1356    "CounterMask": "0",
1357    "Invert": "0",
1358    "AnyThread": "0",
1359    "EdgeDetect": "0",
1360    "PEBS": "0",
1361    "Data_LA": "0",
1362    "L1_Hit_Indication": "0",
1363    "Errata": "0",
1364    "Offcore": "0"
1365  },
1366  {
1367    "EventCode": "0x49",
1368    "UMask": "0x08",
1369    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
1370    "BriefDescription": "Page walk completed due to a demand data store to a 1G page",
1371    "PublicDescription": "Counts completed page walks  (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
1372    "Counter": "0,1,2,3",
1373    "CounterHTOff": "0,1,2,3,4,5,6,7",
1374    "SampleAfterValue": "100003",
1375    "MSRIndex": "0",
1376    "MSRValue": "0",
1377    "TakenAlone": "0",
1378    "CounterMask": "0",
1379    "Invert": "0",
1380    "AnyThread": "0",
1381    "EdgeDetect": "0",
1382    "PEBS": "0",
1383    "Data_LA": "0",
1384    "L1_Hit_Indication": "0",
1385    "Errata": "0",
1386    "Offcore": "0"
1387  },
1388  {
1389    "EventCode": "0x49",
1390    "UMask": "0x0e",
1391    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
1392    "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
1393    "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
1394    "Counter": "0,1,2,3",
1395    "CounterHTOff": "0,1,2,3,4,5,6,7",
1396    "SampleAfterValue": "100003",
1397    "MSRIndex": "0",
1398    "MSRValue": "0",
1399    "TakenAlone": "0",
1400    "CounterMask": "0",
1401    "Invert": "0",
1402    "AnyThread": "0",
1403    "EdgeDetect": "0",
1404    "PEBS": "0",
1405    "Data_LA": "0",
1406    "L1_Hit_Indication": "0",
1407    "Errata": "0",
1408    "Offcore": "0"
1409  },
1410  {
1411    "EventCode": "0x49",
1412    "UMask": "0x10",
1413    "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
1414    "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
1415    "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture.",
1416    "Counter": "0,1,2,3",
1417    "CounterHTOff": "0,1,2,3,4,5,6,7",
1418    "SampleAfterValue": "2000003",
1419    "MSRIndex": "0",
1420    "MSRValue": "0",
1421    "TakenAlone": "0",
1422    "CounterMask": "0",
1423    "Invert": "0",
1424    "AnyThread": "0",
1425    "EdgeDetect": "0",
1426    "PEBS": "0",
1427    "Data_LA": "0",
1428    "L1_Hit_Indication": "0",
1429    "Errata": "0",
1430    "Offcore": "0"
1431  },
1432  {
1433    "EventCode": "0x49",
1434    "UMask": "0x10",
1435    "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
1436    "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
1437    "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.",
1438    "Counter": "0,1,2,3",
1439    "CounterHTOff": "0,1,2,3,4,5,6,7",
1440    "SampleAfterValue": "100003",
1441    "MSRIndex": "0x00",
1442    "MSRValue": "0x00",
1443    "TakenAlone": "0",
1444    "CounterMask": "1",
1445    "Invert": "0",
1446    "AnyThread": "0",
1447    "EdgeDetect": "0",
1448    "PEBS": "0",
1449    "Data_LA": "0",
1450    "L1_Hit_Indication": "0",
1451    "Errata": "0",
1452    "Offcore": "0"
1453  },
1454  {
1455    "EventCode": "0x49",
1456    "UMask": "0x20",
1457    "EventName": "DTLB_STORE_MISSES.STLB_HIT",
1458    "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
1459    "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
1460    "Counter": "0,1,2,3",
1461    "CounterHTOff": "0,1,2,3,4,5,6,7",
1462    "SampleAfterValue": "100003",
1463    "MSRIndex": "0",
1464    "MSRValue": "0",
1465    "TakenAlone": "0",
1466    "CounterMask": "0",
1467    "Invert": "0",
1468    "AnyThread": "0",
1469    "EdgeDetect": "0",
1470    "PEBS": "0",
1471    "Data_LA": "0",
1472    "L1_Hit_Indication": "0",
1473    "Errata": "0",
1474    "Offcore": "0"
1475  },
1476  {
1477    "EventCode": "0x4C",
1478    "UMask": "0x01",
1479    "EventName": "LOAD_HIT_PRE.SW_PF",
1480    "BriefDescription": "Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
1481    "PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
1482    "Counter": "0,1,2,3",
1483    "CounterHTOff": "0,1,2,3,4,5,6,7",
1484    "SampleAfterValue": "100003",
1485    "MSRIndex": "0",
1486    "MSRValue": "0",
1487    "TakenAlone": "0",
1488    "CounterMask": "0",
1489    "Invert": "0",
1490    "AnyThread": "0",
1491    "EdgeDetect": "0",
1492    "PEBS": "0",
1493    "Data_LA": "0",
1494    "L1_Hit_Indication": "0",
1495    "Errata": "0",
1496    "Offcore": "0"
1497  },
1498  {
1499    "EventCode": "0x4f",
1500    "UMask": "0x10",
1501    "EventName": "EPT.WALK_PENDING",
1502    "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.",
1503    "PublicDescription": "Counts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request type.",
1504    "Counter": "0,1,2,3",
1505    "CounterHTOff": "0,1,2,3,4,5,6,7",
1506    "SampleAfterValue": "2000003",
1507    "MSRIndex": "0",
1508    "MSRValue": "0",
1509    "TakenAlone": "0",
1510    "CounterMask": "0",
1511    "Invert": "0",
1512    "AnyThread": "0",
1513    "EdgeDetect": "0",
1514    "PEBS": "0",
1515    "Data_LA": "0",
1516    "L1_Hit_Indication": "0",
1517    "Errata": "0",
1518    "Offcore": "0"
1519  },
1520  {
1521    "EventCode": "0x51",
1522    "UMask": "0x01",
1523    "EventName": "L1D.REPLACEMENT",
1524    "BriefDescription": "L1D data line replacements",
1525    "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
1526    "Counter": "0,1,2,3",
1527    "CounterHTOff": "0,1,2,3,4,5,6,7",
1528    "SampleAfterValue": "2000003",
1529    "MSRIndex": "0",
1530    "MSRValue": "0",
1531    "TakenAlone": "0",
1532    "CounterMask": "0",
1533    "Invert": "0",
1534    "AnyThread": "0",
1535    "EdgeDetect": "0",
1536    "PEBS": "0",
1537    "Data_LA": "0",
1538    "L1_Hit_Indication": "0",
1539    "Errata": "0",
1540    "Offcore": "0"
1541  },
1542  {
1543    "EventCode": "0x54",
1544    "UMask": "0x01",
1545    "EventName": "TX_MEM.ABORT_CONFLICT",
1546    "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
1547    "PublicDescription": "Number of times a TSX line had a cache conflict.",
1548    "Counter": "0,1,2,3",
1549    "CounterHTOff": "0,1,2,3,4,5,6,7",
1550    "SampleAfterValue": "2000003",
1551    "MSRIndex": "0",
1552    "MSRValue": "0",
1553    "TakenAlone": "0",
1554    "CounterMask": "0",
1555    "Invert": "0",
1556    "AnyThread": "0",
1557    "EdgeDetect": "0",
1558    "PEBS": "0",
1559    "Data_LA": "0",
1560    "L1_Hit_Indication": "0",
1561    "Errata": "0",
1562    "Offcore": "0"
1563  },
1564  {
1565    "EventCode": "0x54",
1566    "UMask": "0x02",
1567    "EventName": "TX_MEM.ABORT_CAPACITY",
1568    "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.",
1569    "PublicDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.",
1570    "Counter": "0,1,2,3",
1571    "CounterHTOff": "0,1,2,3,4,5,6,7",
1572    "SampleAfterValue": "2000003",
1573    "MSRIndex": "0",
1574    "MSRValue": "0",
1575    "TakenAlone": "0",
1576    "CounterMask": "0",
1577    "Invert": "0",
1578    "AnyThread": "0",
1579    "EdgeDetect": "0",
1580    "PEBS": "0",
1581    "Data_LA": "0",
1582    "L1_Hit_Indication": "0",
1583    "Errata": "0",
1584    "Offcore": "0"
1585  },
1586  {
1587    "EventCode": "0x54",
1588    "UMask": "0x04",
1589    "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
1590    "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",
1591    "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
1592    "Counter": "0,1,2,3",
1593    "CounterHTOff": "0,1,2,3,4,5,6,7",
1594    "SampleAfterValue": "2000003",
1595    "MSRIndex": "0",
1596    "MSRValue": "0",
1597    "TakenAlone": "0",
1598    "CounterMask": "0",
1599    "Invert": "0",
1600    "AnyThread": "0",
1601    "EdgeDetect": "0",
1602    "PEBS": "0",
1603    "Data_LA": "0",
1604    "L1_Hit_Indication": "0",
1605    "Errata": "0",
1606    "Offcore": "0"
1607  },
1608  {
1609    "EventCode": "0x54",
1610    "UMask": "0x08",
1611    "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
1612    "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
1613    "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
1614    "Counter": "0,1,2,3",
1615    "CounterHTOff": "0,1,2,3,4,5,6,7",
1616    "SampleAfterValue": "2000003",
1617    "MSRIndex": "0",
1618    "MSRValue": "0",
1619    "TakenAlone": "0",
1620    "CounterMask": "0",
1621    "Invert": "0",
1622    "AnyThread": "0",
1623    "EdgeDetect": "0",
1624    "PEBS": "0",
1625    "Data_LA": "0",
1626    "L1_Hit_Indication": "0",
1627    "Errata": "0",
1628    "Offcore": "0"
1629  },
1630  {
1631    "EventCode": "0x54",
1632    "UMask": "0x10",
1633    "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
1634    "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",
1635    "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
1636    "Counter": "0,1,2,3",
1637    "CounterHTOff": "0,1,2,3,4,5,6,7",
1638    "SampleAfterValue": "2000003",
1639    "MSRIndex": "0",
1640    "MSRValue": "0",
1641    "TakenAlone": "0",
1642    "CounterMask": "0",
1643    "Invert": "0",
1644    "AnyThread": "0",
1645    "EdgeDetect": "0",
1646    "PEBS": "0",
1647    "Data_LA": "0",
1648    "L1_Hit_Indication": "0",
1649    "Errata": "0",
1650    "Offcore": "0"
1651  },
1652  {
1653    "EventCode": "0x54",
1654    "UMask": "0x20",
1655    "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
1656    "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
1657    "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
1658    "Counter": "0,1,2,3",
1659    "CounterHTOff": "0,1,2,3,4,5,6,7",
1660    "SampleAfterValue": "2000003",
1661    "MSRIndex": "0",
1662    "MSRValue": "0",
1663    "TakenAlone": "0",
1664    "CounterMask": "0",
1665    "Invert": "0",
1666    "AnyThread": "0",
1667    "EdgeDetect": "0",
1668    "PEBS": "0",
1669    "Data_LA": "0",
1670    "L1_Hit_Indication": "0",
1671    "Errata": "0",
1672    "Offcore": "0"
1673  },
1674  {
1675    "EventCode": "0x54",
1676    "UMask": "0x40",
1677    "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
1678    "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
1679    "PublicDescription": "Number of times we could not allocate Lock Buffer.",
1680    "Counter": "0,1,2,3",
1681    "CounterHTOff": "0,1,2,3,4,5,6,7",
1682    "SampleAfterValue": "2000003",
1683    "MSRIndex": "0",
1684    "MSRValue": "0",
1685    "TakenAlone": "0",
1686    "CounterMask": "0",
1687    "Invert": "0",
1688    "AnyThread": "0",
1689    "EdgeDetect": "0",
1690    "PEBS": "0",
1691    "Data_LA": "0",
1692    "L1_Hit_Indication": "0",
1693    "Errata": "0",
1694    "Offcore": "0"
1695  },
1696  {
1697    "EventCode": "0x59",
1698    "UMask": "0x01",
1699    "EventName": "PARTIAL_RAT_STALLS.SCOREBOARD",
1700    "BriefDescription": "Cycles where the pipeline is stalled due to serializing operations.",
1701    "PublicDescription": "This event counts cycles during which the microcode scoreboard stalls happen.",
1702    "Counter": "0,1,2,3",
1703    "CounterHTOff": "0,1,2,3,4,5,6,7",
1704    "SampleAfterValue": "2000003",
1705    "MSRIndex": "0",
1706    "MSRValue": "0",
1707    "TakenAlone": "0",
1708    "CounterMask": "0",
1709    "Invert": "0",
1710    "AnyThread": "0",
1711    "EdgeDetect": "0",
1712    "PEBS": "0",
1713    "Data_LA": "0",
1714    "L1_Hit_Indication": "0",
1715    "Errata": "0",
1716    "Offcore": "0"
1717  },
1718  {
1719    "EventCode": "0x5d",
1720    "UMask": "0x01",
1721    "EventName": "TX_EXEC.MISC1",
1722    "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
1723    "PublicDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
1724    "Counter": "0,1,2,3",
1725    "CounterHTOff": "0,1,2,3,4,5,6,7",
1726    "SampleAfterValue": "2000003",
1727    "MSRIndex": "0",
1728    "MSRValue": "0",
1729    "TakenAlone": "0",
1730    "CounterMask": "0",
1731    "Invert": "0",
1732    "AnyThread": "0",
1733    "EdgeDetect": "0",
1734    "PEBS": "0",
1735    "Data_LA": "0",
1736    "L1_Hit_Indication": "0",
1737    "Errata": "0",
1738    "Offcore": "0"
1739  },
1740  {
1741    "EventCode": "0x5d",
1742    "UMask": "0x02",
1743    "EventName": "TX_EXEC.MISC2",
1744    "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
1745    "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
1746    "Counter": "0,1,2,3",
1747    "CounterHTOff": "0,1,2,3,4,5,6,7",
1748    "SampleAfterValue": "2000003",
1749    "MSRIndex": "0",
1750    "MSRValue": "0",
1751    "TakenAlone": "0",
1752    "CounterMask": "0",
1753    "Invert": "0",
1754    "AnyThread": "0",
1755    "EdgeDetect": "0",
1756    "PEBS": "0",
1757    "Data_LA": "0",
1758    "L1_Hit_Indication": "0",
1759    "Errata": "0",
1760    "Offcore": "0"
1761  },
1762  {
1763    "EventCode": "0x5d",
1764    "UMask": "0x04",
1765    "EventName": "TX_EXEC.MISC3",
1766    "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
1767    "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
1768    "Counter": "0,1,2,3",
1769    "CounterHTOff": "0,1,2,3,4,5,6,7",
1770    "SampleAfterValue": "2000003",
1771    "MSRIndex": "0",
1772    "MSRValue": "0",
1773    "TakenAlone": "0",
1774    "CounterMask": "0",
1775    "Invert": "0",
1776    "AnyThread": "0",
1777    "EdgeDetect": "0",
1778    "PEBS": "0",
1779    "Data_LA": "0",
1780    "L1_Hit_Indication": "0",
1781    "Errata": "0",
1782    "Offcore": "0"
1783  },
1784  {
1785    "EventCode": "0x5d",
1786    "UMask": "0x08",
1787    "EventName": "TX_EXEC.MISC4",
1788    "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
1789    "PublicDescription": "RTM region detected inside HLE.",
1790    "Counter": "0,1,2,3",
1791    "CounterHTOff": "0,1,2,3,4,5,6,7",
1792    "SampleAfterValue": "2000003",
1793    "MSRIndex": "0",
1794    "MSRValue": "0",
1795    "TakenAlone": "0",
1796    "CounterMask": "0",
1797    "Invert": "0",
1798    "AnyThread": "0",
1799    "EdgeDetect": "0",
1800    "PEBS": "0",
1801    "Data_LA": "0",
1802    "L1_Hit_Indication": "0",
1803    "Errata": "0",
1804    "Offcore": "0"
1805  },
1806  {
1807    "EventCode": "0x5d",
1808    "UMask": "0x10",
1809    "EventName": "TX_EXEC.MISC5",
1810    "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region",
1811    "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
1812    "Counter": "0,1,2,3",
1813    "CounterHTOff": "0,1,2,3,4,5,6,7",
1814    "SampleAfterValue": "2000003",
1815    "MSRIndex": "0",
1816    "MSRValue": "0",
1817    "TakenAlone": "0",
1818    "CounterMask": "0",
1819    "Invert": "0",
1820    "AnyThread": "0",
1821    "EdgeDetect": "0",
1822    "PEBS": "0",
1823    "Data_LA": "0",
1824    "L1_Hit_Indication": "0",
1825    "Errata": "0",
1826    "Offcore": "0"
1827  },
1828  {
1829    "EventCode": "0x5E",
1830    "UMask": "0x01",
1831    "EventName": "RS_EVENTS.EMPTY_CYCLES",
1832    "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
1833    "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.",
1834    "Counter": "0,1,2,3",
1835    "CounterHTOff": "0,1,2,3,4,5,6,7",
1836    "SampleAfterValue": "2000003",
1837    "MSRIndex": "0",
1838    "MSRValue": "0",
1839    "TakenAlone": "0",
1840    "CounterMask": "0",
1841    "Invert": "0",
1842    "AnyThread": "0",
1843    "EdgeDetect": "0",
1844    "PEBS": "0",
1845    "Data_LA": "0",
1846    "L1_Hit_Indication": "0",
1847    "Errata": "0",
1848    "Offcore": "0"
1849  },
1850  {
1851    "EventCode": "0x5E",
1852    "UMask": "0x01",
1853    "EventName": "RS_EVENTS.EMPTY_END",
1854    "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
1855    "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate front-end Latency Bound issues.",
1856    "Counter": "0,1,2,3",
1857    "CounterHTOff": "0,1,2,3,4,5,6,7",
1858    "SampleAfterValue": "2000003",
1859    "MSRIndex": "0",
1860    "MSRValue": "0",
1861    "TakenAlone": "0",
1862    "CounterMask": "1",
1863    "Invert": "1",
1864    "AnyThread": "0",
1865    "EdgeDetect": "1",
1866    "PEBS": "0",
1867    "Data_LA": "0",
1868    "L1_Hit_Indication": "0",
1869    "Errata": "0",
1870    "Offcore": "0"
1871  },
1872  {
1873    "EventCode": "0x60",
1874    "UMask": "0x01",
1875    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
1876    "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
1877    "PublicDescription": "Counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the promotion point.",
1878    "Counter": "0,1,2,3",
1879    "CounterHTOff": "0,1,2,3,4,5,6,7",
1880    "SampleAfterValue": "2000003",
1881    "MSRIndex": "0",
1882    "MSRValue": "0",
1883    "TakenAlone": "0",
1884    "CounterMask": "0",
1885    "Invert": "0",
1886    "AnyThread": "0",
1887    "EdgeDetect": "0",
1888    "PEBS": "0",
1889    "Data_LA": "0",
1890    "L1_Hit_Indication": "0",
1891    "Errata": "0",
1892    "Offcore": "0"
1893  },
1894  {
1895    "EventCode": "0x60",
1896    "UMask": "0x01",
1897    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
1898    "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
1899    "PublicDescription": "Counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).",
1900    "Counter": "0,1,2,3",
1901    "CounterHTOff": "0,1,2,3,4,5,6,7",
1902    "SampleAfterValue": "2000003",
1903    "MSRIndex": "0",
1904    "MSRValue": "0",
1905    "TakenAlone": "0",
1906    "CounterMask": "1",
1907    "Invert": "0",
1908    "AnyThread": "0",
1909    "EdgeDetect": "0",
1910    "PEBS": "0",
1911    "Data_LA": "0",
1912    "L1_Hit_Indication": "0",
1913    "Errata": "0",
1914    "Offcore": "0"
1915  },
1916  {
1917    "EventCode": "0x60",
1918    "UMask": "0x01",
1919    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
1920    "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
1921    "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
1922    "Counter": "0,1,2,3",
1923    "CounterHTOff": "0,1,2,3,4,5,6,7",
1924    "SampleAfterValue": "2000003",
1925    "MSRIndex": "0x00",
1926    "MSRValue": "0x00",
1927    "TakenAlone": "0",
1928    "CounterMask": "6",
1929    "Invert": "0",
1930    "AnyThread": "0",
1931    "EdgeDetect": "0",
1932    "PEBS": "0",
1933    "Data_LA": "0",
1934    "L1_Hit_Indication": "0",
1935    "Errata": "0",
1936    "Offcore": "0"
1937  },
1938  {
1939    "EventCode": "0x60",
1940    "UMask": "0x02",
1941    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
1942    "BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.",
1943    "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
1944    "Counter": "0,1,2,3",
1945    "CounterHTOff": "0,1,2,3,4,5,6,7",
1946    "SampleAfterValue": "2000003",
1947    "MSRIndex": "0",
1948    "MSRValue": "0",
1949    "TakenAlone": "0",
1950    "CounterMask": "0",
1951    "Invert": "0",
1952    "AnyThread": "0",
1953    "EdgeDetect": "0",
1954    "PEBS": "0",
1955    "Data_LA": "0",
1956    "L1_Hit_Indication": "0",
1957    "Errata": "0",
1958    "Offcore": "0"
1959  },
1960  {
1961    "EventCode": "0x60",
1962    "UMask": "0x02",
1963    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
1964    "BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.",
1965    "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
1966    "Counter": "0,1,2,3",
1967    "CounterHTOff": "0,1,2,3,4,5,6,7",
1968    "SampleAfterValue": "2000003",
1969    "MSRIndex": "0",
1970    "MSRValue": "0",
1971    "TakenAlone": "0",
1972    "CounterMask": "1",
1973    "Invert": "0",
1974    "AnyThread": "0",
1975    "EdgeDetect": "0",
1976    "PEBS": "0",
1977    "Data_LA": "0",
1978    "L1_Hit_Indication": "0",
1979    "Errata": "0",
1980    "Offcore": "0"
1981  },
1982  {
1983    "EventCode": "0x60",
1984    "UMask": "0x04",
1985    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
1986    "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
1987    "PublicDescription": "Counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
1988    "Counter": "0,1,2,3",
1989    "CounterHTOff": "0,1,2,3,4,5,6,7",
1990    "SampleAfterValue": "2000003",
1991    "MSRIndex": "0",
1992    "MSRValue": "0",
1993    "TakenAlone": "0",
1994    "CounterMask": "0",
1995    "Invert": "0",
1996    "AnyThread": "0",
1997    "EdgeDetect": "0",
1998    "PEBS": "0",
1999    "Data_LA": "0",
2000    "L1_Hit_Indication": "0",
2001    "Errata": "0",
2002    "Offcore": "0"
2003  },
2004  {
2005    "EventCode": "0x60",
2006    "UMask": "0x04",
2007    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
2008    "BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.",
2009    "PublicDescription": "Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
2010    "Counter": "0,1,2,3",
2011    "CounterHTOff": "0,1,2,3,4,5,6,7",
2012    "SampleAfterValue": "2000003",
2013    "MSRIndex": "0",
2014    "MSRValue": "0",
2015    "TakenAlone": "0",
2016    "CounterMask": "1",
2017    "Invert": "0",
2018    "AnyThread": "0",
2019    "EdgeDetect": "0",
2020    "PEBS": "0",
2021    "Data_LA": "0",
2022    "L1_Hit_Indication": "0",
2023    "Errata": "0",
2024    "Offcore": "0"
2025  },
2026  {
2027    "EventCode": "0x60",
2028    "UMask": "0x08",
2029    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
2030    "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
2031    "PublicDescription": "Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
2032    "Counter": "0,1,2,3",
2033    "CounterHTOff": "0,1,2,3,4,5,6,7",
2034    "SampleAfterValue": "2000003",
2035    "MSRIndex": "0",
2036    "MSRValue": "0",
2037    "TakenAlone": "0",
2038    "CounterMask": "0",
2039    "Invert": "0",
2040    "AnyThread": "0",
2041    "EdgeDetect": "0",
2042    "PEBS": "0",
2043    "Data_LA": "0",
2044    "L1_Hit_Indication": "0",
2045    "Errata": "0",
2046    "Offcore": "0"
2047  },
2048  {
2049    "EventCode": "0x60",
2050    "UMask": "0x08",
2051    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
2052    "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
2053    "PublicDescription": "Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
2054    "Counter": "0,1,2,3",
2055    "CounterHTOff": "0,1,2,3,4,5,6,7",
2056    "SampleAfterValue": "2000003",
2057    "MSRIndex": "0",
2058    "MSRValue": "0",
2059    "TakenAlone": "0",
2060    "CounterMask": "1",
2061    "Invert": "0",
2062    "AnyThread": "0",
2063    "EdgeDetect": "0",
2064    "PEBS": "0",
2065    "Data_LA": "0",
2066    "L1_Hit_Indication": "0",
2067    "Errata": "0",
2068    "Offcore": "0"
2069  },
2070  {
2071    "EventCode": "0x60",
2072    "UMask": "0x10",
2073    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
2074    "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.",
2075    "PublicDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.",
2076    "Counter": "0,1,2,3",
2077    "CounterHTOff": "0,1,2,3,4,5,6,7",
2078    "SampleAfterValue": "2000003",
2079    "MSRIndex": "0",
2080    "MSRValue": "0",
2081    "TakenAlone": "0",
2082    "CounterMask": "0",
2083    "Invert": "0",
2084    "AnyThread": "0",
2085    "EdgeDetect": "0",
2086    "PEBS": "0",
2087    "Data_LA": "0",
2088    "L1_Hit_Indication": "0",
2089    "Errata": "0",
2090    "Offcore": "0"
2091  },
2092  {
2093    "EventCode": "0x60",
2094    "UMask": "0x10",
2095    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
2096    "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.",
2097    "PublicDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.",
2098    "Counter": "0,1,2,3",
2099    "CounterHTOff": "0,1,2,3,4,5,6,7",
2100    "SampleAfterValue": "2000003",
2101    "MSRIndex": "0x00",
2102    "MSRValue": "0x00",
2103    "TakenAlone": "0",
2104    "CounterMask": "1",
2105    "Invert": "0",
2106    "AnyThread": "0",
2107    "EdgeDetect": "0",
2108    "PEBS": "0",
2109    "Data_LA": "0",
2110    "L1_Hit_Indication": "0",
2111    "Errata": "0",
2112    "Offcore": "0"
2113  },
2114  {
2115    "EventCode": "0x60",
2116    "UMask": "0x10",
2117    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6",
2118    "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.",
2119    "PublicDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.",
2120    "Counter": "0,1,2,3",
2121    "CounterHTOff": "0,1,2,3,4,5,6,7",
2122    "SampleAfterValue": "2000003",
2123    "MSRIndex": "0x00",
2124    "MSRValue": "0x00",
2125    "TakenAlone": "0",
2126    "CounterMask": "6",
2127    "Invert": "0",
2128    "AnyThread": "0",
2129    "EdgeDetect": "0",
2130    "PEBS": "0",
2131    "Data_LA": "0",
2132    "L1_Hit_Indication": "0",
2133    "Errata": "0",
2134    "Offcore": "0"
2135  },
2136  {
2137    "EventCode": "0x79",
2138    "UMask": "0x04",
2139    "EventName": "IDQ.MITE_UOPS",
2140    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
2141    "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
2142    "Counter": "0,1,2,3",
2143    "CounterHTOff": "0,1,2,3,4,5,6,7",
2144    "SampleAfterValue": "2000003",
2145    "MSRIndex": "0",
2146    "MSRValue": "0",
2147    "TakenAlone": "0",
2148    "CounterMask": "0",
2149    "Invert": "0",
2150    "AnyThread": "0",
2151    "EdgeDetect": "0",
2152    "PEBS": "0",
2153    "Data_LA": "0",
2154    "L1_Hit_Indication": "0",
2155    "Errata": "0",
2156    "Offcore": "0"
2157  },
2158  {
2159    "EventCode": "0x79",
2160    "UMask": "0x04",
2161    "EventName": "IDQ.MITE_CYCLES",
2162    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
2163    "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ.",
2164    "Counter": "0,1,2,3",
2165    "CounterHTOff": "0,1,2,3,4,5,6,7",
2166    "SampleAfterValue": "2000003",
2167    "MSRIndex": "0",
2168    "MSRValue": "0",
2169    "TakenAlone": "0",
2170    "CounterMask": "1",
2171    "Invert": "0",
2172    "AnyThread": "0",
2173    "EdgeDetect": "0",
2174    "PEBS": "0",
2175    "Data_LA": "0",
2176    "L1_Hit_Indication": "0",
2177    "Errata": "0",
2178    "Offcore": "0"
2179  },
2180  {
2181    "EventCode": "0x79",
2182    "UMask": "0x08",
2183    "EventName": "IDQ.DSB_UOPS",
2184    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
2185    "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.",
2186    "Counter": "0,1,2,3",
2187    "CounterHTOff": "0,1,2,3,4,5,6,7",
2188    "SampleAfterValue": "2000003",
2189    "MSRIndex": "0",
2190    "MSRValue": "0",
2191    "TakenAlone": "0",
2192    "CounterMask": "0",
2193    "Invert": "0",
2194    "AnyThread": "0",
2195    "EdgeDetect": "0",
2196    "PEBS": "0",
2197    "Data_LA": "0",
2198    "L1_Hit_Indication": "0",
2199    "Errata": "0",
2200    "Offcore": "0"
2201  },
2202  {
2203    "EventCode": "0x79",
2204    "UMask": "0x08",
2205    "EventName": "IDQ.DSB_CYCLES",
2206    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
2207    "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.",
2208    "Counter": "0,1,2,3",
2209    "CounterHTOff": "0,1,2,3,4,5,6,7",
2210    "SampleAfterValue": "2000003",
2211    "MSRIndex": "0",
2212    "MSRValue": "0",
2213    "TakenAlone": "0",
2214    "CounterMask": "1",
2215    "Invert": "0",
2216    "AnyThread": "0",
2217    "EdgeDetect": "0",
2218    "PEBS": "0",
2219    "Data_LA": "0",
2220    "L1_Hit_Indication": "0",
2221    "Errata": "0",
2222    "Offcore": "0"
2223  },
2224  {
2225    "EventCode": "0x79",
2226    "UMask": "0x10",
2227    "EventName": "IDQ.MS_DSB_CYCLES",
2228    "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
2229    "PublicDescription": "Counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.",
2230    "Counter": "0,1,2,3",
2231    "CounterHTOff": "0,1,2,3,4,5,6,7",
2232    "SampleAfterValue": "2000003",
2233    "MSRIndex": "0",
2234    "MSRValue": "0",
2235    "TakenAlone": "0",
2236    "CounterMask": "1",
2237    "Invert": "0",
2238    "AnyThread": "0",
2239    "EdgeDetect": "0",
2240    "PEBS": "0",
2241    "Data_LA": "0",
2242    "L1_Hit_Indication": "0",
2243    "Errata": "0",
2244    "Offcore": "0"
2245  },
2246  {
2247    "EventCode": "0x79",
2248    "UMask": "0x18",
2249    "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
2250    "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
2251    "PublicDescription": "Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ.",
2252    "Counter": "0,1,2,3",
2253    "CounterHTOff": "0,1,2,3,4,5,6,7",
2254    "SampleAfterValue": "2000003",
2255    "MSRIndex": "0",
2256    "MSRValue": "0",
2257    "TakenAlone": "0",
2258    "CounterMask": "4",
2259    "Invert": "0",
2260    "AnyThread": "0",
2261    "EdgeDetect": "0",
2262    "PEBS": "0",
2263    "Data_LA": "0",
2264    "L1_Hit_Indication": "0",
2265    "Errata": "0",
2266    "Offcore": "0"
2267  },
2268  {
2269    "EventCode": "0x79",
2270    "UMask": "0x18",
2271    "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
2272    "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
2273    "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ.",
2274    "Counter": "0,1,2,3",
2275    "CounterHTOff": "0,1,2,3,4,5,6,7",
2276    "SampleAfterValue": "2000003",
2277    "MSRIndex": "0",
2278    "MSRValue": "0",
2279    "TakenAlone": "0",
2280    "CounterMask": "1",
2281    "Invert": "0",
2282    "AnyThread": "0",
2283    "EdgeDetect": "0",
2284    "PEBS": "0",
2285    "Data_LA": "0",
2286    "L1_Hit_Indication": "0",
2287    "Errata": "0",
2288    "Offcore": "0"
2289  },
2290  {
2291    "EventCode": "0x79",
2292    "UMask": "0x20",
2293    "EventName": "IDQ.MS_MITE_UOPS",
2294    "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
2295    "PublicDescription": "Counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.",
2296    "Counter": "0,1,2,3",
2297    "CounterHTOff": "0,1,2,3,4,5,6,7",
2298    "SampleAfterValue": "2000003",
2299    "MSRIndex": "0",
2300    "MSRValue": "0",
2301    "TakenAlone": "0",
2302    "CounterMask": "0",
2303    "Invert": "0",
2304    "AnyThread": "0",
2305    "EdgeDetect": "0",
2306    "PEBS": "0",
2307    "Data_LA": "0",
2308    "L1_Hit_Indication": "0",
2309    "Errata": "0",
2310    "Offcore": "0"
2311  },
2312  {
2313    "EventCode": "0x79",
2314    "UMask": "0x24",
2315    "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
2316    "BriefDescription": "Cycles MITE is delivering 4 Uops",
2317    "PublicDescription": "Counts the number of cycles 4 uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
2318    "Counter": "0,1,2,3",
2319    "CounterHTOff": "0,1,2,3,4,5,6,7",
2320    "SampleAfterValue": "2000003",
2321    "MSRIndex": "0",
2322    "MSRValue": "0",
2323    "TakenAlone": "0",
2324    "CounterMask": "4",
2325    "Invert": "0",
2326    "AnyThread": "0",
2327    "EdgeDetect": "0",
2328    "PEBS": "0",
2329    "Data_LA": "0",
2330    "L1_Hit_Indication": "0",
2331    "Errata": "0",
2332    "Offcore": "0"
2333  },
2334  {
2335    "EventCode": "0x79",
2336    "UMask": "0x24",
2337    "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
2338    "BriefDescription": "Cycles MITE is delivering any Uop",
2339    "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
2340    "Counter": "0,1,2,3",
2341    "CounterHTOff": "0,1,2,3,4,5,6,7",
2342    "SampleAfterValue": "2000003",
2343    "MSRIndex": "0",
2344    "MSRValue": "0",
2345    "TakenAlone": "0",
2346    "CounterMask": "1",
2347    "Invert": "0",
2348    "AnyThread": "0",
2349    "EdgeDetect": "0",
2350    "PEBS": "0",
2351    "Data_LA": "0",
2352    "L1_Hit_Indication": "0",
2353    "Errata": "0",
2354    "Offcore": "0"
2355  },
2356  {
2357    "EventCode": "0x79",
2358    "UMask": "0x30",
2359    "EventName": "IDQ.MS_CYCLES",
2360    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
2361    "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
2362    "Counter": "0,1,2,3",
2363    "CounterHTOff": "0,1,2,3,4,5,6,7",
2364    "SampleAfterValue": "2000003",
2365    "MSRIndex": "0",
2366    "MSRValue": "0",
2367    "TakenAlone": "0",
2368    "CounterMask": "1",
2369    "Invert": "0",
2370    "AnyThread": "0",
2371    "EdgeDetect": "0",
2372    "PEBS": "0",
2373    "Data_LA": "0",
2374    "L1_Hit_Indication": "0",
2375    "Errata": "0",
2376    "Offcore": "0"
2377  },
2378  {
2379    "EventCode": "0x79",
2380    "UMask": "0x30",
2381    "EventName": "IDQ.MS_SWITCHES",
2382    "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
2383    "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
2384    "Counter": "0,1,2,3",
2385    "CounterHTOff": "0,1,2,3,4,5,6,7",
2386    "SampleAfterValue": "2000003",
2387    "MSRIndex": "0",
2388    "MSRValue": "0",
2389    "TakenAlone": "0",
2390    "CounterMask": "1",
2391    "Invert": "0",
2392    "AnyThread": "0",
2393    "EdgeDetect": "1",
2394    "PEBS": "0",
2395    "Data_LA": "0",
2396    "L1_Hit_Indication": "0",
2397    "Errata": "0",
2398    "Offcore": "0"
2399  },
2400  {
2401    "EventCode": "0x79",
2402    "UMask": "0x30",
2403    "EventName": "IDQ.MS_UOPS",
2404    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
2405    "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.",
2406    "Counter": "0,1,2,3",
2407    "CounterHTOff": "0,1,2,3,4,5,6,7",
2408    "SampleAfterValue": "2000003",
2409    "MSRIndex": "0",
2410    "MSRValue": "0",
2411    "TakenAlone": "0",
2412    "CounterMask": "0",
2413    "Invert": "0",
2414    "AnyThread": "0",
2415    "EdgeDetect": "0",
2416    "PEBS": "0",
2417    "Data_LA": "0",
2418    "L1_Hit_Indication": "0",
2419    "Errata": "0",
2420    "Offcore": "0"
2421  },
2422  {
2423    "EventCode": "0x80",
2424    "UMask": "0x04",
2425    "EventName": "ICACHE_16B.IFDATA_STALL",
2426    "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
2427    "PublicDescription": "Cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.",
2428    "Counter": "0,1,2,3",
2429    "CounterHTOff": "0,1,2,3,4,5,6,7",
2430    "SampleAfterValue": "2000003",
2431    "MSRIndex": "0",
2432    "MSRValue": "0",
2433    "TakenAlone": "0",
2434    "CounterMask": "0",
2435    "Invert": "0",
2436    "AnyThread": "0",
2437    "EdgeDetect": "0",
2438    "PEBS": "0",
2439    "Data_LA": "0",
2440    "L1_Hit_Indication": "0",
2441    "Errata": "0",
2442    "Offcore": "0"
2443  },
2444  {
2445    "EventCode": "0x83",
2446    "UMask": "0x01",
2447    "EventName": "ICACHE_64B.IFTAG_HIT",
2448    "BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
2449    "PublicDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
2450    "Counter": "0,1,2,3",
2451    "CounterHTOff": "0,1,2,3,4,5,6,7",
2452    "SampleAfterValue": "200003",
2453    "MSRIndex": "0",
2454    "MSRValue": "0",
2455    "TakenAlone": "0",
2456    "CounterMask": "0",
2457    "Invert": "0",
2458    "AnyThread": "0",
2459    "EdgeDetect": "0",
2460    "PEBS": "0",
2461    "Data_LA": "0",
2462    "L1_Hit_Indication": "0",
2463    "Errata": "0",
2464    "Offcore": "0"
2465  },
2466  {
2467    "EventCode": "0x83",
2468    "UMask": "0x02",
2469    "EventName": "ICACHE_64B.IFTAG_MISS",
2470    "BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
2471    "PublicDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
2472    "Counter": "0,1,2,3",
2473    "CounterHTOff": "0,1,2,3,4,5,6,7",
2474    "SampleAfterValue": "200003",
2475    "MSRIndex": "0",
2476    "MSRValue": "0",
2477    "TakenAlone": "0",
2478    "CounterMask": "0",
2479    "Invert": "0",
2480    "AnyThread": "0",
2481    "EdgeDetect": "0",
2482    "PEBS": "0",
2483    "Data_LA": "0",
2484    "L1_Hit_Indication": "0",
2485    "Errata": "0",
2486    "Offcore": "0"
2487  },
2488  {
2489    "EventCode": "0x83",
2490    "UMask": "0x04",
2491    "EventName": "ICACHE_64B.IFTAG_STALL",
2492    "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
2493    "PublicDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
2494    "Counter": "0,1,2,3",
2495    "CounterHTOff": "0,1,2,3,4,5,6,7",
2496    "SampleAfterValue": "200003",
2497    "MSRIndex": "0",
2498    "MSRValue": "0",
2499    "TakenAlone": "0",
2500    "CounterMask": "0",
2501    "Invert": "0",
2502    "AnyThread": "0",
2503    "EdgeDetect": "0",
2504    "PEBS": "0",
2505    "Data_LA": "0",
2506    "L1_Hit_Indication": "0",
2507    "Errata": "0",
2508    "Offcore": "0"
2509  },
2510  {
2511    "EventCode": "0x85",
2512    "UMask": "0x01",
2513    "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
2514    "BriefDescription": "Misses at all ITLB levels that cause page walks",
2515    "PublicDescription": "Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completed.",
2516    "Counter": "0,1,2,3",
2517    "CounterHTOff": "0,1,2,3,4,5,6,7",
2518    "SampleAfterValue": "100003",
2519    "MSRIndex": "0",
2520    "MSRValue": "0",
2521    "TakenAlone": "0",
2522    "CounterMask": "0",
2523    "Invert": "0",
2524    "AnyThread": "0",
2525    "EdgeDetect": "0",
2526    "PEBS": "0",
2527    "Data_LA": "0",
2528    "L1_Hit_Indication": "0",
2529    "Errata": "0",
2530    "Offcore": "0"
2531  },
2532  {
2533    "EventCode": "0x85",
2534    "UMask": "0x02",
2535    "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
2536    "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
2537    "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
2538    "Counter": "0,1,2,3",
2539    "CounterHTOff": "0,1,2,3,4,5,6,7",
2540    "SampleAfterValue": "100003",
2541    "MSRIndex": "0",
2542    "MSRValue": "0",
2543    "TakenAlone": "0",
2544    "CounterMask": "0",
2545    "Invert": "0",
2546    "AnyThread": "0",
2547    "EdgeDetect": "0",
2548    "PEBS": "0",
2549    "Data_LA": "0",
2550    "L1_Hit_Indication": "0",
2551    "Errata": "0",
2552    "Offcore": "0"
2553  },
2554  {
2555    "EventCode": "0x85",
2556    "UMask": "0x04",
2557    "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
2558    "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
2559    "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
2560    "Counter": "0,1,2,3",
2561    "CounterHTOff": "0,1,2,3,4,5,6,7",
2562    "SampleAfterValue": "100003",
2563    "MSRIndex": "0",
2564    "MSRValue": "0",
2565    "TakenAlone": "0",
2566    "CounterMask": "0",
2567    "Invert": "0",
2568    "AnyThread": "0",
2569    "EdgeDetect": "0",
2570    "PEBS": "0",
2571    "Data_LA": "0",
2572    "L1_Hit_Indication": "0",
2573    "Errata": "0",
2574    "Offcore": "0"
2575  },
2576  {
2577    "EventCode": "0x85",
2578    "UMask": "0x08",
2579    "EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
2580    "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)",
2581    "PublicDescription": "Counts completed page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
2582    "Counter": "0,1,2,3",
2583    "CounterHTOff": "0,1,2,3,4,5,6,7",
2584    "SampleAfterValue": "100003",
2585    "MSRIndex": "0",
2586    "MSRValue": "0",
2587    "TakenAlone": "0",
2588    "CounterMask": "0",
2589    "Invert": "0",
2590    "AnyThread": "0",
2591    "EdgeDetect": "0",
2592    "PEBS": "0",
2593    "Data_LA": "0",
2594    "L1_Hit_Indication": "0",
2595    "Errata": "0",
2596    "Offcore": "0"
2597  },
2598  {
2599    "EventCode": "0x85",
2600    "UMask": "0x0e",
2601    "EventName": "ITLB_MISSES.WALK_COMPLETED",
2602    "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
2603    "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
2604    "Counter": "0,1,2,3",
2605    "CounterHTOff": "0,1,2,3,4,5,6,7",
2606    "SampleAfterValue": "100003",
2607    "MSRIndex": "0",
2608    "MSRValue": "0",
2609    "TakenAlone": "0",
2610    "CounterMask": "0",
2611    "Invert": "0",
2612    "AnyThread": "0",
2613    "EdgeDetect": "0",
2614    "PEBS": "0",
2615    "Data_LA": "0",
2616    "L1_Hit_Indication": "0",
2617    "Errata": "0",
2618    "Offcore": "0"
2619  },
2620  {
2621    "EventCode": "0x85",
2622    "UMask": "0x10",
2623    "EventName": "ITLB_MISSES.WALK_PENDING",
2624    "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.",
2625    "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture.",
2626    "Counter": "0,1,2,3",
2627    "CounterHTOff": "0,1,2,3,4,5,6,7",
2628    "SampleAfterValue": "100003",
2629    "MSRIndex": "0",
2630    "MSRValue": "0",
2631    "TakenAlone": "0",
2632    "CounterMask": "0",
2633    "Invert": "0",
2634    "AnyThread": "0",
2635    "EdgeDetect": "0",
2636    "PEBS": "0",
2637    "Data_LA": "0",
2638    "L1_Hit_Indication": "0",
2639    "Errata": "0",
2640    "Offcore": "0"
2641  },
2642  {
2643    "EventCode": "0x85",
2644    "UMask": "0x10",
2645    "EventName": "ITLB_MISSES.WALK_ACTIVE",
2646    "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake.",
2647    "PublicDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake microarchitecture.",
2648    "Counter": "0,1,2,3",
2649    "CounterHTOff": "0,1,2,3,4,5,6,7",
2650    "SampleAfterValue": "100003",
2651    "MSRIndex": "0",
2652    "MSRValue": "0x00",
2653    "TakenAlone": "0",
2654    "CounterMask": "1",
2655    "Invert": "0",
2656    "AnyThread": "0",
2657    "EdgeDetect": "0",
2658    "PEBS": "0",
2659    "Data_LA": "0",
2660    "L1_Hit_Indication": "0",
2661    "Errata": "0",
2662    "Offcore": "0"
2663  },
2664  {
2665    "EventCode": "0x85",
2666    "UMask": "0x20",
2667    "EventName": "ITLB_MISSES.STLB_HIT",
2668    "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
2669    "PublicDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
2670    "Counter": "0,1,2,3",
2671    "CounterHTOff": "0,1,2,3,4,5,6,7",
2672    "SampleAfterValue": "100003",
2673    "MSRIndex": "0",
2674    "MSRValue": "0",
2675    "TakenAlone": "0",
2676    "CounterMask": "0",
2677    "Invert": "0",
2678    "AnyThread": "0",
2679    "EdgeDetect": "0",
2680    "PEBS": "0",
2681    "Data_LA": "0",
2682    "L1_Hit_Indication": "0",
2683    "Errata": "0",
2684    "Offcore": "0"
2685  },
2686  {
2687    "EventCode": "0x87",
2688    "UMask": "0x01",
2689    "EventName": "ILD_STALL.LCP",
2690    "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
2691    "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
2692    "Counter": "0,1,2,3",
2693    "CounterHTOff": "0,1,2,3,4,5,6,7",
2694    "SampleAfterValue": "2000003",
2695    "MSRIndex": "0",
2696    "MSRValue": "0",
2697    "TakenAlone": "0",
2698    "CounterMask": "0",
2699    "Invert": "0",
2700    "AnyThread": "0",
2701    "EdgeDetect": "0",
2702    "PEBS": "0",
2703    "Data_LA": "0",
2704    "L1_Hit_Indication": "0",
2705    "Errata": "0",
2706    "Offcore": "0"
2707  },
2708  {
2709    "EventCode": "0x9C",
2710    "UMask": "0x01",
2711    "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
2712    "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
2713    "PublicDescription": "Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4  x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions).  c. Instruction Decode Queue (IDQ) delivers four uops.",
2714    "Counter": "0,1,2,3",
2715    "CounterHTOff": "0,1,2,3,4,5,6,7",
2716    "SampleAfterValue": "2000003",
2717    "MSRIndex": "0",
2718    "MSRValue": "0",
2719    "TakenAlone": "0",
2720    "CounterMask": "0",
2721    "Invert": "0",
2722    "AnyThread": "0",
2723    "EdgeDetect": "0",
2724    "PEBS": "0",
2725    "Data_LA": "0",
2726    "L1_Hit_Indication": "0",
2727    "Errata": "0",
2728    "Offcore": "0"
2729  },
2730  {
2731    "EventCode": "0x9C",
2732    "UMask": "0x01",
2733    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
2734    "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
2735    "PublicDescription": "Counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.",
2736    "Counter": "0,1,2,3",
2737    "CounterHTOff": "0,1,2,3,4,5,6,7",
2738    "SampleAfterValue": "2000003",
2739    "MSRIndex": "0",
2740    "MSRValue": "0",
2741    "TakenAlone": "0",
2742    "CounterMask": "4",
2743    "Invert": "0",
2744    "AnyThread": "0",
2745    "EdgeDetect": "0",
2746    "PEBS": "0",
2747    "Data_LA": "0",
2748    "L1_Hit_Indication": "0",
2749    "Errata": "0",
2750    "Offcore": "0"
2751  },
2752  {
2753    "EventCode": "0x9C",
2754    "UMask": "0x01",
2755    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
2756    "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
2757    "PublicDescription": "Counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >= 3.",
2758    "Counter": "0,1,2,3",
2759    "CounterHTOff": "0,1,2,3,4,5,6,7",
2760    "SampleAfterValue": "2000003",
2761    "MSRIndex": "0",
2762    "MSRValue": "0",
2763    "TakenAlone": "0",
2764    "CounterMask": "3",
2765    "Invert": "0",
2766    "AnyThread": "0",
2767    "EdgeDetect": "0",
2768    "PEBS": "0",
2769    "Data_LA": "0",
2770    "L1_Hit_Indication": "0",
2771    "Errata": "0",
2772    "Offcore": "0"
2773  },
2774  {
2775    "EventCode": "0x9C",
2776    "UMask": "0x01",
2777    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
2778    "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
2779    "PublicDescription": "Cycles with less than 2 uops delivered by the front-end.",
2780    "Counter": "0,1,2,3",
2781    "CounterHTOff": "0,1,2,3,4,5,6,7",
2782    "SampleAfterValue": "2000003",
2783    "MSRIndex": "0",
2784    "MSRValue": "0",
2785    "TakenAlone": "0",
2786    "CounterMask": "2",
2787    "Invert": "0",
2788    "AnyThread": "0",
2789    "EdgeDetect": "0",
2790    "PEBS": "0",
2791    "Data_LA": "0",
2792    "L1_Hit_Indication": "0",
2793    "Errata": "0",
2794    "Offcore": "0"
2795  },
2796  {
2797    "EventCode": "0x9C",
2798    "UMask": "0x01",
2799    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
2800    "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
2801    "PublicDescription": "Cycles with less than 3 uops delivered by the front-end.",
2802    "Counter": "0,1,2,3",
2803    "CounterHTOff": "0,1,2,3,4,5,6,7",
2804    "SampleAfterValue": "2000003",
2805    "MSRIndex": "0",
2806    "MSRValue": "0",
2807    "TakenAlone": "0",
2808    "CounterMask": "1",
2809    "Invert": "0",
2810    "AnyThread": "0",
2811    "EdgeDetect": "0",
2812    "PEBS": "0",
2813    "Data_LA": "0",
2814    "L1_Hit_Indication": "0",
2815    "Errata": "0",
2816    "Offcore": "0"
2817  },
2818  {
2819    "EventCode": "0x9C",
2820    "UMask": "0x01",
2821    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
2822    "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
2823    "PublicDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
2824    "Counter": "0,1,2,3",
2825    "CounterHTOff": "0,1,2,3,4,5,6,7",
2826    "SampleAfterValue": "2000003",
2827    "MSRIndex": "0",
2828    "MSRValue": "0",
2829    "TakenAlone": "0",
2830    "CounterMask": "1",
2831    "Invert": "1",
2832    "AnyThread": "0",
2833    "EdgeDetect": "0",
2834    "PEBS": "0",
2835    "Data_LA": "0",
2836    "L1_Hit_Indication": "0",
2837    "Errata": "0",
2838    "Offcore": "0"
2839  },
2840  {
2841    "EventCode": "0xA1",
2842    "UMask": "0x01",
2843    "EventName": "UOPS_DISPATCHED_PORT.PORT_0",
2844    "BriefDescription": "Cycles per thread when uops are executed in port 0",
2845    "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.",
2846    "Counter": "0,1,2,3",
2847    "CounterHTOff": "0,1,2,3,4,5,6,7",
2848    "SampleAfterValue": "2000003",
2849    "MSRIndex": "0",
2850    "MSRValue": "0",
2851    "TakenAlone": "0",
2852    "CounterMask": "0",
2853    "Invert": "0",
2854    "AnyThread": "0",
2855    "EdgeDetect": "0",
2856    "PEBS": "0",
2857    "Data_LA": "0",
2858    "L1_Hit_Indication": "0",
2859    "Errata": "0",
2860    "Offcore": "0"
2861  },
2862  {
2863    "EventCode": "0xA1",
2864    "UMask": "0x02",
2865    "EventName": "UOPS_DISPATCHED_PORT.PORT_1",
2866    "BriefDescription": "Cycles per thread when uops are executed in port 1",
2867    "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.",
2868    "Counter": "0,1,2,3",
2869    "CounterHTOff": "0,1,2,3,4,5,6,7",
2870    "SampleAfterValue": "2000003",
2871    "MSRIndex": "0",
2872    "MSRValue": "0",
2873    "TakenAlone": "0",
2874    "CounterMask": "0",
2875    "Invert": "0",
2876    "AnyThread": "0",
2877    "EdgeDetect": "0",
2878    "PEBS": "0",
2879    "Data_LA": "0",
2880    "L1_Hit_Indication": "0",
2881    "Errata": "0",
2882    "Offcore": "0"
2883  },
2884  {
2885    "EventCode": "0xA1",
2886    "UMask": "0x04",
2887    "EventName": "UOPS_DISPATCHED_PORT.PORT_2",
2888    "BriefDescription": "Cycles per thread when uops are executed in port 2",
2889    "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 2.",
2890    "Counter": "0,1,2,3",
2891    "CounterHTOff": "0,1,2,3,4,5,6,7",
2892    "SampleAfterValue": "2000003",
2893    "MSRIndex": "0",
2894    "MSRValue": "0",
2895    "TakenAlone": "0",
2896    "CounterMask": "0",
2897    "Invert": "0",
2898    "AnyThread": "0",
2899    "EdgeDetect": "0",
2900    "PEBS": "0",
2901    "Data_LA": "0",
2902    "L1_Hit_Indication": "0",
2903    "Errata": "0",
2904    "Offcore": "0"
2905  },
2906  {
2907    "EventCode": "0xA1",
2908    "UMask": "0x08",
2909    "EventName": "UOPS_DISPATCHED_PORT.PORT_3",
2910    "BriefDescription": "Cycles per thread when uops are executed in port 3",
2911    "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 3.",
2912    "Counter": "0,1,2,3",
2913    "CounterHTOff": "0,1,2,3,4,5,6,7",
2914    "SampleAfterValue": "2000003",
2915    "MSRIndex": "0",
2916    "MSRValue": "0",
2917    "TakenAlone": "0",
2918    "CounterMask": "0",
2919    "Invert": "0",
2920    "AnyThread": "0",
2921    "EdgeDetect": "0",
2922    "PEBS": "0",
2923    "Data_LA": "0",
2924    "L1_Hit_Indication": "0",
2925    "Errata": "0",
2926    "Offcore": "0"
2927  },
2928  {
2929    "EventCode": "0xA1",
2930    "UMask": "0x10",
2931    "EventName": "UOPS_DISPATCHED_PORT.PORT_4",
2932    "BriefDescription": "Cycles per thread when uops are executed in port 4",
2933    "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 4.",
2934    "Counter": "0,1,2,3",
2935    "CounterHTOff": "0,1,2,3,4,5,6,7",
2936    "SampleAfterValue": "2000003",
2937    "MSRIndex": "0",
2938    "MSRValue": "0",
2939    "TakenAlone": "0",
2940    "CounterMask": "0",
2941    "Invert": "0",
2942    "AnyThread": "0",
2943    "EdgeDetect": "0",
2944    "PEBS": "0",
2945    "Data_LA": "0",
2946    "L1_Hit_Indication": "0",
2947    "Errata": "0",
2948    "Offcore": "0"
2949  },
2950  {
2951    "EventCode": "0xA1",
2952    "UMask": "0x20",
2953    "EventName": "UOPS_DISPATCHED_PORT.PORT_5",
2954    "BriefDescription": "Cycles per thread when uops are executed in port 5",
2955    "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.",
2956    "Counter": "0,1,2,3",
2957    "CounterHTOff": "0,1,2,3,4,5,6,7",
2958    "SampleAfterValue": "2000003",
2959    "MSRIndex": "0",
2960    "MSRValue": "0",
2961    "TakenAlone": "0",
2962    "CounterMask": "0",
2963    "Invert": "0",
2964    "AnyThread": "0",
2965    "EdgeDetect": "0",
2966    "PEBS": "0",
2967    "Data_LA": "0",
2968    "L1_Hit_Indication": "0",
2969    "Errata": "0",
2970    "Offcore": "0"
2971  },
2972  {
2973    "EventCode": "0xA1",
2974    "UMask": "0x40",
2975    "EventName": "UOPS_DISPATCHED_PORT.PORT_6",
2976    "BriefDescription": "Cycles per thread when uops are executed in port 6",
2977    "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.",
2978    "Counter": "0,1,2,3",
2979    "CounterHTOff": "0,1,2,3,4,5,6,7",
2980    "SampleAfterValue": "2000003",
2981    "MSRIndex": "0",
2982    "MSRValue": "0",
2983    "TakenAlone": "0",
2984    "CounterMask": "0",
2985    "Invert": "0",
2986    "AnyThread": "0",
2987    "EdgeDetect": "0",
2988    "PEBS": "0",
2989    "Data_LA": "0",
2990    "L1_Hit_Indication": "0",
2991    "Errata": "0",
2992    "Offcore": "0"
2993  },
2994  {
2995    "EventCode": "0xA1",
2996    "UMask": "0x80",
2997    "EventName": "UOPS_DISPATCHED_PORT.PORT_7",
2998    "BriefDescription": "Cycles per thread when uops are executed in port 7",
2999    "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 7.",
3000    "Counter": "0,1,2,3",
3001    "CounterHTOff": "0,1,2,3,4,5,6,7",
3002    "SampleAfterValue": "2000003",
3003    "MSRIndex": "0",
3004    "MSRValue": "0",
3005    "TakenAlone": "0",
3006    "CounterMask": "0",
3007    "Invert": "0",
3008    "AnyThread": "0",
3009    "EdgeDetect": "0",
3010    "PEBS": "0",
3011    "Data_LA": "0",
3012    "L1_Hit_Indication": "0",
3013    "Errata": "0",
3014    "Offcore": "0"
3015  },
3016  {
3017    "EventCode": "0xa2",
3018    "UMask": "0x01",
3019    "EventName": "RESOURCE_STALLS.ANY",
3020    "BriefDescription": "Resource-related stall cycles",
3021    "PublicDescription": "Counts resource-related stall cycles.",
3022    "Counter": "0,1,2,3",
3023    "CounterHTOff": "0,1,2,3,4,5,6,7",
3024    "SampleAfterValue": "2000003",
3025    "MSRIndex": "0",
3026    "MSRValue": "0",
3027    "TakenAlone": "0",
3028    "CounterMask": "0",
3029    "Invert": "0",
3030    "AnyThread": "0",
3031    "EdgeDetect": "0",
3032    "PEBS": "0",
3033    "Data_LA": "0",
3034    "L1_Hit_Indication": "0",
3035    "Errata": "0",
3036    "Offcore": "0"
3037  },
3038  {
3039    "EventCode": "0xA2",
3040    "UMask": "0x08",
3041    "EventName": "RESOURCE_STALLS.SB",
3042    "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
3043    "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
3044    "Counter": "0,1,2,3",
3045    "CounterHTOff": "0,1,2,3,4,5,6,7",
3046    "SampleAfterValue": "2000003",
3047    "MSRIndex": "0",
3048    "MSRValue": "0",
3049    "TakenAlone": "0",
3050    "CounterMask": "0",
3051    "Invert": "0",
3052    "AnyThread": "0",
3053    "EdgeDetect": "0",
3054    "PEBS": "0",
3055    "Data_LA": "0",
3056    "L1_Hit_Indication": "0",
3057    "Errata": "0",
3058    "Offcore": "0"
3059  },
3060  {
3061    "EventCode": "0xA3",
3062    "UMask": "0x01",
3063    "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
3064    "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
3065    "PublicDescription": "Cycles while L2 cache miss demand load is outstanding.",
3066    "Counter": "0,1,2,3",
3067    "CounterHTOff": "0,1,2,3,4,5,6,7",
3068    "SampleAfterValue": "2000003",
3069    "MSRIndex": "0",
3070    "MSRValue": "0",
3071    "TakenAlone": "0",
3072    "CounterMask": "1",
3073    "Invert": "0",
3074    "AnyThread": "0",
3075    "EdgeDetect": "0",
3076    "PEBS": "0",
3077    "Data_LA": "0",
3078    "L1_Hit_Indication": "0",
3079    "Errata": "0",
3080    "Offcore": "0"
3081  },
3082  {
3083    "EventCode": "0xA3",
3084    "UMask": "0x02",
3085    "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
3086    "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
3087    "PublicDescription": "Cycles while L3 cache miss demand load is outstanding.",
3088    "Counter": "0,1,2,3",
3089    "CounterHTOff": "0,1,2,3,4,5,6,7",
3090    "SampleAfterValue": "2000003",
3091    "MSRIndex": "0x00",
3092    "MSRValue": "0x00",
3093    "TakenAlone": "0",
3094    "CounterMask": "2",
3095    "Invert": "0",
3096    "AnyThread": "0",
3097    "EdgeDetect": "0",
3098    "PEBS": "0",
3099    "Data_LA": "0",
3100    "L1_Hit_Indication": "0",
3101    "Errata": "0",
3102    "Offcore": "0"
3103  },
3104  {
3105    "EventCode": "0xA3",
3106    "UMask": "0x04",
3107    "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
3108    "BriefDescription": "Total execution stalls.",
3109    "PublicDescription": "Total execution stalls.",
3110    "Counter": "0,1,2,3",
3111    "CounterHTOff": "0,1,2,3,4,5,6,7",
3112    "SampleAfterValue": "2000003",
3113    "MSRIndex": "0",
3114    "MSRValue": "0",
3115    "TakenAlone": "0",
3116    "CounterMask": "4",
3117    "Invert": "0",
3118    "AnyThread": "0",
3119    "EdgeDetect": "0",
3120    "PEBS": "0",
3121    "Data_LA": "0",
3122    "L1_Hit_Indication": "0",
3123    "Errata": "0",
3124    "Offcore": "0"
3125  },
3126  {
3127    "EventCode": "0xA3",
3128    "UMask": "0x05",
3129    "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
3130    "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
3131    "PublicDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
3132    "Counter": "0,1,2,3",
3133    "CounterHTOff": "0,1,2,3,4,5,6,7",
3134    "SampleAfterValue": "2000003",
3135    "MSRIndex": "0",
3136    "MSRValue": "0",
3137    "TakenAlone": "0",
3138    "CounterMask": "5",
3139    "Invert": "0",
3140    "AnyThread": "0",
3141    "EdgeDetect": "0",
3142    "PEBS": "0",
3143    "Data_LA": "0",
3144    "L1_Hit_Indication": "0",
3145    "Errata": "0",
3146    "Offcore": "0"
3147  },
3148  {
3149    "EventCode": "0xA3",
3150    "UMask": "0x06",
3151    "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
3152    "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
3153    "PublicDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
3154    "Counter": "0,1,2,3",
3155    "CounterHTOff": "0,1,2,3,4,5,6,7",
3156    "SampleAfterValue": "2000003",
3157    "MSRIndex": "0x00",
3158    "MSRValue": "0x00",
3159    "TakenAlone": "0",
3160    "CounterMask": "6",
3161    "Invert": "0",
3162    "AnyThread": "0",
3163    "EdgeDetect": "0",
3164    "PEBS": "0",
3165    "Data_LA": "0",
3166    "L1_Hit_Indication": "0",
3167    "Errata": "0",
3168    "Offcore": "0"
3169  },
3170  {
3171    "EventCode": "0xA3",
3172    "UMask": "0x08",
3173    "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
3174    "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
3175    "PublicDescription": "Cycles while L1 cache miss demand load is outstanding.",
3176    "Counter": "0,1,2,3",
3177    "CounterHTOff": "0,1,2,3,4,5,6,7",
3178    "SampleAfterValue": "2000003",
3179    "MSRIndex": "0",
3180    "MSRValue": "0",
3181    "TakenAlone": "0",
3182    "CounterMask": "8",
3183    "Invert": "0",
3184    "AnyThread": "0",
3185    "EdgeDetect": "0",
3186    "PEBS": "0",
3187    "Data_LA": "0",
3188    "L1_Hit_Indication": "0",
3189    "Errata": "0",
3190    "Offcore": "0"
3191  },
3192  {
3193    "EventCode": "0xA3",
3194    "UMask": "0x0C",
3195    "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
3196    "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
3197    "PublicDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
3198    "Counter": "0,1,2,3",
3199    "CounterHTOff": "0,1,2,3,4,5,6,7",
3200    "SampleAfterValue": "2000003",
3201    "MSRIndex": "0",
3202    "MSRValue": "0",
3203    "TakenAlone": "0",
3204    "CounterMask": "12",
3205    "Invert": "0",
3206    "AnyThread": "0",
3207    "EdgeDetect": "0",
3208    "PEBS": "0",
3209    "Data_LA": "0",
3210    "L1_Hit_Indication": "0",
3211    "Errata": "0",
3212    "Offcore": "0"
3213  },
3214  {
3215    "EventCode": "0xA3",
3216    "UMask": "0x10",
3217    "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
3218    "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
3219    "PublicDescription": "Cycles while memory subsystem has an outstanding load.",
3220    "Counter": "0,1,2,3",
3221    "CounterHTOff": "0,1,2,3,4,5,6,7",
3222    "SampleAfterValue": "2000003",
3223    "MSRIndex": "0",
3224    "MSRValue": "0",
3225    "TakenAlone": "0",
3226    "CounterMask": "16",
3227    "Invert": "0",
3228    "AnyThread": "0",
3229    "EdgeDetect": "0",
3230    "PEBS": "0",
3231    "Data_LA": "0",
3232    "L1_Hit_Indication": "0",
3233    "Errata": "0",
3234    "Offcore": "0"
3235  },
3236  {
3237    "EventCode": "0xA3",
3238    "UMask": "0x14",
3239    "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
3240    "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
3241    "PublicDescription": "Execution stalls while memory subsystem has an outstanding load.",
3242    "Counter": "0,1,2,3",
3243    "CounterHTOff": "0,1,2,3",
3244    "SampleAfterValue": "2000003",
3245    "MSRIndex": "0",
3246    "MSRValue": "0",
3247    "TakenAlone": "0",
3248    "CounterMask": "20",
3249    "Invert": "0",
3250    "AnyThread": "0",
3251    "EdgeDetect": "0",
3252    "PEBS": "0",
3253    "Data_LA": "0",
3254    "L1_Hit_Indication": "0",
3255    "Errata": "0",
3256    "Offcore": "0"
3257  },
3258  {
3259    "EventCode": "0xA6",
3260    "UMask": "0x01",
3261    "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS",
3262    "BriefDescription": "Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.",
3263    "PublicDescription": "Counts cycles during which no uops were executed on all ports and Reservation Station (RS) was not empty.",
3264    "Counter": "0,1,2,3",
3265    "CounterHTOff": "0,1,2,3,4,5,6,7",
3266    "SampleAfterValue": "2000003",
3267    "MSRIndex": "0",
3268    "MSRValue": "0",
3269    "TakenAlone": "0",
3270    "CounterMask": "0",
3271    "Invert": "0",
3272    "AnyThread": "0",
3273    "EdgeDetect": "0",
3274    "PEBS": "0",
3275    "Data_LA": "0",
3276    "L1_Hit_Indication": "0",
3277    "Errata": "0",
3278    "Offcore": "0"
3279  },
3280  {
3281    "EventCode": "0xA6",
3282    "UMask": "0x02",
3283    "EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
3284    "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
3285    "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.",
3286    "Counter": "0,1,2,3",
3287    "CounterHTOff": "0,1,2,3,4,5,6,7",
3288    "SampleAfterValue": "2000003",
3289    "MSRIndex": "0",
3290    "MSRValue": "0",
3291    "TakenAlone": "0",
3292    "CounterMask": "0",
3293    "Invert": "0",
3294    "AnyThread": "0",
3295    "EdgeDetect": "0",
3296    "PEBS": "0",
3297    "Data_LA": "0",
3298    "L1_Hit_Indication": "0",
3299    "Errata": "0",
3300    "Offcore": "0"
3301  },
3302  {
3303    "EventCode": "0xA6",
3304    "UMask": "0x04",
3305    "EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
3306    "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
3307    "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.",
3308    "Counter": "0,1,2,3",
3309    "CounterHTOff": "0,1,2,3,4,5,6,7",
3310    "SampleAfterValue": "2000003",
3311    "MSRIndex": "0",
3312    "MSRValue": "0",
3313    "TakenAlone": "0",
3314    "CounterMask": "0",
3315    "Invert": "0",
3316    "AnyThread": "0",
3317    "EdgeDetect": "0",
3318    "PEBS": "0",
3319    "Data_LA": "0",
3320    "L1_Hit_Indication": "0",
3321    "Errata": "0",
3322    "Offcore": "0"
3323  },
3324  {
3325    "EventCode": "0xA6",
3326    "UMask": "0x08",
3327    "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
3328    "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
3329    "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
3330    "Counter": "0,1,2,3",
3331    "CounterHTOff": "0,1,2,3,4,5,6,7",
3332    "SampleAfterValue": "2000003",
3333    "MSRIndex": "0",
3334    "MSRValue": "0",
3335    "TakenAlone": "0",
3336    "CounterMask": "0",
3337    "Invert": "0",
3338    "AnyThread": "0",
3339    "EdgeDetect": "0",
3340    "PEBS": "0",
3341    "Data_LA": "0",
3342    "L1_Hit_Indication": "0",
3343    "Errata": "0",
3344    "Offcore": "0"
3345  },
3346  {
3347    "EventCode": "0xA6",
3348    "UMask": "0x10",
3349    "EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
3350    "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
3351    "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.",
3352    "Counter": "0,1,2,3",
3353    "CounterHTOff": "0,1,2,3,4,5,6,7",
3354    "SampleAfterValue": "2000003",
3355    "MSRIndex": "0",
3356    "MSRValue": "0",
3357    "TakenAlone": "0",
3358    "CounterMask": "0",
3359    "Invert": "0",
3360    "AnyThread": "0",
3361    "EdgeDetect": "0",
3362    "PEBS": "0",
3363    "Data_LA": "0",
3364    "L1_Hit_Indication": "0",
3365    "Errata": "0",
3366    "Offcore": "0"
3367  },
3368  {
3369    "EventCode": "0xA6",
3370    "UMask": "0x40",
3371    "EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
3372    "BriefDescription": "Cycles where the Store Buffer was full and no outstanding load.",
3373    "PublicDescription": "Cycles where the Store Buffer was full and no outstanding load.",
3374    "Counter": "0,1,2,3",
3375    "CounterHTOff": "0,1,2,3,4,5,6,7",
3376    "SampleAfterValue": "2000003",
3377    "MSRIndex": "0",
3378    "MSRValue": "0",
3379    "TakenAlone": "0",
3380    "CounterMask": "0",
3381    "Invert": "0",
3382    "AnyThread": "0",
3383    "EdgeDetect": "0",
3384    "PEBS": "0",
3385    "Data_LA": "0",
3386    "L1_Hit_Indication": "0",
3387    "Errata": "0",
3388    "Offcore": "0"
3389  },
3390  {
3391    "EventCode": "0xA8",
3392    "UMask": "0x01",
3393    "EventName": "LSD.UOPS",
3394    "BriefDescription": "Number of Uops delivered by the LSD.",
3395    "PublicDescription": "Number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
3396    "Counter": "0,1,2,3",
3397    "CounterHTOff": "0,1,2,3,4,5,6,7",
3398    "SampleAfterValue": "2000003",
3399    "MSRIndex": "0",
3400    "MSRValue": "0",
3401    "TakenAlone": "0",
3402    "CounterMask": "0",
3403    "Invert": "0",
3404    "AnyThread": "0",
3405    "EdgeDetect": "0",
3406    "PEBS": "0",
3407    "Data_LA": "0",
3408    "L1_Hit_Indication": "0",
3409    "Errata": "0",
3410    "Offcore": "0"
3411  },
3412  {
3413    "EventCode": "0xA8",
3414    "UMask": "0x01",
3415    "EventName": "LSD.CYCLES_ACTIVE",
3416    "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
3417    "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
3418    "Counter": "0,1,2,3",
3419    "CounterHTOff": "0,1,2,3,4,5,6,7",
3420    "SampleAfterValue": "2000003",
3421    "MSRIndex": "0",
3422    "MSRValue": "0",
3423    "TakenAlone": "0",
3424    "CounterMask": "1",
3425    "Invert": "0",
3426    "AnyThread": "0",
3427    "EdgeDetect": "0",
3428    "PEBS": "0",
3429    "Data_LA": "0",
3430    "L1_Hit_Indication": "0",
3431    "Errata": "0",
3432    "Offcore": "0"
3433  },
3434  {
3435    "EventCode": "0xA8",
3436    "UMask": "0x01",
3437    "EventName": "LSD.CYCLES_4_UOPS",
3438    "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
3439    "PublicDescription": "Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector).",
3440    "Counter": "0,1,2,3",
3441    "CounterHTOff": "0,1,2,3,4,5,6,7",
3442    "SampleAfterValue": "2000003",
3443    "MSRIndex": "0",
3444    "MSRValue": "0x00",
3445    "TakenAlone": "0",
3446    "CounterMask": "4",
3447    "Invert": "0",
3448    "AnyThread": "0",
3449    "EdgeDetect": "0",
3450    "PEBS": "0",
3451    "Data_LA": "0",
3452    "L1_Hit_Indication": "0",
3453    "Errata": "0",
3454    "Offcore": "0"
3455  },
3456  {
3457    "EventCode": "0xAB",
3458    "UMask": "0x01",
3459    "EventName": "DSB2MITE_SWITCHES.COUNT",
3460    "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
3461    "PublicDescription": "This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses.\nNote: Invoking MITE requires two or three cycles delay.",
3462    "Counter": "0,1,2,3",
3463    "CounterHTOff": "0,1,2,3,4,5,6,7",
3464    "SampleAfterValue": "2000003",
3465    "MSRIndex": "0",
3466    "MSRValue": "0",
3467    "TakenAlone": "0",
3468    "CounterMask": "0",
3469    "Invert": "0",
3470    "AnyThread": "0",
3471    "EdgeDetect": "0",
3472    "PEBS": "0",
3473    "Data_LA": "0",
3474    "L1_Hit_Indication": "0",
3475    "Errata": "0",
3476    "Offcore": "0"
3477  },
3478  {
3479    "EventCode": "0xAB",
3480    "UMask": "0x02",
3481    "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
3482    "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
3483    "PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
3484    "Counter": "0,1,2,3",
3485    "CounterHTOff": "0,1,2,3,4,5,6,7",
3486    "SampleAfterValue": "2000003",
3487    "MSRIndex": "0",
3488    "MSRValue": "0",
3489    "TakenAlone": "0",
3490    "CounterMask": "0",
3491    "Invert": "0",
3492    "AnyThread": "0",
3493    "EdgeDetect": "0",
3494    "PEBS": "0",
3495    "Data_LA": "0",
3496    "L1_Hit_Indication": "0",
3497    "Errata": "0",
3498    "Offcore": "0"
3499  },
3500  {
3501    "EventCode": "0xAE",
3502    "UMask": "0x01",
3503    "EventName": "ITLB.ITLB_FLUSH",
3504    "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
3505    "PublicDescription": "Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
3506    "Counter": "0,1,2,3",
3507    "CounterHTOff": "0,1,2,3,4,5,6,7",
3508    "SampleAfterValue": "100007",
3509    "MSRIndex": "0",
3510    "MSRValue": "0",
3511    "TakenAlone": "0",
3512    "CounterMask": "0",
3513    "Invert": "0",
3514    "AnyThread": "0",
3515    "EdgeDetect": "0",
3516    "PEBS": "0",
3517    "Data_LA": "0",
3518    "L1_Hit_Indication": "0",
3519    "Errata": "0",
3520    "Offcore": "0"
3521  },
3522  {
3523    "EventCode": "0xB0",
3524    "UMask": "0x01",
3525    "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
3526    "BriefDescription": "Demand Data Read requests sent to uncore",
3527    "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
3528    "Counter": "0,1,2,3",
3529    "CounterHTOff": "0,1,2,3,4,5,6,7",
3530    "SampleAfterValue": "100003",
3531    "MSRIndex": "0",
3532    "MSRValue": "0",
3533    "TakenAlone": "0",
3534    "CounterMask": "0",
3535    "Invert": "0",
3536    "AnyThread": "0",
3537    "EdgeDetect": "0",
3538    "PEBS": "0",
3539    "Data_LA": "0",
3540    "L1_Hit_Indication": "0",
3541    "Errata": "0",
3542    "Offcore": "0"
3543  },
3544  {
3545    "EventCode": "0xB0",
3546    "UMask": "0x02",
3547    "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
3548    "BriefDescription": "Cacheable and noncachaeble code read requests",
3549    "PublicDescription": "Counts both cacheable and non-cacheable code read requests.",
3550    "Counter": "0,1,2,3",
3551    "CounterHTOff": "0,1,2,3,4,5,6,7",
3552    "SampleAfterValue": "100003",
3553    "MSRIndex": "0",
3554    "MSRValue": "0",
3555    "TakenAlone": "0",
3556    "CounterMask": "0",
3557    "Invert": "0",
3558    "AnyThread": "0",
3559    "EdgeDetect": "0",
3560    "PEBS": "0",
3561    "Data_LA": "0",
3562    "L1_Hit_Indication": "0",
3563    "Errata": "0",
3564    "Offcore": "0"
3565  },
3566  {
3567    "EventCode": "0xB0",
3568    "UMask": "0x04",
3569    "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
3570    "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
3571    "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
3572    "Counter": "0,1,2,3",
3573    "CounterHTOff": "0,1,2,3,4,5,6,7",
3574    "SampleAfterValue": "100003",
3575    "MSRIndex": "0",
3576    "MSRValue": "0",
3577    "TakenAlone": "0",
3578    "CounterMask": "0",
3579    "Invert": "0",
3580    "AnyThread": "0",
3581    "EdgeDetect": "0",
3582    "PEBS": "0",
3583    "Data_LA": "0",
3584    "L1_Hit_Indication": "0",
3585    "Errata": "0",
3586    "Offcore": "0"
3587  },
3588  {
3589    "EventCode": "0xB0",
3590    "UMask": "0x08",
3591    "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
3592    "BriefDescription": "Demand and prefetch data reads",
3593    "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
3594    "Counter": "0,1,2,3",
3595    "CounterHTOff": "0,1,2,3,4,5,6,7",
3596    "SampleAfterValue": "100003",
3597    "MSRIndex": "0",
3598    "MSRValue": "0",
3599    "TakenAlone": "0",
3600    "CounterMask": "0",
3601    "Invert": "0",
3602    "AnyThread": "0",
3603    "EdgeDetect": "0",
3604    "PEBS": "0",
3605    "Data_LA": "0",
3606    "L1_Hit_Indication": "0",
3607    "Errata": "0",
3608    "Offcore": "0"
3609  },
3610  {
3611    "EventCode": "0xB0",
3612    "UMask": "0x10",
3613    "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
3614    "BriefDescription": "Demand Data Read requests who miss L3 cache",
3615    "PublicDescription": "Demand Data Read requests who miss L3 cache.",
3616    "Counter": "0,1,2,3",
3617    "CounterHTOff": "0,1,2,3,4,5,6,7",
3618    "SampleAfterValue": "100003",
3619    "MSRIndex": "0",
3620    "MSRValue": "0",
3621    "TakenAlone": "0",
3622    "CounterMask": "0",
3623    "Invert": "0",
3624    "AnyThread": "0",
3625    "EdgeDetect": "0",
3626    "PEBS": "0",
3627    "Data_LA": "0",
3628    "L1_Hit_Indication": "0",
3629    "Errata": "0",
3630    "Offcore": "0"
3631  },
3632  {
3633    "EventCode": "0xB0",
3634    "UMask": "0x80",
3635    "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
3636    "BriefDescription": "Any memory transaction that reached the SQ.",
3637    "PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..",
3638    "Counter": "0,1,2,3",
3639    "CounterHTOff": "0,1,2,3,4,5,6,7",
3640    "SampleAfterValue": "100003",
3641    "MSRIndex": "0",
3642    "MSRValue": "0",
3643    "TakenAlone": "0",
3644    "CounterMask": "0",
3645    "Invert": "0",
3646    "AnyThread": "0",
3647    "EdgeDetect": "0",
3648    "PEBS": "0",
3649    "Data_LA": "0",
3650    "L1_Hit_Indication": "0",
3651    "Errata": "0",
3652    "Offcore": "0"
3653  },
3654  {
3655    "EventCode": "0xB1",
3656    "UMask": "0x01",
3657    "EventName": "UOPS_EXECUTED.THREAD",
3658    "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
3659    "PublicDescription": "Number of uops to be executed per-thread each cycle.",
3660    "Counter": "0,1,2,3",
3661    "CounterHTOff": "0,1,2,3,4,5,6,7",
3662    "SampleAfterValue": "2000003",
3663    "MSRIndex": "0",
3664    "MSRValue": "0",
3665    "TakenAlone": "0",
3666    "CounterMask": "0",
3667    "Invert": "0",
3668    "AnyThread": "0",
3669    "EdgeDetect": "0",
3670    "PEBS": "0",
3671    "Data_LA": "0",
3672    "L1_Hit_Indication": "0",
3673    "Errata": "0",
3674    "Offcore": "0"
3675  },
3676  {
3677    "EventCode": "0xB1",
3678    "UMask": "0x01",
3679    "EventName": "UOPS_EXECUTED.STALL_CYCLES",
3680    "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
3681    "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.",
3682    "Counter": "0,1,2,3",
3683    "CounterHTOff": "0,1,2,3,4,5,6,7",
3684    "SampleAfterValue": "2000003",
3685    "MSRIndex": "0",
3686    "MSRValue": "0",
3687    "TakenAlone": "0",
3688    "CounterMask": "1",
3689    "Invert": "1",
3690    "AnyThread": "0",
3691    "EdgeDetect": "0",
3692    "PEBS": "0",
3693    "Data_LA": "0",
3694    "L1_Hit_Indication": "0",
3695    "Errata": "0",
3696    "Offcore": "0"
3697  },
3698  {
3699    "EventCode": "0xB1",
3700    "UMask": "0x01",
3701    "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
3702    "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
3703    "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
3704    "Counter": "0,1,2,3",
3705    "CounterHTOff": "0,1,2,3,4,5,6,7",
3706    "SampleAfterValue": "2000003",
3707    "MSRIndex": "0",
3708    "MSRValue": "0",
3709    "TakenAlone": "0",
3710    "CounterMask": "1",
3711    "Invert": "0",
3712    "AnyThread": "0",
3713    "EdgeDetect": "0",
3714    "PEBS": "0",
3715    "Data_LA": "0",
3716    "L1_Hit_Indication": "0",
3717    "Errata": "0",
3718    "Offcore": "0"
3719  },
3720  {
3721    "EventCode": "0xB1",
3722    "UMask": "0x01",
3723    "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
3724    "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
3725    "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
3726    "Counter": "0,1,2,3",
3727    "CounterHTOff": "0,1,2,3,4,5,6,7",
3728    "SampleAfterValue": "2000003",
3729    "MSRIndex": "0",
3730    "MSRValue": "0",
3731    "TakenAlone": "0",
3732    "CounterMask": "2",
3733    "Invert": "0",
3734    "AnyThread": "0",
3735    "EdgeDetect": "0",
3736    "PEBS": "0",
3737    "Data_LA": "0",
3738    "L1_Hit_Indication": "0",
3739    "Errata": "0",
3740    "Offcore": "0"
3741  },
3742  {
3743    "EventCode": "0xB1",
3744    "UMask": "0x01",
3745    "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
3746    "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
3747    "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
3748    "Counter": "0,1,2,3",
3749    "CounterHTOff": "0,1,2,3,4,5,6,7",
3750    "SampleAfterValue": "2000003",
3751    "MSRIndex": "0",
3752    "MSRValue": "0",
3753    "TakenAlone": "0",
3754    "CounterMask": "3",
3755    "Invert": "0",
3756    "AnyThread": "0",
3757    "EdgeDetect": "0",
3758    "PEBS": "0",
3759    "Data_LA": "0",
3760    "L1_Hit_Indication": "0",
3761    "Errata": "0",
3762    "Offcore": "0"
3763  },
3764  {
3765    "EventCode": "0xB1",
3766    "UMask": "0x01",
3767    "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
3768    "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
3769    "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
3770    "Counter": "0,1,2,3",
3771    "CounterHTOff": "0,1,2,3,4,5,6,7",
3772    "SampleAfterValue": "2000003",
3773    "MSRIndex": "0",
3774    "MSRValue": "0",
3775    "TakenAlone": "0",
3776    "CounterMask": "4",
3777    "Invert": "0",
3778    "AnyThread": "0",
3779    "EdgeDetect": "0",
3780    "PEBS": "0",
3781    "Data_LA": "0",
3782    "L1_Hit_Indication": "0",
3783    "Errata": "0",
3784    "Offcore": "0"
3785  },
3786  {
3787    "EventCode": "0xB1",
3788    "UMask": "0x02",
3789    "EventName": "UOPS_EXECUTED.CORE",
3790    "BriefDescription": "Number of uops executed on the core.",
3791    "PublicDescription": "Number of uops executed from any thread.",
3792    "Counter": "0,1,2,3",
3793    "CounterHTOff": "0,1,2,3,4,5,6,7",
3794    "SampleAfterValue": "2000003",
3795    "MSRIndex": "0",
3796    "MSRValue": "0",
3797    "TakenAlone": "0",
3798    "CounterMask": "0",
3799    "Invert": "0",
3800    "AnyThread": "0",
3801    "EdgeDetect": "0",
3802    "PEBS": "0",
3803    "Data_LA": "0",
3804    "L1_Hit_Indication": "0",
3805    "Errata": "0",
3806    "Offcore": "0"
3807  },
3808  {
3809    "EventCode": "0xB1",
3810    "UMask": "0x02",
3811    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
3812    "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
3813    "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
3814    "Counter": "0,1,2,3",
3815    "CounterHTOff": "0,1,2,3,4,5,6,7",
3816    "SampleAfterValue": "2000003",
3817    "MSRIndex": "0",
3818    "MSRValue": "0",
3819    "TakenAlone": "0",
3820    "CounterMask": "1",
3821    "Invert": "0",
3822    "AnyThread": "0",
3823    "EdgeDetect": "0",
3824    "PEBS": "0",
3825    "Data_LA": "0",
3826    "L1_Hit_Indication": "0",
3827    "Errata": "0",
3828    "Offcore": "0"
3829  },
3830  {
3831    "EventCode": "0xB1",
3832    "UMask": "0x02",
3833    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
3834    "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
3835    "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
3836    "Counter": "0,1,2,3",
3837    "CounterHTOff": "0,1,2,3,4,5,6,7",
3838    "SampleAfterValue": "2000003",
3839    "MSRIndex": "0",
3840    "MSRValue": "0",
3841    "TakenAlone": "0",
3842    "CounterMask": "2",
3843    "Invert": "0",
3844    "AnyThread": "0",
3845    "EdgeDetect": "0",
3846    "PEBS": "0",
3847    "Data_LA": "0",
3848    "L1_Hit_Indication": "0",
3849    "Errata": "0",
3850    "Offcore": "0"
3851  },
3852  {
3853    "EventCode": "0xB1",
3854    "UMask": "0x02",
3855    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
3856    "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
3857    "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
3858    "Counter": "0,1,2,3",
3859    "CounterHTOff": "0,1,2,3,4,5,6,7",
3860    "SampleAfterValue": "2000003",
3861    "MSRIndex": "0",
3862    "MSRValue": "0",
3863    "TakenAlone": "0",
3864    "CounterMask": "3",
3865    "Invert": "0",
3866    "AnyThread": "0",
3867    "EdgeDetect": "0",
3868    "PEBS": "0",
3869    "Data_LA": "0",
3870    "L1_Hit_Indication": "0",
3871    "Errata": "0",
3872    "Offcore": "0"
3873  },
3874  {
3875    "EventCode": "0xB1",
3876    "UMask": "0x02",
3877    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
3878    "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
3879    "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
3880    "Counter": "0,1,2,3",
3881    "CounterHTOff": "0,1,2,3,4,5,6,7",
3882    "SampleAfterValue": "2000003",
3883    "MSRIndex": "0",
3884    "MSRValue": "0",
3885    "TakenAlone": "0",
3886    "CounterMask": "4",
3887    "Invert": "0",
3888    "AnyThread": "0",
3889    "EdgeDetect": "0",
3890    "PEBS": "0",
3891    "Data_LA": "0",
3892    "L1_Hit_Indication": "0",
3893    "Errata": "0",
3894    "Offcore": "0"
3895  },
3896  {
3897    "EventCode": "0xB1",
3898    "UMask": "0x02",
3899    "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
3900    "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
3901    "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core.",
3902    "Counter": "0,1,2,3",
3903    "CounterHTOff": "0,1,2,3,4,5,6,7",
3904    "SampleAfterValue": "2000003",
3905    "MSRIndex": "0",
3906    "MSRValue": "0",
3907    "TakenAlone": "0",
3908    "CounterMask": "1",
3909    "Invert": "1",
3910    "AnyThread": "0",
3911    "EdgeDetect": "0",
3912    "PEBS": "0",
3913    "Data_LA": "0",
3914    "L1_Hit_Indication": "0",
3915    "Errata": "0",
3916    "Offcore": "0"
3917  },
3918  {
3919    "EventCode": "0xB1",
3920    "UMask": "0x10",
3921    "EventName": "UOPS_EXECUTED.X87",
3922    "BriefDescription": "Counts the number of x87 uops dispatched.",
3923    "PublicDescription": "Counts the number of x87 uops executed.",
3924    "Counter": "0,1,2,3",
3925    "CounterHTOff": "0,1,2,3,4,5,6,7",
3926    "SampleAfterValue": "2000003",
3927    "MSRIndex": "0",
3928    "MSRValue": "0",
3929    "TakenAlone": "0",
3930    "CounterMask": "0",
3931    "Invert": "0",
3932    "AnyThread": "0",
3933    "EdgeDetect": "0",
3934    "PEBS": "0",
3935    "Data_LA": "0",
3936    "L1_Hit_Indication": "0",
3937    "Errata": "0",
3938    "Offcore": "0"
3939  },
3940  {
3941    "EventCode": "0xB2",
3942    "UMask": "0x01",
3943    "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
3944    "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
3945    "PublicDescription": "Counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.Note: Writeback pending FIFO has six entries.",
3946    "Counter": "0,1,2,3",
3947    "CounterHTOff": "0,1,2,3,4,5,6,7",
3948    "SampleAfterValue": "2000003",
3949    "MSRIndex": "0",
3950    "MSRValue": "0",
3951    "TakenAlone": "0",
3952    "CounterMask": "0",
3953    "Invert": "0",
3954    "AnyThread": "0",
3955    "EdgeDetect": "0",
3956    "PEBS": "0",
3957    "Data_LA": "0",
3958    "L1_Hit_Indication": "0",
3959    "Errata": "0",
3960    "Offcore": "0"
3961  },
3962  {
3963    "EventCode": "0xB7, 0xBB",
3964    "UMask": "0x01",
3965    "EventName": "OFFCORE_RESPONSE",
3966    "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction",
3967    "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
3968    "Counter": "0,1,2,3",
3969    "CounterHTOff": "0,1,2,3",
3970    "SampleAfterValue": "100003",
3971    "MSRIndex": "0",
3972    "MSRValue": "0",
3973    "TakenAlone": "0",
3974    "CounterMask": "0",
3975    "Invert": "0",
3976    "AnyThread": "0",
3977    "EdgeDetect": "0",
3978    "PEBS": "0",
3979    "Data_LA": "0",
3980    "L1_Hit_Indication": "0",
3981    "Errata": "null",
3982    "Offcore": "0"
3983  },
3984  {
3985    "EventCode": "0xBD",
3986    "UMask": "0x01",
3987    "EventName": "TLB_FLUSH.DTLB_THREAD",
3988    "BriefDescription": "DTLB flush attempts of the thread-specific entries",
3989    "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
3990    "Counter": "0,1,2,3",
3991    "CounterHTOff": "0,1,2,3,4,5,6,7",
3992    "SampleAfterValue": "100007",
3993    "MSRIndex": "0",
3994    "MSRValue": "0",
3995    "TakenAlone": "0",
3996    "CounterMask": "0",
3997    "Invert": "0",
3998    "AnyThread": "0",
3999    "EdgeDetect": "0",
4000    "PEBS": "0",
4001    "Data_LA": "0",
4002    "L1_Hit_Indication": "0",
4003    "Errata": "0",
4004    "Offcore": "0"
4005  },
4006  {
4007    "EventCode": "0xBD",
4008    "UMask": "0x20",
4009    "EventName": "TLB_FLUSH.STLB_ANY",
4010    "BriefDescription": "STLB flush attempts",
4011    "PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).",
4012    "Counter": "0,1,2,3",
4013    "CounterHTOff": "0,1,2,3,4,5,6,7",
4014    "SampleAfterValue": "100007",
4015    "MSRIndex": "0",
4016    "MSRValue": "0",
4017    "TakenAlone": "0",
4018    "CounterMask": "0",
4019    "Invert": "0",
4020    "AnyThread": "0",
4021    "EdgeDetect": "0",
4022    "PEBS": "0",
4023    "Data_LA": "0",
4024    "L1_Hit_Indication": "0",
4025    "Errata": "0",
4026    "Offcore": "0"
4027  },
4028  {
4029    "EventCode": "0xC0",
4030    "UMask": "0x00",
4031    "EventName": "INST_RETIRED.ANY_P",
4032    "BriefDescription": "Number of instructions retired. General Counter - architectural event",
4033    "PublicDescription": "Counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).",
4034    "Counter": "0,1,2,3",
4035    "CounterHTOff": "0,1,2,3,4,5,6,7",
4036    "SampleAfterValue": "2000003",
4037    "MSRIndex": "0",
4038    "MSRValue": "0",
4039    "TakenAlone": "0",
4040    "CounterMask": "0",
4041    "Invert": "0",
4042    "AnyThread": "0",
4043    "EdgeDetect": "0",
4044    "PEBS": "0",
4045    "Data_LA": "0",
4046    "L1_Hit_Indication": "0",
4047    "Errata": "SKL091, SKL044",
4048    "Offcore": "0"
4049  },
4050  {
4051    "EventCode": "0xC0",
4052    "UMask": "0x01",
4053    "EventName": "INST_RETIRED.PREC_DIST",
4054    "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
4055    "PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled.",
4056    "Counter": "1",
4057    "CounterHTOff": "1",
4058    "SampleAfterValue": "2000003",
4059    "MSRIndex": "0",
4060    "MSRValue": "0",
4061    "TakenAlone": "0",
4062    "CounterMask": "0",
4063    "Invert": "0",
4064    "AnyThread": "0",
4065    "EdgeDetect": "0",
4066    "PEBS": "2",
4067    "Data_LA": "0",
4068    "L1_Hit_Indication": "0",
4069    "Errata": "SKL091, SKL044",
4070    "Offcore": "0"
4071  },
4072  {
4073    "EventCode": "0xC0",
4074    "UMask": "0x01",
4075    "EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
4076    "BriefDescription": "Number of cycles using always true condition applied to  PEBS instructions retired event.",
4077    "PublicDescription": "Number of cycles using an always true condition applied to  PEBS instructions retired event. (inst_ret< 16)",
4078    "Counter": "0,2,3",
4079    "CounterHTOff": "0,2,3",
4080    "SampleAfterValue": "2000003",
4081    "MSRIndex": "0",
4082    "MSRValue": "0",
4083    "TakenAlone": "0",
4084    "CounterMask": "10",
4085    "Invert": "1",
4086    "AnyThread": "0",
4087    "EdgeDetect": "0",
4088    "PEBS": "2",
4089    "Data_LA": "0",
4090    "L1_Hit_Indication": "0",
4091    "Errata": "SKL091, SKL044",
4092    "Offcore": "0"
4093  },
4094  {
4095    "EventCode": "0xC1",
4096    "UMask": "0x3F",
4097    "EventName": "OTHER_ASSISTS.ANY",
4098    "BriefDescription": "Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists.",
4099    "PublicDescription": "Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists.",
4100    "Counter": "0,1,2,3",
4101    "CounterHTOff": "0,1,2,3,4,5,6,7",
4102    "SampleAfterValue": "100003",
4103    "MSRIndex": "0x00",
4104    "MSRValue": "0x00",
4105    "TakenAlone": "0",
4106    "CounterMask": "0",
4107    "Invert": "0",
4108    "AnyThread": "0",
4109    "EdgeDetect": "0",
4110    "PEBS": "0",
4111    "Data_LA": "0",
4112    "L1_Hit_Indication": "0",
4113    "Errata": "0",
4114    "Offcore": "0"
4115  },
4116  {
4117    "EventCode": "0xC2",
4118    "UMask": "0x02",
4119    "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
4120    "BriefDescription": "Retirement slots used.",
4121    "PublicDescription": "Counts the retirement slots used.",
4122    "Counter": "0,1,2,3",
4123    "CounterHTOff": "0,1,2,3,4,5,6,7",
4124    "SampleAfterValue": "2000003",
4125    "MSRIndex": "0",
4126    "MSRValue": "0",
4127    "TakenAlone": "0",
4128    "CounterMask": "0",
4129    "Invert": "0",
4130    "AnyThread": "0",
4131    "EdgeDetect": "0",
4132    "PEBS": "0",
4133    "Data_LA": "0",
4134    "L1_Hit_Indication": "0",
4135    "Errata": "0",
4136    "Offcore": "0"
4137  },
4138  {
4139    "EventCode": "0xC2",
4140    "UMask": "0x02",
4141    "EventName": "UOPS_RETIRED.STALL_CYCLES",
4142    "BriefDescription": "Cycles without actually retired uops.",
4143    "PublicDescription": "This event counts cycles without actually retired uops.",
4144    "Counter": "0,1,2,3",
4145    "CounterHTOff": "0,1,2,3,4,5,6,7",
4146    "SampleAfterValue": "2000003",
4147    "MSRIndex": "0",
4148    "MSRValue": "0",
4149    "TakenAlone": "0",
4150    "CounterMask": "1",
4151    "Invert": "1",
4152    "AnyThread": "0",
4153    "EdgeDetect": "0",
4154    "PEBS": "0",
4155    "Data_LA": "0",
4156    "L1_Hit_Indication": "0",
4157    "Errata": "0",
4158    "Offcore": "0"
4159  },
4160  {
4161    "EventCode": "0xC2",
4162    "UMask": "0x02",
4163    "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
4164    "BriefDescription": "Cycles with less than 10 actually retired uops.",
4165    "PublicDescription": "Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.",
4166    "Counter": "0,1,2,3",
4167    "CounterHTOff": "0,1,2,3,4,5,6,7",
4168    "SampleAfterValue": "2000003",
4169    "MSRIndex": "0",
4170    "MSRValue": "0",
4171    "TakenAlone": "0",
4172    "CounterMask": "10",
4173    "Invert": "1",
4174    "AnyThread": "0",
4175    "EdgeDetect": "0",
4176    "PEBS": "0",
4177    "Data_LA": "0",
4178    "L1_Hit_Indication": "0",
4179    "Errata": "0",
4180    "Offcore": "0"
4181  },
4182  {
4183    "EventCode": "0xc2",
4184    "UMask": "0x04",
4185    "EventName": "UOPS_RETIRED.MACRO_FUSED",
4186    "BriefDescription": "Number of macro-fused uops retired. (non precise)",
4187    "PublicDescription": "Counts the number of macro-fused uops retired. (non precise)",
4188    "Counter": "0,1,2,3",
4189    "CounterHTOff": "0,1,2,3,4,5,6,7",
4190    "SampleAfterValue": "2000003",
4191    "MSRIndex": "0",
4192    "MSRValue": "0",
4193    "TakenAlone": "0",
4194    "CounterMask": "0",
4195    "Invert": "0",
4196    "AnyThread": "0",
4197    "EdgeDetect": "0",
4198    "PEBS": "0",
4199    "Data_LA": "0",
4200    "L1_Hit_Indication": "0",
4201    "Errata": "0",
4202    "Offcore": "0"
4203  },
4204  {
4205    "EventCode": "0xC3",
4206    "UMask": "0x01",
4207    "EventName": "MACHINE_CLEARS.COUNT",
4208    "BriefDescription": "Number of machine clears (nukes) of any type.",
4209    "PublicDescription": "Number of machine clears (nukes) of any type.",
4210    "Counter": "0,1,2,3",
4211    "CounterHTOff": "0,1,2,3,4,5,6,7",
4212    "SampleAfterValue": "100003",
4213    "MSRIndex": "0",
4214    "MSRValue": "0",
4215    "TakenAlone": "0",
4216    "CounterMask": "1",
4217    "Invert": "0",
4218    "AnyThread": "0",
4219    "EdgeDetect": "1",
4220    "PEBS": "0",
4221    "Data_LA": "0",
4222    "L1_Hit_Indication": "0",
4223    "Errata": "0",
4224    "Offcore": "0"
4225  },
4226  {
4227    "EventCode": "0xC3",
4228    "UMask": "0x02",
4229    "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
4230    "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
4231    "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.",
4232    "Counter": "0,1,2,3",
4233    "CounterHTOff": "0,1,2,3,4,5,6,7",
4234    "SampleAfterValue": "100003",
4235    "MSRIndex": "0",
4236    "MSRValue": "0",
4237    "TakenAlone": "0",
4238    "CounterMask": "0",
4239    "Invert": "0",
4240    "AnyThread": "0",
4241    "EdgeDetect": "0",
4242    "PEBS": "0",
4243    "Data_LA": "0",
4244    "L1_Hit_Indication": "0",
4245    "Errata": "SKL089",
4246    "Offcore": "0"
4247  },
4248  {
4249    "EventCode": "0xC3",
4250    "UMask": "0x04",
4251    "EventName": "MACHINE_CLEARS.SMC",
4252    "BriefDescription": "Self-modifying code (SMC) detected.",
4253    "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
4254    "Counter": "0,1,2,3",
4255    "CounterHTOff": "0,1,2,3,4,5,6,7",
4256    "SampleAfterValue": "100003",
4257    "MSRIndex": "0",
4258    "MSRValue": "0",
4259    "TakenAlone": "0",
4260    "CounterMask": "0",
4261    "Invert": "0",
4262    "AnyThread": "0",
4263    "EdgeDetect": "0",
4264    "PEBS": "0",
4265    "Data_LA": "0",
4266    "L1_Hit_Indication": "0",
4267    "Errata": "0",
4268    "Offcore": "0"
4269  },
4270  {
4271    "EventCode": "0xC4",
4272    "UMask": "0x00",
4273    "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
4274    "BriefDescription": "All (macro) branch instructions retired.",
4275    "PublicDescription": "Counts all (macro) branch instructions retired.",
4276    "Counter": "0,1,2,3",
4277    "CounterHTOff": "0,1,2,3,4,5,6,7",
4278    "SampleAfterValue": "400009",
4279    "MSRIndex": "0",
4280    "MSRValue": "0",
4281    "TakenAlone": "0",
4282    "CounterMask": "0",
4283    "Invert": "0",
4284    "AnyThread": "0",
4285    "EdgeDetect": "0",
4286    "PEBS": "0",
4287    "Data_LA": "0",
4288    "L1_Hit_Indication": "0",
4289    "Errata": "SKL091",
4290    "Offcore": "0"
4291  },
4292  {
4293    "EventCode": "0xC4",
4294    "UMask": "0x01",
4295    "EventName": "BR_INST_RETIRED.CONDITIONAL",
4296    "BriefDescription": "Conditional branch instructions retired.",
4297    "PublicDescription": "This event counts conditional branch instructions retired.",
4298    "Counter": "0,1,2,3",
4299    "CounterHTOff": "0,1,2,3,4,5,6,7",
4300    "SampleAfterValue": "400009",
4301    "MSRIndex": "0",
4302    "MSRValue": "0",
4303    "TakenAlone": "0",
4304    "CounterMask": "0",
4305    "Invert": "0",
4306    "AnyThread": "0",
4307    "EdgeDetect": "0",
4308    "PEBS": "1",
4309    "Data_LA": "0",
4310    "L1_Hit_Indication": "0",
4311    "Errata": "SKL091",
4312    "Offcore": "0"
4313  },
4314  {
4315    "EventCode": "0xC4",
4316    "UMask": "0x02",
4317    "EventName": "BR_INST_RETIRED.NEAR_CALL",
4318    "BriefDescription": "Direct and indirect near call instructions retired.",
4319    "PublicDescription": "This event counts both direct and indirect near call instructions retired.",
4320    "Counter": "0,1,2,3",
4321    "CounterHTOff": "0,1,2,3,4,5,6,7",
4322    "SampleAfterValue": "100007",
4323    "MSRIndex": "0",
4324    "MSRValue": "0",
4325    "TakenAlone": "0",
4326    "CounterMask": "0",
4327    "Invert": "0",
4328    "AnyThread": "0",
4329    "EdgeDetect": "0",
4330    "PEBS": "1",
4331    "Data_LA": "0",
4332    "L1_Hit_Indication": "0",
4333    "Errata": "SKL091",
4334    "Offcore": "0"
4335  },
4336  {
4337    "EventCode": "0xC4",
4338    "UMask": "0x04",
4339    "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
4340    "BriefDescription": "All (macro) branch instructions retired.",
4341    "PublicDescription": "This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.",
4342    "Counter": "0,1,2,3",
4343    "CounterHTOff": "0,1,2,3",
4344    "SampleAfterValue": "400009",
4345    "MSRIndex": "0",
4346    "MSRValue": "0",
4347    "TakenAlone": "0",
4348    "CounterMask": "0",
4349    "Invert": "0",
4350    "AnyThread": "0",
4351    "EdgeDetect": "0",
4352    "PEBS": "2",
4353    "Data_LA": "0",
4354    "L1_Hit_Indication": "0",
4355    "Errata": "SKL091",
4356    "Offcore": "0"
4357  },
4358  {
4359    "EventCode": "0xC4",
4360    "UMask": "0x08",
4361    "EventName": "BR_INST_RETIRED.NEAR_RETURN",
4362    "BriefDescription": "Return instructions retired.",
4363    "PublicDescription": "This event counts return instructions retired.",
4364    "Counter": "0,1,2,3",
4365    "CounterHTOff": "0,1,2,3,4,5,6,7",
4366    "SampleAfterValue": "100007",
4367    "MSRIndex": "0",
4368    "MSRValue": "0",
4369    "TakenAlone": "0",
4370    "CounterMask": "0",
4371    "Invert": "0",
4372    "AnyThread": "0",
4373    "EdgeDetect": "0",
4374    "PEBS": "1",
4375    "Data_LA": "0",
4376    "L1_Hit_Indication": "0",
4377    "Errata": "SKL091",
4378    "Offcore": "0"
4379  },
4380  {
4381    "EventCode": "0xC4",
4382    "UMask": "0x10",
4383    "EventName": "BR_INST_RETIRED.NOT_TAKEN",
4384    "BriefDescription": "Not taken branch instructions retired.",
4385    "PublicDescription": "This event counts not taken branch instructions retired.",
4386    "Counter": "0,1,2,3",
4387    "CounterHTOff": "0,1,2,3,4,5,6,7",
4388    "SampleAfterValue": "400009",
4389    "MSRIndex": "0",
4390    "MSRValue": "0",
4391    "TakenAlone": "0",
4392    "CounterMask": "0",
4393    "Invert": "0",
4394    "AnyThread": "0",
4395    "EdgeDetect": "0",
4396    "PEBS": "0",
4397    "Data_LA": "0",
4398    "L1_Hit_Indication": "0",
4399    "Errata": "SKL091",
4400    "Offcore": "0"
4401  },
4402  {
4403    "EventCode": "0xc4",
4404    "UMask": "0x10",
4405    "EventName": "BR_INST_RETIRED.COND_NTAKEN",
4406    "BriefDescription": "Not taken branch instructions retired.",
4407    "PublicDescription": "This event counts not taken branch instructions retired.",
4408    "Counter": "0,1,2,3",
4409    "CounterHTOff": "0,1,2,3,4,5,6,7",
4410    "SampleAfterValue": "400009",
4411    "MSRIndex": "0",
4412    "MSRValue": "0",
4413    "TakenAlone": "0",
4414    "CounterMask": "0",
4415    "Invert": "0",
4416    "AnyThread": "0",
4417    "EdgeDetect": "0",
4418    "PEBS": "0",
4419    "Data_LA": "0",
4420    "L1_Hit_Indication": "0",
4421    "Errata": "SKL091",
4422    "Offcore": "0"
4423  },
4424  {
4425    "EventCode": "0xC4",
4426    "UMask": "0x20",
4427    "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
4428    "BriefDescription": "Taken branch instructions retired.",
4429    "PublicDescription": "This event counts taken branch instructions retired.",
4430    "Counter": "0,1,2,3",
4431    "CounterHTOff": "0,1,2,3,4,5,6,7",
4432    "SampleAfterValue": "400009",
4433    "MSRIndex": "0",
4434    "MSRValue": "0",
4435    "TakenAlone": "0",
4436    "CounterMask": "0",
4437    "Invert": "0",
4438    "AnyThread": "0",
4439    "EdgeDetect": "0",
4440    "PEBS": "1",
4441    "Data_LA": "0",
4442    "L1_Hit_Indication": "0",
4443    "Errata": "SKL091",
4444    "Offcore": "0"
4445  },
4446  {
4447    "EventCode": "0xC4",
4448    "UMask": "0x40",
4449    "EventName": "BR_INST_RETIRED.FAR_BRANCH",
4450    "BriefDescription": "Far branch instructions retired.",
4451    "PublicDescription": "This event counts far branch instructions retired.",
4452    "Counter": "0,1,2,3",
4453    "CounterHTOff": "0,1,2,3,4,5,6,7",
4454    "SampleAfterValue": "100007",
4455    "MSRIndex": "0",
4456    "MSRValue": "0",
4457    "TakenAlone": "0",
4458    "CounterMask": "0",
4459    "Invert": "0",
4460    "AnyThread": "0",
4461    "EdgeDetect": "0",
4462    "PEBS": "1",
4463    "Data_LA": "0",
4464    "L1_Hit_Indication": "0",
4465    "Errata": "SKL091",
4466    "Offcore": "0"
4467  },
4468  {
4469    "EventCode": "0xC5",
4470    "UMask": "0x00",
4471    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
4472    "BriefDescription": "All mispredicted macro branch instructions retired.",
4473    "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch.  When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.",
4474    "Counter": "0,1,2,3",
4475    "CounterHTOff": "0,1,2,3,4,5,6,7",
4476    "SampleAfterValue": "400009",
4477    "MSRIndex": "0",
4478    "MSRValue": "0",
4479    "TakenAlone": "0",
4480    "CounterMask": "0",
4481    "Invert": "0",
4482    "AnyThread": "0",
4483    "EdgeDetect": "0",
4484    "PEBS": "0",
4485    "Data_LA": "0",
4486    "L1_Hit_Indication": "0",
4487    "Errata": "0",
4488    "Offcore": "0"
4489  },
4490  {
4491    "EventCode": "0xC5",
4492    "UMask": "0x01",
4493    "EventName": "BR_MISP_RETIRED.CONDITIONAL",
4494    "BriefDescription": "Mispredicted conditional branch instructions retired.",
4495    "PublicDescription": "This event counts mispredicted conditional branch instructions retired.",
4496    "Counter": "0,1,2,3",
4497    "CounterHTOff": "0,1,2,3,4,5,6,7",
4498    "SampleAfterValue": "400009",
4499    "MSRIndex": "0",
4500    "MSRValue": "0",
4501    "TakenAlone": "0",
4502    "CounterMask": "0",
4503    "Invert": "0",
4504    "AnyThread": "0",
4505    "EdgeDetect": "0",
4506    "PEBS": "1",
4507    "Data_LA": "0",
4508    "L1_Hit_Indication": "0",
4509    "Errata": "0",
4510    "Offcore": "0"
4511  },
4512  {
4513    "EventCode": "0xC5",
4514    "UMask": "0x02",
4515    "EventName": "BR_MISP_RETIRED.NEAR_CALL",
4516    "BriefDescription": "Mispredicted direct and indirect near call instructions retired.",
4517    "PublicDescription": "Counts both taken and not taken retired mispredicted direct and indirect near calls, including both register and memory indirect.",
4518    "Counter": "0,1,2,3",
4519    "CounterHTOff": "0,1,2,3,4,5,6,7",
4520    "SampleAfterValue": "400009",
4521    "MSRIndex": "0",
4522    "MSRValue": "0",
4523    "TakenAlone": "0",
4524    "CounterMask": "0",
4525    "Invert": "0",
4526    "AnyThread": "0",
4527    "EdgeDetect": "0",
4528    "PEBS": "1",
4529    "Data_LA": "0",
4530    "L1_Hit_Indication": "0",
4531    "Errata": "0",
4532    "Offcore": "0"
4533  },
4534  {
4535    "EventCode": "0xC5",
4536    "UMask": "0x04",
4537    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
4538    "BriefDescription": "Mispredicted macro branch instructions retired.",
4539    "PublicDescription": "This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired.",
4540    "Counter": "0,1,2,3",
4541    "CounterHTOff": "0,1,2,3",
4542    "SampleAfterValue": "400009",
4543    "MSRIndex": "0",
4544    "MSRValue": "0",
4545    "TakenAlone": "0",
4546    "CounterMask": "0",
4547    "Invert": "0",
4548    "AnyThread": "0",
4549    "EdgeDetect": "0",
4550    "PEBS": "2",
4551    "Data_LA": "0",
4552    "L1_Hit_Indication": "0",
4553    "Errata": "0",
4554    "Offcore": "0"
4555  },
4556  {
4557    "EventCode": "0xC5",
4558    "UMask": "0x20",
4559    "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
4560    "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
4561    "PublicDescription": "Number of near branch instructions retired that were mispredicted and taken.",
4562    "Counter": "0,1,2,3",
4563    "CounterHTOff": "0,1,2,3,4,5,6,7",
4564    "SampleAfterValue": "400009",
4565    "MSRIndex": "0",
4566    "MSRValue": "0",
4567    "TakenAlone": "0",
4568    "CounterMask": "0",
4569    "Invert": "0",
4570    "AnyThread": "0",
4571    "EdgeDetect": "0",
4572    "PEBS": "1",
4573    "Data_LA": "0",
4574    "L1_Hit_Indication": "0",
4575    "Errata": "0",
4576    "Offcore": "0"
4577  },
4578  {
4579    "EventCode": "0xC6",
4580    "UMask": "0x01",
4581    "EventName": "FRONTEND_RETIRED.DSB_MISS",
4582    "BriefDescription": "Retired Instructions who experienced decode stream buffer (DSB - the decoded instruction-cache) miss.",
4583    "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. ",
4584    "Counter": "0,1,2,3",
4585    "CounterHTOff": "0,1,2,3",
4586    "SampleAfterValue": "100007",
4587    "MSRIndex": "0x3F7",
4588    "MSRValue": "0x11",
4589    "TakenAlone": "1",
4590    "CounterMask": "0",
4591    "Invert": "0",
4592    "AnyThread": "0",
4593    "EdgeDetect": "0",
4594    "PEBS": "1",
4595    "Data_LA": "0",
4596    "L1_Hit_Indication": "0",
4597    "Errata": "0",
4598    "Offcore": "0"
4599  },
4600  {
4601    "EventCode": "0xC6",
4602    "UMask": "0x01",
4603    "EventName": "FRONTEND_RETIRED.L1I_MISS",
4604    "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
4605    "PublicDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
4606    "Counter": "0,1,2,3",
4607    "CounterHTOff": "0,1,2,3",
4608    "SampleAfterValue": "100007",
4609    "MSRIndex": "0x3F7",
4610    "MSRValue": "0x12",
4611    "TakenAlone": "1",
4612    "CounterMask": "0",
4613    "Invert": "0",
4614    "AnyThread": "0",
4615    "EdgeDetect": "0",
4616    "PEBS": "1",
4617    "Data_LA": "0",
4618    "L1_Hit_Indication": "0",
4619    "Errata": "0",
4620    "Offcore": "0"
4621  },
4622  {
4623    "EventCode": "0xC6",
4624    "UMask": "0x01",
4625    "EventName": "FRONTEND_RETIRED.L2_MISS",
4626    "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
4627    "PublicDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
4628    "Counter": "0,1,2,3",
4629    "CounterHTOff": "0,1,2,3",
4630    "SampleAfterValue": "100007",
4631    "MSRIndex": "0x3F7",
4632    "MSRValue": "0x13",
4633    "TakenAlone": "1",
4634    "CounterMask": "0",
4635    "Invert": "0",
4636    "AnyThread": "0",
4637    "EdgeDetect": "0",
4638    "PEBS": "1",
4639    "Data_LA": "0",
4640    "L1_Hit_Indication": "0",
4641    "Errata": "0",
4642    "Offcore": "0"
4643  },
4644  {
4645    "EventCode": "0xC6",
4646    "UMask": "0x01",
4647    "EventName": "FRONTEND_RETIRED.ITLB_MISS",
4648    "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
4649    "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.",
4650    "Counter": "0,1,2,3",
4651    "CounterHTOff": "0,1,2,3",
4652    "SampleAfterValue": "100007",
4653    "MSRIndex": "0x3F7",
4654    "MSRValue": "0x14",
4655    "TakenAlone": "1",
4656    "CounterMask": "0",
4657    "Invert": "0",
4658    "AnyThread": "0",
4659    "EdgeDetect": "0",
4660    "PEBS": "1",
4661    "Data_LA": "0",
4662    "L1_Hit_Indication": "0",
4663    "Errata": "0",
4664    "Offcore": "0"
4665  },
4666  {
4667    "EventCode": "0xC6",
4668    "UMask": "0x01",
4669    "EventName": "FRONTEND_RETIRED.STLB_MISS",
4670    "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
4671    "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss. ",
4672    "Counter": "0,1,2,3",
4673    "CounterHTOff": "0,1,2,3",
4674    "SampleAfterValue": "100007",
4675    "MSRIndex": "0x3F7",
4676    "MSRValue": "0x15",
4677    "TakenAlone": "1",
4678    "CounterMask": "0",
4679    "Invert": "0",
4680    "AnyThread": "0",
4681    "EdgeDetect": "0",
4682    "PEBS": "1",
4683    "Data_LA": "0",
4684    "L1_Hit_Indication": "0",
4685    "Errata": "0",
4686    "Offcore": "0"
4687  },
4688  {
4689    "EventCode": "0xC6",
4690    "UMask": "0x01",
4691    "EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
4692    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.",
4693    "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.",
4694    "Counter": "0,1,2,3",
4695    "CounterHTOff": "0,1,2,3",
4696    "SampleAfterValue": "100007",
4697    "MSRIndex": "0x3F7",
4698    "MSRValue": "0x400206",
4699    "TakenAlone": "1",
4700    "CounterMask": "0",
4701    "Invert": "0",
4702    "AnyThread": "0",
4703    "EdgeDetect": "0",
4704    "PEBS": "1",
4705    "Data_LA": "0",
4706    "L1_Hit_Indication": "0",
4707    "Errata": "0",
4708    "Offcore": "0"
4709  },
4710  {
4711    "EventCode": "0xC6",
4712    "UMask": "0x01",
4713    "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2",
4714    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",
4715    "PublicDescription": "Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",
4716    "Counter": "0,1,2,3",
4717    "CounterHTOff": "0,1,2,3",
4718    "SampleAfterValue": "100007",
4719    "MSRIndex": "0x3F7",
4720    "MSRValue": "0x200206",
4721    "TakenAlone": "1",
4722    "CounterMask": "0",
4723    "Invert": "0",
4724    "AnyThread": "0",
4725    "EdgeDetect": "0",
4726    "PEBS": "1",
4727    "Data_LA": "0",
4728    "L1_Hit_Indication": "0",
4729    "Errata": "0",
4730    "Offcore": "0"
4731  },
4732  {
4733    "EventCode": "0xC6",
4734    "UMask": "0x01",
4735    "EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
4736    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
4737    "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
4738    "Counter": "0,1,2,3",
4739    "CounterHTOff": "0,1,2,3",
4740    "SampleAfterValue": "100007",
4741    "MSRIndex": "0x3F7",
4742    "MSRValue": "0x400406",
4743    "TakenAlone": "1",
4744    "CounterMask": "0",
4745    "Invert": "0",
4746    "AnyThread": "0",
4747    "EdgeDetect": "0",
4748    "PEBS": "1",
4749    "Data_LA": "0",
4750    "L1_Hit_Indication": "0",
4751    "Errata": "0",
4752    "Offcore": "0"
4753  },
4754  {
4755    "EventCode": "0xC6",
4756    "UMask": "0x01",
4757    "EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
4758    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
4759    "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.",
4760    "Counter": "0,1,2,3",
4761    "CounterHTOff": "0,1,2,3",
4762    "SampleAfterValue": "100007",
4763    "MSRIndex": "0x3F7",
4764    "MSRValue": "0x400806",
4765    "TakenAlone": "1",
4766    "CounterMask": "0",
4767    "Invert": "0",
4768    "AnyThread": "0",
4769    "EdgeDetect": "0",
4770    "PEBS": "1",
4771    "Data_LA": "0",
4772    "L1_Hit_Indication": "0",
4773    "Errata": "0",
4774    "Offcore": "0"
4775  },
4776  {
4777    "EventCode": "0xC6",
4778    "UMask": "0x01",
4779    "EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
4780    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
4781    "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.",
4782    "Counter": "0,1,2,3",
4783    "CounterHTOff": "0,1,2,3",
4784    "SampleAfterValue": "100007",
4785    "MSRIndex": "0x3F7",
4786    "MSRValue": "0x401006",
4787    "TakenAlone": "1",
4788    "CounterMask": "0",
4789    "Invert": "0",
4790    "AnyThread": "0",
4791    "EdgeDetect": "0",
4792    "PEBS": "1",
4793    "Data_LA": "0",
4794    "L1_Hit_Indication": "0",
4795    "Errata": "0",
4796    "Offcore": "0"
4797  },
4798  {
4799    "EventCode": "0xC6",
4800    "UMask": "0x01",
4801    "EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
4802    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
4803    "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.",
4804    "Counter": "0,1,2,3",
4805    "CounterHTOff": "0,1,2,3",
4806    "SampleAfterValue": "100007",
4807    "MSRIndex": "0x3F7",
4808    "MSRValue": "0x402006",
4809    "TakenAlone": "1",
4810    "CounterMask": "0",
4811    "Invert": "0",
4812    "AnyThread": "0",
4813    "EdgeDetect": "0",
4814    "PEBS": "1",
4815    "Data_LA": "0",
4816    "L1_Hit_Indication": "0",
4817    "Errata": "0",
4818    "Offcore": "0"
4819  },
4820  {
4821    "EventCode": "0xC6",
4822    "UMask": "0x01",
4823    "EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
4824    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
4825    "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
4826    "Counter": "0,1,2,3",
4827    "CounterHTOff": "0,1,2,3",
4828    "SampleAfterValue": "100007",
4829    "MSRIndex": "0x3F7",
4830    "MSRValue": "0x404006",
4831    "TakenAlone": "1",
4832    "CounterMask": "0",
4833    "Invert": "0",
4834    "AnyThread": "0",
4835    "EdgeDetect": "0",
4836    "PEBS": "1",
4837    "Data_LA": "0",
4838    "L1_Hit_Indication": "0",
4839    "Errata": "0",
4840    "Offcore": "0"
4841  },
4842  {
4843    "EventCode": "0xC6",
4844    "UMask": "0x01",
4845    "EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
4846    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
4847    "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
4848    "Counter": "0,1,2,3",
4849    "CounterHTOff": "0,1,2,3",
4850    "SampleAfterValue": "100007",
4851    "MSRIndex": "0x3F7",
4852    "MSRValue": "0x408006",
4853    "TakenAlone": "1",
4854    "CounterMask": "0",
4855    "Invert": "0",
4856    "AnyThread": "0",
4857    "EdgeDetect": "0",
4858    "PEBS": "1",
4859    "Data_LA": "0",
4860    "L1_Hit_Indication": "0",
4861    "Errata": "0",
4862    "Offcore": "0"
4863  },
4864  {
4865    "EventCode": "0xC6",
4866    "UMask": "0x01",
4867    "EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
4868    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
4869    "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
4870    "Counter": "0,1,2,3",
4871    "CounterHTOff": "0,1,2,3",
4872    "SampleAfterValue": "100007",
4873    "MSRIndex": "0x3F7",
4874    "MSRValue": "0x410006",
4875    "TakenAlone": "1",
4876    "CounterMask": "0",
4877    "Invert": "0",
4878    "AnyThread": "0",
4879    "EdgeDetect": "0",
4880    "PEBS": "1",
4881    "Data_LA": "0",
4882    "L1_Hit_Indication": "0",
4883    "Errata": "0",
4884    "Offcore": "0"
4885  },
4886  {
4887    "EventCode": "0xC6",
4888    "UMask": "0x01",
4889    "EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
4890    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
4891    "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
4892    "Counter": "0,1,2,3",
4893    "CounterHTOff": "0,1,2,3",
4894    "SampleAfterValue": "100007",
4895    "MSRIndex": "0x3F7",
4896    "MSRValue": "0x420006",
4897    "TakenAlone": "1",
4898    "CounterMask": "0",
4899    "Invert": "0",
4900    "AnyThread": "0",
4901    "EdgeDetect": "0",
4902    "PEBS": "1",
4903    "Data_LA": "0",
4904    "L1_Hit_Indication": "0",
4905    "Errata": "0",
4906    "Offcore": "0"
4907  },
4908  {
4909    "EventCode": "0xC6",
4910    "UMask": "0x01",
4911    "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
4912    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
4913    "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.",
4914    "Counter": "0,1,2,3",
4915    "CounterHTOff": "0,1,2,3",
4916    "SampleAfterValue": "100007",
4917    "MSRIndex": "0x3F7",
4918    "MSRValue": "0x100206",
4919    "TakenAlone": "1",
4920    "CounterMask": "0",
4921    "Invert": "0",
4922    "AnyThread": "0",
4923    "EdgeDetect": "0",
4924    "PEBS": "1",
4925    "Data_LA": "0",
4926    "L1_Hit_Indication": "0",
4927    "Errata": "0",
4928    "Offcore": "0"
4929  },
4930  {
4931    "EventCode": "0xC6",
4932    "UMask": "0x01",
4933    "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3",
4934    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",
4935    "PublicDescription": "Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",
4936    "Counter": "0,1,2,3",
4937    "CounterHTOff": "0,1,2,3",
4938    "SampleAfterValue": "100007",
4939    "MSRIndex": "0x3F7",
4940    "MSRValue": "0x300206",
4941    "TakenAlone": "1",
4942    "CounterMask": "0",
4943    "Invert": "0",
4944    "AnyThread": "0",
4945    "EdgeDetect": "0",
4946    "PEBS": "1",
4947    "Data_LA": "0",
4948    "L1_Hit_Indication": "0",
4949    "Errata": "0",
4950    "Offcore": "0"
4951  },
4952  {
4953    "EventCode": "0xc6",
4954    "UMask": "0x01",
4955    "EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
4956    "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
4957    "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.",
4958    "Counter": "0,1,2,3",
4959    "CounterHTOff": "0,1,2,3",
4960    "SampleAfterValue": "100007",
4961    "MSRIndex": "0x3F7",
4962    "MSRValue": "0x400106",
4963    "TakenAlone": "1",
4964    "CounterMask": "0",
4965    "Invert": "0",
4966    "AnyThread": "0",
4967    "EdgeDetect": "0",
4968    "PEBS": "2",
4969    "Data_LA": "0",
4970    "L1_Hit_Indication": "0",
4971    "Errata": "0",
4972    "Offcore": "0"
4973  },
4974  {
4975    "EventCode": "0xC7",
4976    "UMask": "0x01",
4977    "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
4978    "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
4979    "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
4980    "Counter": "0,1,2,3",
4981    "CounterHTOff": "0,1,2,3,4,5,6,7",
4982    "SampleAfterValue": "2000003",
4983    "MSRIndex": "0",
4984    "MSRValue": "0",
4985    "TakenAlone": "0",
4986    "CounterMask": "0",
4987    "Invert": "0",
4988    "AnyThread": "0",
4989    "EdgeDetect": "0",
4990    "PEBS": "0",
4991    "Data_LA": "0",
4992    "L1_Hit_Indication": "0",
4993    "Errata": "0",
4994    "Offcore": "0"
4995  },
4996  {
4997    "EventCode": "0xC7",
4998    "UMask": "0x02",
4999    "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
5000    "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
5001    "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
5002    "Counter": "0,1,2,3",
5003    "CounterHTOff": "0,1,2,3,4,5,6,7",
5004    "SampleAfterValue": "2000003",
5005    "MSRIndex": "0",
5006    "MSRValue": "0",
5007    "TakenAlone": "0",
5008    "CounterMask": "0",
5009    "Invert": "0",
5010    "AnyThread": "0",
5011    "EdgeDetect": "0",
5012    "PEBS": "0",
5013    "Data_LA": "0",
5014    "L1_Hit_Indication": "0",
5015    "Errata": "0",
5016    "Offcore": "0"
5017  },
5018  {
5019    "EventCode": "0xC7",
5020    "UMask": "0x04",
5021    "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
5022    "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
5023    "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
5024    "Counter": "0,1,2,3",
5025    "CounterHTOff": "0,1,2,3,4,5,6,7",
5026    "SampleAfterValue": "2000003",
5027    "MSRIndex": "0",
5028    "MSRValue": "0",
5029    "TakenAlone": "0",
5030    "CounterMask": "0",
5031    "Invert": "0",
5032    "AnyThread": "0",
5033    "EdgeDetect": "0",
5034    "PEBS": "0",
5035    "Data_LA": "0",
5036    "L1_Hit_Indication": "0",
5037    "Errata": "0",
5038    "Offcore": "0"
5039  },
5040  {
5041    "EventCode": "0xC7",
5042    "UMask": "0x08",
5043    "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
5044    "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
5045    "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
5046    "Counter": "0,1,2,3",
5047    "CounterHTOff": "0,1,2,3,4,5,6,7",
5048    "SampleAfterValue": "2000003",
5049    "MSRIndex": "0",
5050    "MSRValue": "0",
5051    "TakenAlone": "0",
5052    "CounterMask": "0",
5053    "Invert": "0",
5054    "AnyThread": "0",
5055    "EdgeDetect": "0",
5056    "PEBS": "0",
5057    "Data_LA": "0",
5058    "L1_Hit_Indication": "0",
5059    "Errata": "0",
5060    "Offcore": "0"
5061  },
5062  {
5063    "EventCode": "0xC7",
5064    "UMask": "0x10",
5065    "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
5066    "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
5067    "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
5068    "Counter": "0,1,2,3",
5069    "CounterHTOff": "0,1,2,3,4,5,6,7",
5070    "SampleAfterValue": "2000003",
5071    "MSRIndex": "0",
5072    "MSRValue": "0",
5073    "TakenAlone": "0",
5074    "CounterMask": "0",
5075    "Invert": "0",
5076    "AnyThread": "0",
5077    "EdgeDetect": "0",
5078    "PEBS": "0",
5079    "Data_LA": "0",
5080    "L1_Hit_Indication": "0",
5081    "Errata": "0",
5082    "Offcore": "0"
5083  },
5084  {
5085    "EventCode": "0xC7",
5086    "UMask": "0x20",
5087    "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
5088    "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
5089    "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
5090    "Counter": "0,1,2,3",
5091    "CounterHTOff": "0,1,2,3,4,5,6,7",
5092    "SampleAfterValue": "2000003",
5093    "MSRIndex": "0",
5094    "MSRValue": "0",
5095    "TakenAlone": "0",
5096    "CounterMask": "0",
5097    "Invert": "0",
5098    "AnyThread": "0",
5099    "EdgeDetect": "0",
5100    "PEBS": "0",
5101    "Data_LA": "0",
5102    "L1_Hit_Indication": "0",
5103    "Errata": "0",
5104    "Offcore": "0"
5105  },
5106  {
5107    "EventCode": "0xC8",
5108    "UMask": "0x01",
5109    "EventName": "HLE_RETIRED.START",
5110    "BriefDescription": "Number of times an HLE execution started.",
5111    "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.",
5112    "Counter": "0,1,2,3",
5113    "CounterHTOff": "0,1,2,3,4,5,6,7",
5114    "SampleAfterValue": "2000003",
5115    "MSRIndex": "0",
5116    "MSRValue": "0",
5117    "TakenAlone": "0",
5118    "CounterMask": "0",
5119    "Invert": "0",
5120    "AnyThread": "0",
5121    "EdgeDetect": "0",
5122    "PEBS": "0",
5123    "Data_LA": "0",
5124    "L1_Hit_Indication": "0",
5125    "Errata": "0",
5126    "Offcore": "0"
5127  },
5128  {
5129    "EventCode": "0xC8",
5130    "UMask": "0x02",
5131    "EventName": "HLE_RETIRED.COMMIT",
5132    "BriefDescription": "Number of times an HLE execution successfully committed",
5133    "PublicDescription": "Number of times HLE commit succeeded.",
5134    "Counter": "0,1,2,3",
5135    "CounterHTOff": "0,1,2,3,4,5,6,7",
5136    "SampleAfterValue": "2000003",
5137    "MSRIndex": "0",
5138    "MSRValue": "0",
5139    "TakenAlone": "0",
5140    "CounterMask": "0",
5141    "Invert": "0",
5142    "AnyThread": "0",
5143    "EdgeDetect": "0",
5144    "PEBS": "0",
5145    "Data_LA": "0",
5146    "L1_Hit_Indication": "0",
5147    "Errata": "0",
5148    "Offcore": "0"
5149  },
5150  {
5151    "EventCode": "0xC8",
5152    "UMask": "0x04",
5153    "EventName": "HLE_RETIRED.ABORTED",
5154    "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one). ",
5155    "PublicDescription": "Number of times HLE abort was triggered.",
5156    "Counter": "0,1,2,3",
5157    "CounterHTOff": "0,1,2,3,4,5,6,7",
5158    "SampleAfterValue": "2000003",
5159    "MSRIndex": "0",
5160    "MSRValue": "0",
5161    "TakenAlone": "0",
5162    "CounterMask": "0",
5163    "Invert": "0",
5164    "AnyThread": "0",
5165    "EdgeDetect": "0",
5166    "PEBS": "1",
5167    "Data_LA": "0",
5168    "L1_Hit_Indication": "0",
5169    "Errata": "0",
5170    "Offcore": "0"
5171  },
5172  {
5173    "EventCode": "0xC8",
5174    "UMask": "0x08",
5175    "EventName": "HLE_RETIRED.ABORTED_MEM",
5176    "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
5177    "PublicDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
5178    "Counter": "0,1,2,3",
5179    "CounterHTOff": "0,1,2,3,4,5,6,7",
5180    "SampleAfterValue": "2000003",
5181    "MSRIndex": "0",
5182    "MSRValue": "0",
5183    "TakenAlone": "0",
5184    "CounterMask": "0",
5185    "Invert": "0",
5186    "AnyThread": "0",
5187    "EdgeDetect": "0",
5188    "PEBS": "0",
5189    "Data_LA": "0",
5190    "L1_Hit_Indication": "0",
5191    "Errata": "0",
5192    "Offcore": "0"
5193  },
5194  {
5195    "EventCode": "0xC8",
5196    "UMask": "0x10",
5197    "EventName": "HLE_RETIRED.ABORTED_TIMER",
5198    "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.",
5199    "PublicDescription": "Number of times an HLE execution aborted due to hardware timer expiration.",
5200    "Counter": "0,1,2,3",
5201    "CounterHTOff": "0,1,2,3,4,5,6,7",
5202    "SampleAfterValue": "2000003",
5203    "MSRIndex": "0",
5204    "MSRValue": "0",
5205    "TakenAlone": "0",
5206    "CounterMask": "0",
5207    "Invert": "0",
5208    "AnyThread": "0",
5209    "EdgeDetect": "0",
5210    "PEBS": "0",
5211    "Data_LA": "0",
5212    "L1_Hit_Indication": "0",
5213    "Errata": "0",
5214    "Offcore": "0"
5215  },
5216  {
5217    "EventCode": "0xC8",
5218    "UMask": "0x20",
5219    "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY",
5220    "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
5221    "PublicDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
5222    "Counter": "0,1,2,3",
5223    "CounterHTOff": "0,1,2,3,4,5,6,7",
5224    "SampleAfterValue": "2000003",
5225    "MSRIndex": "0",
5226    "MSRValue": "0",
5227    "TakenAlone": "0",
5228    "CounterMask": "0",
5229    "Invert": "0",
5230    "AnyThread": "0",
5231    "EdgeDetect": "0",
5232    "PEBS": "0",
5233    "Data_LA": "0",
5234    "L1_Hit_Indication": "0",
5235    "Errata": "0",
5236    "Offcore": "0"
5237  },
5238  {
5239    "EventCode": "0xC8",
5240    "UMask": "0x40",
5241    "EventName": "HLE_RETIRED.ABORTED_MEMTYPE",
5242    "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
5243    "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.",
5244    "Counter": "0,1,2,3",
5245    "CounterHTOff": "0,1,2,3,4,5,6,7",
5246    "SampleAfterValue": "2000003",
5247    "MSRIndex": "0",
5248    "MSRValue": "0",
5249    "TakenAlone": "0",
5250    "CounterMask": "0",
5251    "Invert": "0",
5252    "AnyThread": "0",
5253    "EdgeDetect": "0",
5254    "PEBS": "0",
5255    "Data_LA": "0",
5256    "L1_Hit_Indication": "0",
5257    "Errata": "0",
5258    "Offcore": "0"
5259  },
5260  {
5261    "EventCode": "0xC8",
5262    "UMask": "0x80",
5263    "EventName": "HLE_RETIRED.ABORTED_EVENTS",
5264    "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
5265    "PublicDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
5266    "Counter": "0,1,2,3",
5267    "CounterHTOff": "0,1,2,3,4,5,6,7",
5268    "SampleAfterValue": "2000003",
5269    "MSRIndex": "0",
5270    "MSRValue": "0",
5271    "TakenAlone": "0",
5272    "CounterMask": "0",
5273    "Invert": "0",
5274    "AnyThread": "0",
5275    "EdgeDetect": "0",
5276    "PEBS": "0",
5277    "Data_LA": "0",
5278    "L1_Hit_Indication": "0",
5279    "Errata": "0",
5280    "Offcore": "0"
5281  },
5282  {
5283    "EventCode": "0xC9",
5284    "UMask": "0x01",
5285    "EventName": "RTM_RETIRED.START",
5286    "BriefDescription": "Number of times an RTM execution started.",
5287    "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.",
5288    "Counter": "0,1,2,3",
5289    "CounterHTOff": "0,1,2,3,4,5,6,7",
5290    "SampleAfterValue": "2000003",
5291    "MSRIndex": "0",
5292    "MSRValue": "0",
5293    "TakenAlone": "0",
5294    "CounterMask": "0",
5295    "Invert": "0",
5296    "AnyThread": "0",
5297    "EdgeDetect": "0",
5298    "PEBS": "0",
5299    "Data_LA": "0",
5300    "L1_Hit_Indication": "0",
5301    "Errata": "0",
5302    "Offcore": "0"
5303  },
5304  {
5305    "EventCode": "0xC9",
5306    "UMask": "0x02",
5307    "EventName": "RTM_RETIRED.COMMIT",
5308    "BriefDescription": "Number of times an RTM execution successfully committed",
5309    "PublicDescription": "Number of times RTM commit succeeded.",
5310    "Counter": "0,1,2,3",
5311    "CounterHTOff": "0,1,2,3,4,5,6,7",
5312    "SampleAfterValue": "2000003",
5313    "MSRIndex": "0",
5314    "MSRValue": "0",
5315    "TakenAlone": "0",
5316    "CounterMask": "0",
5317    "Invert": "0",
5318    "AnyThread": "0",
5319    "EdgeDetect": "0",
5320    "PEBS": "0",
5321    "Data_LA": "0",
5322    "L1_Hit_Indication": "0",
5323    "Errata": "0",
5324    "Offcore": "0"
5325  },
5326  {
5327    "EventCode": "0xC9",
5328    "UMask": "0x04",
5329    "EventName": "RTM_RETIRED.ABORTED",
5330    "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one). ",
5331    "PublicDescription": "Number of times RTM abort was triggered.",
5332    "Counter": "0,1,2,3",
5333    "CounterHTOff": "0,1,2,3,4,5,6,7",
5334    "SampleAfterValue": "2000003",
5335    "MSRIndex": "0",
5336    "MSRValue": "0",
5337    "TakenAlone": "0",
5338    "CounterMask": "0",
5339    "Invert": "0",
5340    "AnyThread": "0",
5341    "EdgeDetect": "0",
5342    "PEBS": "1",
5343    "Data_LA": "0",
5344    "L1_Hit_Indication": "0",
5345    "Errata": "0",
5346    "Offcore": "0"
5347  },
5348  {
5349    "EventCode": "0xC9",
5350    "UMask": "0x08",
5351    "EventName": "RTM_RETIRED.ABORTED_MEM",
5352    "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
5353    "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
5354    "Counter": "0,1,2,3",
5355    "CounterHTOff": "0,1,2,3,4,5,6,7",
5356    "SampleAfterValue": "2000003",
5357    "MSRIndex": "0",
5358    "MSRValue": "0",
5359    "TakenAlone": "0",
5360    "CounterMask": "0",
5361    "Invert": "0",
5362    "AnyThread": "0",
5363    "EdgeDetect": "0",
5364    "PEBS": "0",
5365    "Data_LA": "0",
5366    "L1_Hit_Indication": "0",
5367    "Errata": "0",
5368    "Offcore": "0"
5369  },
5370  {
5371    "EventCode": "0xC9",
5372    "UMask": "0x10",
5373    "EventName": "RTM_RETIRED.ABORTED_TIMER",
5374    "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.",
5375    "PublicDescription": "Number of times an RTM execution aborted due to uncommon conditions.",
5376    "Counter": "0,1,2,3",
5377    "CounterHTOff": "0,1,2,3,4,5,6,7",
5378    "SampleAfterValue": "2000003",
5379    "MSRIndex": "0",
5380    "MSRValue": "0",
5381    "TakenAlone": "0",
5382    "CounterMask": "0",
5383    "Invert": "0",
5384    "AnyThread": "0",
5385    "EdgeDetect": "0",
5386    "PEBS": "0",
5387    "Data_LA": "0",
5388    "L1_Hit_Indication": "0",
5389    "Errata": "0",
5390    "Offcore": "0"
5391  },
5392  {
5393    "EventCode": "0xC9",
5394    "UMask": "0x20",
5395    "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
5396    "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
5397    "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.",
5398    "Counter": "0,1,2,3",
5399    "CounterHTOff": "0,1,2,3,4,5,6,7",
5400    "SampleAfterValue": "2000003",
5401    "MSRIndex": "0",
5402    "MSRValue": "0",
5403    "TakenAlone": "0",
5404    "CounterMask": "0",
5405    "Invert": "0",
5406    "AnyThread": "0",
5407    "EdgeDetect": "0",
5408    "PEBS": "0",
5409    "Data_LA": "0",
5410    "L1_Hit_Indication": "0",
5411    "Errata": "0",
5412    "Offcore": "0"
5413  },
5414  {
5415    "EventCode": "0xC9",
5416    "UMask": "0x40",
5417    "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
5418    "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
5419    "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.",
5420    "Counter": "0,1,2,3",
5421    "CounterHTOff": "0,1,2,3,4,5,6,7",
5422    "SampleAfterValue": "2000003",
5423    "MSRIndex": "0",
5424    "MSRValue": "0",
5425    "TakenAlone": "0",
5426    "CounterMask": "0",
5427    "Invert": "0",
5428    "AnyThread": "0",
5429    "EdgeDetect": "0",
5430    "PEBS": "0",
5431    "Data_LA": "0",
5432    "L1_Hit_Indication": "0",
5433    "Errata": "0",
5434    "Offcore": "0"
5435  },
5436  {
5437    "EventCode": "0xC9",
5438    "UMask": "0x80",
5439    "EventName": "RTM_RETIRED.ABORTED_EVENTS",
5440    "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
5441    "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
5442    "Counter": "0,1,2,3",
5443    "CounterHTOff": "0,1,2,3,4,5,6,7",
5444    "SampleAfterValue": "2000003",
5445    "MSRIndex": "0",
5446    "MSRValue": "0",
5447    "TakenAlone": "0",
5448    "CounterMask": "0",
5449    "Invert": "0",
5450    "AnyThread": "0",
5451    "EdgeDetect": "0",
5452    "PEBS": "0",
5453    "Data_LA": "0",
5454    "L1_Hit_Indication": "0",
5455    "Errata": "0",
5456    "Offcore": "0"
5457  },
5458  {
5459    "EventCode": "0xCA",
5460    "UMask": "0x1E",
5461    "EventName": "FP_ASSIST.ANY",
5462    "BriefDescription": "Cycles with any input/output SSE or FP assist",
5463    "PublicDescription": "Counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.",
5464    "Counter": "0,1,2,3",
5465    "CounterHTOff": "0,1,2,3,4,5,6,7",
5466    "SampleAfterValue": "100003",
5467    "MSRIndex": "0",
5468    "MSRValue": "0",
5469    "TakenAlone": "0",
5470    "CounterMask": "1",
5471    "Invert": "0",
5472    "AnyThread": "0",
5473    "EdgeDetect": "0",
5474    "PEBS": "0",
5475    "Data_LA": "0",
5476    "L1_Hit_Indication": "0",
5477    "Errata": "0",
5478    "Offcore": "0"
5479  },
5480  {
5481    "EventCode": "0xCB",
5482    "UMask": "0x01",
5483    "EventName": "HW_INTERRUPTS.RECEIVED",
5484    "BriefDescription": "Number of hardware interrupts received by the processor.",
5485    "PublicDescription": "Counts the number of hardware interruptions received by the processor.",
5486    "Counter": "0,1,2,3",
5487    "CounterHTOff": "0,1,2,3,4,5,6,7",
5488    "SampleAfterValue": "203",
5489    "MSRIndex": "0",
5490    "MSRValue": "0",
5491    "TakenAlone": "0",
5492    "CounterMask": "0",
5493    "Invert": "0",
5494    "AnyThread": "0",
5495    "EdgeDetect": "0",
5496    "PEBS": "0",
5497    "Data_LA": "0",
5498    "L1_Hit_Indication": "0",
5499    "Errata": "0",
5500    "Offcore": "0"
5501  },
5502  {
5503    "EventCode": "0xCC",
5504    "UMask": "0x20",
5505    "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
5506    "BriefDescription": "Increments whenever there is an update to the LBR array.",
5507    "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.",
5508    "Counter": "0,1,2,3",
5509    "CounterHTOff": "0,1,2,3,4,5,6,7",
5510    "SampleAfterValue": "2000003",
5511    "MSRIndex": "0",
5512    "MSRValue": "0",
5513    "TakenAlone": "0",
5514    "CounterMask": "0",
5515    "Invert": "0",
5516    "AnyThread": "0",
5517    "EdgeDetect": "0",
5518    "PEBS": "0",
5519    "Data_LA": "0",
5520    "L1_Hit_Indication": "0",
5521    "Errata": "0",
5522    "Offcore": "0"
5523  },
5524  {
5525    "EventCode": "0xCC",
5526    "UMask": "0x40",
5527    "EventName": "ROB_MISC_EVENTS.PAUSE_INST",
5528    "BriefDescription": "Number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted). This event is not supported on first SKL and KBL products.",
5529    "PublicDescription": "Number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted). This event is not supported on first SKL and KBL products.",
5530    "Counter": "0,1,2,3",
5531    "CounterHTOff": "0,1,2,3,4,5,6,7",
5532    "SampleAfterValue": "2000003",
5533    "MSRIndex": "0",
5534    "MSRValue": "0",
5535    "TakenAlone": "0",
5536    "CounterMask": "0",
5537    "Invert": "0",
5538    "AnyThread": "0",
5539    "EdgeDetect": "0",
5540    "PEBS": "0",
5541    "Data_LA": "0",
5542    "L1_Hit_Indication": "0",
5543    "Errata": "0",
5544    "Offcore": "0"
5545  },
5546  {
5547    "EventCode": "0xcd",
5548    "UMask": "0x01",
5549    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
5550    "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
5551    "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency.",
5552    "Counter": "0,1,2,3",
5553    "CounterHTOff": "0,1,2,3",
5554    "SampleAfterValue": "100003",
5555    "MSRIndex": "0x3F6",
5556    "MSRValue": "0x4",
5557    "TakenAlone": "1",
5558    "CounterMask": "0",
5559    "Invert": "0",
5560    "AnyThread": "0",
5561    "EdgeDetect": "0",
5562    "PEBS": "2",
5563    "Data_LA": "1",
5564    "L1_Hit_Indication": "0",
5565    "Errata": "0",
5566    "Offcore": "0"
5567  },
5568  {
5569    "EventCode": "0xcd",
5570    "UMask": "0x01",
5571    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
5572    "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
5573    "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency.",
5574    "Counter": "0,1,2,3",
5575    "CounterHTOff": "0,1,2,3",
5576    "SampleAfterValue": "50021",
5577    "MSRIndex": "0x3F6",
5578    "MSRValue": "0x8",
5579    "TakenAlone": "1",
5580    "CounterMask": "0",
5581    "Invert": "0",
5582    "AnyThread": "0",
5583    "EdgeDetect": "0",
5584    "PEBS": "2",
5585    "Data_LA": "1",
5586    "L1_Hit_Indication": "0",
5587    "Errata": "0",
5588    "Offcore": "0"
5589  },
5590  {
5591    "EventCode": "0xcd",
5592    "UMask": "0x01",
5593    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
5594    "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
5595    "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency.",
5596    "Counter": "0,1,2,3",
5597    "CounterHTOff": "0,1,2,3",
5598    "SampleAfterValue": "20011",
5599    "MSRIndex": "0x3F6",
5600    "MSRValue": "0x10",
5601    "TakenAlone": "1",
5602    "CounterMask": "0",
5603    "Invert": "0",
5604    "AnyThread": "0",
5605    "EdgeDetect": "0",
5606    "PEBS": "2",
5607    "Data_LA": "1",
5608    "L1_Hit_Indication": "0",
5609    "Errata": "0",
5610    "Offcore": "0"
5611  },
5612  {
5613    "EventCode": "0xcd",
5614    "UMask": "0x01",
5615    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
5616    "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
5617    "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency.",
5618    "Counter": "0,1,2,3",
5619    "CounterHTOff": "0,1,2,3",
5620    "SampleAfterValue": "100007",
5621    "MSRIndex": "0x3F6",
5622    "MSRValue": "0x20",
5623    "TakenAlone": "1",
5624    "CounterMask": "0",
5625    "Invert": "0",
5626    "AnyThread": "0",
5627    "EdgeDetect": "0",
5628    "PEBS": "2",
5629    "Data_LA": "1",
5630    "L1_Hit_Indication": "0",
5631    "Errata": "0",
5632    "Offcore": "0"
5633  },
5634  {
5635    "EventCode": "0xcd",
5636    "UMask": "0x01",
5637    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
5638    "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
5639    "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency.",
5640    "Counter": "0,1,2,3",
5641    "CounterHTOff": "0,1,2,3",
5642    "SampleAfterValue": "2003",
5643    "MSRIndex": "0x3F6",
5644    "MSRValue": "0x40",
5645    "TakenAlone": "1",
5646    "CounterMask": "0",
5647    "Invert": "0",
5648    "AnyThread": "0",
5649    "EdgeDetect": "0",
5650    "PEBS": "2",
5651    "Data_LA": "1",
5652    "L1_Hit_Indication": "0",
5653    "Errata": "0",
5654    "Offcore": "0"
5655  },
5656  {
5657    "EventCode": "0xcd",
5658    "UMask": "0x01",
5659    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
5660    "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
5661    "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency.",
5662    "Counter": "0,1,2,3",
5663    "CounterHTOff": "0,1,2,3",
5664    "SampleAfterValue": "1009",
5665    "MSRIndex": "0x3F6",
5666    "MSRValue": "0x80",
5667    "TakenAlone": "1",
5668    "CounterMask": "0",
5669    "Invert": "0",
5670    "AnyThread": "0",
5671    "EdgeDetect": "0",
5672    "PEBS": "2",
5673    "Data_LA": "1",
5674    "L1_Hit_Indication": "0",
5675    "Errata": "0",
5676    "Offcore": "0"
5677  },
5678  {
5679    "EventCode": "0xcd",
5680    "UMask": "0x01",
5681    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
5682    "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
5683    "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency.",
5684    "Counter": "0,1,2,3",
5685    "CounterHTOff": "0,1,2,3",
5686    "SampleAfterValue": "503",
5687    "MSRIndex": "0x3F6",
5688    "MSRValue": "0x100",
5689    "TakenAlone": "1",
5690    "CounterMask": "0",
5691    "Invert": "0",
5692    "AnyThread": "0",
5693    "EdgeDetect": "0",
5694    "PEBS": "2",
5695    "Data_LA": "1",
5696    "L1_Hit_Indication": "0",
5697    "Errata": "0",
5698    "Offcore": "0"
5699  },
5700  {
5701    "EventCode": "0xcd",
5702    "UMask": "0x01",
5703    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
5704    "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
5705    "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency.",
5706    "Counter": "0,1,2,3",
5707    "CounterHTOff": "0,1,2,3",
5708    "SampleAfterValue": "101",
5709    "MSRIndex": "0x3F6",
5710    "MSRValue": "0x200",
5711    "TakenAlone": "1",
5712    "CounterMask": "0",
5713    "Invert": "0",
5714    "AnyThread": "0",
5715    "EdgeDetect": "0",
5716    "PEBS": "2",
5717    "Data_LA": "1",
5718    "L1_Hit_Indication": "0",
5719    "Errata": "0",
5720    "Offcore": "0"
5721  },
5722  {
5723    "EventCode": "0xD0",
5724    "UMask": "0x11",
5725    "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
5726    "BriefDescription": "Retired load instructions that miss the STLB.",
5727    "PublicDescription": "Retired load instructions that miss the STLB.",
5728    "Counter": "0,1,2,3",
5729    "CounterHTOff": "0,1,2,3",
5730    "SampleAfterValue": "100003",
5731    "MSRIndex": "0",
5732    "MSRValue": "0",
5733    "TakenAlone": "0",
5734    "CounterMask": "0",
5735    "Invert": "0",
5736    "AnyThread": "0",
5737    "EdgeDetect": "0",
5738    "PEBS": "1",
5739    "Data_LA": "1",
5740    "L1_Hit_Indication": "0",
5741    "Errata": "0",
5742    "Offcore": "0"
5743  },
5744  {
5745    "EventCode": "0xD0",
5746    "UMask": "0x12",
5747    "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
5748    "BriefDescription": "Retired store instructions that miss the STLB.",
5749    "PublicDescription": "Retired store instructions that miss the STLB.",
5750    "Counter": "0,1,2,3",
5751    "CounterHTOff": "0,1,2,3",
5752    "SampleAfterValue": "100003",
5753    "MSRIndex": "0",
5754    "MSRValue": "0",
5755    "TakenAlone": "0",
5756    "CounterMask": "0",
5757    "Invert": "0",
5758    "AnyThread": "0",
5759    "EdgeDetect": "0",
5760    "PEBS": "1",
5761    "Data_LA": "1",
5762    "L1_Hit_Indication": "1",
5763    "Errata": "0",
5764    "Offcore": "0"
5765  },
5766  {
5767    "EventCode": "0xD0",
5768    "UMask": "0x21",
5769    "EventName": "MEM_INST_RETIRED.LOCK_LOADS",
5770    "BriefDescription": "Retired load instructions with locked access.",
5771    "PublicDescription": "Retired load instructions with locked access.",
5772    "Counter": "0,1,2,3",
5773    "CounterHTOff": "0,1,2,3",
5774    "SampleAfterValue": "100007",
5775    "MSRIndex": "0",
5776    "MSRValue": "0",
5777    "TakenAlone": "0",
5778    "CounterMask": "0",
5779    "Invert": "0",
5780    "AnyThread": "0",
5781    "EdgeDetect": "0",
5782    "PEBS": "1",
5783    "Data_LA": "1",
5784    "L1_Hit_Indication": "0",
5785    "Errata": "0",
5786    "Offcore": "0"
5787  },
5788  {
5789    "EventCode": "0xD0",
5790    "UMask": "0x41",
5791    "EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
5792    "BriefDescription": "Retired load instructions that split across a cacheline boundary.",
5793    "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.",
5794    "Counter": "0,1,2,3",
5795    "CounterHTOff": "0,1,2,3",
5796    "SampleAfterValue": "100003",
5797    "MSRIndex": "0",
5798    "MSRValue": "0",
5799    "TakenAlone": "0",
5800    "CounterMask": "0",
5801    "Invert": "0",
5802    "AnyThread": "0",
5803    "EdgeDetect": "0",
5804    "PEBS": "1",
5805    "Data_LA": "1",
5806    "L1_Hit_Indication": "0",
5807    "Errata": "0",
5808    "Offcore": "0"
5809  },
5810  {
5811    "EventCode": "0xD0",
5812    "UMask": "0x42",
5813    "EventName": "MEM_INST_RETIRED.SPLIT_STORES",
5814    "BriefDescription": "Retired store instructions that split across a cacheline boundary.",
5815    "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
5816    "Counter": "0,1,2,3",
5817    "CounterHTOff": "0,1,2,3",
5818    "SampleAfterValue": "100003",
5819    "MSRIndex": "0",
5820    "MSRValue": "0",
5821    "TakenAlone": "0",
5822    "CounterMask": "0",
5823    "Invert": "0",
5824    "AnyThread": "0",
5825    "EdgeDetect": "0",
5826    "PEBS": "1",
5827    "Data_LA": "1",
5828    "L1_Hit_Indication": "1",
5829    "Errata": "0",
5830    "Offcore": "0"
5831  },
5832  {
5833    "EventCode": "0xD0",
5834    "UMask": "0x81",
5835    "EventName": "MEM_INST_RETIRED.ALL_LOADS",
5836    "BriefDescription": "All retired load instructions.",
5837    "PublicDescription": "All retired load instructions.",
5838    "Counter": "0,1,2,3",
5839    "CounterHTOff": "0,1,2,3",
5840    "SampleAfterValue": "2000003",
5841    "MSRIndex": "0",
5842    "MSRValue": "0",
5843    "TakenAlone": "0",
5844    "CounterMask": "0",
5845    "Invert": "0",
5846    "AnyThread": "0",
5847    "EdgeDetect": "0",
5848    "PEBS": "1",
5849    "Data_LA": "1",
5850    "L1_Hit_Indication": "0",
5851    "Errata": "0",
5852    "Offcore": "0"
5853  },
5854  {
5855    "EventCode": "0xD0",
5856    "UMask": "0x82",
5857    "EventName": "MEM_INST_RETIRED.ALL_STORES",
5858    "BriefDescription": "All retired store instructions.",
5859    "PublicDescription": "All retired store instructions.",
5860    "Counter": "0,1,2,3",
5861    "CounterHTOff": "0,1,2,3",
5862    "SampleAfterValue": "2000003",
5863    "MSRIndex": "0",
5864    "MSRValue": "0",
5865    "TakenAlone": "0",
5866    "CounterMask": "0",
5867    "Invert": "0",
5868    "AnyThread": "0",
5869    "EdgeDetect": "0",
5870    "PEBS": "1",
5871    "Data_LA": "1",
5872    "L1_Hit_Indication": "1",
5873    "Errata": "0",
5874    "Offcore": "0"
5875  },
5876  {
5877    "EventCode": "0xD1",
5878    "UMask": "0x01",
5879    "EventName": "MEM_LOAD_RETIRED.L1_HIT",
5880    "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
5881    "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.",
5882    "Counter": "0,1,2,3",
5883    "CounterHTOff": "0,1,2,3",
5884    "SampleAfterValue": "2000003",
5885    "MSRIndex": "0",
5886    "MSRValue": "0",
5887    "TakenAlone": "0",
5888    "CounterMask": "0",
5889    "Invert": "0",
5890    "AnyThread": "0",
5891    "EdgeDetect": "0",
5892    "PEBS": "1",
5893    "Data_LA": "1",
5894    "L1_Hit_Indication": "0",
5895    "Errata": "0",
5896    "Offcore": "0"
5897  },
5898  {
5899    "EventCode": "0xD1",
5900    "UMask": "0x02",
5901    "EventName": "MEM_LOAD_RETIRED.L2_HIT",
5902    "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
5903    "PublicDescription": "Retired load instructions with L2 cache hits as data sources.",
5904    "Counter": "0,1,2,3",
5905    "CounterHTOff": "0,1,2,3",
5906    "SampleAfterValue": "100003",
5907    "MSRIndex": "0",
5908    "MSRValue": "0",
5909    "TakenAlone": "0",
5910    "CounterMask": "0",
5911    "Invert": "0",
5912    "AnyThread": "0",
5913    "EdgeDetect": "0",
5914    "PEBS": "1",
5915    "Data_LA": "1",
5916    "L1_Hit_Indication": "0",
5917    "Errata": "0",
5918    "Offcore": "0"
5919  },
5920  {
5921    "EventCode": "0xD1",
5922    "UMask": "0x04",
5923    "EventName": "MEM_LOAD_RETIRED.L3_HIT",
5924    "BriefDescription": "Retired load instructions with L3 cache hits as data sources",
5925    "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache. ",
5926    "Counter": "0,1,2,3",
5927    "CounterHTOff": "0,1,2,3",
5928    "SampleAfterValue": "50021",
5929    "MSRIndex": "0",
5930    "MSRValue": "0",
5931    "TakenAlone": "0",
5932    "CounterMask": "0",
5933    "Invert": "0",
5934    "AnyThread": "0",
5935    "EdgeDetect": "0",
5936    "PEBS": "1",
5937    "Data_LA": "1",
5938    "L1_Hit_Indication": "0",
5939    "Errata": "0",
5940    "Offcore": "0"
5941  },
5942  {
5943    "EventCode": "0xD1",
5944    "UMask": "0x08",
5945    "EventName": "MEM_LOAD_RETIRED.L1_MISS",
5946    "BriefDescription": "Retired load instructions missed L1 cache as data sources",
5947    "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.",
5948    "Counter": "0,1,2,3",
5949    "CounterHTOff": "0,1,2,3",
5950    "SampleAfterValue": "100003",
5951    "MSRIndex": "0",
5952    "MSRValue": "0",
5953    "TakenAlone": "0",
5954    "CounterMask": "0",
5955    "Invert": "0",
5956    "AnyThread": "0",
5957    "EdgeDetect": "0",
5958    "PEBS": "1",
5959    "Data_LA": "1",
5960    "L1_Hit_Indication": "0",
5961    "Errata": "0",
5962    "Offcore": "0"
5963  },
5964  {
5965    "EventCode": "0xD1",
5966    "UMask": "0x10",
5967    "EventName": "MEM_LOAD_RETIRED.L2_MISS",
5968    "BriefDescription": "Retired load instructions missed L2 cache as data sources",
5969    "PublicDescription": "Retired load instructions missed L2 cache as data sources.",
5970    "Counter": "0,1,2,3",
5971    "CounterHTOff": "0,1,2,3",
5972    "SampleAfterValue": "50021",
5973    "MSRIndex": "0",
5974    "MSRValue": "0",
5975    "TakenAlone": "0",
5976    "CounterMask": "0",
5977    "Invert": "0",
5978    "AnyThread": "0",
5979    "EdgeDetect": "0",
5980    "PEBS": "1",
5981    "Data_LA": "1",
5982    "L1_Hit_Indication": "0",
5983    "Errata": "0",
5984    "Offcore": "0"
5985  },
5986  {
5987    "EventCode": "0xD1",
5988    "UMask": "0x20",
5989    "EventName": "MEM_LOAD_RETIRED.L3_MISS",
5990    "BriefDescription": "Retired load instructions missed L3 cache as data sources",
5991    "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache. ",
5992    "Counter": "0,1,2,3",
5993    "CounterHTOff": "0,1,2,3",
5994    "SampleAfterValue": "100007",
5995    "MSRIndex": "0",
5996    "MSRValue": "0",
5997    "TakenAlone": "0",
5998    "CounterMask": "0",
5999    "Invert": "0",
6000    "AnyThread": "0",
6001    "EdgeDetect": "0",
6002    "PEBS": "1",
6003    "Data_LA": "1",
6004    "L1_Hit_Indication": "0",
6005    "Errata": "0",
6006    "Offcore": "0"
6007  },
6008  {
6009    "EventCode": "0xD1",
6010    "UMask": "0x40",
6011    "EventName": "MEM_LOAD_RETIRED.FB_HIT",
6012    "BriefDescription": "Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready",
6013    "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready. ",
6014    "Counter": "0,1,2,3",
6015    "CounterHTOff": "0,1,2,3",
6016    "SampleAfterValue": "100007",
6017    "MSRIndex": "0",
6018    "MSRValue": "0",
6019    "TakenAlone": "0",
6020    "CounterMask": "0",
6021    "Invert": "0",
6022    "AnyThread": "0",
6023    "EdgeDetect": "0",
6024    "PEBS": "1",
6025    "Data_LA": "1",
6026    "L1_Hit_Indication": "0",
6027    "Errata": "0",
6028    "Offcore": "0"
6029  },
6030  {
6031    "EventCode": "0xD2",
6032    "UMask": "0x01",
6033    "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
6034    "BriefDescription": "Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
6035    "PublicDescription": "Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
6036    "Counter": "0,1,2,3",
6037    "CounterHTOff": "0,1,2,3",
6038    "SampleAfterValue": "20011",
6039    "MSRIndex": "0",
6040    "MSRValue": "0",
6041    "TakenAlone": "0",
6042    "CounterMask": "0",
6043    "Invert": "0",
6044    "AnyThread": "0",
6045    "EdgeDetect": "0",
6046    "PEBS": "1",
6047    "Data_LA": "1",
6048    "L1_Hit_Indication": "0",
6049    "Errata": "0",
6050    "Offcore": "0"
6051  },
6052  {
6053    "EventCode": "0xD2",
6054    "UMask": "0x02",
6055    "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",
6056    "BriefDescription": "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache",
6057    "PublicDescription": "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache.",
6058    "Counter": "0,1,2,3",
6059    "CounterHTOff": "0,1,2,3",
6060    "SampleAfterValue": "20011",
6061    "MSRIndex": "0",
6062    "MSRValue": "0",
6063    "TakenAlone": "0",
6064    "CounterMask": "0",
6065    "Invert": "0",
6066    "AnyThread": "0",
6067    "EdgeDetect": "0",
6068    "PEBS": "1",
6069    "Data_LA": "1",
6070    "L1_Hit_Indication": "0",
6071    "Errata": "0",
6072    "Offcore": "0"
6073  },
6074  {
6075    "EventCode": "0xD2",
6076    "UMask": "0x04",
6077    "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
6078    "BriefDescription": "Retired load instructions which data sources were HitM responses from shared L3",
6079    "PublicDescription": "Retired load instructions which data sources were HitM responses from shared L3.",
6080    "Counter": "0,1,2,3",
6081    "CounterHTOff": "0,1,2,3",
6082    "SampleAfterValue": "20011",
6083    "MSRIndex": "0",
6084    "MSRValue": "0",
6085    "TakenAlone": "0",
6086    "CounterMask": "0",
6087    "Invert": "0",
6088    "AnyThread": "0",
6089    "EdgeDetect": "0",
6090    "PEBS": "1",
6091    "Data_LA": "1",
6092    "L1_Hit_Indication": "0",
6093    "Errata": "0",
6094    "Offcore": "0"
6095  },
6096  {
6097    "EventCode": "0xD2",
6098    "UMask": "0x08",
6099    "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
6100    "BriefDescription": "Retired load instructions which data sources were hits in L3 without snoops required",
6101    "PublicDescription": "Retired load instructions which data sources were hits in L3 without snoops required.",
6102    "Counter": "0,1,2,3",
6103    "CounterHTOff": "0,1,2,3",
6104    "SampleAfterValue": "100003",
6105    "MSRIndex": "0",
6106    "MSRValue": "0",
6107    "TakenAlone": "0",
6108    "CounterMask": "0",
6109    "Invert": "0",
6110    "AnyThread": "0",
6111    "EdgeDetect": "0",
6112    "PEBS": "1",
6113    "Data_LA": "1",
6114    "L1_Hit_Indication": "0",
6115    "Errata": "0",
6116    "Offcore": "0"
6117  },
6118  {
6119    "EventCode": "0xD4",
6120    "UMask": "0x04",
6121    "EventName": "MEM_LOAD_MISC_RETIRED.UC",
6122    "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.",
6123    "PublicDescription": "Retired instructions with at least 1 uncacheable load or lock.",
6124    "Counter": "0,1,2,3",
6125    "CounterHTOff": "0,1,2,3",
6126    "SampleAfterValue": "100007",
6127    "MSRIndex": "0",
6128    "MSRValue": "0",
6129    "TakenAlone": "0",
6130    "CounterMask": "0",
6131    "Invert": "0",
6132    "AnyThread": "0",
6133    "EdgeDetect": "0",
6134    "PEBS": "1",
6135    "Data_LA": "1",
6136    "L1_Hit_Indication": "0",
6137    "Errata": "0",
6138    "Offcore": "0"
6139  },
6140  {
6141    "EventCode": "0xE6",
6142    "UMask": "0x01",
6143    "EventName": "BACLEARS.ANY",
6144    "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
6145    "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
6146    "Counter": "0,1,2,3",
6147    "CounterHTOff": "0,1,2,3,4,5,6,7",
6148    "SampleAfterValue": "100003",
6149    "MSRIndex": "0",
6150    "MSRValue": "0",
6151    "TakenAlone": "0",
6152    "CounterMask": "0",
6153    "Invert": "0",
6154    "AnyThread": "0",
6155    "EdgeDetect": "0",
6156    "PEBS": "0",
6157    "Data_LA": "0",
6158    "L1_Hit_Indication": "0",
6159    "Errata": "0",
6160    "Offcore": "0"
6161  },
6162  {
6163    "EventCode": "0xF0",
6164    "UMask": "0x40",
6165    "EventName": "L2_TRANS.L2_WB",
6166    "BriefDescription": "L2 writebacks that access L2 cache",
6167    "PublicDescription": "Counts L2 writebacks that access L2 cache.",
6168    "Counter": "0,1,2,3",
6169    "CounterHTOff": "0,1,2,3,4,5,6,7",
6170    "SampleAfterValue": "200003",
6171    "MSRIndex": "0",
6172    "MSRValue": "0",
6173    "TakenAlone": "0",
6174    "CounterMask": "0",
6175    "Invert": "0",
6176    "AnyThread": "0",
6177    "EdgeDetect": "0",
6178    "PEBS": "0",
6179    "Data_LA": "0",
6180    "L1_Hit_Indication": "0",
6181    "Errata": "0",
6182    "Offcore": "0"
6183  },
6184  {
6185    "EventCode": "0xF1",
6186    "UMask": "0x1F",
6187    "EventName": "L2_LINES_IN.ALL",
6188    "BriefDescription": "L2 cache lines filling L2",
6189    "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
6190    "Counter": "0,1,2,3",
6191    "CounterHTOff": "0,1,2,3,4,5,6,7",
6192    "SampleAfterValue": "100003",
6193    "MSRIndex": "0",
6194    "MSRValue": "0",
6195    "TakenAlone": "0",
6196    "CounterMask": "0",
6197    "Invert": "0",
6198    "AnyThread": "0",
6199    "EdgeDetect": "0",
6200    "PEBS": "0",
6201    "Data_LA": "0",
6202    "L1_Hit_Indication": "0",
6203    "Errata": "0",
6204    "Offcore": "0"
6205  },
6206  {
6207    "EventCode": "0xF2",
6208    "UMask": "0x01",
6209    "EventName": "L2_LINES_OUT.SILENT",
6210    "BriefDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
6211    "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
6212    "Counter": "0,1,2,3",
6213    "CounterHTOff": "0,1,2,3,4,5,6,7",
6214    "SampleAfterValue": "200003",
6215    "MSRIndex": "0",
6216    "MSRValue": "0",
6217    "TakenAlone": "0",
6218    "CounterMask": "0",
6219    "Invert": "0",
6220    "AnyThread": "0",
6221    "EdgeDetect": "0",
6222    "PEBS": "0",
6223    "Data_LA": "0",
6224    "L1_Hit_Indication": "0",
6225    "Errata": "0",
6226    "Offcore": "0"
6227  },
6228  {
6229    "EventCode": "0xF2",
6230    "UMask": "0x02",
6231    "EventName": "L2_LINES_OUT.NON_SILENT",
6232    "BriefDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3",
6233    "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3",
6234    "Counter": "0,1,2,3",
6235    "CounterHTOff": "0,1,2,3,4,5,6,7",
6236    "SampleAfterValue": "200003",
6237    "MSRIndex": "0",
6238    "MSRValue": "0",
6239    "TakenAlone": "0",
6240    "CounterMask": "0",
6241    "Invert": "0",
6242    "AnyThread": "0",
6243    "EdgeDetect": "0",
6244    "PEBS": "0",
6245    "Data_LA": "0",
6246    "L1_Hit_Indication": "0",
6247    "Errata": "0",
6248    "Offcore": "0"
6249  },
6250  {
6251    "EventCode": "0xF2",
6252    "UMask": "0x04",
6253    "EventName": "L2_LINES_OUT.USELESS_PREF",
6254    "BriefDescription": "This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF",
6255    "PublicDescription": "This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF",
6256    "Counter": "0,1,2,3",
6257    "CounterHTOff": "0,1,2,3,4,5,6,7",
6258    "SampleAfterValue": "200003",
6259    "MSRIndex": "0",
6260    "MSRValue": "0",
6261    "TakenAlone": "0",
6262    "CounterMask": "0",
6263    "Invert": "0",
6264    "AnyThread": "0",
6265    "EdgeDetect": "0",
6266    "PEBS": "0",
6267    "Data_LA": "0",
6268    "L1_Hit_Indication": "0",
6269    "Errata": "0",
6270    "Offcore": "0"
6271  },
6272  {
6273    "EventCode": "0xF2",
6274    "UMask": "0x04",
6275    "EventName": "L2_LINES_OUT.USELESS_HWPF",
6276    "BriefDescription": "Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache",
6277    "PublicDescription": "Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache",
6278    "Counter": "0,1,2,3",
6279    "CounterHTOff": "0,1,2,3,4,5,6,7",
6280    "SampleAfterValue": "200003",
6281    "MSRIndex": "0",
6282    "MSRValue": "0",
6283    "TakenAlone": "0",
6284    "CounterMask": "0",
6285    "Invert": "0",
6286    "AnyThread": "0",
6287    "EdgeDetect": "0",
6288    "PEBS": "0",
6289    "Data_LA": "0",
6290    "L1_Hit_Indication": "0",
6291    "Errata": "0",
6292    "Offcore": "0"
6293  },
6294  {
6295    "EventCode": "0xF4",
6296    "UMask": "0x10",
6297    "EventName": "SQ_MISC.SPLIT_LOCK",
6298    "BriefDescription": "Number of cache line split locks sent to uncore.",
6299    "PublicDescription": "Counts the number of cache line split locks sent to the uncore.",
6300    "Counter": "0,1,2,3",
6301    "CounterHTOff": "0,1,2,3,4,5,6,7",
6302    "SampleAfterValue": "100003",
6303    "MSRIndex": "0",
6304    "MSRValue": "0",
6305    "TakenAlone": "0",
6306    "CounterMask": "0",
6307    "Invert": "0",
6308    "AnyThread": "0",
6309    "EdgeDetect": "0",
6310    "PEBS": "0",
6311    "Data_LA": "0",
6312    "L1_Hit_Indication": "0",
6313    "Errata": "0",
6314    "Offcore": "0"
6315  },
6316  {
6317    "EventCode": "0xB7, 0xBB",
6318    "UMask": "0x01",
6319    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP",
6320    "BriefDescription": "Counts any other requests ",
6321    "PublicDescription": "Counts any other requests",
6322    "Counter": "0,1,2,3",
6323    "CounterHTOff": "0,1,2,3",
6324    "SampleAfterValue": "100003",
6325    "MSRIndex": "0x1a6,0x1a7",
6326    "MSRValue": "0x3FFC408000",
6327    "TakenAlone": "0",
6328    "CounterMask": "0",
6329    "Invert": "0",
6330    "AnyThread": "0",
6331    "EdgeDetect": "0",
6332    "PEBS": "0",
6333    "Data_LA": "0",
6334    "L1_Hit_Indication": "0",
6335    "Errata": "null",
6336    "Offcore": "1"
6337  },
6338  {
6339    "EventCode": "0xB7, 0xBB",
6340    "UMask": "0x01",
6341    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NON_DRAM",
6342    "BriefDescription": "Counts any other requests ",
6343    "PublicDescription": "Counts any other requests",
6344    "Counter": "0,1,2,3",
6345    "CounterHTOff": "0,1,2,3",
6346    "SampleAfterValue": "100003",
6347    "MSRIndex": "0x1a6,0x1a7",
6348    "MSRValue": "0x203C408000",
6349    "TakenAlone": "0",
6350    "CounterMask": "0",
6351    "Invert": "0",
6352    "AnyThread": "0",
6353    "EdgeDetect": "0",
6354    "PEBS": "0",
6355    "Data_LA": "0",
6356    "L1_Hit_Indication": "0",
6357    "Errata": "null",
6358    "Offcore": "1"
6359  },
6360  {
6361    "EventCode": "0xB7, 0xBB",
6362    "UMask": "0x01",
6363    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HITM",
6364    "BriefDescription": "Counts any other requests ",
6365    "PublicDescription": "Counts any other requests",
6366    "Counter": "0,1,2,3",
6367    "CounterHTOff": "0,1,2,3",
6368    "SampleAfterValue": "100003",
6369    "MSRIndex": "0x1a6,0x1a7",
6370    "MSRValue": "0x103C408000",
6371    "TakenAlone": "0",
6372    "CounterMask": "0",
6373    "Invert": "0",
6374    "AnyThread": "0",
6375    "EdgeDetect": "0",
6376    "PEBS": "0",
6377    "Data_LA": "0",
6378    "L1_Hit_Indication": "0",
6379    "Errata": "null",
6380    "Offcore": "1"
6381  },
6382  {
6383    "EventCode": "0xB7, 0xBB",
6384    "UMask": "0x01",
6385    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD",
6386    "BriefDescription": "Counts any other requests ",
6387    "PublicDescription": "Counts any other requests",
6388    "Counter": "0,1,2,3",
6389    "CounterHTOff": "0,1,2,3",
6390    "SampleAfterValue": "100003",
6391    "MSRIndex": "0x1a6,0x1a7",
6392    "MSRValue": "0x043C408000",
6393    "TakenAlone": "0",
6394    "CounterMask": "0",
6395    "Invert": "0",
6396    "AnyThread": "0",
6397    "EdgeDetect": "0",
6398    "PEBS": "0",
6399    "Data_LA": "0",
6400    "L1_Hit_Indication": "0",
6401    "Errata": "null",
6402    "Offcore": "1"
6403  },
6404  {
6405    "EventCode": "0xB7, 0xBB",
6406    "UMask": "0x01",
6407    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS",
6408    "BriefDescription": "Counts any other requests ",
6409    "PublicDescription": "Counts any other requests",
6410    "Counter": "0,1,2,3",
6411    "CounterHTOff": "0,1,2,3",
6412    "SampleAfterValue": "100003",
6413    "MSRIndex": "0x1a6,0x1a7",
6414    "MSRValue": "0x023C408000",
6415    "TakenAlone": "0",
6416    "CounterMask": "0",
6417    "Invert": "0",
6418    "AnyThread": "0",
6419    "EdgeDetect": "0",
6420    "PEBS": "0",
6421    "Data_LA": "0",
6422    "L1_Hit_Indication": "0",
6423    "Errata": "null",
6424    "Offcore": "1"
6425  },
6426  {
6427    "EventCode": "0xB7, 0xBB",
6428    "UMask": "0x01",
6429    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED",
6430    "BriefDescription": "Counts any other requests ",
6431    "PublicDescription": "Counts any other requests",
6432    "Counter": "0,1,2,3",
6433    "CounterHTOff": "0,1,2,3",
6434    "SampleAfterValue": "100003",
6435    "MSRIndex": "0x1a6,0x1a7",
6436    "MSRValue": "0x013C408000",
6437    "TakenAlone": "0",
6438    "CounterMask": "0",
6439    "Invert": "0",
6440    "AnyThread": "0",
6441    "EdgeDetect": "0",
6442    "PEBS": "0",
6443    "Data_LA": "0",
6444    "L1_Hit_Indication": "0",
6445    "Errata": "null",
6446    "Offcore": "1"
6447  },
6448  {
6449    "EventCode": "0xB7, 0xBB",
6450    "UMask": "0x01",
6451    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE",
6452    "BriefDescription": "Counts any other requests ",
6453    "PublicDescription": "Counts any other requests",
6454    "Counter": "0,1,2,3",
6455    "CounterHTOff": "0,1,2,3",
6456    "SampleAfterValue": "100003",
6457    "MSRIndex": "0x1a6,0x1a7",
6458    "MSRValue": "0x00BC408000",
6459    "TakenAlone": "0",
6460    "CounterMask": "0",
6461    "Invert": "0",
6462    "AnyThread": "0",
6463    "EdgeDetect": "0",
6464    "PEBS": "0",
6465    "Data_LA": "0",
6466    "L1_Hit_Indication": "0",
6467    "Errata": "null",
6468    "Offcore": "1"
6469  },
6470  {
6471    "EventCode": "0xB7, 0xBB",
6472    "UMask": "0x01",
6473    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SPL_HIT",
6474    "BriefDescription": "Counts any other requests ",
6475    "PublicDescription": "Counts any other requests",
6476    "Counter": "0,1,2,3",
6477    "CounterHTOff": "0,1,2,3",
6478    "SampleAfterValue": "100003",
6479    "MSRIndex": "0x1a6,0x1a7",
6480    "MSRValue": "0x007C408000",
6481    "TakenAlone": "0",
6482    "CounterMask": "0",
6483    "Invert": "0",
6484    "AnyThread": "0",
6485    "EdgeDetect": "0",
6486    "PEBS": "0",
6487    "Data_LA": "0",
6488    "L1_Hit_Indication": "0",
6489    "Errata": "null",
6490    "Offcore": "1"
6491  },
6492  {
6493    "EventCode": "0xB7, 0xBB",
6494    "UMask": "0x01",
6495    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
6496    "BriefDescription": "Counts any other requests ",
6497    "PublicDescription": "Counts any other requests",
6498    "Counter": "0,1,2,3",
6499    "CounterHTOff": "0,1,2,3",
6500    "SampleAfterValue": "100003",
6501    "MSRIndex": "0x1a6,0x1a7",
6502    "MSRValue": "0x3FC4008000",
6503    "TakenAlone": "0",
6504    "CounterMask": "0",
6505    "Invert": "0",
6506    "AnyThread": "0",
6507    "EdgeDetect": "0",
6508    "PEBS": "0",
6509    "Data_LA": "0",
6510    "L1_Hit_Indication": "0",
6511    "Errata": "null",
6512    "Offcore": "1"
6513  },
6514  {
6515    "EventCode": "0xB7, 0xBB",
6516    "UMask": "0x01",
6517    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
6518    "BriefDescription": "Counts any other requests ",
6519    "PublicDescription": "Counts any other requests",
6520    "Counter": "0,1,2,3",
6521    "CounterHTOff": "0,1,2,3",
6522    "SampleAfterValue": "100003",
6523    "MSRIndex": "0x1a6,0x1a7",
6524    "MSRValue": "0x2004008000",
6525    "TakenAlone": "0",
6526    "CounterMask": "0",
6527    "Invert": "0",
6528    "AnyThread": "0",
6529    "EdgeDetect": "0",
6530    "PEBS": "0",
6531    "Data_LA": "0",
6532    "L1_Hit_Indication": "0",
6533    "Errata": "null",
6534    "Offcore": "1"
6535  },
6536  {
6537    "EventCode": "0xB7, 0xBB",
6538    "UMask": "0x01",
6539    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
6540    "BriefDescription": "Counts any other requests ",
6541    "PublicDescription": "Counts any other requests",
6542    "Counter": "0,1,2,3",
6543    "CounterHTOff": "0,1,2,3",
6544    "SampleAfterValue": "100003",
6545    "MSRIndex": "0x1a6,0x1a7",
6546    "MSRValue": "0x1004008000",
6547    "TakenAlone": "0",
6548    "CounterMask": "0",
6549    "Invert": "0",
6550    "AnyThread": "0",
6551    "EdgeDetect": "0",
6552    "PEBS": "0",
6553    "Data_LA": "0",
6554    "L1_Hit_Indication": "0",
6555    "Errata": "null",
6556    "Offcore": "1"
6557  },
6558  {
6559    "EventCode": "0xB7, 0xBB",
6560    "UMask": "0x01",
6561    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
6562    "BriefDescription": "Counts any other requests ",
6563    "PublicDescription": "Counts any other requests",
6564    "Counter": "0,1,2,3",
6565    "CounterHTOff": "0,1,2,3",
6566    "SampleAfterValue": "100003",
6567    "MSRIndex": "0x1a6,0x1a7",
6568    "MSRValue": "0x0404008000",
6569    "TakenAlone": "0",
6570    "CounterMask": "0",
6571    "Invert": "0",
6572    "AnyThread": "0",
6573    "EdgeDetect": "0",
6574    "PEBS": "0",
6575    "Data_LA": "0",
6576    "L1_Hit_Indication": "0",
6577    "Errata": "null",
6578    "Offcore": "1"
6579  },
6580  {
6581    "EventCode": "0xB7, 0xBB",
6582    "UMask": "0x01",
6583    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
6584    "BriefDescription": "Counts any other requests ",
6585    "PublicDescription": "Counts any other requests",
6586    "Counter": "0,1,2,3",
6587    "CounterHTOff": "0,1,2,3",
6588    "SampleAfterValue": "100003",
6589    "MSRIndex": "0x1a6,0x1a7",
6590    "MSRValue": "0x0204008000",
6591    "TakenAlone": "0",
6592    "CounterMask": "0",
6593    "Invert": "0",
6594    "AnyThread": "0",
6595    "EdgeDetect": "0",
6596    "PEBS": "0",
6597    "Data_LA": "0",
6598    "L1_Hit_Indication": "0",
6599    "Errata": "null",
6600    "Offcore": "1"
6601  },
6602  {
6603    "EventCode": "0xB7, 0xBB",
6604    "UMask": "0x01",
6605    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
6606    "BriefDescription": "Counts any other requests ",
6607    "PublicDescription": "Counts any other requests",
6608    "Counter": "0,1,2,3",
6609    "CounterHTOff": "0,1,2,3",
6610    "SampleAfterValue": "100003",
6611    "MSRIndex": "0x1a6,0x1a7",
6612    "MSRValue": "0x0104008000",
6613    "TakenAlone": "0",
6614    "CounterMask": "0",
6615    "Invert": "0",
6616    "AnyThread": "0",
6617    "EdgeDetect": "0",
6618    "PEBS": "0",
6619    "Data_LA": "0",
6620    "L1_Hit_Indication": "0",
6621    "Errata": "null",
6622    "Offcore": "1"
6623  },
6624  {
6625    "EventCode": "0xB7, 0xBB",
6626    "UMask": "0x01",
6627    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
6628    "BriefDescription": "Counts any other requests ",
6629    "PublicDescription": "Counts any other requests",
6630    "Counter": "0,1,2,3",
6631    "CounterHTOff": "0,1,2,3",
6632    "SampleAfterValue": "100003",
6633    "MSRIndex": "0x1a6,0x1a7",
6634    "MSRValue": "0x0084008000",
6635    "TakenAlone": "0",
6636    "CounterMask": "0",
6637    "Invert": "0",
6638    "AnyThread": "0",
6639    "EdgeDetect": "0",
6640    "PEBS": "0",
6641    "Data_LA": "0",
6642    "L1_Hit_Indication": "0",
6643    "Errata": "null",
6644    "Offcore": "1"
6645  },
6646  {
6647    "EventCode": "0xB7, 0xBB",
6648    "UMask": "0x01",
6649    "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SPL_HIT",
6650    "BriefDescription": "Counts any other requests ",
6651    "PublicDescription": "Counts any other requests",
6652    "Counter": "0,1,2,3",
6653    "CounterHTOff": "0,1,2,3",
6654    "SampleAfterValue": "100003",
6655    "MSRIndex": "0x1a6,0x1a7",
6656    "MSRValue": "0x0044008000",
6657    "TakenAlone": "0",
6658    "CounterMask": "0",
6659    "Invert": "0",
6660    "AnyThread": "0",
6661    "EdgeDetect": "0",
6662    "PEBS": "0",
6663    "Data_LA": "0",
6664    "L1_Hit_Indication": "0",
6665    "Errata": "null",
6666    "Offcore": "1"
6667  },
6668  {
6669    "EventCode": "0xB7, 0xBB",
6670    "UMask": "0x01",
6671    "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.ANY_SNOOP",
6672    "BriefDescription": "Counts any other requests ",
6673    "PublicDescription": "Counts any other requests",
6674    "Counter": "0,1,2,3",
6675    "CounterHTOff": "0,1,2,3",
6676    "SampleAfterValue": "100003",
6677    "MSRIndex": "0x1a6,0x1a7",
6678    "MSRValue": "0x3FC0408000",
6679    "TakenAlone": "0",
6680    "CounterMask": "0",
6681    "Invert": "0",
6682    "AnyThread": "0",
6683    "EdgeDetect": "0",
6684    "PEBS": "0",
6685    "Data_LA": "0",
6686    "L1_Hit_Indication": "0",
6687    "Errata": "null",
6688    "Offcore": "1"
6689  },
6690  {
6691    "EventCode": "0xB7, 0xBB",
6692    "UMask": "0x01",
6693    "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
6694    "BriefDescription": "Counts any other requests ",
6695    "PublicDescription": "Counts any other requests",
6696    "Counter": "0,1,2,3",
6697    "CounterHTOff": "0,1,2,3",
6698    "SampleAfterValue": "100003",
6699    "MSRIndex": "0x1a6,0x1a7",
6700    "MSRValue": "0x2000408000",
6701    "TakenAlone": "0",
6702    "CounterMask": "0",
6703    "Invert": "0",
6704    "AnyThread": "0",
6705    "EdgeDetect": "0",
6706    "PEBS": "0",
6707    "Data_LA": "0",
6708    "L1_Hit_Indication": "0",
6709    "Errata": "null",
6710    "Offcore": "1"
6711  },
6712  {
6713    "EventCode": "0xB7, 0xBB",
6714    "UMask": "0x01",
6715    "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HITM",
6716    "BriefDescription": "Counts any other requests ",
6717    "PublicDescription": "Counts any other requests",
6718    "Counter": "0,1,2,3",
6719    "CounterHTOff": "0,1,2,3",
6720    "SampleAfterValue": "100003",
6721    "MSRIndex": "0x1a6,0x1a7",
6722    "MSRValue": "0x1000408000",
6723    "TakenAlone": "0",
6724    "CounterMask": "0",
6725    "Invert": "0",
6726    "AnyThread": "0",
6727    "EdgeDetect": "0",
6728    "PEBS": "0",
6729    "Data_LA": "0",
6730    "L1_Hit_Indication": "0",
6731    "Errata": "null",
6732    "Offcore": "1"
6733  },
6734  {
6735    "EventCode": "0xB7, 0xBB",
6736    "UMask": "0x01",
6737    "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
6738    "BriefDescription": "Counts any other requests ",
6739    "PublicDescription": "Counts any other requests",
6740    "Counter": "0,1,2,3",
6741    "CounterHTOff": "0,1,2,3",
6742    "SampleAfterValue": "100003",
6743    "MSRIndex": "0x1a6,0x1a7",
6744    "MSRValue": "0x0400408000",
6745    "TakenAlone": "0",
6746    "CounterMask": "0",
6747    "Invert": "0",
6748    "AnyThread": "0",
6749    "EdgeDetect": "0",
6750    "PEBS": "0",
6751    "Data_LA": "0",
6752    "L1_Hit_Indication": "0",
6753    "Errata": "null",
6754    "Offcore": "1"
6755  },
6756  {
6757    "EventCode": "0xB7, 0xBB",
6758    "UMask": "0x01",
6759    "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_MISS",
6760    "BriefDescription": "Counts any other requests ",
6761    "PublicDescription": "Counts any other requests",
6762    "Counter": "0,1,2,3",
6763    "CounterHTOff": "0,1,2,3",
6764    "SampleAfterValue": "100003",
6765    "MSRIndex": "0x1a6,0x1a7",
6766    "MSRValue": "0x0200408000",
6767    "TakenAlone": "0",
6768    "CounterMask": "0",
6769    "Invert": "0",
6770    "AnyThread": "0",
6771    "EdgeDetect": "0",
6772    "PEBS": "0",
6773    "Data_LA": "0",
6774    "L1_Hit_Indication": "0",
6775    "Errata": "null",
6776    "Offcore": "1"
6777  },
6778  {
6779    "EventCode": "0xB7, 0xBB",
6780    "UMask": "0x01",
6781    "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
6782    "BriefDescription": "Counts any other requests ",
6783    "PublicDescription": "Counts any other requests",
6784    "Counter": "0,1,2,3",
6785    "CounterHTOff": "0,1,2,3",
6786    "SampleAfterValue": "100003",
6787    "MSRIndex": "0x1a6,0x1a7",
6788    "MSRValue": "0x0100408000",
6789    "TakenAlone": "0",
6790    "CounterMask": "0",
6791    "Invert": "0",
6792    "AnyThread": "0",
6793    "EdgeDetect": "0",
6794    "PEBS": "0",
6795    "Data_LA": "0",
6796    "L1_Hit_Indication": "0",
6797    "Errata": "null",
6798    "Offcore": "1"
6799  },
6800  {
6801    "EventCode": "0xB7, 0xBB",
6802    "UMask": "0x01",
6803    "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NONE",
6804    "BriefDescription": "Counts any other requests ",
6805    "PublicDescription": "Counts any other requests",
6806    "Counter": "0,1,2,3",
6807    "CounterHTOff": "0,1,2,3",
6808    "SampleAfterValue": "100003",
6809    "MSRIndex": "0x1a6,0x1a7",
6810    "MSRValue": "0x0080408000",
6811    "TakenAlone": "0",
6812    "CounterMask": "0",
6813    "Invert": "0",
6814    "AnyThread": "0",
6815    "EdgeDetect": "0",
6816    "PEBS": "0",
6817    "Data_LA": "0",
6818    "L1_Hit_Indication": "0",
6819    "Errata": "null",
6820    "Offcore": "1"
6821  },
6822  {
6823    "EventCode": "0xB7, 0xBB",
6824    "UMask": "0x01",
6825    "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SPL_HIT",
6826    "BriefDescription": "Counts any other requests ",
6827    "PublicDescription": "Counts any other requests",
6828    "Counter": "0,1,2,3",
6829    "CounterHTOff": "0,1,2,3",
6830    "SampleAfterValue": "100003",
6831    "MSRIndex": "0x1a6,0x1a7",
6832    "MSRValue": "0x0040408000",
6833    "TakenAlone": "0",
6834    "CounterMask": "0",
6835    "Invert": "0",
6836    "AnyThread": "0",
6837    "EdgeDetect": "0",
6838    "PEBS": "0",
6839    "Data_LA": "0",
6840    "L1_Hit_Indication": "0",
6841    "Errata": "null",
6842    "Offcore": "1"
6843  },
6844  {
6845    "EventCode": "0xB7, 0xBB",
6846    "UMask": "0x01",
6847    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP",
6848    "BriefDescription": "Counts any other requests ",
6849    "PublicDescription": "Counts any other requests",
6850    "Counter": "0,1,2,3",
6851    "CounterHTOff": "0,1,2,3",
6852    "SampleAfterValue": "100003",
6853    "MSRIndex": "0x1a6,0x1a7",
6854    "MSRValue": "0x3FC01C8000",
6855    "TakenAlone": "0",
6856    "CounterMask": "0",
6857    "Invert": "0",
6858    "AnyThread": "0",
6859    "EdgeDetect": "0",
6860    "PEBS": "0",
6861    "Data_LA": "0",
6862    "L1_Hit_Indication": "0",
6863    "Errata": "null",
6864    "Offcore": "1"
6865  },
6866  {
6867    "EventCode": "0xB7, 0xBB",
6868    "UMask": "0x01",
6869    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NON_DRAM",
6870    "BriefDescription": "Counts any other requests ",
6871    "PublicDescription": "Counts any other requests",
6872    "Counter": "0,1,2,3",
6873    "CounterHTOff": "0,1,2,3",
6874    "SampleAfterValue": "100003",
6875    "MSRIndex": "0x1a6,0x1a7",
6876    "MSRValue": "0x20001C8000",
6877    "TakenAlone": "0",
6878    "CounterMask": "0",
6879    "Invert": "0",
6880    "AnyThread": "0",
6881    "EdgeDetect": "0",
6882    "PEBS": "0",
6883    "Data_LA": "0",
6884    "L1_Hit_Indication": "0",
6885    "Errata": "null",
6886    "Offcore": "1"
6887  },
6888  {
6889    "EventCode": "0xB7, 0xBB",
6890    "UMask": "0x01",
6891    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HITM",
6892    "BriefDescription": "Counts any other requests ",
6893    "PublicDescription": "Counts any other requests",
6894    "Counter": "0,1,2,3",
6895    "CounterHTOff": "0,1,2,3",
6896    "SampleAfterValue": "100003",
6897    "MSRIndex": "0x1a6,0x1a7",
6898    "MSRValue": "0x10001C8000",
6899    "TakenAlone": "0",
6900    "CounterMask": "0",
6901    "Invert": "0",
6902    "AnyThread": "0",
6903    "EdgeDetect": "0",
6904    "PEBS": "0",
6905    "Data_LA": "0",
6906    "L1_Hit_Indication": "0",
6907    "Errata": "null",
6908    "Offcore": "1"
6909  },
6910  {
6911    "EventCode": "0xB7, 0xBB",
6912    "UMask": "0x01",
6913    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_NO_FWD",
6914    "BriefDescription": "Counts any other requests ",
6915    "PublicDescription": "Counts any other requests",
6916    "Counter": "0,1,2,3",
6917    "CounterHTOff": "0,1,2,3",
6918    "SampleAfterValue": "100003",
6919    "MSRIndex": "0x1a6,0x1a7",
6920    "MSRValue": "0x04001C8000",
6921    "TakenAlone": "0",
6922    "CounterMask": "0",
6923    "Invert": "0",
6924    "AnyThread": "0",
6925    "EdgeDetect": "0",
6926    "PEBS": "0",
6927    "Data_LA": "0",
6928    "L1_Hit_Indication": "0",
6929    "Errata": "null",
6930    "Offcore": "1"
6931  },
6932  {
6933    "EventCode": "0xB7, 0xBB",
6934    "UMask": "0x01",
6935    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS",
6936    "BriefDescription": "Counts any other requests ",
6937    "PublicDescription": "Counts any other requests",
6938    "Counter": "0,1,2,3",
6939    "CounterHTOff": "0,1,2,3",
6940    "SampleAfterValue": "100003",
6941    "MSRIndex": "0x1a6,0x1a7",
6942    "MSRValue": "0x02001C8000",
6943    "TakenAlone": "0",
6944    "CounterMask": "0",
6945    "Invert": "0",
6946    "AnyThread": "0",
6947    "EdgeDetect": "0",
6948    "PEBS": "0",
6949    "Data_LA": "0",
6950    "L1_Hit_Indication": "0",
6951    "Errata": "null",
6952    "Offcore": "1"
6953  },
6954  {
6955    "EventCode": "0xB7, 0xBB",
6956    "UMask": "0x01",
6957    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NOT_NEEDED",
6958    "BriefDescription": "Counts any other requests ",
6959    "PublicDescription": "Counts any other requests",
6960    "Counter": "0,1,2,3",
6961    "CounterHTOff": "0,1,2,3",
6962    "SampleAfterValue": "100003",
6963    "MSRIndex": "0x1a6,0x1a7",
6964    "MSRValue": "0x01001C8000",
6965    "TakenAlone": "0",
6966    "CounterMask": "0",
6967    "Invert": "0",
6968    "AnyThread": "0",
6969    "EdgeDetect": "0",
6970    "PEBS": "0",
6971    "Data_LA": "0",
6972    "L1_Hit_Indication": "0",
6973    "Errata": "null",
6974    "Offcore": "1"
6975  },
6976  {
6977    "EventCode": "0xB7, 0xBB",
6978    "UMask": "0x01",
6979    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE",
6980    "BriefDescription": "Counts any other requests ",
6981    "PublicDescription": "Counts any other requests",
6982    "Counter": "0,1,2,3",
6983    "CounterHTOff": "0,1,2,3",
6984    "SampleAfterValue": "100003",
6985    "MSRIndex": "0x1a6,0x1a7",
6986    "MSRValue": "0x00801C8000",
6987    "TakenAlone": "0",
6988    "CounterMask": "0",
6989    "Invert": "0",
6990    "AnyThread": "0",
6991    "EdgeDetect": "0",
6992    "PEBS": "0",
6993    "Data_LA": "0",
6994    "L1_Hit_Indication": "0",
6995    "Errata": "null",
6996    "Offcore": "1"
6997  },
6998  {
6999    "EventCode": "0xB7, 0xBB",
7000    "UMask": "0x01",
7001    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SPL_HIT",
7002    "BriefDescription": "Counts any other requests ",
7003    "PublicDescription": "Counts any other requests",
7004    "Counter": "0,1,2,3",
7005    "CounterHTOff": "0,1,2,3",
7006    "SampleAfterValue": "100003",
7007    "MSRIndex": "0x1a6,0x1a7",
7008    "MSRValue": "0x00401C8000",
7009    "TakenAlone": "0",
7010    "CounterMask": "0",
7011    "Invert": "0",
7012    "AnyThread": "0",
7013    "EdgeDetect": "0",
7014    "PEBS": "0",
7015    "Data_LA": "0",
7016    "L1_Hit_Indication": "0",
7017    "Errata": "null",
7018    "Offcore": "1"
7019  },
7020  {
7021    "EventCode": "0xB7, 0xBB",
7022    "UMask": "0x01",
7023    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.ANY_SNOOP",
7024    "BriefDescription": "Counts any other requests ",
7025    "PublicDescription": "Counts any other requests",
7026    "Counter": "0,1,2,3",
7027    "CounterHTOff": "0,1,2,3",
7028    "SampleAfterValue": "100003",
7029    "MSRIndex": "0x1a6,0x1a7",
7030    "MSRValue": "0x3FC0108000",
7031    "TakenAlone": "0",
7032    "CounterMask": "0",
7033    "Invert": "0",
7034    "AnyThread": "0",
7035    "EdgeDetect": "0",
7036    "PEBS": "0",
7037    "Data_LA": "0",
7038    "L1_Hit_Indication": "0",
7039    "Errata": "null",
7040    "Offcore": "1"
7041  },
7042  {
7043    "EventCode": "0xB7, 0xBB",
7044    "UMask": "0x01",
7045    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NON_DRAM",
7046    "BriefDescription": "Counts any other requests ",
7047    "PublicDescription": "Counts any other requests",
7048    "Counter": "0,1,2,3",
7049    "CounterHTOff": "0,1,2,3",
7050    "SampleAfterValue": "100003",
7051    "MSRIndex": "0x1a6,0x1a7",
7052    "MSRValue": "0x2000108000",
7053    "TakenAlone": "0",
7054    "CounterMask": "0",
7055    "Invert": "0",
7056    "AnyThread": "0",
7057    "EdgeDetect": "0",
7058    "PEBS": "0",
7059    "Data_LA": "0",
7060    "L1_Hit_Indication": "0",
7061    "Errata": "null",
7062    "Offcore": "1"
7063  },
7064  {
7065    "EventCode": "0xB7, 0xBB",
7066    "UMask": "0x01",
7067    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HITM",
7068    "BriefDescription": "Counts any other requests ",
7069    "PublicDescription": "Counts any other requests",
7070    "Counter": "0,1,2,3",
7071    "CounterHTOff": "0,1,2,3",
7072    "SampleAfterValue": "100003",
7073    "MSRIndex": "0x1a6,0x1a7",
7074    "MSRValue": "0x1000108000",
7075    "TakenAlone": "0",
7076    "CounterMask": "0",
7077    "Invert": "0",
7078    "AnyThread": "0",
7079    "EdgeDetect": "0",
7080    "PEBS": "0",
7081    "Data_LA": "0",
7082    "L1_Hit_Indication": "0",
7083    "Errata": "null",
7084    "Offcore": "1"
7085  },
7086  {
7087    "EventCode": "0xB7, 0xBB",
7088    "UMask": "0x01",
7089    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HIT_NO_FWD",
7090    "BriefDescription": "Counts any other requests ",
7091    "PublicDescription": "Counts any other requests",
7092    "Counter": "0,1,2,3",
7093    "CounterHTOff": "0,1,2,3",
7094    "SampleAfterValue": "100003",
7095    "MSRIndex": "0x1a6,0x1a7",
7096    "MSRValue": "0x0400108000",
7097    "TakenAlone": "0",
7098    "CounterMask": "0",
7099    "Invert": "0",
7100    "AnyThread": "0",
7101    "EdgeDetect": "0",
7102    "PEBS": "0",
7103    "Data_LA": "0",
7104    "L1_Hit_Indication": "0",
7105    "Errata": "null",
7106    "Offcore": "1"
7107  },
7108  {
7109    "EventCode": "0xB7, 0xBB",
7110    "UMask": "0x01",
7111    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_MISS",
7112    "BriefDescription": "Counts any other requests ",
7113    "PublicDescription": "Counts any other requests",
7114    "Counter": "0,1,2,3",
7115    "CounterHTOff": "0,1,2,3",
7116    "SampleAfterValue": "100003",
7117    "MSRIndex": "0x1a6,0x1a7",
7118    "MSRValue": "0x0200108000",
7119    "TakenAlone": "0",
7120    "CounterMask": "0",
7121    "Invert": "0",
7122    "AnyThread": "0",
7123    "EdgeDetect": "0",
7124    "PEBS": "0",
7125    "Data_LA": "0",
7126    "L1_Hit_Indication": "0",
7127    "Errata": "null",
7128    "Offcore": "1"
7129  },
7130  {
7131    "EventCode": "0xB7, 0xBB",
7132    "UMask": "0x01",
7133    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NOT_NEEDED",
7134    "BriefDescription": "Counts any other requests ",
7135    "PublicDescription": "Counts any other requests",
7136    "Counter": "0,1,2,3",
7137    "CounterHTOff": "0,1,2,3",
7138    "SampleAfterValue": "100003",
7139    "MSRIndex": "0x1a6,0x1a7",
7140    "MSRValue": "0x0100108000",
7141    "TakenAlone": "0",
7142    "CounterMask": "0",
7143    "Invert": "0",
7144    "AnyThread": "0",
7145    "EdgeDetect": "0",
7146    "PEBS": "0",
7147    "Data_LA": "0",
7148    "L1_Hit_Indication": "0",
7149    "Errata": "null",
7150    "Offcore": "1"
7151  },
7152  {
7153    "EventCode": "0xB7, 0xBB",
7154    "UMask": "0x01",
7155    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NONE",
7156    "BriefDescription": "Counts any other requests ",
7157    "PublicDescription": "Counts any other requests",
7158    "Counter": "0,1,2,3",
7159    "CounterHTOff": "0,1,2,3",
7160    "SampleAfterValue": "100003",
7161    "MSRIndex": "0x1a6,0x1a7",
7162    "MSRValue": "0x0080108000",
7163    "TakenAlone": "0",
7164    "CounterMask": "0",
7165    "Invert": "0",
7166    "AnyThread": "0",
7167    "EdgeDetect": "0",
7168    "PEBS": "0",
7169    "Data_LA": "0",
7170    "L1_Hit_Indication": "0",
7171    "Errata": "null",
7172    "Offcore": "1"
7173  },
7174  {
7175    "EventCode": "0xB7, 0xBB",
7176    "UMask": "0x01",
7177    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SPL_HIT",
7178    "BriefDescription": "Counts any other requests ",
7179    "PublicDescription": "Counts any other requests",
7180    "Counter": "0,1,2,3",
7181    "CounterHTOff": "0,1,2,3",
7182    "SampleAfterValue": "100003",
7183    "MSRIndex": "0x1a6,0x1a7",
7184    "MSRValue": "0x0040108000",
7185    "TakenAlone": "0",
7186    "CounterMask": "0",
7187    "Invert": "0",
7188    "AnyThread": "0",
7189    "EdgeDetect": "0",
7190    "PEBS": "0",
7191    "Data_LA": "0",
7192    "L1_Hit_Indication": "0",
7193    "Errata": "null",
7194    "Offcore": "1"
7195  },
7196  {
7197    "EventCode": "0xB7, 0xBB",
7198    "UMask": "0x01",
7199    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.ANY_SNOOP",
7200    "BriefDescription": "Counts any other requests ",
7201    "PublicDescription": "Counts any other requests",
7202    "Counter": "0,1,2,3",
7203    "CounterHTOff": "0,1,2,3",
7204    "SampleAfterValue": "100003",
7205    "MSRIndex": "0x1a6,0x1a7",
7206    "MSRValue": "0x3FC0088000",
7207    "TakenAlone": "0",
7208    "CounterMask": "0",
7209    "Invert": "0",
7210    "AnyThread": "0",
7211    "EdgeDetect": "0",
7212    "PEBS": "0",
7213    "Data_LA": "0",
7214    "L1_Hit_Indication": "0",
7215    "Errata": "null",
7216    "Offcore": "1"
7217  },
7218  {
7219    "EventCode": "0xB7, 0xBB",
7220    "UMask": "0x01",
7221    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NON_DRAM",
7222    "BriefDescription": "Counts any other requests ",
7223    "PublicDescription": "Counts any other requests",
7224    "Counter": "0,1,2,3",
7225    "CounterHTOff": "0,1,2,3",
7226    "SampleAfterValue": "100003",
7227    "MSRIndex": "0x1a6,0x1a7",
7228    "MSRValue": "0x2000088000",
7229    "TakenAlone": "0",
7230    "CounterMask": "0",
7231    "Invert": "0",
7232    "AnyThread": "0",
7233    "EdgeDetect": "0",
7234    "PEBS": "0",
7235    "Data_LA": "0",
7236    "L1_Hit_Indication": "0",
7237    "Errata": "null",
7238    "Offcore": "1"
7239  },
7240  {
7241    "EventCode": "0xB7, 0xBB",
7242    "UMask": "0x01",
7243    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HITM",
7244    "BriefDescription": "Counts any other requests ",
7245    "PublicDescription": "Counts any other requests",
7246    "Counter": "0,1,2,3",
7247    "CounterHTOff": "0,1,2,3",
7248    "SampleAfterValue": "100003",
7249    "MSRIndex": "0x1a6,0x1a7",
7250    "MSRValue": "0x1000088000",
7251    "TakenAlone": "0",
7252    "CounterMask": "0",
7253    "Invert": "0",
7254    "AnyThread": "0",
7255    "EdgeDetect": "0",
7256    "PEBS": "0",
7257    "Data_LA": "0",
7258    "L1_Hit_Indication": "0",
7259    "Errata": "null",
7260    "Offcore": "1"
7261  },
7262  {
7263    "EventCode": "0xB7, 0xBB",
7264    "UMask": "0x01",
7265    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HIT_NO_FWD",
7266    "BriefDescription": "Counts any other requests ",
7267    "PublicDescription": "Counts any other requests",
7268    "Counter": "0,1,2,3",
7269    "CounterHTOff": "0,1,2,3",
7270    "SampleAfterValue": "100003",
7271    "MSRIndex": "0x1a6,0x1a7",
7272    "MSRValue": "0x0400088000",
7273    "TakenAlone": "0",
7274    "CounterMask": "0",
7275    "Invert": "0",
7276    "AnyThread": "0",
7277    "EdgeDetect": "0",
7278    "PEBS": "0",
7279    "Data_LA": "0",
7280    "L1_Hit_Indication": "0",
7281    "Errata": "null",
7282    "Offcore": "1"
7283  },
7284  {
7285    "EventCode": "0xB7, 0xBB",
7286    "UMask": "0x01",
7287    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_MISS",
7288    "BriefDescription": "Counts any other requests ",
7289    "PublicDescription": "Counts any other requests",
7290    "Counter": "0,1,2,3",
7291    "CounterHTOff": "0,1,2,3",
7292    "SampleAfterValue": "100003",
7293    "MSRIndex": "0x1a6,0x1a7",
7294    "MSRValue": "0x0200088000",
7295    "TakenAlone": "0",
7296    "CounterMask": "0",
7297    "Invert": "0",
7298    "AnyThread": "0",
7299    "EdgeDetect": "0",
7300    "PEBS": "0",
7301    "Data_LA": "0",
7302    "L1_Hit_Indication": "0",
7303    "Errata": "null",
7304    "Offcore": "1"
7305  },
7306  {
7307    "EventCode": "0xB7, 0xBB",
7308    "UMask": "0x01",
7309    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NOT_NEEDED",
7310    "BriefDescription": "Counts any other requests ",
7311    "PublicDescription": "Counts any other requests",
7312    "Counter": "0,1,2,3",
7313    "CounterHTOff": "0,1,2,3",
7314    "SampleAfterValue": "100003",
7315    "MSRIndex": "0x1a6,0x1a7",
7316    "MSRValue": "0x0100088000",
7317    "TakenAlone": "0",
7318    "CounterMask": "0",
7319    "Invert": "0",
7320    "AnyThread": "0",
7321    "EdgeDetect": "0",
7322    "PEBS": "0",
7323    "Data_LA": "0",
7324    "L1_Hit_Indication": "0",
7325    "Errata": "null",
7326    "Offcore": "1"
7327  },
7328  {
7329    "EventCode": "0xB7, 0xBB",
7330    "UMask": "0x01",
7331    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NONE",
7332    "BriefDescription": "Counts any other requests ",
7333    "PublicDescription": "Counts any other requests",
7334    "Counter": "0,1,2,3",
7335    "CounterHTOff": "0,1,2,3",
7336    "SampleAfterValue": "100003",
7337    "MSRIndex": "0x1a6,0x1a7",
7338    "MSRValue": "0x0080088000",
7339    "TakenAlone": "0",
7340    "CounterMask": "0",
7341    "Invert": "0",
7342    "AnyThread": "0",
7343    "EdgeDetect": "0",
7344    "PEBS": "0",
7345    "Data_LA": "0",
7346    "L1_Hit_Indication": "0",
7347    "Errata": "null",
7348    "Offcore": "1"
7349  },
7350  {
7351    "EventCode": "0xB7, 0xBB",
7352    "UMask": "0x01",
7353    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SPL_HIT",
7354    "BriefDescription": "Counts any other requests ",
7355    "PublicDescription": "Counts any other requests",
7356    "Counter": "0,1,2,3",
7357    "CounterHTOff": "0,1,2,3",
7358    "SampleAfterValue": "100003",
7359    "MSRIndex": "0x1a6,0x1a7",
7360    "MSRValue": "0x0040088000",
7361    "TakenAlone": "0",
7362    "CounterMask": "0",
7363    "Invert": "0",
7364    "AnyThread": "0",
7365    "EdgeDetect": "0",
7366    "PEBS": "0",
7367    "Data_LA": "0",
7368    "L1_Hit_Indication": "0",
7369    "Errata": "null",
7370    "Offcore": "1"
7371  },
7372  {
7373    "EventCode": "0xB7, 0xBB",
7374    "UMask": "0x01",
7375    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.ANY_SNOOP",
7376    "BriefDescription": "Counts any other requests ",
7377    "PublicDescription": "Counts any other requests",
7378    "Counter": "0,1,2,3",
7379    "CounterHTOff": "0,1,2,3",
7380    "SampleAfterValue": "100003",
7381    "MSRIndex": "0x1a6,0x1a7",
7382    "MSRValue": "0x3FC0048000",
7383    "TakenAlone": "0",
7384    "CounterMask": "0",
7385    "Invert": "0",
7386    "AnyThread": "0",
7387    "EdgeDetect": "0",
7388    "PEBS": "0",
7389    "Data_LA": "0",
7390    "L1_Hit_Indication": "0",
7391    "Errata": "null",
7392    "Offcore": "1"
7393  },
7394  {
7395    "EventCode": "0xB7, 0xBB",
7396    "UMask": "0x01",
7397    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NON_DRAM",
7398    "BriefDescription": "Counts any other requests ",
7399    "PublicDescription": "Counts any other requests",
7400    "Counter": "0,1,2,3",
7401    "CounterHTOff": "0,1,2,3",
7402    "SampleAfterValue": "100003",
7403    "MSRIndex": "0x1a6,0x1a7",
7404    "MSRValue": "0x2000048000",
7405    "TakenAlone": "0",
7406    "CounterMask": "0",
7407    "Invert": "0",
7408    "AnyThread": "0",
7409    "EdgeDetect": "0",
7410    "PEBS": "0",
7411    "Data_LA": "0",
7412    "L1_Hit_Indication": "0",
7413    "Errata": "null",
7414    "Offcore": "1"
7415  },
7416  {
7417    "EventCode": "0xB7, 0xBB",
7418    "UMask": "0x01",
7419    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HITM",
7420    "BriefDescription": "Counts any other requests ",
7421    "PublicDescription": "Counts any other requests",
7422    "Counter": "0,1,2,3",
7423    "CounterHTOff": "0,1,2,3",
7424    "SampleAfterValue": "100003",
7425    "MSRIndex": "0x1a6,0x1a7",
7426    "MSRValue": "0x1000048000",
7427    "TakenAlone": "0",
7428    "CounterMask": "0",
7429    "Invert": "0",
7430    "AnyThread": "0",
7431    "EdgeDetect": "0",
7432    "PEBS": "0",
7433    "Data_LA": "0",
7434    "L1_Hit_Indication": "0",
7435    "Errata": "null",
7436    "Offcore": "1"
7437  },
7438  {
7439    "EventCode": "0xB7, 0xBB",
7440    "UMask": "0x01",
7441    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HIT_NO_FWD",
7442    "BriefDescription": "Counts any other requests ",
7443    "PublicDescription": "Counts any other requests",
7444    "Counter": "0,1,2,3",
7445    "CounterHTOff": "0,1,2,3",
7446    "SampleAfterValue": "100003",
7447    "MSRIndex": "0x1a6,0x1a7",
7448    "MSRValue": "0x0400048000",
7449    "TakenAlone": "0",
7450    "CounterMask": "0",
7451    "Invert": "0",
7452    "AnyThread": "0",
7453    "EdgeDetect": "0",
7454    "PEBS": "0",
7455    "Data_LA": "0",
7456    "L1_Hit_Indication": "0",
7457    "Errata": "null",
7458    "Offcore": "1"
7459  },
7460  {
7461    "EventCode": "0xB7, 0xBB",
7462    "UMask": "0x01",
7463    "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_MISS",
7464    "BriefDescription": "Counts any other requests ",
7465    "PublicDescription": "Counts any other requests",
7466    "Counter": "0,1,2,3",
7467    "CounterHTOff": "0,1,2,3",
7468    "SampleAfterValue": "100003",
7469    "MSRIndex": "0x1a6,0x1a7",
7470    "MSRValue": "0x0200048000",
7471    "TakenAlone": "0",
7472    "CounterMask": "0",
7473    "Invert": "0",
7474    "AnyThread": "0",
7475