1[
2  {
3    "Unit": "ARB",
4    "EventCode": "0x80",
5    "UMask": "0x01",
6    "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
7    "BriefDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.",
8    "PublicDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.",
9    "Counter": "0",
10    "CounterMask": "0",
11    "Invert": "0",
12    "EdgeDetect": "0"
13  },
14  {
15    "Unit": "ARB",
16    "EventCode": "0x81",
17    "UMask": "0x01",
18    "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
19    "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
20    "PublicDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
21    "Counter": "0,1",
22    "CounterMask": "0",
23    "Invert": "0",
24    "EdgeDetect": "0"
25  },
26  {
27    "Unit": "ARB",
28    "EventCode": "0x81",
29    "UMask": "0x20",
30    "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
31    "BriefDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.",
32    "PublicDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.",
33    "Counter": "0,1",
34    "CounterMask": "0",
35    "Invert": "0",
36    "EdgeDetect": "0"
37  },
38  {
39    "Unit": "ARB",
40    "EventCode": "0x81",
41    "UMask": "0x80",
42    "EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS",
43    "BriefDescription": "Counts the number of LLC evictions allocated.",
44    "PublicDescription": "Counts the number of LLC evictions allocated.",
45    "Counter": "0,1",
46    "CounterMask": "0",
47    "Invert": "0",
48    "EdgeDetect": "0"
49  },
50  {
51    "Unit": "ARB",
52    "EventCode": "0x83",
53    "UMask": "0x01",
54    "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL",
55    "BriefDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
56    "PublicDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
57    "Counter": "0",
58    "CounterMask": "0",
59    "Invert": "0",
60    "EdgeDetect": "0"
61  },
62  {
63    "Unit": "ARB",
64    "EventCode": "0x84",
65    "UMask": "0x01",
66    "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
67    "BriefDescription": "Number of requests allocated in Coherency Tracker.",
68    "PublicDescription": "Number of requests allocated in Coherency Tracker.",
69    "Counter": "0,1",
70    "CounterMask": "0",
71    "Invert": "0",
72    "EdgeDetect": "0"
73  },
74  {
75    "Unit": "ARB",
76    "EventCode": "0x80",
77    "UMask": "0x01",
78    "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
79    "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
80    "PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
81    "Counter": "0,1",
82    "CounterMask": "1",
83    "Invert": "0",
84    "EdgeDetect": "0"
85  },
86  {
87    "Unit": "ARB",
88    "EventCode": "0x80",
89    "UMask": "0x01",
90    "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL",
91    "BriefDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
92    "PublicDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
93    "Counter": "0,1",
94    "CounterMask": "10",
95    "Invert": "0",
96    "EdgeDetect": "0"
97  },
98  {
99    "Unit": "ARB",
100    "EventCode": "0x0",
101    "UMask": "0x01",
102    "EventName": "UNC_CLOCK.SOCKET",
103    "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
104    "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
105    "Counter": "Fixed",
106    "CounterMask": "0",
107    "Invert": "0",
108    "EdgeDetect": "0"
109  },
110  {
111    "Unit": "CBO",
112    "EventCode": "0x34",
113    "UMask": "0x11",
114    "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",
115    "BriefDescription": "L3 Lookup read request that access cache and found line in M-state.",
116    "PublicDescription": "L3 Lookup read request that access cache and found line in M-state.",
117    "Counter": "0,1",
118    "CounterMask": "0",
119    "Invert": "0",
120    "EdgeDetect": "0"
121  },
122  {
123    "Unit": "CBO",
124    "EventCode": "0x34",
125    "UMask": "0x21",
126    "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
127    "BriefDescription": "L3 Lookup write request that access cache and found line in M-state.",
128    "PublicDescription": "L3 Lookup write request that access cache and found line in M-state.",
129    "Counter": "0,1",
130    "CounterMask": "0",
131    "Invert": "0",
132    "EdgeDetect": "0"
133  },
134  {
135    "Unit": "CBO",
136    "EventCode": "0x34",
137    "UMask": "0x41",
138    "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M",
139    "BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
140    "PublicDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
141    "Counter": "0,1",
142    "CounterMask": "0",
143    "Invert": "0",
144    "EdgeDetect": "0"
145  },
146  {
147    "Unit": "CBO",
148    "EventCode": "0x34",
149    "UMask": "0x81",
150    "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
151    "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.",
152    "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
153    "Counter": "0,1",
154    "CounterMask": "0",
155    "Invert": "0",
156    "EdgeDetect": "0"
157  },
158  {
159    "Unit": "CBO",
160    "EventCode": "0x34",
161    "UMask": "0x18",
162    "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
163    "BriefDescription": "L3 Lookup read request that access cache and found line in I-state.",
164    "PublicDescription": "L3 Lookup read request that access cache and found line in I-state.",
165    "Counter": "0,1",
166    "CounterMask": "0",
167    "Invert": "0",
168    "EdgeDetect": "0"
169  },
170  {
171    "Unit": "CBO",
172    "EventCode": "0x34",
173    "UMask": "0x28",
174    "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I",
175    "BriefDescription": "L3 Lookup write request that access cache and found line in I-state.",
176    "PublicDescription": "L3 Lookup write request that access cache and found line in I-state.",
177    "Counter": "0,1",
178    "CounterMask": "0",
179    "Invert": "0",
180    "EdgeDetect": "0"
181  },
182  {
183    "Unit": "CBO",
184    "EventCode": "0x34",
185    "UMask": "0x48",
186    "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I",
187    "BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
188    "PublicDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
189    "Counter": "0,1",
190    "CounterMask": "0",
191    "Invert": "0",
192    "EdgeDetect": "0"
193  },
194  {
195    "Unit": "CBO",
196    "EventCode": "0x34",
197    "UMask": "0x88",
198    "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
199    "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.",
200    "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
201    "Counter": "0,1",
202    "CounterMask": "0",
203    "Invert": "0",
204    "EdgeDetect": "0"
205  },
206  {
207    "Unit": "CBO",
208    "EventCode": "0x34",
209    "UMask": "0x1f",
210    "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
211    "BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
212    "PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
213    "Counter": "0,1",
214    "CounterMask": "0",
215    "Invert": "0",
216    "EdgeDetect": "0"
217  },
218  {
219    "Unit": "CBO",
220    "EventCode": "0x34",
221    "UMask": "0x2f",
222    "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
223    "BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
224    "PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
225    "Counter": "0,1",
226    "CounterMask": "0",
227    "Invert": "0",
228    "EdgeDetect": "0"
229  },
230  {
231    "Unit": "CBO",
232    "EventCode": "0x34",
233    "UMask": "0x4f",
234    "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI",
235    "BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
236    "PublicDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
237    "Counter": "0,1",
238    "CounterMask": "0",
239    "Invert": "0",
240    "EdgeDetect": "0"
241  },
242  {
243    "Unit": "CBO",
244    "EventCode": "0x34",
245    "UMask": "0x8f",
246    "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
247    "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
248    "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
249    "Counter": "0,1",
250    "CounterMask": "0",
251    "Invert": "0",
252    "EdgeDetect": "0"
253  },
254  {
255    "Unit": "CBO",
256    "EventCode": "0x34",
257    "UMask": "0x86",
258    "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
259    "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
260    "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
261    "Counter": "0,1",
262    "CounterMask": "0",
263    "Invert": "0",
264    "EdgeDetect": "0"
265  },
266  {
267    "Unit": "CBO",
268    "EventCode": "0x34",
269    "UMask": "0x46",
270    "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES",
271    "BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
272    "PublicDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
273    "Counter": "0,1",
274    "CounterMask": "0",
275    "Invert": "0",
276    "EdgeDetect": "0"
277  },
278  {
279    "Unit": "CBO",
280    "EventCode": "0x34",
281    "UMask": "0x16",
282    "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
283    "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
284    "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
285    "Counter": "0,1",
286    "CounterMask": "0",
287    "Invert": "0",
288    "EdgeDetect": "0"
289  },
290  {
291    "Unit": "CBO",
292    "EventCode": "0x34",
293    "UMask": "0x26",
294    "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
295    "BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
296    "PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
297    "Counter": "0,1",
298    "CounterMask": "0",
299    "Invert": "0",
300    "EdgeDetect": "0"
301  },
302  {
303    "Unit": "CBO",
304    "EventCode": "0x22",
305    "UMask": "0x21",
306    "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL",
307    "BriefDescription": "An external snoop misses in some processor core.",
308    "PublicDescription": "An external snoop misses in some processor core.",
309    "Counter": "0,1",
310    "CounterMask": "0",
311    "Invert": "0",
312    "EdgeDetect": "0"
313  },
314  {
315    "Unit": "CBO",
316    "EventCode": "0x22",
317    "UMask": "0x41",
318    "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
319    "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
320    "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
321    "Counter": "0,1",
322    "CounterMask": "0",
323    "Invert": "0",
324    "EdgeDetect": "0"
325  },
326  {
327    "Unit": "CBO",
328    "EventCode": "0x22",
329    "UMask": "0x81",
330    "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
331    "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
332    "PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
333    "Counter": "0,1",
334    "CounterMask": "0",
335    "Invert": "0",
336    "EdgeDetect": "0"
337  },
338  {
339    "Unit": "CBO",
340    "EventCode": "0x22",
341    "UMask": "0x24",
342    "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL",
343    "BriefDescription": "An external snoop hits a non-modified line in some processor core.",
344    "PublicDescription": "An external snoop hits a non-modified line in some processor core.",
345    "Counter": "0,1",
346    "CounterMask": "0",
347    "Invert": "0",
348    "EdgeDetect": "0"
349  },
350  {
351    "Unit": "CBO",
352    "EventCode": "0x22",
353    "UMask": "0x44",
354    "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
355    "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
356    "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
357    "Counter": "0,1",
358    "CounterMask": "0",
359    "Invert": "0",
360    "EdgeDetect": "0"
361  },
362  {
363    "Unit": "CBO",
364    "EventCode": "0x22",
365    "UMask": "0x84",
366    "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION",
367    "BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
368    "PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
369    "Counter": "0,1",
370    "CounterMask": "0",
371    "Invert": "0",
372    "EdgeDetect": "0"
373  },
374  {
375    "Unit": "CBO",
376    "EventCode": "0x22",
377    "UMask": "0x28",
378    "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL",
379    "BriefDescription": "An external snoop hits a modified line in some processor core.",
380    "PublicDescription": "An external snoop hits a modified line in some processor core.",
381    "Counter": "0,1",
382    "CounterMask": "0",
383    "Invert": "0",
384    "EdgeDetect": "0"
385  },
386  {
387    "Unit": "CBO",
388    "EventCode": "0x22",
389    "UMask": "0x48",
390    "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
391    "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
392    "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
393    "Counter": "0,1",
394    "CounterMask": "0",
395    "Invert": "0",
396    "EdgeDetect": "0"
397  },
398  {
399    "Unit": "CBO",
400    "EventCode": "0x22",
401    "UMask": "0x88",
402    "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION",
403    "BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
404    "PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
405    "Counter": "0,1",
406    "CounterMask": "0",
407    "Invert": "0",
408    "EdgeDetect": "0"
409  }
410]