1[
2  {
3    "MATRIX_REQUEST": "DEMAND_DATA_RD",
4    "MATRIX_RESPONSE": "Null",
5    "MATRIX_VALUE": "0x0001 ",
6    "MATRIX_REGISTER": "0,1",
7    "DESCRIPTION": "Counts demand cacheable data reads of full cache lines"
8  },
9  {
10    "MATRIX_REQUEST": "DEMAND_RFO",
11    "MATRIX_RESPONSE": "Null",
12    "MATRIX_VALUE": "0x0002 ",
13    "MATRIX_REGISTER": "0,1",
14    "DESCRIPTION": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line"
15  },
16  {
17    "MATRIX_REQUEST": "DEMAND_CODE_RD",
18    "MATRIX_RESPONSE": "Null",
19    "MATRIX_VALUE": "0x0004 ",
20    "MATRIX_REGISTER": "0,1",
21    "DESCRIPTION": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache"
22  },
23  {
24    "MATRIX_REQUEST": "COREWB",
25    "MATRIX_RESPONSE": "Null",
26    "MATRIX_VALUE": "0x0008 ",
27    "MATRIX_REGISTER": "0",
28    "DESCRIPTION": "Counts the number of writeback transactions caused by L1 or L2 cache evictions"
29  },
30  {
31    "MATRIX_REQUEST": "PF_L2_DATA_RD",
32    "MATRIX_RESPONSE": "Null",
33    "MATRIX_VALUE": "0x0010 ",
34    "MATRIX_REGISTER": "0,1",
35    "DESCRIPTION": "Counts data cacheline reads generated by hardware L2 cache prefetcher"
36  },
37  {
38    "MATRIX_REQUEST": "PF_L2_RFO",
39    "MATRIX_RESPONSE": "Null",
40    "MATRIX_VALUE": "0x0020 ",
41    "MATRIX_REGISTER": "0,1",
42    "DESCRIPTION": "Counts reads for ownership (RFO) requests generated by L2 prefetcher"
43  },
44  {
45    "MATRIX_REQUEST": "PARTIAL_READS",
46    "MATRIX_RESPONSE": "Null",
47    "MATRIX_VALUE": "0x0080 ",
48    "MATRIX_REGISTER": "0,1",
49    "DESCRIPTION": "Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types"
50  },
51  {
52    "MATRIX_REQUEST": "PARTIAL_WRITES",
53    "MATRIX_RESPONSE": "Null",
54    "MATRIX_VALUE": "0x0100 ",
55    "MATRIX_REGISTER": "0,1",
56    "DESCRIPTION": "Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory"
57  },
58  {
59    "MATRIX_REQUEST": "UC_CODE_RD",
60    "MATRIX_RESPONSE": "Null",
61    "MATRIX_VALUE": "0x0200 ",
62    "MATRIX_REGISTER": "0,1",
63    "DESCRIPTION": "Counts code reads in uncacheable (UC) memory region"
64  },
65  {
66    "MATRIX_REQUEST": "BUS_LOCKS",
67    "MATRIX_RESPONSE": "Null",
68    "MATRIX_VALUE": "0x0400 ",
69    "MATRIX_REGISTER": "0,1",
70    "DESCRIPTION": "Counts bus lock and split lock requests"
71  },
72  {
73    "MATRIX_REQUEST": "FULL_STREAMING_STORES",
74    "MATRIX_RESPONSE": "Null",
75    "MATRIX_VALUE": "0x0800 ",
76    "MATRIX_REGISTER": "0,1",
77    "DESCRIPTION": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes"
78  },
79  {
80    "MATRIX_REQUEST": "SW_PREFETCH",
81    "MATRIX_RESPONSE": "Null",
82    "MATRIX_VALUE": "0x1000 ",
83    "MATRIX_REGISTER": "0,1",
84    "DESCRIPTION": "Counts data cache lines requests by software prefetch instructions"
85  },
86  {
87    "MATRIX_REQUEST": "PF_L1_DATA_RD",
88    "MATRIX_RESPONSE": "Null",
89    "MATRIX_VALUE": "0x2000 ",
90    "MATRIX_REGISTER": "0,1",
91    "DESCRIPTION": "Counts data cache line reads generated by hardware L1 data cache prefetcher"
92  },
93  {
94    "MATRIX_REQUEST": "PARTIAL_STREAMING_STORES",
95    "MATRIX_RESPONSE": "Null",
96    "MATRIX_VALUE": "0x4000 ",
97    "MATRIX_REGISTER": "0,1",
98    "DESCRIPTION": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region"
99  },
100  {
101    "MATRIX_REQUEST": "STREAMING_STORES",
102    "MATRIX_RESPONSE": "Null",
103    "MATRIX_VALUE": "0x4800 ",
104    "MATRIX_REGISTER": "0,1",
105    "DESCRIPTION": "Counts any data writes to uncacheable write combining (USWC) memory region"
106  },
107  {
108    "MATRIX_REQUEST": "ANY_REQUEST",
109    "MATRIX_RESPONSE": "Null",
110    "MATRIX_VALUE": "0x8000 ",
111    "MATRIX_REGISTER": "0,1",
112    "DESCRIPTION": "Counts requests to the uncore subsystem"
113  },
114  {
115    "MATRIX_REQUEST": "ANY_PF_DATA_RD",
116    "MATRIX_RESPONSE": "Null",
117    "MATRIX_VALUE": "0x3010 ",
118    "MATRIX_REGISTER": "0,1",
119    "DESCRIPTION": "Counts data reads generated by L1 or L2 prefetchers"
120  },
121  {
122    "MATRIX_REQUEST": "ANY_DATA_RD",
123    "MATRIX_RESPONSE": "Null",
124    "MATRIX_VALUE": "0x3091",
125    "MATRIX_REGISTER": "0,1",
126    "DESCRIPTION": "Counts data reads (demand & prefetch)"
127  },
128  {
129    "MATRIX_REQUEST": "ANY_RFO",
130    "MATRIX_RESPONSE": "Null",
131    "MATRIX_VALUE": "0x0022 ",
132    "MATRIX_REGISTER": "0,1",
133    "DESCRIPTION": "Counts reads for ownership (RFO) requests (demand & prefetch)"
134  },
135  {
136    "MATRIX_REQUEST": "ANY_READ",
137    "MATRIX_RESPONSE": "Null",
138    "MATRIX_VALUE": "0x32b7 ",
139    "MATRIX_REGISTER": "0,1",
140    "DESCRIPTION": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch)"
141  },
142  {
143    "MATRIX_REQUEST": "Null",
144    "MATRIX_RESPONSE": "ANY_RESPONSE",
145    "MATRIX_VALUE": "0x000001 ",
146    "MATRIX_REGISTER": "0,1",
147    "DESCRIPTION": "have any transaction responses from the uncore subsystem."
148  },
149  {
150    "MATRIX_REQUEST": "Null",
151    "MATRIX_RESPONSE": "L2_HIT",
152    "MATRIX_VALUE": "0x000004 ",
153    "MATRIX_REGISTER": "0,1",
154    "DESCRIPTION": "hit the L2 cache."
155  },
156  {
157    "MATRIX_REQUEST": "Null",
158    "MATRIX_RESPONSE": "L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
159    "MATRIX_VALUE": "0x020000 ",
160    "MATRIX_REGISTER": "0,1",
161    "DESCRIPTION": "true miss for the L2 cache with a snoop miss in the other processor module."
162  },
163  {
164    "MATRIX_REQUEST": "Null",
165    "MATRIX_RESPONSE": "L2_MISS.HIT_OTHER_CORE_NO_FWD",
166    "MATRIX_VALUE": "0x040000 ",
167    "MATRIX_REGISTER": "0,1",
168    "DESCRIPTION": "miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required."
169  },
170  {
171    "MATRIX_REQUEST": "Null",
172    "MATRIX_RESPONSE": "L2_MISS.HITM_OTHER_CORE",
173    "MATRIX_VALUE": "0x100000 ",
174    "MATRIX_REGISTER": "0,1",
175    "DESCRIPTION": "miss the L2 cache with a snoop hit in the other processor module, data forwarding is required."
176  },
177  {
178    "MATRIX_REQUEST": "Null",
179    "MATRIX_RESPONSE": "L2_MISS.NON_DRAM",
180    "MATRIX_VALUE": "0x200000 ",
181    "MATRIX_REGISTER": "0,1",
182    "DESCRIPTION": "miss the L2 cache and targets non-DRAM system address."
183  },
184  {
185    "MATRIX_REQUEST": "Null",
186    "MATRIX_RESPONSE": "L2_MISS.ANY",
187    "MATRIX_VALUE": "0x360000 ",
188    "MATRIX_REGISTER": "0,1",
189    "DESCRIPTION": "miss the L2 cache."
190  },
191  {
192    "MATRIX_REQUEST": "Null",
193    "MATRIX_RESPONSE": "OUTSTANDING",
194    "MATRIX_VALUE": "0x400000 ",
195    "MATRIX_REGISTER": "0",
196    "DESCRIPTION": "outstanding, per cycle, from the time of the L2 miss to when any response is received."
197  }
198]