1[
2  {
3    "EventCode": "0x2",
4    "UMask": "0x83",
5    "EventName": "STORE_FORWARDS.ANY",
6    "BriefDescription": "All store forwards",
7    "PublicDescription": "All store forwards",
8    "Counter": "0,1",
9    "SampleAfterValue": "200000",
10    "MSRIndex": "0",
11    "MSRValue": "0",
12    "CounterMask": "0",
13    "Invert": "0",
14    "AnyThread": "0",
15    "EdgeDetect": "0",
16    "PEBS": "0",
17    "Errata": "null",
18    "Offcore": "0"
19  },
20  {
21    "EventCode": "0x2",
22    "UMask": "0x81",
23    "EventName": "STORE_FORWARDS.GOOD",
24    "BriefDescription": "Good store forwards",
25    "PublicDescription": "Good store forwards",
26    "Counter": "0,1",
27    "SampleAfterValue": "200000",
28    "MSRIndex": "0",
29    "MSRValue": "0",
30    "CounterMask": "0",
31    "Invert": "0",
32    "AnyThread": "0",
33    "EdgeDetect": "0",
34    "PEBS": "0",
35    "Errata": "null",
36    "Offcore": "0"
37  },
38  {
39    "EventCode": "0x3",
40    "UMask": "0x7F",
41    "EventName": "REISSUE.ANY",
42    "BriefDescription": "Micro-op reissues for any cause",
43    "PublicDescription": "Micro-op reissues for any cause",
44    "Counter": "0,1",
45    "SampleAfterValue": "200000",
46    "MSRIndex": "0",
47    "MSRValue": "0",
48    "CounterMask": "0",
49    "Invert": "0",
50    "AnyThread": "0",
51    "EdgeDetect": "0",
52    "PEBS": "0",
53    "Errata": "null",
54    "Offcore": "0"
55  },
56  {
57    "EventCode": "0x3",
58    "UMask": "0xFF",
59    "EventName": "REISSUE.ANY.AR",
60    "BriefDescription": "Micro-op reissues for any cause (At Retirement)",
61    "PublicDescription": "Micro-op reissues for any cause (At Retirement)",
62    "Counter": "0,1",
63    "SampleAfterValue": "200000",
64    "MSRIndex": "0",
65    "MSRValue": "0",
66    "CounterMask": "0",
67    "Invert": "0",
68    "AnyThread": "0",
69    "EdgeDetect": "0",
70    "PEBS": "0",
71    "Errata": "null",
72    "Offcore": "0"
73  },
74  {
75    "EventCode": "0x5",
76    "UMask": "0xF",
77    "EventName": "MISALIGN_MEM_REF.SPLIT",
78    "BriefDescription": "Memory references that cross an 8-byte boundary.",
79    "PublicDescription": "Memory references that cross an 8-byte boundary.",
80    "Counter": "0,1",
81    "SampleAfterValue": "200000",
82    "MSRIndex": "0",
83    "MSRValue": "0",
84    "CounterMask": "0",
85    "Invert": "0",
86    "AnyThread": "0",
87    "EdgeDetect": "0",
88    "PEBS": "0",
89    "Errata": "null",
90    "Offcore": "0"
91  },
92  {
93    "EventCode": "0x5",
94    "UMask": "0x9",
95    "EventName": "MISALIGN_MEM_REF.LD_SPLIT",
96    "BriefDescription": "Load splits",
97    "PublicDescription": "Load splits",
98    "Counter": "0,1",
99    "SampleAfterValue": "200000",
100    "MSRIndex": "0",
101    "MSRValue": "0",
102    "CounterMask": "0",
103    "Invert": "0",
104    "AnyThread": "0",
105    "EdgeDetect": "0",
106    "PEBS": "0",
107    "Errata": "null",
108    "Offcore": "0"
109  },
110  {
111    "EventCode": "0x5",
112    "UMask": "0xA",
113    "EventName": "MISALIGN_MEM_REF.ST_SPLIT",
114    "BriefDescription": "Store splits",
115    "PublicDescription": "Store splits",
116    "Counter": "0,1",
117    "SampleAfterValue": "200000",
118    "MSRIndex": "0",
119    "MSRValue": "0",
120    "CounterMask": "0",
121    "Invert": "0",
122    "AnyThread": "0",
123    "EdgeDetect": "0",
124    "PEBS": "0",
125    "Errata": "null",
126    "Offcore": "0"
127  },
128  {
129    "EventCode": "0x5",
130    "UMask": "0x8F",
131    "EventName": "MISALIGN_MEM_REF.SPLIT.AR",
132    "BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)",
133    "PublicDescription": "Memory references that cross an 8-byte boundary (At Retirement)",
134    "Counter": "0,1",
135    "SampleAfterValue": "200000",
136    "MSRIndex": "0",
137    "MSRValue": "0",
138    "CounterMask": "0",
139    "Invert": "0",
140    "AnyThread": "0",
141    "EdgeDetect": "0",
142    "PEBS": "0",
143    "Errata": "null",
144    "Offcore": "0"
145  },
146  {
147    "EventCode": "0x5",
148    "UMask": "0x89",
149    "EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR",
150    "BriefDescription": "Load splits (At Retirement)",
151    "PublicDescription": "Load splits (At Retirement)",
152    "Counter": "0,1",
153    "SampleAfterValue": "200000",
154    "MSRIndex": "0",
155    "MSRValue": "0",
156    "CounterMask": "0",
157    "Invert": "0",
158    "AnyThread": "0",
159    "EdgeDetect": "0",
160    "PEBS": "0",
161    "Errata": "null",
162    "Offcore": "0"
163  },
164  {
165    "EventCode": "0x5",
166    "UMask": "0x8A",
167    "EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR",
168    "BriefDescription": "Store splits (Ar Retirement)",
169    "PublicDescription": "Store splits (Ar Retirement)",
170    "Counter": "0,1",
171    "SampleAfterValue": "200000",
172    "MSRIndex": "0",
173    "MSRValue": "0",
174    "CounterMask": "0",
175    "Invert": "0",
176    "AnyThread": "0",
177    "EdgeDetect": "0",
178    "PEBS": "0",
179    "Errata": "null",
180    "Offcore": "0"
181  },
182  {
183    "EventCode": "0x5",
184    "UMask": "0x8C",
185    "EventName": "MISALIGN_MEM_REF.RMW_SPLIT",
186    "BriefDescription": "ld-op-st splits",
187    "PublicDescription": "ld-op-st splits",
188    "Counter": "0,1",
189    "SampleAfterValue": "200000",
190    "MSRIndex": "0",
191    "MSRValue": "0",
192    "CounterMask": "0",
193    "Invert": "0",
194    "AnyThread": "0",
195    "EdgeDetect": "0",
196    "PEBS": "0",
197    "Errata": "null",
198    "Offcore": "0"
199  },
200  {
201    "EventCode": "0x5",
202    "UMask": "0x97",
203    "EventName": "MISALIGN_MEM_REF.BUBBLE",
204    "BriefDescription": "Nonzero segbase 1 bubble",
205    "PublicDescription": "Nonzero segbase 1 bubble",
206    "Counter": "0,1",
207    "SampleAfterValue": "200000",
208    "MSRIndex": "0",
209    "MSRValue": "0",
210    "CounterMask": "0",
211    "Invert": "0",
212    "AnyThread": "0",
213    "EdgeDetect": "0",
214    "PEBS": "0",
215    "Errata": "null",
216    "Offcore": "0"
217  },
218  {
219    "EventCode": "0x5",
220    "UMask": "0x91",
221    "EventName": "MISALIGN_MEM_REF.LD_BUBBLE",
222    "BriefDescription": "Nonzero segbase load 1 bubble",
223    "PublicDescription": "Nonzero segbase load 1 bubble",
224    "Counter": "0,1",
225    "SampleAfterValue": "200000",
226    "MSRIndex": "0",
227    "MSRValue": "0",
228    "CounterMask": "0",
229    "Invert": "0",
230    "AnyThread": "0",
231    "EdgeDetect": "0",
232    "PEBS": "0",
233    "Errata": "null",
234    "Offcore": "0"
235  },
236  {
237    "EventCode": "0x5",
238    "UMask": "0x92",
239    "EventName": "MISALIGN_MEM_REF.ST_BUBBLE",
240    "BriefDescription": "Nonzero segbase store 1 bubble",
241    "PublicDescription": "Nonzero segbase store 1 bubble",
242    "Counter": "0,1",
243    "SampleAfterValue": "200000",
244    "MSRIndex": "0",
245    "MSRValue": "0",
246    "CounterMask": "0",
247    "Invert": "0",
248    "AnyThread": "0",
249    "EdgeDetect": "0",
250    "PEBS": "0",
251    "Errata": "null",
252    "Offcore": "0"
253  },
254  {
255    "EventCode": "0x5",
256    "UMask": "0x94",
257    "EventName": "MISALIGN_MEM_REF.RMW_BUBBLE",
258    "BriefDescription": "Nonzero segbase ld-op-st 1 bubble",
259    "PublicDescription": "Nonzero segbase ld-op-st 1 bubble",
260    "Counter": "0,1",
261    "SampleAfterValue": "200000",
262    "MSRIndex": "0",
263    "MSRValue": "0",
264    "CounterMask": "0",
265    "Invert": "0",
266    "AnyThread": "0",
267    "EdgeDetect": "0",
268    "PEBS": "0",
269    "Errata": "null",
270    "Offcore": "0"
271  },
272  {
273    "EventCode": "0x6",
274    "UMask": "0x80",
275    "EventName": "SEGMENT_REG_LOADS.ANY",
276    "BriefDescription": "Number of segment register loads.",
277    "PublicDescription": "Number of segment register loads.",
278    "Counter": "0,1",
279    "SampleAfterValue": "200000",
280    "MSRIndex": "0",
281    "MSRValue": "0",
282    "CounterMask": "0",
283    "Invert": "0",
284    "AnyThread": "0",
285    "EdgeDetect": "0",
286    "PEBS": "0",
287    "Errata": "null",
288    "Offcore": "0"
289  },
290  {
291    "EventCode": "0x7",
292    "UMask": "0x81",
293    "EventName": "PREFETCH.PREFETCHT0",
294    "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed.",
295    "PublicDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed.",
296    "Counter": "0,1",
297    "SampleAfterValue": "200000",
298    "MSRIndex": "0",
299    "MSRValue": "0",
300    "CounterMask": "0",
301    "Invert": "0",
302    "AnyThread": "0",
303    "EdgeDetect": "0",
304    "PEBS": "0",
305    "Errata": "null",
306    "Offcore": "0"
307  },
308  {
309    "EventCode": "0x7",
310    "UMask": "0x82",
311    "EventName": "PREFETCH.PREFETCHT1",
312    "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed.",
313    "PublicDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed.",
314    "Counter": "0,1",
315    "SampleAfterValue": "200000",
316    "MSRIndex": "0",
317    "MSRValue": "0",
318    "CounterMask": "0",
319    "Invert": "0",
320    "AnyThread": "0",
321    "EdgeDetect": "0",
322    "PEBS": "0",
323    "Errata": "null",
324    "Offcore": "0"
325  },
326  {
327    "EventCode": "0x7",
328    "UMask": "0x84",
329    "EventName": "PREFETCH.PREFETCHT2",
330    "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed.",
331    "PublicDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed.",
332    "Counter": "0,1",
333    "SampleAfterValue": "200000",
334    "MSRIndex": "0",
335    "MSRValue": "0",
336    "CounterMask": "0",
337    "Invert": "0",
338    "AnyThread": "0",
339    "EdgeDetect": "0",
340    "PEBS": "0",
341    "Errata": "null",
342    "Offcore": "0"
343  },
344  {
345    "EventCode": "0x7",
346    "UMask": "0x86",
347    "EventName": "PREFETCH.SW_L2",
348    "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed",
349    "PublicDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed",
350    "Counter": "0,1",
351    "SampleAfterValue": "200000",
352    "MSRIndex": "0",
353    "MSRValue": "0",
354    "CounterMask": "0",
355    "Invert": "0",
356    "AnyThread": "0",
357    "EdgeDetect": "0",
358    "PEBS": "0",
359    "Errata": "null",
360    "Offcore": "0"
361  },
362  {
363    "EventCode": "0x7",
364    "UMask": "0x88",
365    "EventName": "PREFETCH.PREFETCHNTA",
366    "BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed",
367    "PublicDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed",
368    "Counter": "0,1",
369    "SampleAfterValue": "200000",
370    "MSRIndex": "0",
371    "MSRValue": "0",
372    "CounterMask": "0",
373    "Invert": "0",
374    "AnyThread": "0",
375    "EdgeDetect": "0",
376    "PEBS": "0",
377    "Errata": "null",
378    "Offcore": "0"
379  },
380  {
381    "EventCode": "0x7",
382    "UMask": "0x10",
383    "EventName": "PREFETCH.HW_PREFETCH",
384    "BriefDescription": "L1 hardware prefetch request",
385    "PublicDescription": "L1 hardware prefetch request",
386    "Counter": "0,1",
387    "SampleAfterValue": "2000000",
388    "MSRIndex": "0",
389    "MSRValue": "0",
390    "CounterMask": "0",
391    "Invert": "0",
392    "AnyThread": "0",
393    "EdgeDetect": "0",
394    "PEBS": "0",
395    "Errata": "null",
396    "Offcore": "0"
397  },
398  {
399    "EventCode": "0x7",
400    "UMask": "0xF",
401    "EventName": "PREFETCH.SOFTWARE_PREFETCH",
402    "BriefDescription": "Any Software prefetch",
403    "PublicDescription": "Any Software prefetch",
404    "Counter": "0,1",
405    "SampleAfterValue": "200000",
406    "MSRIndex": "0",
407    "MSRValue": "0",
408    "CounterMask": "0",
409    "Invert": "0",
410    "AnyThread": "0",
411    "EdgeDetect": "0",
412    "PEBS": "0",
413    "Errata": "null",
414    "Offcore": "0"
415  },
416  {
417    "EventCode": "0x7",
418    "UMask": "0x8F",
419    "EventName": "PREFETCH.SOFTWARE_PREFETCH.AR",
420    "BriefDescription": "Any Software prefetch",
421    "PublicDescription": "Any Software prefetch",
422    "Counter": "0,1",
423    "SampleAfterValue": "200000",
424    "MSRIndex": "0",
425    "MSRValue": "0",
426    "CounterMask": "0",
427    "Invert": "0",
428    "AnyThread": "0",
429    "EdgeDetect": "0",
430    "PEBS": "0",
431    "Errata": "null",
432    "Offcore": "0"
433  },
434  {
435    "EventCode": "0x8",
436    "UMask": "0x7",
437    "EventName": "DATA_TLB_MISSES.DTLB_MISS",
438    "BriefDescription": "Memory accesses that missed the DTLB.",
439    "PublicDescription": "Memory accesses that missed the DTLB.",
440    "Counter": "0,1",
441    "SampleAfterValue": "200000",
442    "MSRIndex": "0",
443    "MSRValue": "0",
444    "CounterMask": "0",
445    "Invert": "0",
446    "AnyThread": "0",
447    "EdgeDetect": "0",
448    "PEBS": "0",
449    "Errata": "null",
450    "Offcore": "0"
451  },
452  {
453    "EventCode": "0x8",
454    "UMask": "0x5",
455    "EventName": "DATA_TLB_MISSES.DTLB_MISS_LD",
456    "BriefDescription": "DTLB misses due to load operations.",
457    "PublicDescription": "DTLB misses due to load operations.",
458    "Counter": "0,1",
459    "SampleAfterValue": "200000",
460    "MSRIndex": "0",
461    "MSRValue": "0",
462    "CounterMask": "0",
463    "Invert": "0",
464    "AnyThread": "0",
465    "EdgeDetect": "0",
466    "PEBS": "0",
467    "Errata": "null",
468    "Offcore": "0"
469  },
470  {
471    "EventCode": "0x8",
472    "UMask": "0x9",
473    "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD",
474    "BriefDescription": "L0 DTLB misses due to load operations.",
475    "PublicDescription": "L0 DTLB misses due to load operations.",
476    "Counter": "0,1",
477    "SampleAfterValue": "200000",
478    "MSRIndex": "0",
479    "MSRValue": "0",
480    "CounterMask": "0",
481    "Invert": "0",
482    "AnyThread": "0",
483    "EdgeDetect": "0",
484    "PEBS": "0",
485    "Errata": "null",
486    "Offcore": "0"
487  },
488  {
489    "EventCode": "0x8",
490    "UMask": "0x6",
491    "EventName": "DATA_TLB_MISSES.DTLB_MISS_ST",
492    "BriefDescription": "DTLB misses due to store operations.",
493    "PublicDescription": "DTLB misses due to store operations.",
494    "Counter": "0,1",
495    "SampleAfterValue": "200000",
496    "MSRIndex": "0",
497    "MSRValue": "0",
498    "CounterMask": "0",
499    "Invert": "0",
500    "AnyThread": "0",
501    "EdgeDetect": "0",
502    "PEBS": "0",
503    "Errata": "null",
504    "Offcore": "0"
505  },
506  {
507    "EventCode": "0x8",
508    "UMask": "0xA",
509    "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST",
510    "BriefDescription": "L0 DTLB misses due to store operations",
511    "PublicDescription": "L0 DTLB misses due to store operations",
512    "Counter": "0,1",
513    "SampleAfterValue": "200000",
514    "MSRIndex": "0",
515    "MSRValue": "0",
516    "CounterMask": "0",
517    "Invert": "0",
518    "AnyThread": "0",
519    "EdgeDetect": "0",
520    "PEBS": "0",
521    "Errata": "null",
522    "Offcore": "0"
523  },
524  {
525    "EventCode": "0x9",
526    "UMask": "0x20",
527    "EventName": "DISPATCH_BLOCKED.ANY",
528    "BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason",
529    "PublicDescription": "Memory cluster signals to block micro-op dispatch for any reason",
530    "Counter": "0,1",
531    "SampleAfterValue": "200000",
532    "MSRIndex": "0",
533    "MSRValue": "0",
534    "CounterMask": "0",
535    "Invert": "0",
536    "AnyThread": "0",
537    "EdgeDetect": "0",
538    "PEBS": "0",
539    "Errata": "null",
540    "Offcore": "0"
541  },
542  {
543    "EventCode": "0xC",
544    "UMask": "0x3",
545    "EventName": "PAGE_WALKS.WALKS",
546    "BriefDescription": "Number of page-walks executed.",
547    "PublicDescription": "Number of page-walks executed.",
548    "Counter": "0,1",
549    "SampleAfterValue": "200000",
550    "MSRIndex": "0",
551    "MSRValue": "0",
552    "CounterMask": "0",
553    "Invert": "0",
554    "AnyThread": "0",
555    "EdgeDetect": "0",
556    "PEBS": "0",
557    "Errata": "null",
558    "Offcore": "0"
559  },
560  {
561    "EventCode": "0xC",
562    "UMask": "0x3",
563    "EventName": "PAGE_WALKS.CYCLES",
564    "BriefDescription": "Duration of page-walks in core cycles",
565    "PublicDescription": "Duration of page-walks in core cycles",
566    "Counter": "0,1",
567    "SampleAfterValue": "2000000",
568    "MSRIndex": "0",
569    "MSRValue": "0",
570    "CounterMask": "0",
571    "Invert": "0",
572    "AnyThread": "0",
573    "EdgeDetect": "0",
574    "PEBS": "0",
575    "Errata": "null",
576    "Offcore": "0"
577  },
578  {
579    "EventCode": "0xC",
580    "UMask": "0x1",
581    "EventName": "PAGE_WALKS.D_SIDE_WALKS",
582    "BriefDescription": "Number of D-side only page walks",
583    "PublicDescription": "Number of D-side only page walks",
584    "Counter": "0,1",
585    "SampleAfterValue": "200000",
586    "MSRIndex": "0",
587    "MSRValue": "0",
588    "CounterMask": "0",
589    "Invert": "0",
590    "AnyThread": "0",
591    "EdgeDetect": "0",
592    "PEBS": "0",
593    "Errata": "null",
594    "Offcore": "0"
595  },
596  {
597    "EventCode": "0xC",
598    "UMask": "0x1",
599    "EventName": "PAGE_WALKS.D_SIDE_CYCLES",
600    "BriefDescription": "Duration of D-side only page walks",
601    "PublicDescription": "Duration of D-side only page walks",
602    "Counter": "0,1",
603    "SampleAfterValue": "2000000",
604    "MSRIndex": "0",
605    "MSRValue": "0",
606    "CounterMask": "0",
607    "Invert": "0",
608    "AnyThread": "0",
609    "EdgeDetect": "0",
610    "PEBS": "0",
611    "Errata": "null",
612    "Offcore": "0"
613  },
614  {
615    "EventCode": "0xC",
616    "UMask": "0x2",
617    "EventName": "PAGE_WALKS.I_SIDE_WALKS",
618    "BriefDescription": "Number of I-Side page walks",
619    "PublicDescription": "Number of I-Side page walks",
620    "Counter": "0,1",
621    "SampleAfterValue": "200000",
622    "MSRIndex": "0",
623    "MSRValue": "0",
624    "CounterMask": "0",
625    "Invert": "0",
626    "AnyThread": "0",
627    "EdgeDetect": "0",
628    "PEBS": "0",
629    "Errata": "null",
630    "Offcore": "0"
631  },
632  {
633    "EventCode": "0xC",
634    "UMask": "0x2",
635    "EventName": "PAGE_WALKS.I_SIDE_CYCLES",
636    "BriefDescription": "Duration of I-Side page walks",
637    "PublicDescription": "Duration of I-Side page walks",
638    "Counter": "0,1",
639    "SampleAfterValue": "2000000",
640    "MSRIndex": "0",
641    "MSRValue": "0",
642    "CounterMask": "0",
643    "Invert": "0",
644    "AnyThread": "0",
645    "EdgeDetect": "0",
646    "PEBS": "0",
647    "Errata": "null",
648    "Offcore": "0"
649  },
650  {
651    "EventCode": "0x10",
652    "UMask": "0x1",
653    "EventName": "X87_COMP_OPS_EXE.ANY.S",
654    "BriefDescription": "Floating point computational micro-ops executed.",
655    "PublicDescription": "Floating point computational micro-ops executed.",
656    "Counter": "0,1",
657    "SampleAfterValue": "2000000",
658    "MSRIndex": "0",
659    "MSRValue": "0",
660    "CounterMask": "0",
661    "Invert": "0",
662    "AnyThread": "0",
663    "EdgeDetect": "0",
664    "PEBS": "0",
665    "Errata": "null",
666    "Offcore": "0"
667  },
668  {
669    "EventCode": "0x10",
670    "UMask": "0x81",
671    "EventName": "X87_COMP_OPS_EXE.ANY.AR",
672    "BriefDescription": "Floating point computational micro-ops retired.",
673    "PublicDescription": "Floating point computational micro-ops retired.",
674    "Counter": "0,1",
675    "SampleAfterValue": "2000000",
676    "MSRIndex": "0",
677    "MSRValue": "0",
678    "CounterMask": "0",
679    "Invert": "0",
680    "AnyThread": "0",
681    "EdgeDetect": "0",
682    "PEBS": "2",
683    "Errata": "null",
684    "Offcore": "0"
685  },
686  {
687    "EventCode": "0x10",
688    "UMask": "0x2",
689    "EventName": "X87_COMP_OPS_EXE.FXCH.S",
690    "BriefDescription": "FXCH uops executed.",
691    "PublicDescription": "FXCH uops executed.",
692    "Counter": "0,1",
693    "SampleAfterValue": "2000000",
694    "MSRIndex": "0",
695    "MSRValue": "0",
696    "CounterMask": "0",
697    "Invert": "0",
698    "AnyThread": "0",
699    "EdgeDetect": "0",
700    "PEBS": "0",
701    "Errata": "null",
702    "Offcore": "0"
703  },
704  {
705    "EventCode": "0x10",
706    "UMask": "0x82",
707    "EventName": "X87_COMP_OPS_EXE.FXCH.AR",
708    "BriefDescription": "FXCH uops retired.",
709    "PublicDescription": "FXCH uops retired.",
710    "Counter": "0,1",
711    "SampleAfterValue": "2000000",
712    "MSRIndex": "0",
713    "MSRValue": "0",
714    "CounterMask": "0",
715    "Invert": "0",
716    "AnyThread": "0",
717    "EdgeDetect": "0",
718    "PEBS": "2",
719    "Errata": "null",
720    "Offcore": "0"
721  },
722  {
723    "EventCode": "0x11",
724    "UMask": "0x1",
725    "EventName": "FP_ASSIST.S",
726    "BriefDescription": "Floating point assists.",
727    "PublicDescription": "Floating point assists.",
728    "Counter": "0,1",
729    "SampleAfterValue": "10000",
730    "MSRIndex": "0",
731    "MSRValue": "0",
732    "CounterMask": "0",
733    "Invert": "0",
734    "AnyThread": "0",
735    "EdgeDetect": "0",
736    "PEBS": "0",
737    "Errata": "null",
738    "Offcore": "0"
739  },
740  {
741    "EventCode": "0x11",
742    "UMask": "0x81",
743    "EventName": "FP_ASSIST.AR",
744    "BriefDescription": "Floating point assists for retired operations.",
745    "PublicDescription": "Floating point assists for retired operations.",
746    "Counter": "0,1",
747    "SampleAfterValue": "10000",
748    "MSRIndex": "0",
749    "MSRValue": "0",
750    "CounterMask": "0",
751    "Invert": "0",
752    "AnyThread": "0",
753    "EdgeDetect": "0",
754    "PEBS": "0",
755    "Errata": "null",
756    "Offcore": "0"
757  },
758  {
759    "EventCode": "0x12",
760    "UMask": "0x1",
761    "EventName": "MUL.S",
762    "BriefDescription": "Multiply operations executed.",
763    "PublicDescription": "Multiply operations executed.",
764    "Counter": "0,1",
765    "SampleAfterValue": "2000000",
766    "MSRIndex": "0",
767    "MSRValue": "0",
768    "CounterMask": "0",
769    "Invert": "0",
770    "AnyThread": "0",
771    "EdgeDetect": "0",
772    "PEBS": "0",
773    "Errata": "null",
774    "Offcore": "0"
775  },
776  {
777    "EventCode": "0x12",
778    "UMask": "0x81",
779    "EventName": "MUL.AR",
780    "BriefDescription": "Multiply operations retired",
781    "PublicDescription": "Multiply operations retired",
782    "Counter": "0,1",
783    "SampleAfterValue": "2000000",
784    "MSRIndex": "0",
785    "MSRValue": "0",
786    "CounterMask": "0",
787    "Invert": "0",
788    "AnyThread": "0",
789    "EdgeDetect": "0",
790    "PEBS": "0",
791    "Errata": "null",
792    "Offcore": "0"
793  },
794  {
795    "EventCode": "0x13",
796    "UMask": "0x1",
797    "EventName": "DIV.S",
798    "BriefDescription": "Divide operations executed.",
799    "PublicDescription": "Divide operations executed.",
800    "Counter": "0,1",
801    "SampleAfterValue": "2000000",
802    "MSRIndex": "0",
803    "MSRValue": "0",
804    "CounterMask": "0",
805    "Invert": "0",
806    "AnyThread": "0",
807    "EdgeDetect": "0",
808    "PEBS": "0",
809    "Errata": "null",
810    "Offcore": "0"
811  },
812  {
813    "EventCode": "0x13",
814    "UMask": "0x81",
815    "EventName": "DIV.AR",
816    "BriefDescription": "Divide operations retired",
817    "PublicDescription": "Divide operations retired",
818    "Counter": "0,1",
819    "SampleAfterValue": "2000000",
820    "MSRIndex": "0",
821    "MSRValue": "0",
822    "CounterMask": "0",
823    "Invert": "0",
824    "AnyThread": "0",
825    "EdgeDetect": "0",
826    "PEBS": "0",
827    "Errata": "null",
828    "Offcore": "0"
829  },
830  {
831    "EventCode": "0x14",
832    "UMask": "0x1",
833    "EventName": "CYCLES_DIV_BUSY",
834    "BriefDescription": "Cycles the divider is busy.",
835    "PublicDescription": "Cycles the divider is busy.",
836    "Counter": "0,1",
837    "SampleAfterValue": "2000000",
838    "MSRIndex": "0",
839    "MSRValue": "0",
840    "CounterMask": "0",
841    "Invert": "0",
842    "AnyThread": "0",
843    "EdgeDetect": "0",
844    "PEBS": "0",
845    "Errata": "null",
846    "Offcore": "0"
847  },
848  {
849    "EventCode": "0x21",
850    "UMask": "0x40",
851    "EventName": "L2_ADS.SELF",
852    "BriefDescription": "Cycles L2 address bus is in use.",
853    "PublicDescription": "Cycles L2 address bus is in use.",
854    "Counter": "0,1",
855    "SampleAfterValue": "200000",
856    "MSRIndex": "0",
857    "MSRValue": "0",
858    "CounterMask": "0",
859    "Invert": "0",
860    "AnyThread": "0",
861    "EdgeDetect": "0",
862    "PEBS": "0",
863    "Errata": "null",
864    "Offcore": "0"
865  },
866  {
867    "EventCode": "0x22",
868    "UMask": "0x40",
869    "EventName": "L2_DBUS_BUSY.SELF",
870    "BriefDescription": "Cycles the L2 cache data bus is busy.",
871    "PublicDescription": "Cycles the L2 cache data bus is busy.",
872    "Counter": "0,1",
873    "SampleAfterValue": "200000",
874    "MSRIndex": "0",
875    "MSRValue": "0",
876    "CounterMask": "0",
877    "Invert": "0",
878    "AnyThread": "0",
879    "EdgeDetect": "0",
880    "PEBS": "0",
881    "Errata": "null",
882    "Offcore": "0"
883  },
884  {
885    "EventCode": "0x23",
886    "UMask": "0x40",
887    "EventName": "L2_DBUS_BUSY_RD.SELF",
888    "BriefDescription": "Cycles the L2 transfers data to the core.",
889    "PublicDescription": "Cycles the L2 transfers data to the core.",
890    "Counter": "0,1",
891    "SampleAfterValue": "200000",
892    "MSRIndex": "0",
893    "MSRValue": "0",
894    "CounterMask": "0",
895    "Invert": "0",
896    "AnyThread": "0",
897    "EdgeDetect": "0",
898    "PEBS": "0",
899    "Errata": "null",
900    "Offcore": "0"
901  },
902  {
903    "EventCode": "0x24",
904    "UMask": "0x70",
905    "EventName": "L2_LINES_IN.SELF.ANY",
906    "BriefDescription": "L2 cache misses.",
907    "PublicDescription": "L2 cache misses.",
908    "Counter": "0,1",
909    "SampleAfterValue": "200000",
910    "MSRIndex": "0",
911    "MSRValue": "0",
912    "CounterMask": "0",
913    "Invert": "0",
914    "AnyThread": "0",
915    "EdgeDetect": "0",
916    "PEBS": "0",
917    "Errata": "null",
918    "Offcore": "0"
919  },
920  {
921    "EventCode": "0x24",
922    "UMask": "0x40",
923    "EventName": "L2_LINES_IN.SELF.DEMAND",
924    "BriefDescription": "L2 cache misses.",
925    "PublicDescription": "L2 cache misses.",
926    "Counter": "0,1",
927    "SampleAfterValue": "200000",
928    "MSRIndex": "0",
929    "MSRValue": "0",
930    "CounterMask": "0",
931    "Invert": "0",
932    "AnyThread": "0",
933    "EdgeDetect": "0",
934    "PEBS": "0",
935    "Errata": "null",
936    "Offcore": "0"
937  },
938  {
939    "EventCode": "0x24",
940    "UMask": "0x50",
941    "EventName": "L2_LINES_IN.SELF.PREFETCH",
942    "BriefDescription": "L2 cache misses.",
943    "PublicDescription": "L2 cache misses.",
944    "Counter": "0,1",
945    "SampleAfterValue": "200000",
946    "MSRIndex": "0",
947    "MSRValue": "0",
948    "CounterMask": "0",
949    "Invert": "0",
950    "AnyThread": "0",
951    "EdgeDetect": "0",
952    "PEBS": "0",
953    "Errata": "null",
954    "Offcore": "0"
955  },
956  {
957    "EventCode": "0x25",
958    "UMask": "0x40",
959    "EventName": "L2_M_LINES_IN.SELF",
960    "BriefDescription": "L2 cache line modifications.",
961    "PublicDescription": "L2 cache line modifications.",
962    "Counter": "0,1",
963    "SampleAfterValue": "200000",
964    "MSRIndex": "0",
965    "MSRValue": "0",
966    "CounterMask": "0",
967    "Invert": "0",
968    "AnyThread": "0",
969    "EdgeDetect": "0",
970    "PEBS": "0",
971    "Errata": "null",
972    "Offcore": "0"
973  },
974  {
975    "EventCode": "0x26",
976    "UMask": "0x70",
977    "EventName": "L2_LINES_OUT.SELF.ANY",
978    "BriefDescription": "L2 cache lines evicted.",
979    "PublicDescription": "L2 cache lines evicted.",
980    "Counter": "0,1",
981    "SampleAfterValue": "200000",
982    "MSRIndex": "0",
983    "MSRValue": "0",
984    "CounterMask": "0",
985    "Invert": "0",
986    "AnyThread": "0",
987    "EdgeDetect": "0",
988    "PEBS": "0",
989    "Errata": "null",
990    "Offcore": "0"
991  },
992  {
993    "EventCode": "0x26",
994    "UMask": "0x40",
995    "EventName": "L2_LINES_OUT.SELF.DEMAND",
996    "BriefDescription": "L2 cache lines evicted.",
997    "PublicDescription": "L2 cache lines evicted.",
998    "Counter": "0,1",
999    "SampleAfterValue": "200000",
1000    "MSRIndex": "0",
1001    "MSRValue": "0",
1002    "CounterMask": "0",
1003    "Invert": "0",
1004    "AnyThread": "0",
1005    "EdgeDetect": "0",
1006    "PEBS": "0",
1007    "Errata": "null",
1008    "Offcore": "0"
1009  },
1010  {
1011    "EventCode": "0x26",
1012    "UMask": "0x50",
1013    "EventName": "L2_LINES_OUT.SELF.PREFETCH",
1014    "BriefDescription": "L2 cache lines evicted.",
1015    "PublicDescription": "L2 cache lines evicted.",
1016    "Counter": "0,1",
1017    "SampleAfterValue": "200000",
1018    "MSRIndex": "0",
1019    "MSRValue": "0",
1020    "CounterMask": "0",
1021    "Invert": "0",
1022    "AnyThread": "0",
1023    "EdgeDetect": "0",
1024    "PEBS": "0",
1025    "Errata": "null",
1026    "Offcore": "0"
1027  },
1028  {
1029    "EventCode": "0x27",
1030    "UMask": "0x70",
1031    "EventName": "L2_M_LINES_OUT.SELF.ANY",
1032    "BriefDescription": "Modified lines evicted from the L2 cache",
1033    "PublicDescription": "Modified lines evicted from the L2 cache",
1034    "Counter": "0,1",
1035    "SampleAfterValue": "200000",
1036    "MSRIndex": "0",
1037    "MSRValue": "0",
1038    "CounterMask": "0",
1039    "Invert": "0",
1040    "AnyThread": "0",
1041    "EdgeDetect": "0",
1042    "PEBS": "0",
1043    "Errata": "null",
1044    "Offcore": "0"
1045  },
1046  {
1047    "EventCode": "0x27",
1048    "UMask": "0x40",
1049    "EventName": "L2_M_LINES_OUT.SELF.DEMAND",
1050    "BriefDescription": "Modified lines evicted from the L2 cache",
1051    "PublicDescription": "Modified lines evicted from the L2 cache",
1052    "Counter": "0,1",
1053    "SampleAfterValue": "200000",
1054    "MSRIndex": "0",
1055    "MSRValue": "0",
1056    "CounterMask": "0",
1057    "Invert": "0",
1058    "AnyThread": "0",
1059    "EdgeDetect": "0",
1060    "PEBS": "0",
1061    "Errata": "null",
1062    "Offcore": "0"
1063  },
1064  {
1065    "EventCode": "0x27",
1066    "UMask": "0x50",
1067    "EventName": "L2_M_LINES_OUT.SELF.PREFETCH",
1068    "BriefDescription": "Modified lines evicted from the L2 cache",
1069    "PublicDescription": "Modified lines evicted from the L2 cache",
1070    "Counter": "0,1",
1071    "SampleAfterValue": "200000",
1072    "MSRIndex": "0",
1073    "MSRValue": "0",
1074    "CounterMask": "0",
1075    "Invert": "0",
1076    "AnyThread": "0",
1077    "EdgeDetect": "0",
1078    "PEBS": "0",
1079    "Errata": "null",
1080    "Offcore": "0"
1081  },
1082  {
1083    "EventCode": "0x28",
1084    "UMask": "0x44",
1085    "EventName": "L2_IFETCH.SELF.E_STATE",
1086    "BriefDescription": "L2 cacheable instruction fetch requests",
1087    "PublicDescription": "L2 cacheable instruction fetch requests",
1088    "Counter": "0,1",
1089    "SampleAfterValue": "200000",
1090    "MSRIndex": "0",
1091    "MSRValue": "0",
1092    "CounterMask": "0",
1093    "Invert": "0",
1094    "AnyThread": "0",
1095    "EdgeDetect": "0",
1096    "PEBS": "0",
1097    "Errata": "null",
1098    "Offcore": "0"
1099  },
1100  {
1101    "EventCode": "0x28",
1102    "UMask": "0x41",
1103    "EventName": "L2_IFETCH.SELF.I_STATE",
1104    "BriefDescription": "L2 cacheable instruction fetch requests",
1105    "PublicDescription": "L2 cacheable instruction fetch requests",
1106    "Counter": "0,1",
1107    "SampleAfterValue": "200000",
1108    "MSRIndex": "0",
1109    "MSRValue": "0",
1110    "CounterMask": "0",
1111    "Invert": "0",
1112    "AnyThread": "0",
1113    "EdgeDetect": "0",
1114    "PEBS": "0",
1115    "Errata": "null",
1116    "Offcore": "0"
1117  },
1118  {
1119    "EventCode": "0x28",
1120    "UMask": "0x48",
1121    "EventName": "L2_IFETCH.SELF.M_STATE",
1122    "BriefDescription": "L2 cacheable instruction fetch requests",
1123    "PublicDescription": "L2 cacheable instruction fetch requests",
1124    "Counter": "0,1",
1125    "SampleAfterValue": "200000",
1126    "MSRIndex": "0",
1127    "MSRValue": "0",
1128    "CounterMask": "0",
1129    "Invert": "0",
1130    "AnyThread": "0",
1131    "EdgeDetect": "0",
1132    "PEBS": "0",
1133    "Errata": "null",
1134    "Offcore": "0"
1135  },
1136  {
1137    "EventCode": "0x28",
1138    "UMask": "0x42",
1139    "EventName": "L2_IFETCH.SELF.S_STATE",
1140    "BriefDescription": "L2 cacheable instruction fetch requests",
1141    "PublicDescription": "L2 cacheable instruction fetch requests",
1142    "Counter": "0,1",
1143    "SampleAfterValue": "200000",
1144    "MSRIndex": "0",
1145    "MSRValue": "0",
1146    "CounterMask": "0",
1147    "Invert": "0",
1148    "AnyThread": "0",
1149    "EdgeDetect": "0",
1150    "PEBS": "0",
1151    "Errata": "null",
1152    "Offcore": "0"
1153  },
1154  {
1155    "EventCode": "0x28",
1156    "UMask": "0x4F",
1157    "EventName": "L2_IFETCH.SELF.MESI",
1158    "BriefDescription": "L2 cacheable instruction fetch requests",
1159    "PublicDescription": "L2 cacheable instruction fetch requests",
1160    "Counter": "0,1",
1161    "SampleAfterValue": "200000",
1162    "MSRIndex": "0",
1163    "MSRValue": "0",
1164    "CounterMask": "0",
1165    "Invert": "0",
1166    "AnyThread": "0",
1167    "EdgeDetect": "0",
1168    "PEBS": "0",
1169    "Errata": "null",
1170    "Offcore": "0"
1171  },
1172  {
1173    "EventCode": "0x29",
1174    "UMask": "0x74",
1175    "EventName": "L2_LD.SELF.ANY.E_STATE",
1176    "BriefDescription": "L2 cache reads",
1177    "PublicDescription": "L2 cache reads",
1178    "Counter": "0,1",
1179    "SampleAfterValue": "200000",
1180    "MSRIndex": "0",
1181    "MSRValue": "0",
1182    "CounterMask": "0",
1183    "Invert": "0",
1184    "AnyThread": "0",
1185    "EdgeDetect": "0",
1186    "PEBS": "0",
1187    "Errata": "null",
1188    "Offcore": "0"
1189  },
1190  {
1191    "EventCode": "0x29",
1192    "UMask": "0x71",
1193    "EventName": "L2_LD.SELF.ANY.I_STATE",
1194    "BriefDescription": "L2 cache reads",
1195    "PublicDescription": "L2 cache reads",
1196    "Counter": "0,1",
1197    "SampleAfterValue": "200000",
1198    "MSRIndex": "0",
1199    "MSRValue": "0",
1200    "CounterMask": "0",
1201    "Invert": "0",
1202    "AnyThread": "0",
1203    "EdgeDetect": "0",
1204    "PEBS": "0",
1205    "Errata": "null",
1206    "Offcore": "0"
1207  },
1208  {
1209    "EventCode": "0x29",
1210    "UMask": "0x78",
1211    "EventName": "L2_LD.SELF.ANY.M_STATE",
1212    "BriefDescription": "L2 cache reads",
1213    "PublicDescription": "L2 cache reads",
1214    "Counter": "0,1",
1215    "SampleAfterValue": "200000",
1216    "MSRIndex": "0",
1217    "MSRValue": "0",
1218    "CounterMask": "0",
1219    "Invert": "0",
1220    "AnyThread": "0",
1221    "EdgeDetect": "0",
1222    "PEBS": "0",
1223    "Errata": "null",
1224    "Offcore": "0"
1225  },
1226  {
1227    "EventCode": "0x29",
1228    "UMask": "0x72",
1229    "EventName": "L2_LD.SELF.ANY.S_STATE",
1230    "BriefDescription": "L2 cache reads",
1231    "PublicDescription": "L2 cache reads",
1232    "Counter": "0,1",
1233    "SampleAfterValue": "200000",
1234    "MSRIndex": "0",
1235    "MSRValue": "0",
1236    "CounterMask": "0",
1237    "Invert": "0",
1238    "AnyThread": "0",
1239    "EdgeDetect": "0",
1240    "PEBS": "0",
1241    "Errata": "null",
1242    "Offcore": "0"
1243  },
1244  {
1245    "EventCode": "0x29",
1246    "UMask": "0x7F",
1247    "EventName": "L2_LD.SELF.ANY.MESI",
1248    "BriefDescription": "L2 cache reads",
1249    "PublicDescription": "L2 cache reads",
1250    "Counter": "0,1",
1251    "SampleAfterValue": "200000",
1252    "MSRIndex": "0",
1253    "MSRValue": "0",
1254    "CounterMask": "0",
1255    "Invert": "0",
1256    "AnyThread": "0",
1257    "EdgeDetect": "0",
1258    "PEBS": "0",
1259    "Errata": "null",
1260    "Offcore": "0"
1261  },
1262  {
1263    "EventCode": "0x29",
1264    "UMask": "0x44",
1265    "EventName": "L2_LD.SELF.DEMAND.E_STATE",
1266    "BriefDescription": "L2 cache reads",
1267    "PublicDescription": "L2 cache reads",
1268    "Counter": "0,1",
1269    "SampleAfterValue": "200000",
1270    "MSRIndex": "0",
1271    "MSRValue": "0",
1272    "CounterMask": "0",
1273    "Invert": "0",
1274    "AnyThread": "0",
1275    "EdgeDetect": "0",
1276    "PEBS": "0",
1277    "Errata": "null",
1278    "Offcore": "0"
1279  },
1280  {
1281    "EventCode": "0x29",
1282    "UMask": "0x41",
1283    "EventName": "L2_LD.SELF.DEMAND.I_STATE",
1284    "BriefDescription": "L2 cache reads",
1285    "PublicDescription": "L2 cache reads",
1286    "Counter": "0,1",
1287    "SampleAfterValue": "200000",
1288    "MSRIndex": "0",
1289    "MSRValue": "0",
1290    "CounterMask": "0",
1291    "Invert": "0",
1292    "AnyThread": "0",
1293    "EdgeDetect": "0",
1294    "PEBS": "0",
1295    "Errata": "null",
1296    "Offcore": "0"
1297  },
1298  {
1299    "EventCode": "0x29",
1300    "UMask": "0x48",
1301    "EventName": "L2_LD.SELF.DEMAND.M_STATE",
1302    "BriefDescription": "L2 cache reads",
1303    "PublicDescription": "L2 cache reads",
1304    "Counter": "0,1",
1305    "SampleAfterValue": "200000",
1306    "MSRIndex": "0",
1307    "MSRValue": "0",
1308    "CounterMask": "0",
1309    "Invert": "0",
1310    "AnyThread": "0",
1311    "EdgeDetect": "0",
1312    "PEBS": "0",
1313    "Errata": "null",
1314    "Offcore": "0"
1315  },
1316  {
1317    "EventCode": "0x29",
1318    "UMask": "0x42",
1319    "EventName": "L2_LD.SELF.DEMAND.S_STATE",
1320    "BriefDescription": "L2 cache reads",
1321    "PublicDescription": "L2 cache reads",
1322    "Counter": "0,1",
1323    "SampleAfterValue": "200000",
1324    "MSRIndex": "0",
1325    "MSRValue": "0",
1326    "CounterMask": "0",
1327    "Invert": "0",
1328    "AnyThread": "0",
1329    "EdgeDetect": "0",
1330    "PEBS": "0",
1331    "Errata": "null",
1332    "Offcore": "0"
1333  },
1334  {
1335    "EventCode": "0x29",
1336    "UMask": "0x4F",
1337    "EventName": "L2_LD.SELF.DEMAND.MESI",
1338    "BriefDescription": "L2 cache reads",
1339    "PublicDescription": "L2 cache reads",
1340    "Counter": "0,1",
1341    "SampleAfterValue": "200000",
1342    "MSRIndex": "0",
1343    "MSRValue": "0",
1344    "CounterMask": "0",
1345    "Invert": "0",
1346    "AnyThread": "0",
1347    "EdgeDetect": "0",
1348    "PEBS": "0",
1349    "Errata": "null",
1350    "Offcore": "0"
1351  },
1352  {
1353    "EventCode": "0x29",
1354    "UMask": "0x54",
1355    "EventName": "L2_LD.SELF.PREFETCH.E_STATE",
1356    "BriefDescription": "L2 cache reads",
1357    "PublicDescription": "L2 cache reads",
1358    "Counter": "0,1",
1359    "SampleAfterValue": "200000",
1360    "MSRIndex": "0",
1361    "MSRValue": "0",
1362    "CounterMask": "0",
1363    "Invert": "0",
1364    "AnyThread": "0",
1365    "EdgeDetect": "0",
1366    "PEBS": "0",
1367    "Errata": "null",
1368    "Offcore": "0"
1369  },
1370  {
1371    "EventCode": "0x29",
1372    "UMask": "0x51",
1373    "EventName": "L2_LD.SELF.PREFETCH.I_STATE",
1374    "BriefDescription": "L2 cache reads",
1375    "PublicDescription": "L2 cache reads",
1376    "Counter": "0,1",
1377    "SampleAfterValue": "200000",
1378    "MSRIndex": "0",
1379    "MSRValue": "0",
1380    "CounterMask": "0",
1381    "Invert": "0",
1382    "AnyThread": "0",
1383    "EdgeDetect": "0",
1384    "PEBS": "0",
1385    "Errata": "null",
1386    "Offcore": "0"
1387  },
1388  {
1389    "EventCode": "0x29",
1390    "UMask": "0x58",
1391    "EventName": "L2_LD.SELF.PREFETCH.M_STATE",
1392    "BriefDescription": "L2 cache reads",
1393    "PublicDescription": "L2 cache reads",
1394    "Counter": "0,1",
1395    "SampleAfterValue": "200000",
1396    "MSRIndex": "0",
1397    "MSRValue": "0",
1398    "CounterMask": "0",
1399    "Invert": "0",
1400    "AnyThread": "0",
1401    "EdgeDetect": "0",
1402    "PEBS": "0",
1403    "Errata": "null",
1404    "Offcore": "0"
1405  },
1406  {
1407    "EventCode": "0x29",
1408    "UMask": "0x52",
1409    "EventName": "L2_LD.SELF.PREFETCH.S_STATE",
1410    "BriefDescription": "L2 cache reads",
1411    "PublicDescription": "L2 cache reads",
1412    "Counter": "0,1",
1413    "SampleAfterValue": "200000",
1414    "MSRIndex": "0",
1415    "MSRValue": "0",
1416    "CounterMask": "0",
1417    "Invert": "0",
1418    "AnyThread": "0",
1419    "EdgeDetect": "0",
1420    "PEBS": "0",
1421    "Errata": "null",
1422    "Offcore": "0"
1423  },
1424  {
1425    "EventCode": "0x29",
1426    "UMask": "0x5F",
1427    "EventName": "L2_LD.SELF.PREFETCH.MESI",
1428    "BriefDescription": "L2 cache reads",
1429    "PublicDescription": "L2 cache reads",
1430    "Counter": "0,1",
1431    "SampleAfterValue": "200000",
1432    "MSRIndex": "0",
1433    "MSRValue": "0",
1434    "CounterMask": "0",
1435    "Invert": "0",
1436    "AnyThread": "0",
1437    "EdgeDetect": "0",
1438    "PEBS": "0",
1439    "Errata": "null",
1440    "Offcore": "0"
1441  },
1442  {
1443    "EventCode": "0x2A",
1444    "UMask": "0x44",
1445    "EventName": "L2_ST.SELF.E_STATE",
1446    "BriefDescription": "L2 store requests",
1447    "PublicDescription": "L2 store requests",
1448    "Counter": "0,1",
1449    "SampleAfterValue": "200000",
1450    "MSRIndex": "0",
1451    "MSRValue": "0",
1452    "CounterMask": "0",
1453    "Invert": "0",
1454    "AnyThread": "0",
1455    "EdgeDetect": "0",
1456    "PEBS": "0",
1457    "Errata": "null",
1458    "Offcore": "0"
1459  },
1460  {
1461    "EventCode": "0x2A",
1462    "UMask": "0x41",
1463    "EventName": "L2_ST.SELF.I_STATE",
1464    "BriefDescription": "L2 store requests",
1465    "PublicDescription": "L2 store requests",
1466    "Counter": "0,1",
1467    "SampleAfterValue": "200000",
1468    "MSRIndex": "0",
1469    "MSRValue": "0",
1470    "CounterMask": "0",
1471    "Invert": "0",
1472    "AnyThread": "0",
1473    "EdgeDetect": "0",
1474    "PEBS": "0",
1475    "Errata": "null",
1476    "Offcore": "0"
1477  },
1478  {
1479    "EventCode": "0x2A",
1480    "UMask": "0x48",
1481    "EventName": "L2_ST.SELF.M_STATE",
1482    "BriefDescription": "L2 store requests",
1483    "PublicDescription": "L2 store requests",
1484    "Counter": "0,1",
1485    "SampleAfterValue": "200000",
1486    "MSRIndex": "0",
1487    "MSRValue": "0",
1488    "CounterMask": "0",
1489    "Invert": "0",
1490    "AnyThread": "0",
1491    "EdgeDetect": "0",
1492    "PEBS": "0",
1493    "Errata": "null",
1494    "Offcore": "0"
1495  },
1496  {
1497    "EventCode": "0x2A",
1498    "UMask": "0x42",
1499    "EventName": "L2_ST.SELF.S_STATE",
1500    "BriefDescription": "L2 store requests",
1501    "PublicDescription": "L2 store requests",
1502    "Counter": "0,1",
1503    "SampleAfterValue": "200000",
1504    "MSRIndex": "0",
1505    "MSRValue": "0",
1506    "CounterMask": "0",
1507    "Invert": "0",
1508    "AnyThread": "0",
1509    "EdgeDetect": "0",
1510    "PEBS": "0",
1511    "Errata": "null",
1512    "Offcore": "0"
1513  },
1514  {
1515    "EventCode": "0x2A",
1516    "UMask": "0x4F",
1517    "EventName": "L2_ST.SELF.MESI",
1518    "BriefDescription": "L2 store requests",
1519    "PublicDescription": "L2 store requests",
1520    "Counter": "0,1",
1521    "SampleAfterValue": "200000",
1522    "MSRIndex": "0",
1523    "MSRValue": "0",
1524    "CounterMask": "0",
1525    "Invert": "0",
1526    "AnyThread": "0",
1527    "EdgeDetect": "0",
1528    "PEBS": "0",
1529    "Errata": "null",
1530    "Offcore": "0"
1531  },
1532  {
1533    "EventCode": "0x2B",
1534    "UMask": "0x44",
1535    "EventName": "L2_LOCK.SELF.E_STATE",
1536    "BriefDescription": "L2 locked accesses",
1537    "PublicDescription": "L2 locked accesses",
1538    "Counter": "0,1",
1539    "SampleAfterValue": "200000",
1540    "MSRIndex": "0",
1541    "MSRValue": "0",
1542    "CounterMask": "0",
1543    "Invert": "0",
1544    "AnyThread": "0",
1545    "EdgeDetect": "0",
1546    "PEBS": "0",
1547    "Errata": "null",
1548    "Offcore": "0"
1549  },
1550  {
1551    "EventCode": "0x2B",
1552    "UMask": "0x41",
1553    "EventName": "L2_LOCK.SELF.I_STATE",
1554    "BriefDescription": "L2 locked accesses",
1555    "PublicDescription": "L2 locked accesses",
1556    "Counter": "0,1",
1557    "SampleAfterValue": "200000",
1558    "MSRIndex": "0",
1559    "MSRValue": "0",
1560    "CounterMask": "0",
1561    "Invert": "0",
1562    "AnyThread": "0",
1563    "EdgeDetect": "0",
1564    "PEBS": "0",
1565    "Errata": "null",
1566    "Offcore": "0"
1567  },
1568  {
1569    "EventCode": "0x2B",
1570    "UMask": "0x48",
1571    "EventName": "L2_LOCK.SELF.M_STATE",
1572    "BriefDescription": "L2 locked accesses",
1573    "PublicDescription": "L2 locked accesses",
1574    "Counter": "0,1",
1575    "SampleAfterValue": "200000",
1576    "MSRIndex": "0",
1577    "MSRValue": "0",
1578    "CounterMask": "0",
1579    "Invert": "0",
1580    "AnyThread": "0",
1581    "EdgeDetect": "0",
1582    "PEBS": "0",
1583    "Errata": "null",
1584    "Offcore": "0"
1585  },
1586  {
1587    "EventCode": "0x2B",
1588    "UMask": "0x42",
1589    "EventName": "L2_LOCK.SELF.S_STATE",
1590    "BriefDescription": "L2 locked accesses",
1591    "PublicDescription": "L2 locked accesses",
1592    "Counter": "0,1",
1593    "SampleAfterValue": "200000",
1594    "MSRIndex": "0",
1595    "MSRValue": "0",
1596    "CounterMask": "0",
1597    "Invert": "0",
1598    "AnyThread": "0",
1599    "EdgeDetect": "0",
1600    "PEBS": "0",
1601    "Errata": "null",
1602    "Offcore": "0"
1603  },
1604  {
1605    "EventCode": "0x2B",
1606    "UMask": "0x4F",
1607    "EventName": "L2_LOCK.SELF.MESI",
1608    "BriefDescription": "L2 locked accesses",
1609    "PublicDescription": "L2 locked accesses",
1610    "Counter": "0,1",
1611    "SampleAfterValue": "200000",
1612    "MSRIndex": "0",
1613    "MSRValue": "0",
1614    "CounterMask": "0",
1615    "Invert": "0",
1616    "AnyThread": "0",
1617    "EdgeDetect": "0",
1618    "PEBS": "0",
1619    "Errata": "null",
1620    "Offcore": "0"
1621  },
1622  {
1623    "EventCode": "0x2C",
1624    "UMask": "0x44",
1625    "EventName": "L2_DATA_RQSTS.SELF.E_STATE",
1626    "BriefDescription": "All data requests from the L1 data cache",
1627    "PublicDescription": "All data requests from the L1 data cache",
1628    "Counter": "0,1",
1629    "SampleAfterValue": "200000",
1630    "MSRIndex": "0",
1631    "MSRValue": "0",
1632    "CounterMask": "0",
1633    "Invert": "0",
1634    "AnyThread": "0",
1635    "EdgeDetect": "0",
1636    "PEBS": "0",
1637    "Errata": "null",
1638    "Offcore": "0"
1639  },
1640  {
1641    "EventCode": "0x2C",
1642    "UMask": "0x41",
1643    "EventName": "L2_DATA_RQSTS.SELF.I_STATE",
1644    "BriefDescription": "All data requests from the L1 data cache",
1645    "PublicDescription": "All data requests from the L1 data cache",
1646    "Counter": "0,1",
1647    "SampleAfterValue": "200000",
1648    "MSRIndex": "0",
1649    "MSRValue": "0",
1650    "CounterMask": "0",
1651    "Invert": "0",
1652    "AnyThread": "0",
1653    "EdgeDetect": "0",
1654    "PEBS": "0",
1655    "Errata": "null",
1656    "Offcore": "0"
1657  },
1658  {
1659    "EventCode": "0x2C",
1660    "UMask": "0x48",
1661    "EventName": "L2_DATA_RQSTS.SELF.M_STATE",
1662    "BriefDescription": "All data requests from the L1 data cache",
1663    "PublicDescription": "All data requests from the L1 data cache",
1664    "Counter": "0,1",
1665    "SampleAfterValue": "200000",
1666    "MSRIndex": "0",
1667    "MSRValue": "0",
1668    "CounterMask": "0",
1669    "Invert": "0",
1670    "AnyThread": "0",
1671    "EdgeDetect": "0",
1672    "PEBS": "0",
1673    "Errata": "null",
1674    "Offcore": "0"
1675  },
1676  {
1677    "EventCode": "0x2C",
1678    "UMask": "0x42",
1679    "EventName": "L2_DATA_RQSTS.SELF.S_STATE",
1680    "BriefDescription": "All data requests from the L1 data cache",
1681    "PublicDescription": "All data requests from the L1 data cache",
1682    "Counter": "0,1",
1683    "SampleAfterValue": "200000",
1684    "MSRIndex": "0",
1685    "MSRValue": "0",
1686    "CounterMask": "0",
1687    "Invert": "0",
1688    "AnyThread": "0",
1689    "EdgeDetect": "0",
1690    "PEBS": "0",
1691    "Errata": "null",
1692    "Offcore": "0"
1693  },
1694  {
1695    "EventCode": "0x2C",
1696    "UMask": "0x4F",
1697    "EventName": "L2_DATA_RQSTS.SELF.MESI",
1698    "BriefDescription": "All data requests from the L1 data cache",
1699    "PublicDescription": "All data requests from the L1 data cache",
1700    "Counter": "0,1",
1701    "SampleAfterValue": "200000",
1702    "MSRIndex": "0",
1703    "MSRValue": "0",
1704    "CounterMask": "0",
1705    "Invert": "0",
1706    "AnyThread": "0",
1707    "EdgeDetect": "0",
1708    "PEBS": "0",
1709    "Errata": "null",
1710    "Offcore": "0"
1711  },
1712  {
1713    "EventCode": "0x2D",
1714    "UMask": "0x44",
1715    "EventName": "L2_LD_IFETCH.SELF.E_STATE",
1716    "BriefDescription": "All read requests from L1 instruction and data caches",
1717    "PublicDescription": "All read requests from L1 instruction and data caches",
1718    "Counter": "0,1",
1719    "SampleAfterValue": "200000",
1720    "MSRIndex": "0",
1721    "MSRValue": "0",
1722    "CounterMask": "0",
1723    "Invert": "0",
1724    "AnyThread": "0",
1725    "EdgeDetect": "0",
1726    "PEBS": "0",
1727    "Errata": "null",
1728    "Offcore": "0"
1729  },
1730  {
1731    "EventCode": "0x2D",
1732    "UMask": "0x41",
1733    "EventName": "L2_LD_IFETCH.SELF.I_STATE",
1734    "BriefDescription": "All read requests from L1 instruction and data caches",
1735    "PublicDescription": "All read requests from L1 instruction and data caches",
1736    "Counter": "0,1",
1737    "SampleAfterValue": "200000",
1738    "MSRIndex": "0",
1739    "MSRValue": "0",
1740    "CounterMask": "0",
1741    "Invert": "0",
1742    "AnyThread": "0",
1743    "EdgeDetect": "0",
1744    "PEBS": "0",
1745    "Errata": "null",
1746    "Offcore": "0"
1747  },
1748  {
1749    "EventCode": "0x2D",
1750    "UMask": "0x48",
1751    "EventName": "L2_LD_IFETCH.SELF.M_STATE",
1752    "BriefDescription": "All read requests from L1 instruction and data caches",
1753    "PublicDescription": "All read requests from L1 instruction and data caches",
1754    "Counter": "0,1",
1755    "SampleAfterValue": "200000",
1756    "MSRIndex": "0",
1757    "MSRValue": "0",
1758    "CounterMask": "0",
1759    "Invert": "0",
1760    "AnyThread": "0",
1761    "EdgeDetect": "0",
1762    "PEBS": "0",
1763    "Errata": "null",
1764    "Offcore": "0"
1765  },
1766  {
1767    "EventCode": "0x2D",
1768    "UMask": "0x42",
1769    "EventName": "L2_LD_IFETCH.SELF.S_STATE",
1770    "BriefDescription": "All read requests from L1 instruction and data caches",
1771    "PublicDescription": "All read requests from L1 instruction and data caches",
1772    "Counter": "0,1",
1773    "SampleAfterValue": "200000",
1774    "MSRIndex": "0",
1775    "MSRValue": "0",
1776    "CounterMask": "0",
1777    "Invert": "0",
1778    "AnyThread": "0",
1779    "EdgeDetect": "0",
1780    "PEBS": "0",
1781    "Errata": "null",
1782    "Offcore": "0"
1783  },
1784  {
1785    "EventCode": "0x2D",
1786    "UMask": "0x4F",
1787    "EventName": "L2_LD_IFETCH.SELF.MESI",
1788    "BriefDescription": "All read requests from L1 instruction and data caches",
1789    "PublicDescription": "All read requests from L1 instruction and data caches",
1790    "Counter": "0,1",
1791    "SampleAfterValue": "200000",
1792    "MSRIndex": "0",
1793    "MSRValue": "0",
1794    "CounterMask": "0",
1795    "Invert": "0",
1796    "AnyThread": "0",
1797    "EdgeDetect": "0",
1798    "PEBS": "0",
1799    "Errata": "null",
1800    "Offcore": "0"
1801  },
1802  {
1803    "EventCode": "0x2E",
1804    "UMask": "0x74",
1805    "EventName": "L2_RQSTS.SELF.ANY.E_STATE",
1806    "BriefDescription": "L2 cache requests",
1807    "PublicDescription": "L2 cache requests",
1808    "Counter": "0,1",
1809    "SampleAfterValue": "200000",
1810    "MSRIndex": "0",
1811    "MSRValue": "0",
1812    "CounterMask": "0",
1813    "Invert": "0",
1814    "AnyThread": "0",
1815    "EdgeDetect": "0",
1816    "PEBS": "0",
1817    "Errata": "null",
1818    "Offcore": "0"
1819  },
1820  {
1821    "EventCode": "0x2E",
1822    "UMask": "0x71",
1823    "EventName": "L2_RQSTS.SELF.ANY.I_STATE",
1824    "BriefDescription": "L2 cache requests",
1825    "PublicDescription": "L2 cache requests",
1826    "Counter": "0,1",
1827    "SampleAfterValue": "200000",
1828    "MSRIndex": "0",
1829    "MSRValue": "0",
1830    "CounterMask": "0",
1831    "Invert": "0",
1832    "AnyThread": "0",
1833    "EdgeDetect": "0",
1834    "PEBS": "0",
1835    "Errata": "null",
1836    "Offcore": "0"
1837  },
1838  {
1839    "EventCode": "0x2E",
1840    "UMask": "0x78",
1841    "EventName": "L2_RQSTS.SELF.ANY.M_STATE",
1842    "BriefDescription": "L2 cache requests",
1843    "PublicDescription": "L2 cache requests",
1844    "Counter": "0,1",
1845    "SampleAfterValue": "200000",
1846    "MSRIndex": "0",
1847    "MSRValue": "0",
1848    "CounterMask": "0",
1849    "Invert": "0",
1850    "AnyThread": "0",
1851    "EdgeDetect": "0",
1852    "PEBS": "0",
1853    "Errata": "null",
1854    "Offcore": "0"
1855  },
1856  {
1857    "EventCode": "0x2E",
1858    "UMask": "0x72",
1859    "EventName": "L2_RQSTS.SELF.ANY.S_STATE",
1860    "BriefDescription": "L2 cache requests",
1861    "PublicDescription": "L2 cache requests",
1862    "Counter": "0,1",
1863    "SampleAfterValue": "200000",
1864    "MSRIndex": "0",
1865    "MSRValue": "0",
1866    "CounterMask": "0",
1867    "Invert": "0",
1868    "AnyThread": "0",
1869    "EdgeDetect": "0",
1870    "PEBS": "0",
1871    "Errata": "null",
1872    "Offcore": "0"
1873  },
1874  {
1875    "EventCode": "0x2E",
1876    "UMask": "0x7F",
1877    "EventName": "L2_RQSTS.SELF.ANY.MESI",
1878    "BriefDescription": "L2 cache requests",
1879    "PublicDescription": "L2 cache requests",
1880    "Counter": "0,1",
1881    "SampleAfterValue": "200000",
1882    "MSRIndex": "0",
1883    "MSRValue": "0",
1884    "CounterMask": "0",
1885    "Invert": "0",
1886    "AnyThread": "0",
1887    "EdgeDetect": "0",
1888    "PEBS": "0",
1889    "Errata": "null",
1890    "Offcore": "0"
1891  },
1892  {
1893    "EventCode": "0x2E",
1894    "UMask": "0x44",
1895    "EventName": "L2_RQSTS.SELF.DEMAND.E_STATE",
1896    "BriefDescription": "L2 cache requests",
1897    "PublicDescription": "L2 cache requests",
1898    "Counter": "0,1",
1899    "SampleAfterValue": "200000",
1900    "MSRIndex": "0",
1901    "MSRValue": "0",
1902    "CounterMask": "0",
1903    "Invert": "0",
1904    "AnyThread": "0",
1905    "EdgeDetect": "0",
1906    "PEBS": "0",
1907    "Errata": "null",
1908    "Offcore": "0"
1909  },
1910  {
1911    "EventCode": "0x2E",
1912    "UMask": "0x48",
1913    "EventName": "L2_RQSTS.SELF.DEMAND.M_STATE",
1914    "BriefDescription": "L2 cache requests",
1915    "PublicDescription": "L2 cache requests",
1916    "Counter": "0,1",
1917    "SampleAfterValue": "200000",
1918    "MSRIndex": "0",
1919    "MSRValue": "0",
1920    "CounterMask": "0",
1921    "Invert": "0",
1922    "AnyThread": "0",
1923    "EdgeDetect": "0",
1924    "PEBS": "0",
1925    "Errata": "null",
1926    "Offcore": "0"
1927  },
1928  {
1929    "EventCode": "0x2E",
1930    "UMask": "0x42",
1931    "EventName": "L2_RQSTS.SELF.DEMAND.S_STATE",
1932    "BriefDescription": "L2 cache requests",
1933    "PublicDescription": "L2 cache requests",
1934    "Counter": "0,1",
1935    "SampleAfterValue": "200000",
1936    "MSRIndex": "0",
1937    "MSRValue": "0",
1938    "CounterMask": "0",
1939    "Invert": "0",
1940    "AnyThread": "0",
1941    "EdgeDetect": "0",
1942    "PEBS": "0",
1943    "Errata": "null",
1944    "Offcore": "0"
1945  },
1946  {
1947    "EventCode": "0x2E",
1948    "UMask": "0x54",
1949    "EventName": "L2_RQSTS.SELF.PREFETCH.E_STATE",
1950    "BriefDescription": "L2 cache requests",
1951    "PublicDescription": "L2 cache requests",
1952    "Counter": "0,1",
1953    "SampleAfterValue": "200000",
1954    "MSRIndex": "0",
1955    "MSRValue": "0",
1956    "CounterMask": "0",
1957    "Invert": "0",
1958    "AnyThread": "0",
1959    "EdgeDetect": "0",
1960    "PEBS": "0",
1961    "Errata": "null",
1962    "Offcore": "0"
1963  },
1964  {
1965    "EventCode": "0x2E",
1966    "UMask": "0x51",
1967    "EventName": "L2_RQSTS.SELF.PREFETCH.I_STATE",
1968    "BriefDescription": "L2 cache requests",
1969    "PublicDescription": "L2 cache requests",
1970    "Counter": "0,1",
1971    "SampleAfterValue": "200000",
1972    "MSRIndex": "0",
1973    "MSRValue": "0",
1974    "CounterMask": "0",
1975    "Invert": "0",
1976    "AnyThread": "0",
1977    "EdgeDetect": "0",
1978    "PEBS": "0",
1979    "Errata": "null",
1980    "Offcore": "0"
1981  },
1982  {
1983    "EventCode": "0x2E",
1984    "UMask": "0x58",
1985    "EventName": "L2_RQSTS.SELF.PREFETCH.M_STATE",
1986    "BriefDescription": "L2 cache requests",
1987    "PublicDescription": "L2 cache requests",
1988    "Counter": "0,1",
1989    "SampleAfterValue": "200000",
1990    "MSRIndex": "0",
1991    "MSRValue": "0",
1992    "CounterMask": "0",
1993    "Invert": "0",
1994    "AnyThread": "0",
1995    "EdgeDetect": "0",
1996    "PEBS": "0",
1997    "Errata": "null",
1998    "Offcore": "0"
1999  },
2000  {
2001    "EventCode": "0x2E",
2002    "UMask": "0x52",
2003    "EventName": "L2_RQSTS.SELF.PREFETCH.S_STATE",
2004    "BriefDescription": "L2 cache requests",
2005    "PublicDescription": "L2 cache requests",
2006    "Counter": "0,1",
2007    "SampleAfterValue": "200000",
2008    "MSRIndex": "0",
2009    "MSRValue": "0",
2010    "CounterMask": "0",
2011    "Invert": "0",
2012    "AnyThread": "0",
2013    "EdgeDetect": "0",
2014    "PEBS": "0",
2015    "Errata": "null",
2016    "Offcore": "0"
2017  },
2018  {
2019    "EventCode": "0x2E",
2020    "UMask": "0x5F",
2021    "EventName": "L2_RQSTS.SELF.PREFETCH.MESI",
2022    "BriefDescription": "L2 cache requests",
2023    "PublicDescription": "L2 cache requests",
2024    "Counter": "0,1",
2025    "SampleAfterValue": "200000",
2026    "MSRIndex": "0",
2027    "MSRValue": "0",
2028    "CounterMask": "0",
2029    "Invert": "0",
2030    "AnyThread": "0",
2031    "EdgeDetect": "0",
2032    "PEBS": "0",
2033    "Errata": "null",
2034    "Offcore": "0"
2035  },
2036  {
2037    "EventCode": "0x2E",
2038    "UMask": "0x41",
2039    "EventName": "L2_RQSTS.SELF.DEMAND.I_STATE",
2040    "BriefDescription": "L2 cache demand requests from this core that missed the L2",
2041    "PublicDescription": "L2 cache demand requests from this core that missed the L2",
2042    "Counter": "0,1",
2043    "SampleAfterValue": "200000",
2044    "MSRIndex": "0",
2045    "MSRValue": "0",
2046    "CounterMask": "0",
2047    "Invert": "0",
2048    "AnyThread": "0",
2049    "EdgeDetect": "0",
2050    "PEBS": "0",
2051    "Errata": "null",
2052    "Offcore": "0"
2053  },
2054  {
2055    "EventCode": "0x2E",
2056    "UMask": "0x4F",
2057    "EventName": "L2_RQSTS.SELF.DEMAND.MESI",
2058    "BriefDescription": "L2 cache demand requests from this core",
2059    "PublicDescription": "L2 cache demand requests from this core",
2060    "Counter": "0,1",
2061    "SampleAfterValue": "200000",
2062    "MSRIndex": "0",
2063    "MSRValue": "0",
2064    "CounterMask": "0",
2065    "Invert": "0",
2066    "AnyThread": "0",
2067    "EdgeDetect": "0",
2068    "PEBS": "0",
2069    "Errata": "null",
2070    "Offcore": "0"
2071  },
2072  {
2073    "EventCode": "0x30",
2074    "UMask": "0x74",
2075    "EventName": "L2_REJECT_BUSQ.SELF.ANY.E_STATE",
2076    "BriefDescription": "Rejected L2 cache requests",
2077    "PublicDescription": "Rejected L2 cache requests",
2078    "Counter": "0,1",
2079    "SampleAfterValue": "200000",
2080    "MSRIndex": "0",
2081    "MSRValue": "0",
2082    "CounterMask": "0",
2083    "Invert": "0",
2084    "AnyThread": "0",
2085    "EdgeDetect": "0",
2086    "PEBS": "0",
2087    "Errata": "null",
2088    "Offcore": "0"
2089  },
2090  {
2091    "EventCode": "0x30",
2092    "UMask": "0x71",
2093    "EventName": "L2_REJECT_BUSQ.SELF.ANY.I_STATE",
2094    "BriefDescription": "Rejected L2 cache requests",
2095    "PublicDescription": "Rejected L2 cache requests",
2096    "Counter": "0,1",
2097    "SampleAfterValue": "200000",
2098    "MSRIndex": "0",
2099    "MSRValue": "0",
2100    "CounterMask": "0",
2101    "Invert": "0",
2102    "AnyThread": "0",
2103    "EdgeDetect": "0",
2104    "PEBS": "0",
2105    "Errata": "null",
2106    "Offcore": "0"
2107  },
2108  {
2109    "EventCode": "0x30",
2110    "UMask": "0x78",
2111    "EventName": "L2_REJECT_BUSQ.SELF.ANY.M_STATE",
2112    "BriefDescription": "Rejected L2 cache requests",
2113    "PublicDescription": "Rejected L2 cache requests",
2114    "Counter": "0,1",
2115    "SampleAfterValue": "200000",
2116    "MSRIndex": "0",
2117    "MSRValue": "0",
2118    "CounterMask": "0",
2119    "Invert": "0",
2120    "AnyThread": "0",
2121    "EdgeDetect": "0",
2122    "PEBS": "0",
2123    "Errata": "null",
2124    "Offcore": "0"
2125  },
2126  {
2127    "EventCode": "0x30",
2128    "UMask": "0x72",
2129    "EventName": "L2_REJECT_BUSQ.SELF.ANY.S_STATE",
2130    "BriefDescription": "Rejected L2 cache requests",
2131    "PublicDescription": "Rejected L2 cache requests",
2132    "Counter": "0,1",
2133    "SampleAfterValue": "200000",
2134    "MSRIndex": "0",
2135    "MSRValue": "0",
2136    "CounterMask": "0",
2137    "Invert": "0",
2138    "AnyThread": "0",
2139    "EdgeDetect": "0",
2140    "PEBS": "0",
2141    "Errata": "null",
2142    "Offcore": "0"
2143  },
2144  {
2145    "EventCode": "0x30",
2146    "UMask": "0x7F",
2147    "EventName": "L2_REJECT_BUSQ.SELF.ANY.MESI",
2148    "BriefDescription": "Rejected L2 cache requests",
2149    "PublicDescription": "Rejected L2 cache requests",
2150    "Counter": "0,1",
2151    "SampleAfterValue": "200000",
2152    "MSRIndex": "0",
2153    "MSRValue": "0",
2154    "CounterMask": "0",
2155    "Invert": "0",
2156    "AnyThread": "0",
2157    "EdgeDetect": "0",
2158    "PEBS": "0",
2159    "Errata": "null",
2160    "Offcore": "0"
2161  },
2162  {
2163    "EventCode": "0x30",
2164    "UMask": "0x44",
2165    "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.E_STATE",
2166    "BriefDescription": "Rejected L2 cache requests",
2167    "PublicDescription": "Rejected L2 cache requests",
2168    "Counter": "0,1",
2169    "SampleAfterValue": "200000",
2170    "MSRIndex": "0",
2171    "MSRValue": "0",
2172    "CounterMask": "0",
2173    "Invert": "0",
2174    "AnyThread": "0",
2175    "EdgeDetect": "0",
2176    "PEBS": "0",
2177    "Errata": "null",
2178    "Offcore": "0"
2179  },
2180  {
2181    "EventCode": "0x30",
2182    "UMask": "0x41",
2183    "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.I_STATE",
2184    "BriefDescription": "Rejected L2 cache requests",
2185    "PublicDescription": "Rejected L2 cache requests",
2186    "Counter": "0,1",
2187    "SampleAfterValue": "200000",
2188    "MSRIndex": "0",
2189    "MSRValue": "0",
2190    "CounterMask": "0",
2191    "Invert": "0",
2192    "AnyThread": "0",
2193    "EdgeDetect": "0",
2194    "PEBS": "0",
2195    "Errata": "null",
2196    "Offcore": "0"
2197  },
2198  {
2199    "EventCode": "0x30",
2200    "UMask": "0x48",
2201    "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.M_STATE",
2202    "BriefDescription": "Rejected L2 cache requests",
2203    "PublicDescription": "Rejected L2 cache requests",
2204    "Counter": "0,1",
2205    "SampleAfterValue": "200000",
2206    "MSRIndex": "0",
2207    "MSRValue": "0",
2208    "CounterMask": "0",
2209    "Invert": "0",
2210    "AnyThread": "0",
2211    "EdgeDetect": "0",
2212    "PEBS": "0",
2213    "Errata": "null",
2214    "Offcore": "0"
2215  },
2216  {
2217    "EventCode": "0x30",
2218    "UMask": "0x42",
2219    "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.S_STATE",
2220    "BriefDescription": "Rejected L2 cache requests",
2221    "PublicDescription": "Rejected L2 cache requests",
2222    "Counter": "0,1",
2223    "SampleAfterValue": "200000",
2224    "MSRIndex": "0",
2225    "MSRValue": "0",
2226    "CounterMask": "0",
2227    "Invert": "0",
2228    "AnyThread": "0",
2229    "EdgeDetect": "0",
2230    "PEBS": "0",
2231    "Errata": "null",
2232    "Offcore": "0"
2233  },
2234  {
2235    "EventCode": "0x30",
2236    "UMask": "0x4F",
2237    "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.MESI",
2238    "BriefDescription": "Rejected L2 cache requests",
2239    "PublicDescription": "Rejected L2 cache requests",
2240    "Counter": "0,1",
2241    "SampleAfterValue": "200000",
2242    "MSRIndex": "0",
2243    "MSRValue": "0",
2244    "CounterMask": "0",
2245    "Invert": "0",
2246    "AnyThread": "0",
2247    "EdgeDetect": "0",
2248    "PEBS": "0",
2249    "Errata": "null",
2250    "Offcore": "0"
2251  },
2252  {
2253    "EventCode": "0x30",
2254    "UMask": "0x54",
2255    "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE",
2256    "BriefDescription": "Rejected L2 cache requests",
2257    "PublicDescription": "Rejected L2 cache requests",
2258    "Counter": "0,1",
2259    "SampleAfterValue": "200000",
2260    "MSRIndex": "0",
2261    "MSRValue": "0",
2262    "CounterMask": "0",
2263    "Invert": "0",
2264    "AnyThread": "0",
2265    "EdgeDetect": "0",
2266    "PEBS": "0",
2267    "Errata": "null",
2268    "Offcore": "0"
2269  },
2270  {
2271    "EventCode": "0x30",
2272    "UMask": "0x51",
2273    "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE",
2274    "BriefDescription": "Rejected L2 cache requests",
2275    "PublicDescription": "Rejected L2 cache requests",
2276    "Counter": "0,1",
2277    "SampleAfterValue": "200000",
2278    "MSRIndex": "0",
2279    "MSRValue": "0",
2280    "CounterMask": "0",
2281    "Invert": "0",
2282    "AnyThread": "0",
2283    "EdgeDetect": "0",
2284    "PEBS": "0",
2285    "Errata": "null",
2286    "Offcore": "0"
2287  },
2288  {
2289    "EventCode": "0x30",
2290    "UMask": "0x58",
2291    "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE",
2292    "BriefDescription": "Rejected L2 cache requests",
2293    "PublicDescription": "Rejected L2 cache requests",
2294    "Counter": "0,1",
2295    "SampleAfterValue": "200000",
2296    "MSRIndex": "0",
2297    "MSRValue": "0",
2298    "CounterMask": "0",
2299    "Invert": "0",
2300    "AnyThread": "0",
2301    "EdgeDetect": "0",
2302    "PEBS": "0",
2303    "Errata": "null",
2304    "Offcore": "0"
2305  },
2306  {
2307    "EventCode": "0x30",
2308    "UMask": "0x52",
2309    "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE",
2310    "BriefDescription": "Rejected L2 cache requests",
2311    "PublicDescription": "Rejected L2 cache requests",
2312    "Counter": "0,1",
2313    "SampleAfterValue": "200000",
2314    "MSRIndex": "0",
2315    "MSRValue": "0",
2316    "CounterMask": "0",
2317    "Invert": "0",
2318    "AnyThread": "0",
2319    "EdgeDetect": "0",
2320    "PEBS": "0",
2321    "Errata": "null",
2322    "Offcore": "0"
2323  },
2324  {
2325    "EventCode": "0x30",
2326    "UMask": "0x5F",
2327    "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.MESI",
2328    "BriefDescription": "Rejected L2 cache requests",
2329    "PublicDescription": "Rejected L2 cache requests",
2330    "Counter": "0,1",
2331    "SampleAfterValue": "200000",
2332    "MSRIndex": "0",
2333    "MSRValue": "0",
2334    "CounterMask": "0",
2335    "Invert": "0",
2336    "AnyThread": "0",
2337    "EdgeDetect": "0",
2338    "PEBS": "0",
2339    "Errata": "null",
2340    "Offcore": "0"
2341  },
2342  {
2343    "EventCode": "0x32",
2344    "UMask": "0x40",
2345    "EventName": "L2_NO_REQ.SELF",
2346    "BriefDescription": "Cycles no L2 cache requests are pending",
2347    "PublicDescription": "Cycles no L2 cache requests are pending",
2348    "Counter": "0,1",
2349    "SampleAfterValue": "200000",
2350    "MSRIndex": "0",
2351    "MSRValue": "0",
2352    "CounterMask": "0",
2353    "Invert": "0",
2354    "AnyThread": "0",
2355    "EdgeDetect": "0",
2356    "PEBS": "0",
2357    "Errata": "null",
2358    "Offcore": "0"
2359  },
2360  {
2361    "EventCode": "0x3A",
2362    "UMask": "0x0",
2363    "EventName": "EIST_TRANS",
2364    "BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions",
2365    "PublicDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions",
2366    "Counter": "0,1",
2367    "SampleAfterValue": "200000",
2368    "MSRIndex": "0",
2369    "MSRValue": "0",
2370    "CounterMask": "0",
2371    "Invert": "0",
2372    "AnyThread": "0",
2373    "EdgeDetect": "0",
2374    "PEBS": "0",
2375    "Errata": "null",
2376    "Offcore": "0"
2377  },
2378  {
2379    "EventCode": "0x3B",
2380    "UMask": "0xC0",
2381    "EventName": "THERMAL_TRIP",
2382    "BriefDescription": "Number of thermal trips",
2383    "PublicDescription": "Number of thermal trips",
2384    "Counter": "0,1",
2385    "SampleAfterValue": "200000",
2386    "MSRIndex": "0",
2387    "MSRValue": "0",
2388    "CounterMask": "0",
2389    "Invert": "0",
2390    "AnyThread": "0",
2391    "EdgeDetect": "0",
2392    "PEBS": "0",
2393    "Errata": "null",
2394    "Offcore": "0"
2395  },
2396  {
2397    "EventCode": "0x3C",
2398    "UMask": "0x0",
2399    "EventName": "CPU_CLK_UNHALTED.CORE_P",
2400    "BriefDescription": "Core cycles when core is not halted",
2401    "PublicDescription": "Core cycles when core is not halted",
2402    "Counter": "0,1",
2403    "SampleAfterValue": "2000000",
2404    "MSRIndex": "0",
2405    "MSRValue": "0",
2406    "CounterMask": "0",
2407    "Invert": "0",
2408    "AnyThread": "0",
2409    "EdgeDetect": "0",
2410    "PEBS": "0",
2411    "Errata": "null",
2412    "Offcore": "0"
2413  },
2414  {
2415    "EventCode": "0x3C",
2416    "UMask": "0x1",
2417    "EventName": "CPU_CLK_UNHALTED.BUS",
2418    "BriefDescription": "Bus cycles when core is not halted",
2419    "PublicDescription": "Bus cycles when core is not halted",
2420    "Counter": "0,1",
2421    "SampleAfterValue": "200000",
2422    "MSRIndex": "0",
2423    "MSRValue": "0",
2424    "CounterMask": "0",
2425    "Invert": "0",
2426    "AnyThread": "0",
2427    "EdgeDetect": "0",
2428    "PEBS": "0",
2429    "Errata": "null",
2430    "Offcore": "0"
2431  },
2432  {
2433    "EventCode": "0xA",
2434    "UMask": "0x0",
2435    "EventName": "CPU_CLK_UNHALTED.CORE",
2436    "BriefDescription": "Core cycles when core is not halted",
2437    "PublicDescription": "Core cycles when core is not halted",
2438    "Counter": "Fixed counter 2",
2439    "SampleAfterValue": "2000000",
2440    "MSRIndex": "0",
2441    "MSRValue": "0",
2442    "CounterMask": "0",
2443    "Invert": "0",
2444    "AnyThread": "0",
2445    "EdgeDetect": "0",
2446    "PEBS": "0",
2447    "Errata": "null",
2448    "Offcore": "0"
2449  },
2450  {
2451    "EventCode": "0xA",
2452    "UMask": "0x0",
2453    "EventName": "CPU_CLK_UNHALTED.REF",
2454    "BriefDescription": "Reference cycles when core is not halted.",
2455    "PublicDescription": "Reference cycles when core is not halted.",
2456    "Counter": "Fixed counter 3",
2457    "SampleAfterValue": "2000000",
2458    "MSRIndex": "0",
2459    "MSRValue": "0",
2460    "CounterMask": "0",
2461    "Invert": "0",
2462    "AnyThread": "0",
2463    "EdgeDetect": "0",
2464    "PEBS": "0",
2465    "Errata": "null",
2466    "Offcore": "0"
2467  },
2468  {
2469    "EventCode": "0x40",
2470    "UMask": "0xA1",
2471    "EventName": "L1D_CACHE.LD",
2472    "BriefDescription": "L1 Cacheable Data Reads",
2473    "PublicDescription": "L1 Cacheable Data Reads",
2474    "Counter": "0,1",
2475    "SampleAfterValue": "2000000",
2476    "MSRIndex": "0",
2477    "MSRValue": "0",
2478    "CounterMask": "0",
2479    "Invert": "0",
2480    "AnyThread": "0",
2481    "EdgeDetect": "0",
2482    "PEBS": "0",
2483    "Errata": "null",
2484    "Offcore": "0"
2485  },
2486  {
2487    "EventCode": "0x40",
2488    "UMask": "0xA2",
2489    "EventName": "L1D_CACHE.ST",
2490    "BriefDescription": "L1 Cacheable Data Writes",
2491    "PublicDescription": "L1 Cacheable Data Writes",
2492    "Counter": "0,1",
2493    "SampleAfterValue": "2000000",
2494    "MSRIndex": "0",
2495    "MSRValue": "0",
2496    "CounterMask": "0",
2497    "Invert": "0",
2498    "AnyThread": "0",
2499    "EdgeDetect": "0",
2500    "PEBS": "0",
2501    "Errata": "null",
2502    "Offcore": "0"
2503  },
2504  {
2505    "EventCode": "0x40",
2506    "UMask": "0x83",
2507    "EventName": "L1D_CACHE.ALL_REF",
2508    "BriefDescription": "L1 Data reads and writes",
2509    "PublicDescription": "L1 Data reads and writes",
2510    "Counter": "0,1",
2511    "SampleAfterValue": "2000000",
2512    "MSRIndex": "0",
2513    "MSRValue": "0",
2514    "CounterMask": "0",
2515    "Invert": "0",
2516    "AnyThread": "0",
2517    "EdgeDetect": "0",
2518    "PEBS": "0",
2519    "Errata": "null",
2520    "Offcore": "0"
2521  },
2522  {
2523    "EventCode": "0x40",
2524    "UMask": "0xA3",
2525    "EventName": "L1D_CACHE.ALL_CACHE_REF",
2526    "BriefDescription": "L1 Data Cacheable reads and writes",
2527    "PublicDescription": "L1 Data Cacheable reads and writes",
2528    "Counter": "0,1",
2529    "SampleAfterValue": "2000000",
2530    "MSRIndex": "0",
2531    "MSRValue": "0",
2532    "CounterMask": "0",
2533    "Invert": "0",
2534    "AnyThread": "0",
2535    "EdgeDetect": "0",
2536    "PEBS": "0",
2537    "Errata": "null",
2538    "Offcore": "0"
2539  },
2540  {
2541    "EventCode": "0x40",
2542    "UMask": "0x8",
2543    "EventName": "L1D_CACHE.REPL",
2544    "BriefDescription": "L1 Data line replacements",
2545    "PublicDescription": "L1 Data line replacements",
2546    "Counter": "0,1",
2547    "SampleAfterValue": "200000",
2548    "MSRIndex": "0",
2549    "MSRValue": "0",
2550    "CounterMask": "0",
2551    "Invert": "0",
2552    "AnyThread": "0",
2553    "EdgeDetect": "0",
2554    "PEBS": "0",
2555    "Errata": "null",
2556    "Offcore": "0"
2557  },
2558  {
2559    "EventCode": "0x40",
2560    "UMask": "0x48",
2561    "EventName": "L1D_CACHE.REPLM",
2562    "BriefDescription": "Modified cache lines allocated in the L1 data cache",
2563    "PublicDescription": "Modified cache lines allocated in the L1 data cache",
2564    "Counter": "0,1",
2565    "SampleAfterValue": "200000",
2566    "MSRIndex": "0",
2567    "MSRValue": "0",
2568    "CounterMask": "0",
2569    "Invert": "0",
2570    "AnyThread": "0",
2571    "EdgeDetect": "0",
2572    "PEBS": "0",
2573    "Errata": "null",
2574    "Offcore": "0"
2575  },
2576  {
2577    "EventCode": "0x40",
2578    "UMask": "0x10",
2579    "EventName": "L1D_CACHE.EVICT",
2580    "BriefDescription": "Modified cache lines evicted from the L1 data cache",
2581    "PublicDescription": "Modified cache lines evicted from the L1 data cache",
2582    "Counter": "0,1",
2583    "SampleAfterValue": "200000",
2584    "MSRIndex": "0",
2585    "MSRValue": "0",
2586    "CounterMask": "0",
2587    "Invert": "0",
2588    "AnyThread": "0",
2589    "EdgeDetect": "0",
2590    "PEBS": "0",
2591    "Errata": "null",
2592    "Offcore": "0"
2593  },
2594  {
2595    "EventCode": "0x60",
2596    "UMask": "0xE0",
2597    "EventName": "BUS_REQUEST_OUTSTANDING.ALL_AGENTS",
2598    "BriefDescription": "Outstanding cacheable data read bus requests duration.",
2599    "PublicDescription": "Outstanding cacheable data read bus requests duration.",
2600    "Counter": "0,1",
2601    "SampleAfterValue": "200000",
2602    "MSRIndex": "0",
2603    "MSRValue": "0",
2604    "CounterMask": "0",
2605    "Invert": "0",
2606    "AnyThread": "0",
2607    "EdgeDetect": "0",
2608    "PEBS": "0",
2609    "Errata": "null",
2610    "Offcore": "0"
2611  },
2612  {
2613    "EventCode": "0x60",
2614    "UMask": "0x40",
2615    "EventName": "BUS_REQUEST_OUTSTANDING.SELF",
2616    "BriefDescription": "Outstanding cacheable data read bus requests duration.",
2617    "PublicDescription": "Outstanding cacheable data read bus requests duration.",
2618    "Counter": "0,1",
2619    "SampleAfterValue": "200000",
2620    "MSRIndex": "0",
2621    "MSRValue": "0",
2622    "CounterMask": "0",
2623    "Invert": "0",
2624    "AnyThread": "0",
2625    "EdgeDetect": "0",
2626    "PEBS": "0",
2627    "Errata": "null",
2628    "Offcore": "0"
2629  },
2630  {
2631    "EventCode": "0x61",
2632    "UMask": "0x20",
2633    "EventName": "BUS_BNR_DRV.ALL_AGENTS",
2634    "BriefDescription": "Number of Bus Not Ready signals asserted.",
2635    "PublicDescription": "Number of Bus Not Ready signals asserted.",
2636    "Counter": "0,1",
2637    "SampleAfterValue": "200000",
2638    "MSRIndex": "0",
2639    "MSRValue": "0",
2640    "CounterMask": "0",
2641    "Invert": "0",
2642    "AnyThread": "0",
2643    "EdgeDetect": "0",
2644    "PEBS": "0",
2645    "Errata": "null",
2646    "Offcore": "0"
2647  },
2648  {
2649    "EventCode": "0x61",
2650    "UMask": "0x0",
2651    "EventName": "BUS_BNR_DRV.THIS_AGENT",
2652    "BriefDescription": "Number of Bus Not Ready signals asserted.",
2653    "PublicDescription": "Number of Bus Not Ready signals asserted.",
2654    "Counter": "0,1",
2655    "SampleAfterValue": "200000",
2656    "MSRIndex": "0",
2657    "MSRValue": "0",
2658    "CounterMask": "0",
2659    "Invert": "0",
2660    "AnyThread": "0",
2661    "EdgeDetect": "0",
2662    "PEBS": "0",
2663    "Errata": "null",
2664    "Offcore": "0"
2665  },
2666  {
2667    "EventCode": "0x62",
2668    "UMask": "0x20",
2669    "EventName": "BUS_DRDY_CLOCKS.ALL_AGENTS",
2670    "BriefDescription": "Bus cycles when data is sent on the bus.",
2671    "PublicDescription": "Bus cycles when data is sent on the bus.",
2672    "Counter": "0,1",
2673    "SampleAfterValue": "200000",
2674    "MSRIndex": "0",
2675    "MSRValue": "0",
2676    "CounterMask": "0",
2677    "Invert": "0",
2678    "AnyThread": "0",
2679    "EdgeDetect": "0",
2680    "PEBS": "0",
2681    "Errata": "null",
2682    "Offcore": "0"
2683  },
2684  {
2685    "EventCode": "0x62",
2686    "UMask": "0x0",
2687    "EventName": "BUS_DRDY_CLOCKS.THIS_AGENT",
2688    "BriefDescription": "Bus cycles when data is sent on the bus.",
2689    "PublicDescription": "Bus cycles when data is sent on the bus.",
2690    "Counter": "0,1",
2691    "SampleAfterValue": "200000",
2692    "MSRIndex": "0",
2693    "MSRValue": "0",
2694    "CounterMask": "0",
2695    "Invert": "0",
2696    "AnyThread": "0",
2697    "EdgeDetect": "0",
2698    "PEBS": "0",
2699    "Errata": "null",
2700    "Offcore": "0"
2701  },
2702  {
2703    "EventCode": "0x63",
2704    "UMask": "0xE0",
2705    "EventName": "BUS_LOCK_CLOCKS.ALL_AGENTS",
2706    "BriefDescription": "Bus cycles when a LOCK signal is asserted.",
2707    "PublicDescription": "Bus cycles when a LOCK signal is asserted.",
2708    "Counter": "0,1",
2709    "SampleAfterValue": "200000",
2710    "MSRIndex": "0",
2711    "MSRValue": "0",
2712    "CounterMask": "0",
2713    "Invert": "0",
2714    "AnyThread": "0",
2715    "EdgeDetect": "0",
2716    "PEBS": "0",
2717    "Errata": "null",
2718    "Offcore": "0"
2719  },
2720  {
2721    "EventCode": "0x63",
2722    "UMask": "0x40",
2723    "EventName": "BUS_LOCK_CLOCKS.SELF",
2724    "BriefDescription": "Bus cycles when a LOCK signal is asserted.",
2725    "PublicDescription": "Bus cycles when a LOCK signal is asserted.",
2726    "Counter": "0,1",
2727    "SampleAfterValue": "200000",
2728    "MSRIndex": "0",
2729    "MSRValue": "0",
2730    "CounterMask": "0",
2731    "Invert": "0",
2732    "AnyThread": "0",
2733    "EdgeDetect": "0",
2734    "PEBS": "0",
2735    "Errata": "null",
2736    "Offcore": "0"
2737  },
2738  {
2739    "EventCode": "0x64",
2740    "UMask": "0x40",
2741    "EventName": "BUS_DATA_RCV.SELF",
2742    "BriefDescription": "Bus cycles while processor receives data.",
2743    "PublicDescription": "Bus cycles while processor receives data.",
2744    "Counter": "0,1",
2745    "SampleAfterValue": "200000",
2746    "MSRIndex": "0",
2747    "MSRValue": "0",
2748    "CounterMask": "0",
2749    "Invert": "0",
2750    "AnyThread": "0",
2751    "EdgeDetect": "0",
2752    "PEBS": "0",
2753    "Errata": "null",
2754    "Offcore": "0"
2755  },
2756  {
2757    "EventCode": "0x65",
2758    "UMask": "0xE0",
2759    "EventName": "BUS_TRANS_BRD.ALL_AGENTS",
2760    "BriefDescription": "Burst read bus transactions.",
2761    "PublicDescription": "Burst read bus transactions.",
2762    "Counter": "0,1",
2763    "SampleAfterValue": "200000",
2764    "MSRIndex": "0",
2765    "MSRValue": "0",
2766    "CounterMask": "0",
2767    "Invert": "0",
2768    "AnyThread": "0",
2769    "EdgeDetect": "0",
2770    "PEBS": "0",
2771    "Errata": "null",
2772    "Offcore": "0"
2773  },
2774  {
2775    "EventCode": "0x65",
2776    "UMask": "0x40",
2777    "EventName": "BUS_TRANS_BRD.SELF",
2778    "BriefDescription": "Burst read bus transactions.",
2779    "PublicDescription": "Burst read bus transactions.",
2780    "Counter": "0,1",
2781    "SampleAfterValue": "200000",
2782    "MSRIndex": "0",
2783    "MSRValue": "0",
2784    "CounterMask": "0",
2785    "Invert": "0",
2786    "AnyThread": "0",
2787    "EdgeDetect": "0",
2788    "PEBS": "0",
2789    "Errata": "null",
2790    "Offcore": "0"
2791  },
2792  {
2793    "EventCode": "0x66",
2794    "UMask": "0xE0",
2795    "EventName": "BUS_TRANS_RFO.ALL_AGENTS",
2796    "BriefDescription": "RFO bus transactions.",
2797    "PublicDescription": "RFO bus transactions.",
2798    "Counter": "0,1",
2799    "SampleAfterValue": "200000",
2800    "MSRIndex": "0",
2801    "MSRValue": "0",
2802    "CounterMask": "0",
2803    "Invert": "0",
2804    "AnyThread": "0",
2805    "EdgeDetect": "0",
2806    "PEBS": "0",
2807    "Errata": "null",
2808    "Offcore": "0"
2809  },
2810  {
2811    "EventCode": "0x66",
2812    "UMask": "0x40",
2813    "EventName": "BUS_TRANS_RFO.SELF",
2814    "BriefDescription": "RFO bus transactions.",
2815    "PublicDescription": "RFO bus transactions.",
2816    "Counter": "0,1",
2817    "SampleAfterValue": "200000",
2818    "MSRIndex": "0",
2819    "MSRValue": "0",
2820    "CounterMask": "0",
2821    "Invert": "0",
2822    "AnyThread": "0",
2823    "EdgeDetect": "0",
2824    "PEBS": "0",
2825    "Errata": "null",
2826    "Offcore": "0"
2827  },
2828  {
2829    "EventCode": "0x67",
2830    "UMask": "0xE0",
2831    "EventName": "BUS_TRANS_WB.ALL_AGENTS",
2832    "BriefDescription": "Explicit writeback bus transactions.",
2833    "PublicDescription": "Explicit writeback bus transactions.",
2834    "Counter": "0,1",
2835    "SampleAfterValue": "200000",
2836    "MSRIndex": "0",
2837    "MSRValue": "0",
2838    "CounterMask": "0",
2839    "Invert": "0",
2840    "AnyThread": "0",
2841    "EdgeDetect": "0",
2842    "PEBS": "0",
2843    "Errata": "null",
2844    "Offcore": "0"
2845  },
2846  {
2847    "EventCode": "0x67",
2848    "UMask": "0x40",
2849    "EventName": "BUS_TRANS_WB.SELF",
2850    "BriefDescription": "Explicit writeback bus transactions.",
2851    "PublicDescription": "Explicit writeback bus transactions.",
2852    "Counter": "0,1",
2853    "SampleAfterValue": "200000",
2854    "MSRIndex": "0",
2855    "MSRValue": "0",
2856    "CounterMask": "0",
2857    "Invert": "0",
2858    "AnyThread": "0",
2859    "EdgeDetect": "0",
2860    "PEBS": "0",
2861    "Errata": "null",
2862    "Offcore": "0"
2863  },
2864  {
2865    "EventCode": "0x68",
2866    "UMask": "0xE0",
2867    "EventName": "BUS_TRANS_IFETCH.ALL_AGENTS",
2868    "BriefDescription": "Instruction-fetch bus transactions.",
2869    "PublicDescription": "Instruction-fetch bus transactions.",
2870    "Counter": "0,1",
2871    "SampleAfterValue": "200000",
2872    "MSRIndex": "0",
2873    "MSRValue": "0",
2874    "CounterMask": "0",
2875    "Invert": "0",
2876    "AnyThread": "0",
2877    "EdgeDetect": "0",
2878    "PEBS": "0",
2879    "Errata": "null",
2880    "Offcore": "0"
2881  },
2882  {
2883    "EventCode": "0x68",
2884    "UMask": "0x40",
2885    "EventName": "BUS_TRANS_IFETCH.SELF",
2886    "BriefDescription": "Instruction-fetch bus transactions.",
2887    "PublicDescription": "Instruction-fetch bus transactions.",
2888    "Counter": "0,1",
2889    "SampleAfterValue": "200000",
2890    "MSRIndex": "0",
2891    "MSRValue": "0",
2892    "CounterMask": "0",
2893    "Invert": "0",
2894    "AnyThread": "0",
2895    "EdgeDetect": "0",
2896    "PEBS": "0",
2897    "Errata": "null",
2898    "Offcore": "0"
2899  },
2900  {
2901    "EventCode": "0x69",
2902    "UMask": "0xE0",
2903    "EventName": "BUS_TRANS_INVAL.ALL_AGENTS",
2904    "BriefDescription": "Invalidate bus transactions.",
2905    "PublicDescription": "Invalidate bus transactions.",
2906    "Counter": "0,1",
2907    "SampleAfterValue": "200000",
2908    "MSRIndex": "0",
2909    "MSRValue": "0",
2910    "CounterMask": "0",
2911    "Invert": "0",
2912    "AnyThread": "0",
2913    "EdgeDetect": "0",
2914    "PEBS": "0",
2915    "Errata": "null",
2916    "Offcore": "0"
2917  },
2918  {
2919    "EventCode": "0x69",
2920    "UMask": "0x40",
2921    "EventName": "BUS_TRANS_INVAL.SELF",
2922    "BriefDescription": "Invalidate bus transactions.",
2923    "PublicDescription": "Invalidate bus transactions.",
2924    "Counter": "0,1",
2925    "SampleAfterValue": "200000",
2926    "MSRIndex": "0",
2927    "MSRValue": "0",
2928    "CounterMask": "0",
2929    "Invert": "0",
2930    "AnyThread": "0",
2931    "EdgeDetect": "0",
2932    "PEBS": "0",
2933    "Errata": "null",
2934    "Offcore": "0"
2935  },
2936  {
2937    "EventCode": "0x6A",
2938    "UMask": "0xE0",
2939    "EventName": "BUS_TRANS_PWR.ALL_AGENTS",
2940    "BriefDescription": "Partial write bus transaction.",
2941    "PublicDescription": "Partial write bus transaction.",
2942    "Counter": "0,1",
2943    "SampleAfterValue": "200000",
2944    "MSRIndex": "0",
2945    "MSRValue": "0",
2946    "CounterMask": "0",
2947    "Invert": "0",
2948    "AnyThread": "0",
2949    "EdgeDetect": "0",
2950    "PEBS": "0",
2951    "Errata": "null",
2952    "Offcore": "0"
2953  },
2954  {
2955    "EventCode": "0x6A",
2956    "UMask": "0x40",
2957    "EventName": "BUS_TRANS_PWR.SELF",
2958    "BriefDescription": "Partial write bus transaction.",
2959    "PublicDescription": "Partial write bus transaction.",
2960    "Counter": "0,1",
2961    "SampleAfterValue": "200000",
2962    "MSRIndex": "0",
2963    "MSRValue": "0",
2964    "CounterMask": "0",
2965    "Invert": "0",
2966    "AnyThread": "0",
2967    "EdgeDetect": "0",
2968    "PEBS": "0",
2969    "Errata": "null",
2970    "Offcore": "0"
2971  },
2972  {
2973    "EventCode": "0x6B",
2974    "UMask": "0xE0",
2975    "EventName": "BUS_TRANS_P.ALL_AGENTS",
2976    "BriefDescription": "Partial bus transactions.",
2977    "PublicDescription": "Partial bus transactions.",
2978    "Counter": "0,1",
2979    "SampleAfterValue": "200000",
2980    "MSRIndex": "0",
2981    "MSRValue": "0",
2982    "CounterMask": "0",
2983    "Invert": "0",
2984    "AnyThread": "0",
2985    "EdgeDetect": "0",
2986    "PEBS": "0",
2987    "Errata": "null",
2988    "Offcore": "0"
2989  },
2990  {
2991    "EventCode": "0x6B",
2992    "UMask": "0x40",
2993    "EventName": "BUS_TRANS_P.SELF",
2994    "BriefDescription": "Partial bus transactions.",
2995    "PublicDescription": "Partial bus transactions.",
2996    "Counter": "0,1",
2997    "SampleAfterValue": "200000",
2998    "MSRIndex": "0",
2999    "MSRValue": "0",
3000    "CounterMask": "0",
3001    "Invert": "0",
3002    "AnyThread": "0",
3003    "EdgeDetect": "0",
3004    "PEBS": "0",
3005    "Errata": "null",
3006    "Offcore": "0"
3007  },
3008  {
3009    "EventCode": "0x6C",
3010    "UMask": "0xE0",
3011    "EventName": "BUS_TRANS_IO.ALL_AGENTS",
3012    "BriefDescription": "IO bus transactions.",
3013    "PublicDescription": "IO bus transactions.",
3014    "Counter": "0,1",
3015    "SampleAfterValue": "200000",
3016    "MSRIndex": "0",
3017    "MSRValue": "0",
3018    "CounterMask": "0",
3019    "Invert": "0",
3020    "AnyThread": "0",
3021    "EdgeDetect": "0",
3022    "PEBS": "0",
3023    "Errata": "null",
3024    "Offcore": "0"
3025  },
3026  {
3027    "EventCode": "0x6C",
3028    "UMask": "0x40",
3029    "EventName": "BUS_TRANS_IO.SELF",
3030    "BriefDescription": "IO bus transactions.",
3031    "PublicDescription": "IO bus transactions.",
3032    "Counter": "0,1",
3033    "SampleAfterValue": "200000",
3034    "MSRIndex": "0",
3035    "MSRValue": "0",
3036    "CounterMask": "0",
3037    "Invert": "0",
3038    "AnyThread": "0",
3039    "EdgeDetect": "0",
3040    "PEBS": "0",
3041    "Errata": "null",
3042    "Offcore": "0"
3043  },
3044  {
3045    "EventCode": "0x6D",
3046    "UMask": "0xE0",
3047    "EventName": "BUS_TRANS_DEF.ALL_AGENTS",
3048    "BriefDescription": "Deferred bus transactions.",
3049    "PublicDescription": "Deferred bus transactions.",
3050    "Counter": "0,1",
3051    "SampleAfterValue": "200000",
3052    "MSRIndex": "0",
3053    "MSRValue": "0",
3054    "CounterMask": "0",
3055    "Invert": "0",
3056    "AnyThread": "0",
3057    "EdgeDetect": "0",
3058    "PEBS": "0",
3059    "Errata": "null",
3060    "Offcore": "0"
3061  },
3062  {
3063    "EventCode": "0x6D",
3064    "UMask": "0x40",
3065    "EventName": "BUS_TRANS_DEF.SELF",
3066    "BriefDescription": "Deferred bus transactions.",
3067    "PublicDescription": "Deferred bus transactions.",
3068    "Counter": "0,1",
3069    "SampleAfterValue": "200000",
3070    "MSRIndex": "0",
3071    "MSRValue": "0",
3072    "CounterMask": "0",
3073    "Invert": "0",
3074    "AnyThread": "0",
3075    "EdgeDetect": "0",
3076    "PEBS": "0",
3077    "Errata": "null",
3078    "Offcore": "0"
3079  },
3080  {
3081    "EventCode": "0x6E",
3082    "UMask": "0xE0",
3083    "EventName": "BUS_TRANS_BURST.ALL_AGENTS",
3084    "BriefDescription": "Burst (full cache-line) bus transactions.",
3085    "PublicDescription": "Burst (full cache-line) bus transactions.",
3086    "Counter": "0,1",
3087    "SampleAfterValue": "200000",
3088    "MSRIndex": "0",
3089    "MSRValue": "0",
3090    "CounterMask": "0",
3091    "Invert": "0",
3092    "AnyThread": "0",
3093    "EdgeDetect": "0",
3094    "PEBS": "0",
3095    "Errata": "null",
3096    "Offcore": "0"
3097  },
3098  {
3099    "EventCode": "0x6E",
3100    "UMask": "0x40",
3101    "EventName": "BUS_TRANS_BURST.SELF",
3102    "BriefDescription": "Burst (full cache-line) bus transactions.",
3103    "PublicDescription": "Burst (full cache-line) bus transactions.",
3104    "Counter": "0,1",
3105    "SampleAfterValue": "200000",
3106    "MSRIndex": "0",
3107    "MSRValue": "0",
3108    "CounterMask": "0",
3109    "Invert": "0",
3110    "AnyThread": "0",
3111    "EdgeDetect": "0",
3112    "PEBS": "0",
3113    "Errata": "null",
3114    "Offcore": "0"
3115  },
3116  {
3117    "EventCode": "0x6F",
3118    "UMask": "0xE0",
3119    "EventName": "BUS_TRANS_MEM.ALL_AGENTS",
3120    "BriefDescription": "Memory bus transactions.",
3121    "PublicDescription": "Memory bus transactions.",
3122    "Counter": "0,1",
3123    "SampleAfterValue": "200000",
3124    "MSRIndex": "0",
3125    "MSRValue": "0",
3126    "CounterMask": "0",
3127    "Invert": "0",
3128    "AnyThread": "0",
3129    "EdgeDetect": "0",
3130    "PEBS": "0",
3131    "Errata": "null",
3132    "Offcore": "0"
3133  },
3134  {
3135    "EventCode": "0x6F",
3136    "UMask": "0x40",
3137    "EventName": "BUS_TRANS_MEM.SELF",
3138    "BriefDescription": "Memory bus transactions.",
3139    "PublicDescription": "Memory bus transactions.",
3140    "Counter": "0,1",
3141    "SampleAfterValue": "200000",
3142    "MSRIndex": "0",
3143    "MSRValue": "0",
3144    "CounterMask": "0",
3145    "Invert": "0",
3146    "AnyThread": "0",
3147    "EdgeDetect": "0",
3148    "PEBS": "0",
3149    "Errata": "null",
3150    "Offcore": "0"
3151  },
3152  {
3153    "EventCode": "0x70",
3154    "UMask": "0xE0",
3155    "EventName": "BUS_TRANS_ANY.ALL_AGENTS",
3156    "BriefDescription": "All bus transactions.",
3157    "PublicDescription": "All bus transactions.",
3158    "Counter": "0,1",
3159    "SampleAfterValue": "200000",
3160    "MSRIndex": "0",
3161    "MSRValue": "0",
3162    "CounterMask": "0",
3163    "Invert": "0",
3164    "AnyThread": "0",
3165    "EdgeDetect": "0",
3166    "PEBS": "0",
3167    "Errata": "null",
3168    "Offcore": "0"
3169  },
3170  {
3171    "EventCode": "0x70",
3172    "UMask": "0x40",
3173    "EventName": "BUS_TRANS_ANY.SELF",
3174    "BriefDescription": "All bus transactions.",
3175    "PublicDescription": "All bus transactions.",
3176    "Counter": "0,1",
3177    "SampleAfterValue": "200000",
3178    "MSRIndex": "0",
3179    "MSRValue": "0",
3180    "CounterMask": "0",
3181    "Invert": "0",
3182    "AnyThread": "0",
3183    "EdgeDetect": "0",
3184    "PEBS": "0",
3185    "Errata": "null",
3186    "Offcore": "0"
3187  },
3188  {
3189    "EventCode": "0x77",
3190    "UMask": "0xB",
3191    "EventName": "EXT_SNOOP.THIS_AGENT.ANY",
3192    "BriefDescription": "External snoops.",
3193    "PublicDescription": "External snoops.",
3194    "Counter": "0,1",
3195    "SampleAfterValue": "200000",
3196    "MSRIndex": "0",
3197    "MSRValue": "0",
3198    "CounterMask": "0",
3199    "Invert": "0",
3200    "AnyThread": "0",
3201    "EdgeDetect": "0",
3202    "PEBS": "0",
3203    "Errata": "null",
3204    "Offcore": "0"
3205  },
3206  {
3207    "EventCode": "0x77",
3208    "UMask": "0x1",
3209    "EventName": "EXT_SNOOP.THIS_AGENT.CLEAN",
3210    "BriefDescription": "External snoops.",
3211    "PublicDescription": "External snoops.",
3212    "Counter": "0,1",
3213    "SampleAfterValue": "200000",
3214    "MSRIndex": "0",
3215    "MSRValue": "0",
3216    "CounterMask": "0",
3217    "Invert": "0",
3218    "AnyThread": "0",
3219    "EdgeDetect": "0",
3220    "PEBS": "0",
3221    "Errata": "null",
3222    "Offcore": "0"
3223  },
3224  {
3225    "EventCode": "0x77",
3226    "UMask": "0x2",
3227    "EventName": "EXT_SNOOP.THIS_AGENT.HIT",
3228    "BriefDescription": "External snoops.",
3229    "PublicDescription": "External snoops.",
3230    "Counter": "0,1",
3231    "SampleAfterValue": "200000",
3232    "MSRIndex": "0",
3233    "MSRValue": "0",
3234    "CounterMask": "0",
3235    "Invert": "0",
3236    "AnyThread": "0",
3237    "EdgeDetect": "0",
3238    "PEBS": "0",
3239    "Errata": "null",
3240    "Offcore": "0"
3241  },
3242  {
3243    "EventCode": "0x77",
3244    "UMask": "0x8",
3245    "EventName": "EXT_SNOOP.THIS_AGENT.HITM",
3246    "BriefDescription": "External snoops.",
3247    "PublicDescription": "External snoops.",
3248    "Counter": "0,1",
3249    "SampleAfterValue": "200000",
3250    "MSRIndex": "0",
3251    "MSRValue": "0",
3252    "CounterMask": "0",
3253    "Invert": "0",
3254    "AnyThread": "0",
3255    "EdgeDetect": "0",
3256    "PEBS": "0",
3257    "Errata": "null",
3258    "Offcore": "0"
3259  },
3260  {
3261    "EventCode": "0x77",
3262    "UMask": "0x2B",
3263    "EventName": "EXT_SNOOP.ALL_AGENTS.ANY",
3264    "BriefDescription": "External snoops.",
3265    "PublicDescription": "External snoops.",
3266    "Counter": "0,1",
3267    "SampleAfterValue": "200000",
3268    "MSRIndex": "0",
3269    "MSRValue": "0",
3270    "CounterMask": "0",
3271    "Invert": "0",
3272    "AnyThread": "0",
3273    "EdgeDetect": "0",
3274    "PEBS": "0",
3275    "Errata": "null",
3276    "Offcore": "0"
3277  },
3278  {
3279    "EventCode": "0x77",
3280    "UMask": "0x21",
3281    "EventName": "EXT_SNOOP.ALL_AGENTS.CLEAN",
3282    "BriefDescription": "External snoops.",
3283    "PublicDescription": "External snoops.",
3284    "Counter": "0,1",
3285    "SampleAfterValue": "200000",
3286    "MSRIndex": "0",
3287    "MSRValue": "0",
3288    "CounterMask": "0",
3289    "Invert": "0",
3290    "AnyThread": "0",
3291    "EdgeDetect": "0",
3292    "PEBS": "0",
3293    "Errata": "null",
3294    "Offcore": "0"
3295  },
3296  {
3297    "EventCode": "0x77",
3298    "UMask": "0x22",
3299    "EventName": "EXT_SNOOP.ALL_AGENTS.HIT",
3300    "BriefDescription": "External snoops.",
3301    "PublicDescription": "External snoops.",
3302    "Counter": "0,1",
3303    "SampleAfterValue": "200000",
3304    "MSRIndex": "0",
3305    "MSRValue": "0",
3306    "CounterMask": "0",
3307    "Invert": "0",
3308    "AnyThread": "0",
3309    "EdgeDetect": "0",
3310    "PEBS": "0",
3311    "Errata": "null",
3312    "Offcore": "0"
3313  },
3314  {
3315    "EventCode": "0x77",
3316    "UMask": "0x28",
3317    "EventName": "EXT_SNOOP.ALL_AGENTS.HITM",
3318    "BriefDescription": "External snoops.",
3319    "PublicDescription": "External snoops.",
3320    "Counter": "0,1",
3321    "SampleAfterValue": "200000",
3322    "MSRIndex": "0",
3323    "MSRValue": "0",
3324    "CounterMask": "0",
3325    "Invert": "0",
3326    "AnyThread": "0",
3327    "EdgeDetect": "0",
3328    "PEBS": "0",
3329    "Errata": "null",
3330    "Offcore": "0"
3331  },
3332  {
3333    "EventCode": "0x7A",
3334    "UMask": "0x20",
3335    "EventName": "BUS_HIT_DRV.ALL_AGENTS",
3336    "BriefDescription": "HIT signal asserted.",
3337    "PublicDescription": "HIT signal asserted.",
3338    "Counter": "0,1",
3339    "SampleAfterValue": "200000",
3340    "MSRIndex": "0",
3341    "MSRValue": "0",
3342    "CounterMask": "0",
3343    "Invert": "0",
3344    "AnyThread": "0",
3345    "EdgeDetect": "0",
3346    "PEBS": "0",
3347    "Errata": "null",
3348    "Offcore": "0"
3349  },
3350  {
3351    "EventCode": "0x7A",
3352    "UMask": "0x0",
3353    "EventName": "BUS_HIT_DRV.THIS_AGENT",
3354    "BriefDescription": "HIT signal asserted.",
3355    "PublicDescription": "HIT signal asserted.",
3356    "Counter": "0,1",
3357    "SampleAfterValue": "200000",
3358    "MSRIndex": "0",
3359    "MSRValue": "0",
3360    "CounterMask": "0",
3361    "Invert": "0",
3362    "AnyThread": "0",
3363    "EdgeDetect": "0",
3364    "PEBS": "0",
3365    "Errata": "null",
3366    "Offcore": "0"
3367  },
3368  {
3369    "EventCode": "0x7B",
3370    "UMask": "0x20",
3371    "EventName": "BUS_HITM_DRV.ALL_AGENTS",
3372    "BriefDescription": "HITM signal asserted.",
3373    "PublicDescription": "HITM signal asserted.",
3374    "Counter": "0,1",
3375    "SampleAfterValue": "200000",
3376    "MSRIndex": "0",
3377    "MSRValue": "0",
3378    "CounterMask": "0",
3379    "Invert": "0",
3380    "AnyThread": "0",
3381    "EdgeDetect": "0",
3382    "PEBS": "0",
3383    "Errata": "null",
3384    "Offcore": "0"
3385  },
3386  {
3387    "EventCode": "0x7B",
3388    "UMask": "0x0",
3389    "EventName": "BUS_HITM_DRV.THIS_AGENT",
3390    "BriefDescription": "HITM signal asserted.",
3391    "PublicDescription": "HITM signal asserted.",
3392    "Counter": "0,1",
3393    "SampleAfterValue": "200000",
3394    "MSRIndex": "0",
3395    "MSRValue": "0",
3396    "CounterMask": "0",
3397    "Invert": "0",
3398    "AnyThread": "0",
3399    "EdgeDetect": "0",
3400    "PEBS": "0",
3401    "Errata": "null",
3402    "Offcore": "0"
3403  },
3404  {
3405    "EventCode": "0x7D",
3406    "UMask": "0x40",
3407    "EventName": "BUSQ_EMPTY.SELF",
3408    "BriefDescription": "Bus queue is empty.",
3409    "PublicDescription": "Bus queue is empty.",
3410    "Counter": "0,1",
3411    "SampleAfterValue": "200000",
3412    "MSRIndex": "0",
3413    "MSRValue": "0",
3414    "CounterMask": "0",
3415    "Invert": "0",
3416    "AnyThread": "0",
3417    "EdgeDetect": "0",
3418    "PEBS": "0",
3419    "Errata": "null",
3420    "Offcore": "0"
3421  },
3422  {
3423    "EventCode": "0x7E",
3424    "UMask": "0xE0",
3425    "EventName": "SNOOP_STALL_DRV.ALL_AGENTS",
3426    "BriefDescription": "Bus stalled for snoops.",
3427    "PublicDescription": "Bus stalled for snoops.",
3428    "Counter": "0,1",
3429    "SampleAfterValue": "200000",
3430    "MSRIndex": "0",
3431    "MSRValue": "0",
3432    "CounterMask": "0",
3433    "Invert": "0",
3434    "AnyThread": "0",
3435    "EdgeDetect": "0",
3436    "PEBS": "0",
3437    "Errata": "null",
3438    "Offcore": "0"
3439  },
3440  {
3441    "EventCode": "0x7E",
3442    "UMask": "0x40",
3443    "EventName": "SNOOP_STALL_DRV.SELF",
3444    "BriefDescription": "Bus stalled for snoops.",
3445    "PublicDescription": "Bus stalled for snoops.",
3446    "Counter": "0,1",
3447    "SampleAfterValue": "200000",
3448    "MSRIndex": "0",
3449    "MSRValue": "0",
3450    "CounterMask": "0",
3451    "Invert": "0",
3452    "AnyThread": "0",
3453    "EdgeDetect": "0",
3454    "PEBS": "0",
3455    "Errata": "null",
3456    "Offcore": "0"
3457  },
3458  {
3459    "EventCode": "0x7F",
3460    "UMask": "0x40",
3461    "EventName": "BUS_IO_WAIT.SELF",
3462    "BriefDescription": "IO requests waiting in the bus queue.",
3463    "PublicDescription": "IO requests waiting in the bus queue.",
3464    "Counter": "0,1",
3465    "SampleAfterValue": "200000",
3466    "MSRIndex": "0",
3467    "MSRValue": "0",
3468    "CounterMask": "0",
3469    "Invert": "0",
3470    "AnyThread": "0",
3471    "EdgeDetect": "0",
3472    "PEBS": "0",
3473    "Errata": "null",
3474    "Offcore": "0"
3475  },
3476  {
3477    "EventCode": "0x80",
3478    "UMask": "0x3",
3479    "EventName": "ICACHE.ACCESSES",
3480    "BriefDescription": "Instruction fetches.",
3481    "PublicDescription": "Instruction fetches.",
3482    "Counter": "0,1",
3483    "SampleAfterValue": "200000",
3484    "MSRIndex": "0",
3485    "MSRValue": "0",
3486    "CounterMask": "0",
3487    "Invert": "0",
3488    "AnyThread": "0",
3489    "EdgeDetect": "0",
3490    "PEBS": "0",
3491    "Errata": "null",
3492    "Offcore": "0"
3493  },
3494  {
3495    "EventCode": "0x80",
3496    "UMask": "0x1",
3497    "EventName": "ICACHE.HIT",
3498    "BriefDescription": "Icache hit",
3499    "PublicDescription": "Icache hit",
3500    "Counter": "0,1",
3501    "SampleAfterValue": "200000",
3502    "MSRIndex": "0",
3503    "MSRValue": "0",
3504    "CounterMask": "0",
3505    "Invert": "0",
3506    "AnyThread": "0",
3507    "EdgeDetect": "0",
3508    "PEBS": "0",
3509    "Errata": "null",
3510    "Offcore": "0"
3511  },
3512  {
3513    "EventCode": "0x80",
3514    "UMask": "0x2",
3515    "EventName": "ICACHE.MISSES",
3516    "BriefDescription": "Icache miss",
3517    "PublicDescription": "Icache miss",
3518    "Counter": "0,1",
3519    "SampleAfterValue": "200000",
3520    "MSRIndex": "0",
3521    "MSRValue": "0",
3522    "CounterMask": "0",
3523    "Invert": "0",
3524    "AnyThread": "0",
3525    "EdgeDetect": "0",
3526    "PEBS": "0",
3527    "Errata": "null",
3528    "Offcore": "0"
3529  },
3530  {
3531    "EventCode": "0x82",
3532    "UMask": "0x1",
3533    "EventName": "ITLB.HIT",
3534    "BriefDescription": "ITLB hits.",
3535    "PublicDescription": "ITLB hits.",
3536    "Counter": "0,1",
3537    "SampleAfterValue": "200000",
3538    "MSRIndex": "0",
3539    "MSRValue": "0",
3540    "CounterMask": "0",
3541    "Invert": "0",
3542    "AnyThread": "0",
3543    "EdgeDetect": "0",
3544    "PEBS": "0",
3545    "Errata": "null",
3546    "Offcore": "0"
3547  },
3548  {
3549    "EventCode": "0x82",
3550    "UMask": "0x4",
3551    "EventName": "ITLB.FLUSH",
3552    "BriefDescription": "ITLB flushes.",
3553    "PublicDescription": "ITLB flushes.",
3554    "Counter": "0,1",
3555    "SampleAfterValue": "200000",
3556    "MSRIndex": "0",
3557    "MSRValue": "0",
3558    "CounterMask": "0",
3559    "Invert": "0",
3560    "AnyThread": "0",
3561    "EdgeDetect": "0",
3562    "PEBS": "0",
3563    "Errata": "null",
3564    "Offcore": "0"
3565  },
3566  {
3567    "EventCode": "0x82",
3568    "UMask": "0x2",
3569    "EventName": "ITLB.MISSES",
3570    "BriefDescription": "ITLB misses.",
3571    "PublicDescription": "ITLB misses.",
3572    "Counter": "0,1",
3573    "SampleAfterValue": "200000",
3574    "MSRIndex": "0",
3575    "MSRValue": "0",
3576    "CounterMask": "0",
3577    "Invert": "0",
3578    "AnyThread": "0",
3579    "EdgeDetect": "0",
3580    "PEBS": "2",
3581    "Errata": "null",
3582    "Offcore": "0"
3583  },
3584  {
3585    "EventCode": "0x86",
3586    "UMask": "0x1",
3587    "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED",
3588    "BriefDescription": "Cycles during which instruction fetches are  stalled.",
3589    "PublicDescription": "Cycles during which instruction fetches are  stalled.",
3590    "Counter": "0,1",
3591    "SampleAfterValue": "2000000",
3592    "MSRIndex": "0",
3593    "MSRValue": "0",
3594    "CounterMask": "0",
3595    "Invert": "0",
3596    "AnyThread": "0",
3597    "EdgeDetect": "0",
3598    "PEBS": "0",
3599    "Errata": "null",
3600    "Offcore": "0"
3601  },
3602  {
3603    "EventCode": "0x87",
3604    "UMask": "0x1",
3605    "EventName": "DECODE_STALL.PFB_EMPTY",
3606    "BriefDescription": "Decode stall due to PFB empty",
3607    "PublicDescription": "Decode stall due to PFB empty",
3608    "Counter": "0,1",
3609    "SampleAfterValue": "2000000",
3610    "MSRIndex": "0",
3611    "MSRValue": "0",
3612    "CounterMask": "0",
3613    "Invert": "0",
3614    "AnyThread": "0",
3615    "EdgeDetect": "0",
3616    "PEBS": "0",
3617    "Errata": "null",
3618    "Offcore": "0"
3619  },
3620  {
3621    "EventCode": "0x87",
3622    "UMask": "0x2",
3623    "EventName": "DECODE_STALL.IQ_FULL",
3624    "BriefDescription": "Decode stall due to IQ full",
3625    "PublicDescription": "Decode stall due to IQ full",
3626    "Counter": "0,1",
3627    "SampleAfterValue": "2000000",
3628    "MSRIndex": "0",
3629    "MSRValue": "0",
3630    "CounterMask": "0",
3631    "Invert": "0",
3632    "AnyThread": "0",
3633    "EdgeDetect": "0",
3634    "PEBS": "0",
3635    "Errata": "null",
3636    "Offcore": "0"
3637  },
3638  {
3639    "EventCode": "0x88",
3640    "UMask": "0x1",
3641    "EventName": "BR_INST_TYPE_RETIRED.COND",
3642    "BriefDescription": "All macro conditional branch instructions.",
3643    "PublicDescription": "All macro conditional branch instructions.",
3644    "Counter": "0,1",
3645    "SampleAfterValue": "2000000",
3646    "MSRIndex": "0",
3647    "MSRValue": "0",
3648    "CounterMask": "0",
3649    "Invert": "0",
3650    "AnyThread": "0",
3651    "EdgeDetect": "0",
3652    "PEBS": "0",
3653    "Errata": "null",
3654    "Offcore": "0"
3655  },
3656  {
3657    "EventCode": "0x88",
3658    "UMask": "0x2",
3659    "EventName": "BR_INST_TYPE_RETIRED.UNCOND",
3660    "BriefDescription": "All macro unconditional branch instructions, excluding calls and indirects",
3661    "PublicDescription": "All macro unconditional branch instructions, excluding calls and indirects",
3662    "Counter": "0,1",
3663    "SampleAfterValue": "2000000",
3664    "MSRIndex": "0",
3665    "MSRValue": "0",
3666    "CounterMask": "0",
3667    "Invert": "0",
3668    "AnyThread": "0",
3669    "EdgeDetect": "0",
3670    "PEBS": "0",
3671    "Errata": "null",
3672    "Offcore": "0"
3673  },
3674  {
3675    "EventCode": "0x88",
3676    "UMask": "0x4",
3677    "EventName": "BR_INST_TYPE_RETIRED.IND",
3678    "BriefDescription": "All indirect branches that are not calls.",
3679    "PublicDescription": "All indirect branches that are not calls.",
3680    "Counter": "0,1",
3681    "SampleAfterValue": "2000000",
3682    "MSRIndex": "0",
3683    "MSRValue": "0",
3684    "CounterMask": "0",
3685    "Invert": "0",
3686    "AnyThread": "0",
3687    "EdgeDetect": "0",
3688    "PEBS": "0",
3689    "Errata": "null",
3690    "Offcore": "0"
3691  },
3692  {
3693    "EventCode": "0x88",
3694    "UMask": "0x8",
3695    "EventName": "BR_INST_TYPE_RETIRED.RET",
3696    "BriefDescription": "All indirect branches that have a return mnemonic",
3697    "PublicDescription": "All indirect branches that have a return mnemonic",
3698    "Counter": "0,1",
3699    "SampleAfterValue": "2000000",
3700    "MSRIndex": "0",
3701    "MSRValue": "0",
3702    "CounterMask": "0",
3703    "Invert": "0",
3704    "AnyThread": "0",
3705    "EdgeDetect": "0",
3706    "PEBS": "0",
3707    "Errata": "null",
3708    "Offcore": "0"
3709  },
3710  {
3711    "EventCode": "0x88",
3712    "UMask": "0x10",
3713    "EventName": "BR_INST_TYPE_RETIRED.DIR_CALL",
3714    "BriefDescription": "All non-indirect calls",
3715    "PublicDescription": "All non-indirect calls",
3716    "Counter": "0,1",
3717    "SampleAfterValue": "2000000",
3718    "MSRIndex": "0",
3719    "MSRValue": "0",
3720    "CounterMask": "0",
3721    "Invert": "0",
3722    "AnyThread": "0",
3723    "EdgeDetect": "0",
3724    "PEBS": "0",
3725    "Errata": "null",
3726    "Offcore": "0"
3727  },
3728  {
3729    "EventCode": "0x88",
3730    "UMask": "0x20",
3731    "EventName": "BR_INST_TYPE_RETIRED.IND_CALL",
3732    "BriefDescription": "All indirect calls, including both register and memory indirect.",
3733    "PublicDescription": "All indirect calls, including both register and memory indirect.",
3734    "Counter": "0,1",
3735    "SampleAfterValue": "2000000",
3736    "MSRIndex": "0",
3737    "MSRValue": "0",
3738    "CounterMask": "0",
3739    "Invert": "0",
3740    "AnyThread": "0",
3741    "EdgeDetect": "0",
3742    "PEBS": "0",
3743    "Errata": "null",
3744    "Offcore": "0"
3745  },
3746  {
3747    "EventCode": "0x88",
3748    "UMask": "0x41",
3749    "EventName": "BR_INST_TYPE_RETIRED.COND_TAKEN",
3750    "BriefDescription": "Only taken macro conditional branch instructions",
3751    "PublicDescription": "Only taken macro conditional branch instructions",
3752    "Counter": "0,1",
3753    "SampleAfterValue": "2000000",
3754    "MSRIndex": "0",
3755    "MSRValue": "0",
3756    "CounterMask": "0",
3757    "Invert": "0",
3758    "AnyThread": "0",
3759    "EdgeDetect": "0",
3760    "PEBS": "0",
3761    "Errata": "null",
3762    "Offcore": "0"
3763  },
3764  {
3765    "EventCode": "0x89",
3766    "UMask": "0x1",
3767    "EventName": "BR_MISSP_TYPE_RETIRED.COND",
3768    "BriefDescription": "Mispredicted cond branch instructions retired",
3769    "PublicDescription": "Mispredicted cond branch instructions retired",
3770    "Counter": "0,1",
3771    "SampleAfterValue": "200000",
3772    "MSRIndex": "0",
3773    "MSRValue": "0",
3774    "CounterMask": "0",
3775    "Invert": "0",
3776    "AnyThread": "0",
3777    "EdgeDetect": "0",
3778    "PEBS": "0",
3779    "Errata": "null",
3780    "Offcore": "0"
3781  },
3782  {
3783    "EventCode": "0x89",
3784    "UMask": "0x2",
3785    "EventName": "BR_MISSP_TYPE_RETIRED.IND",
3786    "BriefDescription": "Mispredicted ind branches that are not calls",
3787    "PublicDescription": "Mispredicted ind branches that are not calls",
3788    "Counter": "0,1",
3789    "SampleAfterValue": "200000",
3790    "MSRIndex": "0",
3791    "MSRValue": "0",
3792    "CounterMask": "0",
3793    "Invert": "0",
3794    "AnyThread": "0",
3795    "EdgeDetect": "0",
3796    "PEBS": "0",
3797    "Errata": "null",
3798    "Offcore": "0"
3799  },
3800  {
3801    "EventCode": "0x89",
3802    "UMask": "0x4",
3803    "EventName": "BR_MISSP_TYPE_RETIRED.RETURN",
3804    "BriefDescription": "Mispredicted return branches",
3805    "PublicDescription": "Mispredicted return branches",
3806    "Counter": "0,1",
3807    "SampleAfterValue": "200000",
3808    "MSRIndex": "0",
3809    "MSRValue": "0",
3810    "CounterMask": "0",
3811    "Invert": "0",
3812    "AnyThread": "0",
3813    "EdgeDetect": "0",
3814    "PEBS": "0",
3815    "Errata": "null",
3816    "Offcore": "0"
3817  },
3818  {
3819    "EventCode": "0x89",
3820    "UMask": "0x8",
3821    "EventName": "BR_MISSP_TYPE_RETIRED.IND_CALL",
3822    "BriefDescription": "Mispredicted indirect calls, including both register and memory indirect. ",
3823    "PublicDescription": "Mispredicted indirect calls, including both register and memory indirect. ",
3824    "Counter": "0,1",
3825    "SampleAfterValue": "200000",
3826    "MSRIndex": "0",
3827    "MSRValue": "0",
3828    "CounterMask": "0",
3829    "Invert": "0",
3830    "AnyThread": "0",
3831    "EdgeDetect": "0",
3832    "PEBS": "0",
3833    "Errata": "null",
3834    "Offcore": "0"
3835  },
3836  {
3837    "EventCode": "0x89",
3838    "UMask": "0x11",
3839    "EventName": "BR_MISSP_TYPE_RETIRED.COND_TAKEN",
3840    "BriefDescription": "Mispredicted and taken cond branch instructions retired",
3841    "PublicDescription": "Mispredicted and taken cond branch instructions retired",
3842    "Counter": "0,1",
3843    "SampleAfterValue": "200000",
3844    "MSRIndex": "0",
3845    "MSRValue": "0",
3846    "CounterMask": "0",
3847    "Invert": "0",
3848    "AnyThread": "0",
3849    "EdgeDetect": "0",
3850    "PEBS": "0",
3851    "Errata": "null",
3852    "Offcore": "0"
3853  },
3854  {
3855    "EventCode": "0xAA",
3856    "UMask": "0x1",
3857    "EventName": "MACRO_INSTS.NON_CISC_DECODED",
3858    "BriefDescription": "Non-CISC nacro instructions decoded",
3859    "PublicDescription": "Non-CISC nacro instructions decoded",
3860    "Counter": "0,1",
3861    "SampleAfterValue": "2000000",
3862    "MSRIndex": "0",
3863    "MSRValue": "0",
3864    "CounterMask": "0",
3865    "Invert": "0",
3866    "AnyThread": "0",
3867    "EdgeDetect": "0",
3868    "PEBS": "0",
3869    "Errata": "null",
3870    "Offcore": "0"
3871  },
3872  {
3873    "EventCode": "0xAA",
3874    "UMask": "0x2",
3875    "EventName": "MACRO_INSTS.CISC_DECODED",
3876    "BriefDescription": "CISC macro instructions decoded",
3877    "PublicDescription": "CISC macro instructions decoded",
3878    "Counter": "0,1",
3879    "SampleAfterValue": "2000000",
3880    "MSRIndex": "0",
3881    "MSRValue": "0",
3882    "CounterMask": "0",
3883    "Invert": "0",
3884    "AnyThread": "0",
3885    "EdgeDetect": "0",
3886    "PEBS": "0",
3887    "Errata": "null",
3888    "Offcore": "0"
3889  },
3890  {
3891    "EventCode": "0xAA",
3892    "UMask": "0x3",
3893    "EventName": "MACRO_INSTS.ALL_DECODED",
3894    "BriefDescription": "All Instructions decoded",
3895    "PublicDescription": "All Instructions decoded",
3896    "Counter": "0,1",
3897    "SampleAfterValue": "2000000",
3898    "MSRIndex": "0",
3899    "MSRValue": "0",
3900    "CounterMask": "0",
3901    "Invert": "0",
3902    "AnyThread": "0",
3903    "EdgeDetect": "0",
3904    "PEBS": "0",
3905    "Errata": "null",
3906    "Offcore": "0"
3907  },
3908  {
3909    "EventCode": "0xB0",
3910    "UMask": "0x0",
3911    "EventName": "SIMD_UOPS_EXEC.S",
3912    "BriefDescription": "SIMD micro-ops executed (excluding stores).",
3913    "PublicDescription": "SIMD micro-ops executed (excluding stores).",
3914    "Counter": "0,1",
3915    "SampleAfterValue": "2000000",
3916    "MSRIndex": "0",
3917    "MSRValue": "0",
3918    "CounterMask": "0",
3919    "Invert": "0",
3920    "AnyThread": "0",
3921    "EdgeDetect": "0",
3922    "PEBS": "0",
3923    "Errata": "null",
3924    "Offcore": "0"
3925  },
3926  {
3927    "EventCode": "0xB0",
3928    "UMask": "0x80",
3929    "EventName": "SIMD_UOPS_EXEC.AR",
3930    "BriefDescription": "SIMD micro-ops retired (excluding stores).",
3931    "PublicDescription": "SIMD micro-ops retired (excluding stores).",
3932    "Counter": "0,1",
3933    "SampleAfterValue": "2000000",
3934    "MSRIndex": "0",
3935    "MSRValue": "0",
3936    "CounterMask": "0",
3937    "Invert": "0",
3938    "AnyThread": "0",
3939    "EdgeDetect": "0",
3940    "PEBS": "2",
3941    "Errata": "null",
3942    "Offcore": "0"
3943  },
3944  {
3945    "EventCode": "0xB1",
3946    "UMask": "0x0",
3947    "EventName": "SIMD_SAT_UOP_EXEC.S",
3948    "BriefDescription": "SIMD saturated arithmetic micro-ops executed.",
3949    "PublicDescription": "SIMD saturated arithmetic micro-ops executed.",
3950    "Counter": "0,1",
3951    "SampleAfterValue": "2000000",
3952    "MSRIndex": "0",
3953    "MSRValue": "0",
3954    "CounterMask": "0",
3955    "Invert": "0",
3956    "AnyThread": "0",
3957    "EdgeDetect": "0",
3958    "PEBS": "0",
3959    "Errata": "null",
3960    "Offcore": "0"
3961  },
3962  {
3963    "EventCode": "0xB1",
3964    "UMask": "0x80",
3965    "EventName": "SIMD_SAT_UOP_EXEC.AR",
3966    "BriefDescription": "SIMD saturated arithmetic micro-ops retired.",
3967    "PublicDescription": "SIMD saturated arithmetic micro-ops retired.",
3968    "Counter": "0,1",
3969    "SampleAfterValue": "2000000",
3970    "MSRIndex": "0",
3971    "MSRValue": "0",
3972    "CounterMask": "0",
3973    "Invert": "0",
3974    "AnyThread": "0",
3975    "EdgeDetect": "0",
3976    "PEBS": "0",
3977    "Errata": "null",
3978    "Offcore": "0"
3979  },
3980  {
3981    "EventCode": "0xB3",
3982    "UMask": "0x1",
3983    "EventName": "SIMD_UOP_TYPE_EXEC.MUL.S",
3984    "BriefDescription": "SIMD packed multiply micro-ops executed",
3985    "PublicDescription": "SIMD packed multiply micro-ops executed",
3986    "Counter": "0,1",
3987    "SampleAfterValue": "2000000",
3988    "MSRIndex": "0",
3989    "MSRValue": "0",
3990    "CounterMask": "0",
3991    "Invert": "0",
3992    "AnyThread": "0",
3993    "EdgeDetect": "0",
3994    "PEBS": "0",
3995    "Errata": "null",
3996    "Offcore": "0"
3997  },
3998  {
3999    "EventCode": "0xB3",
4000    "UMask": "0x81",
4001    "EventName": "SIMD_UOP_TYPE_EXEC.MUL.AR",
4002    "BriefDescription": "SIMD packed multiply micro-ops retired",
4003    "PublicDescription": "SIMD packed multiply micro-ops retired",
4004    "Counter": "0,1",
4005    "SampleAfterValue": "2000000",
4006    "MSRIndex": "0",
4007    "MSRValue": "0",
4008    "CounterMask": "0",
4009    "Invert": "0",
4010    "AnyThread": "0",
4011    "EdgeDetect": "0",
4012    "PEBS": "0",
4013    "Errata": "null",
4014    "Offcore": "0"
4015  },
4016  {
4017    "EventCode": "0xB3",
4018    "UMask": "0x2",
4019    "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.S",
4020    "BriefDescription": "SIMD packed shift micro-ops executed",
4021    "PublicDescription": "SIMD packed shift micro-ops executed",
4022    "Counter": "0,1",
4023    "SampleAfterValue": "2000000",
4024    "MSRIndex": "0",
4025    "MSRValue": "0",
4026    "CounterMask": "0",
4027    "Invert": "0",
4028    "AnyThread": "0",
4029    "EdgeDetect": "0",
4030    "PEBS": "0",
4031    "Errata": "null",
4032    "Offcore": "0"
4033  },
4034  {
4035    "EventCode": "0xB3",
4036    "UMask": "0x82",
4037    "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.AR",
4038    "BriefDescription": "SIMD packed shift micro-ops retired",
4039    "PublicDescription": "SIMD packed shift micro-ops retired",
4040    "Counter": "0,1",
4041    "SampleAfterValue": "2000000",
4042    "MSRIndex": "0",
4043    "MSRValue": "0",
4044    "CounterMask": "0",
4045    "Invert": "0",
4046    "AnyThread": "0",
4047    "EdgeDetect": "0",
4048    "PEBS": "0",
4049    "Errata": "null",
4050    "Offcore": "0"
4051  },
4052  {
4053    "EventCode": "0xB3",
4054    "UMask": "0x4",
4055    "EventName": "SIMD_UOP_TYPE_EXEC.PACK.S",
4056    "BriefDescription": "SIMD packed micro-ops executed",
4057    "PublicDescription": "SIMD packed micro-ops executed",
4058    "Counter": "0,1",
4059    "SampleAfterValue": "2000000",
4060    "MSRIndex": "0",
4061    "MSRValue": "0",
4062    "CounterMask": "0",
4063    "Invert": "0",
4064    "AnyThread": "0",
4065    "EdgeDetect": "0",
4066    "PEBS": "0",
4067    "Errata": "null",
4068    "Offcore": "0"
4069  },
4070  {
4071    "EventCode": "0xB3",
4072    "UMask": "0x84",
4073    "EventName": "SIMD_UOP_TYPE_EXEC.PACK.AR",
4074    "BriefDescription": "SIMD packed micro-ops retired",
4075    "PublicDescription": "SIMD packed micro-ops retired",
4076    "Counter": "0,1",
4077    "SampleAfterValue": "2000000",
4078    "MSRIndex": "0",
4079    "MSRValue": "0",
4080    "CounterMask": "0",
4081    "Invert": "0",
4082    "AnyThread": "0",
4083    "EdgeDetect": "0",
4084    "PEBS": "0",
4085    "Errata": "null",
4086    "Offcore": "0"
4087  },
4088  {
4089    "EventCode": "0xB3",
4090    "UMask": "0x8",
4091    "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.S",
4092    "BriefDescription": "SIMD unpacked micro-ops executed",
4093    "PublicDescription": "SIMD unpacked micro-ops executed",
4094    "Counter": "0,1",
4095    "SampleAfterValue": "2000000",
4096    "MSRIndex": "0",
4097    "MSRValue": "0",
4098    "CounterMask": "0",
4099    "Invert": "0",
4100    "AnyThread": "0",
4101    "EdgeDetect": "0",
4102    "PEBS": "0",
4103    "Errata": "null",
4104    "Offcore": "0"
4105  },
4106  {
4107    "EventCode": "0xB3",
4108    "UMask": "0x88",
4109    "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.AR",
4110    "BriefDescription": "SIMD unpacked micro-ops retired",
4111    "PublicDescription": "SIMD unpacked micro-ops retired",
4112    "Counter": "0,1",
4113    "SampleAfterValue": "2000000",
4114    "MSRIndex": "0",
4115    "MSRValue": "0",
4116    "CounterMask": "0",
4117    "Invert": "0",
4118    "AnyThread": "0",
4119    "EdgeDetect": "0",
4120    "PEBS": "0",
4121    "Errata": "null",
4122    "Offcore": "0"
4123  },
4124  {
4125    "EventCode": "0xB3",
4126    "UMask": "0x10",
4127    "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.S",
4128    "BriefDescription": "SIMD packed logical micro-ops executed",
4129    "PublicDescription": "SIMD packed logical micro-ops executed",
4130    "Counter": "0,1",
4131    "SampleAfterValue": "2000000",
4132    "MSRIndex": "0",
4133    "MSRValue": "0",
4134    "CounterMask": "0",
4135    "Invert": "0",
4136    "AnyThread": "0",
4137    "EdgeDetect": "0",
4138    "PEBS": "0",
4139    "Errata": "null",
4140    "Offcore": "0"
4141  },
4142  {
4143    "EventCode": "0xB3",
4144    "UMask": "0x90",
4145    "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.AR",
4146    "BriefDescription": "SIMD packed logical micro-ops retired",
4147    "PublicDescription": "SIMD packed logical micro-ops retired",
4148    "Counter": "0,1",
4149    "SampleAfterValue": "2000000",
4150    "MSRIndex": "0",
4151    "MSRValue": "0",
4152    "CounterMask": "0",
4153    "Invert": "0",
4154    "AnyThread": "0",
4155    "EdgeDetect": "0",
4156    "PEBS": "0",
4157    "Errata": "null",
4158    "Offcore": "0"
4159  },
4160  {
4161    "EventCode": "0xB3",
4162    "UMask": "0x20",
4163    "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.S",
4164    "BriefDescription": "SIMD packed arithmetic micro-ops executed",
4165    "PublicDescription": "SIMD packed arithmetic micro-ops executed",
4166    "Counter": "0,1",
4167    "SampleAfterValue": "2000000",
4168    "MSRIndex": "0",
4169    "MSRValue": "0",
4170    "CounterMask": "0",
4171    "Invert": "0",
4172    "AnyThread": "0",
4173    "EdgeDetect": "0",
4174    "PEBS": "0",
4175    "Errata": "null",
4176    "Offcore": "0"
4177  },
4178  {
4179    "EventCode": "0xB3",
4180    "UMask": "0xA0",
4181    "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR",
4182    "BriefDescription": "SIMD packed arithmetic micro-ops retired",
4183    "PublicDescription": "SIMD packed arithmetic micro-ops retired",
4184    "Counter": "0,1",
4185    "SampleAfterValue": "2000000",
4186    "MSRIndex": "0",
4187    "MSRValue": "0",
4188    "CounterMask": "0",
4189    "Invert": "0",
4190    "AnyThread": "0",
4191    "EdgeDetect": "0",
4192    "PEBS": "0",
4193    "Errata": "null",
4194    "Offcore": "0"
4195  },
4196  {
4197    "EventCode": "0xC0",
4198    "UMask": "0x0",
4199    "EventName": "INST_RETIRED.ANY_P",
4200    "BriefDescription": "Instructions retired (precise event).",
4201    "PublicDescription": "Instructions retired (precise event).",
4202    "Counter": "0,1",
4203    "SampleAfterValue": "2000000",
4204    "MSRIndex": "0",
4205    "MSRValue": "0",
4206    "CounterMask": "0",
4207    "Invert": "0",
4208    "AnyThread": "0",
4209    "EdgeDetect": "0",
4210    "PEBS": "2",
4211    "Errata": "null",
4212    "Offcore": "0"
4213  },
4214  {
4215    "EventCode": "0xA",
4216    "UMask": "0x0",
4217    "EventName": "INST_RETIRED.ANY",
4218    "BriefDescription": "Instructions retired.",
4219    "PublicDescription": "Instructions retired.",
4220    "Counter": "Fixed counter 1",
4221    "SampleAfterValue": "2000000",
4222    "MSRIndex": "0",
4223    "MSRValue": "0",
4224    "CounterMask": "0",
4225    "Invert": "0",
4226    "AnyThread": "0",
4227    "EdgeDetect": "0",
4228    "PEBS": "0",
4229    "Errata": "null",
4230    "Offcore": "0"
4231  },
4232  {
4233    "EventCode": "0xC2",
4234    "UMask": "0x10",
4235    "EventName": "UOPS_RETIRED.ANY",
4236    "BriefDescription": "Micro-ops retired.",
4237    "PublicDescription": "Micro-ops retired.",
4238    "Counter": "0,1",
4239    "SampleAfterValue": "2000000",
4240    "MSRIndex": "0",
4241    "MSRValue": "0",
4242    "CounterMask": "0",
4243    "Invert": "0",
4244    "AnyThread": "0",
4245    "EdgeDetect": "0",
4246    "PEBS": "0",
4247    "Errata": "null",
4248    "Offcore": "0"
4249  },
4250  {
4251    "EventCode": "0xC2",
4252    "UMask": "0x10",
4253    "EventName": "UOPS_RETIRED.STALLED_CYCLES",
4254    "BriefDescription": "Cycles no micro-ops retired.",
4255    "PublicDescription": "Cycles no micro-ops retired.",
4256    "Counter": "0,1",
4257    "SampleAfterValue": "2000000",
4258    "MSRIndex": "0",
4259    "MSRValue": "0",
4260    "CounterMask": "0",
4261    "Invert": "0",
4262    "AnyThread": "0",
4263    "EdgeDetect": "0",
4264    "PEBS": "0",
4265    "Errata": "null",
4266    "Offcore": "0"
4267  },
4268  {
4269    "EventCode": "0xC2",
4270    "UMask": "0x10",
4271    "EventName": "UOPS_RETIRED.STALLS",
4272    "BriefDescription": "Periods no micro-ops retired.",
4273    "PublicDescription": "Periods no micro-ops retired.",
4274    "Counter": "0,1",
4275    "SampleAfterValue": "2000000",
4276    "MSRIndex": "0",
4277    "MSRValue": "0",
4278    "CounterMask": "0",
4279    "Invert": "0",
4280    "AnyThread": "0",
4281    "EdgeDetect": "0",
4282    "PEBS": "0",
4283    "Errata": "null",
4284    "Offcore": "0"
4285  },
4286  {
4287    "EventCode": "0xA9",
4288    "UMask": "0x1",
4289    "EventName": "UOPS.MS_CYCLES",
4290    "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ. ",
4291    "PublicDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ. ",
4292    "Counter": "0,1",
4293    "SampleAfterValue": "2000000",
4294    "MSRIndex": "0",
4295    "MSRValue": "0",
4296    "CounterMask": "1",
4297    "Invert": "0",
4298    "AnyThread": "0",
4299    "EdgeDetect": "0",
4300    "PEBS": "0",
4301    "Errata": "null",
4302    "Offcore": "0"
4303  },
4304  {
4305    "EventCode": "0xC3",
4306    "UMask": "0x1",
4307    "EventName": "MACHINE_CLEARS.SMC",
4308    "BriefDescription": "Self-Modifying Code detected.",
4309    "PublicDescription": "Self-Modifying Code detected.",
4310    "Counter": "0,1",
4311    "SampleAfterValue": "200000",
4312    "MSRIndex": "0",
4313    "MSRValue": "0",
4314    "CounterMask": "0",
4315    "Invert": "0",
4316    "AnyThread": "0",
4317    "EdgeDetect": "0",
4318    "PEBS": "0",
4319    "Errata": "null",
4320    "Offcore": "0"
4321  },
4322  {
4323    "EventCode": "0xC4",
4324    "UMask": "0x0",
4325    "EventName": "BR_INST_RETIRED.ANY",
4326    "BriefDescription": "Retired branch instructions.",
4327    "PublicDescription": "Retired branch instructions.",
4328    "Counter": "0,1",
4329    "SampleAfterValue": "2000000",
4330    "MSRIndex": "0",
4331    "MSRValue": "0",
4332    "CounterMask": "0",
4333    "Invert": "0",
4334    "AnyThread": "0",
4335    "EdgeDetect": "0",
4336    "PEBS": "0",
4337    "Errata": "null",
4338    "Offcore": "0"
4339  },
4340  {
4341    "EventCode": "0xC4",
4342    "UMask": "0x1",
4343    "EventName": "BR_INST_RETIRED.PRED_NOT_TAKEN",
4344    "BriefDescription": "Retired branch instructions that were predicted not-taken.",
4345    "PublicDescription": "Retired branch instructions that were predicted not-taken.",
4346    "Counter": "0,1",
4347    "SampleAfterValue": "2000000",
4348    "MSRIndex": "0",
4349    "MSRValue": "0",
4350    "CounterMask": "0",
4351    "Invert": "0",
4352    "AnyThread": "0",
4353    "EdgeDetect": "0",
4354    "PEBS": "0",
4355    "Errata": "null",
4356    "Offcore": "0"
4357  },
4358  {
4359    "EventCode": "0xC4",
4360    "UMask": "0x2",
4361    "EventName": "BR_INST_RETIRED.MISPRED_NOT_TAKEN",
4362    "BriefDescription": "Retired branch instructions that were mispredicted not-taken.",
4363    "PublicDescription": "Retired branch instructions that were mispredicted not-taken.",
4364    "Counter": "0,1",
4365    "SampleAfterValue": "200000",
4366    "MSRIndex": "0",
4367    "MSRValue": "0",
4368    "CounterMask": "0",
4369    "Invert": "0",
4370    "AnyThread": "0",
4371    "EdgeDetect": "0",
4372    "PEBS": "0",
4373    "Errata": "null",
4374    "Offcore": "0"
4375  },
4376  {
4377    "EventCode": "0xC4",
4378    "UMask": "0x4",
4379    "EventName": "BR_INST_RETIRED.PRED_TAKEN",
4380    "BriefDescription": "Retired branch instructions that were predicted taken.",
4381    "PublicDescription": "Retired branch instructions that were predicted taken.",
4382    "Counter": "0,1",
4383    "SampleAfterValue": "2000000",
4384    "MSRIndex": "0",
4385    "MSRValue": "0",
4386    "CounterMask": "0",
4387    "Invert": "0",
4388    "AnyThread": "0",
4389    "EdgeDetect": "0",
4390    "PEBS": "0",
4391    "Errata": "null",
4392    "Offcore": "0"
4393  },
4394  {
4395    "EventCode": "0xC4",
4396    "UMask": "0x8",
4397    "EventName": "BR_INST_RETIRED.MISPRED_TAKEN",
4398    "BriefDescription": "Retired branch instructions that were mispredicted taken.",
4399    "PublicDescription": "Retired branch instructions that were mispredicted taken.",
4400    "Counter": "0,1",
4401    "SampleAfterValue": "200000",
4402    "MSRIndex": "0",
4403    "MSRValue": "0",
4404    "CounterMask": "0",
4405    "Invert": "0",
4406    "AnyThread": "0",
4407    "EdgeDetect": "0",
4408    "PEBS": "0",
4409    "Errata": "null",
4410    "Offcore": "0"
4411  },
4412  {
4413    "EventCode": "0xC4",
4414    "UMask": "0xC",
4415    "EventName": "BR_INST_RETIRED.TAKEN",
4416    "BriefDescription": "Retired taken branch instructions.",
4417    "PublicDescription": "Retired taken branch instructions.",
4418    "Counter": "0,1",
4419    "SampleAfterValue": "2000000",
4420    "MSRIndex": "0",
4421    "MSRValue": "0",
4422    "CounterMask": "0",
4423    "Invert": "0",
4424    "AnyThread": "0",
4425    "EdgeDetect": "0",
4426    "PEBS": "0",
4427    "Errata": "null",
4428    "Offcore": "0"
4429  },
4430  {
4431    "EventCode": "0xC4",
4432    "UMask": "0xF",
4433    "EventName": "BR_INST_RETIRED.ANY1",
4434    "BriefDescription": "Retired branch instructions.",
4435    "PublicDescription": "Retired branch instructions.",
4436    "Counter": "0,1",
4437    "SampleAfterValue": "2000000",
4438    "MSRIndex": "0",
4439    "MSRValue": "0",
4440    "CounterMask": "0",
4441    "Invert": "0",
4442    "AnyThread": "0",
4443    "EdgeDetect": "0",
4444    "PEBS": "0",
4445    "Errata": "null",
4446    "Offcore": "0"
4447  },
4448  {
4449    "EventCode": "0xC5",
4450    "UMask": "0x0",
4451    "EventName": "BR_INST_RETIRED.MISPRED",
4452    "BriefDescription": "Retired mispredicted branch instructions (precise event).",
4453    "PublicDescription": "Retired mispredicted branch instructions (precise event).",
4454    "Counter": "0,1",
4455    "SampleAfterValue": "200000",
4456    "MSRIndex": "0",
4457    "MSRValue": "0",
4458    "CounterMask": "0",
4459    "Invert": "0",
4460    "AnyThread": "0",
4461    "EdgeDetect": "0",
4462    "PEBS": "1",
4463    "Errata": "null",
4464    "Offcore": "0"
4465  },
4466  {
4467    "EventCode": "0xC6",
4468    "UMask": "0x1",
4469    "EventName": "CYCLES_INT_MASKED.CYCLES_INT_MASKED",
4470    "BriefDescription": "Cycles during which interrupts are disabled.",
4471    "PublicDescription": "Cycles during which interrupts are disabled.",
4472    "Counter": "0,1",
4473    "SampleAfterValue": "2000000",
4474    "MSRIndex": "0",
4475    "MSRValue": "0",
4476    "CounterMask": "0",
4477    "Invert": "0",
4478    "AnyThread": "0",
4479    "EdgeDetect": "0",
4480    "PEBS": "0",
4481    "Errata": "null",
4482    "Offcore": "0"
4483  },
4484  {
4485    "EventCode": "0xC6",
4486    "UMask": "0x2",
4487    "EventName": "CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED",
4488    "BriefDescription": "Cycles during which interrupts are pending and disabled.",
4489    "PublicDescription": "Cycles during which interrupts are pending and disabled.",
4490    "Counter": "0,1",
4491    "SampleAfterValue": "2000000",
4492    "MSRIndex": "0",
4493    "MSRValue": "0",
4494    "CounterMask": "0",
4495    "Invert": "0",
4496    "AnyThread": "0",
4497    "EdgeDetect": "0",
4498    "PEBS": "0",
4499    "Errata": "null",
4500    "Offcore": "0"
4501  },
4502  {
4503    "EventCode": "0xC7",
4504    "UMask": "0x1",
4505    "EventName": "SIMD_INST_RETIRED.PACKED_SINGLE",
4506    "BriefDescription": "Retired Streaming SIMD Extensions (SSE) packed-single instructions.",
4507    "PublicDescription": "Retired Streaming SIMD Extensions (SSE) packed-single instructions.",
4508    "Counter": "0,1",
4509    "SampleAfterValue": "2000000",
4510    "MSRIndex": "0",
4511    "MSRValue": "0",
4512    "CounterMask": "0",
4513    "Invert": "0",
4514    "AnyThread": "0",
4515    "EdgeDetect": "0",
4516    "PEBS": "0",
4517    "Errata": "null",
4518    "Offcore": "0"
4519  },
4520  {
4521    "EventCode": "0xC7",
4522    "UMask": "0x2",
4523    "EventName": "SIMD_INST_RETIRED.SCALAR_SINGLE",
4524    "BriefDescription": "Retired Streaming SIMD Extensions (SSE) scalar-single instructions.",
4525    "PublicDescription": "Retired Streaming SIMD Extensions (SSE) scalar-single instructions.",
4526    "Counter": "0,1",
4527    "SampleAfterValue": "2000000",
4528    "MSRIndex": "0",
4529    "MSRValue": "0",
4530    "CounterMask": "0",
4531    "Invert": "0",
4532    "AnyThread": "0",
4533    "EdgeDetect": "0",
4534    "PEBS": "0",
4535    "Errata": "null",
4536    "Offcore": "0"
4537  },
4538  {
4539    "EventCode": "0xC7",
4540    "UMask": "0x8",
4541    "EventName": "SIMD_INST_RETIRED.SCALAR_DOUBLE",
4542    "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
4543    "PublicDescription": "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
4544    "Counter": "0,1",
4545    "SampleAfterValue": "2000000",
4546    "MSRIndex": "0",
4547    "MSRValue": "0",
4548    "CounterMask": "0",
4549    "Invert": "0",
4550    "AnyThread": "0",
4551    "EdgeDetect": "0",
4552    "PEBS": "0",
4553    "Errata": "null",
4554    "Offcore": "0"
4555  },
4556  {
4557    "EventCode": "0xC7",
4558    "UMask": "0x10",
4559    "EventName": "SIMD_INST_RETIRED.VECTOR",
4560    "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) vector instructions.",
4561    "PublicDescription": "Retired Streaming SIMD Extensions 2 (SSE2) vector instructions.",
4562    "Counter": "0,1",
4563    "SampleAfterValue": "2000000",
4564    "MSRIndex": "0",
4565    "MSRValue": "0",
4566    "CounterMask": "0",
4567    "Invert": "0",
4568    "AnyThread": "0",
4569    "EdgeDetect": "0",
4570    "PEBS": "0",
4571    "Errata": "null",
4572    "Offcore": "0"
4573  },
4574  {
4575    "EventCode": "0xC8",
4576    "UMask": "0x0",
4577    "EventName": "HW_INT_RCV",
4578    "BriefDescription": "Hardware interrupts received.",
4579    "PublicDescription": "Hardware interrupts received.",
4580    "Counter": "0,1",
4581    "SampleAfterValue": "200000",
4582    "MSRIndex": "0",
4583    "MSRValue": "0",
4584    "CounterMask": "0",
4585    "Invert": "0",
4586    "AnyThread": "0",
4587    "EdgeDetect": "0",
4588    "PEBS": "0",
4589    "Errata": "null",
4590    "Offcore": "0"
4591  },
4592  {
4593    "EventCode": "0xCA",
4594    "UMask": "0x1",
4595    "EventName": "SIMD_COMP_INST_RETIRED.PACKED_SINGLE",
4596    "BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions.",
4597    "PublicDescription": "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions.",
4598    "Counter": "0,1",
4599    "SampleAfterValue": "2000000",
4600    "MSRIndex": "0",
4601    "MSRValue": "0",
4602    "CounterMask": "0",
4603    "Invert": "0",
4604    "AnyThread": "0",
4605    "EdgeDetect": "0",
4606    "PEBS": "0",
4607    "Errata": "null",
4608    "Offcore": "0"
4609  },
4610  {
4611    "EventCode": "0xCA",
4612    "UMask": "0x2",
4613    "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_SINGLE",
4614    "BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions.",
4615    "PublicDescription": "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions.",
4616    "Counter": "0,1",
4617    "SampleAfterValue": "2000000",
4618    "MSRIndex": "0",
4619    "MSRValue": "0",
4620    "CounterMask": "0",
4621    "Invert": "0",
4622    "AnyThread": "0",
4623    "EdgeDetect": "0",
4624    "PEBS": "0",
4625    "Errata": "null",
4626    "Offcore": "0"
4627  },
4628  {
4629    "EventCode": "0xCA",
4630    "UMask": "0x8",
4631    "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE",
4632    "BriefDescription": "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
4633    "PublicDescription": "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
4634    "Counter": "0,1",
4635    "SampleAfterValue": "2000000",
4636    "MSRIndex": "0",
4637    "MSRValue": "0",
4638    "CounterMask": "0",
4639    "Invert": "0",
4640    "AnyThread": "0",
4641    "EdgeDetect": "0",
4642    "PEBS": "0",
4643    "Errata": "null",
4644    "Offcore": "0"
4645  },
4646  {
4647    "EventCode": "0xCB",
4648    "UMask": "0x1",
4649    "EventName": "MEM_LOAD_RETIRED.L2_HIT",
4650    "BriefDescription": "Retired loads that hit the L2 cache (precise event).",
4651    "PublicDescription": "Retired loads that hit the L2 cache (precise event).",
4652    "Counter": "0,1",
4653    "SampleAfterValue": "200000",
4654    "MSRIndex": "0",
4655    "MSRValue": "0",
4656    "CounterMask": "0",
4657    "Invert": "0",
4658    "AnyThread": "0",
4659    "EdgeDetect": "0",
4660    "PEBS": "0",
4661    "Errata": "null",
4662    "Offcore": "0"
4663  },
4664  {
4665    "EventCode": "0xCB",
4666    "UMask": "0x2",
4667    "EventName": "MEM_LOAD_RETIRED.L2_MISS",
4668    "BriefDescription": "Retired loads that miss the L2 cache",
4669    "PublicDescription": "Retired loads that miss the L2 cache",
4670    "Counter": "0,1",
4671    "SampleAfterValue": "10000",
4672    "MSRIndex": "0",
4673    "MSRValue": "0",
4674    "CounterMask": "0",
4675    "Invert": "0",
4676    "AnyThread": "0",
4677    "EdgeDetect": "0",
4678    "PEBS": "0",
4679    "Errata": "null",
4680    "Offcore": "0"
4681  },
4682  {
4683    "EventCode": "0xCB",
4684    "UMask": "0x4",
4685    "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
4686    "BriefDescription": "Retired loads that miss the DTLB (precise event).",
4687    "PublicDescription": "Retired loads that miss the DTLB (precise event).",
4688    "Counter": "0,1",
4689    "SampleAfterValue": "200000",
4690    "MSRIndex": "0",
4691    "MSRValue": "0",
4692    "CounterMask": "0",
4693    "Invert": "0",
4694    "AnyThread": "0",
4695    "EdgeDetect": "0",
4696    "PEBS": "1",
4697    "Errata": "null",
4698    "Offcore": "0"
4699  },
4700  {
4701    "EventCode": "0xCD",
4702    "UMask": "0x0",
4703    "EventName": "SIMD_ASSIST",
4704    "BriefDescription": "SIMD assists invoked.",
4705    "PublicDescription": "SIMD assists invoked.",
4706    "Counter": "0,1",
4707    "SampleAfterValue": "100000",
4708    "MSRIndex": "0",
4709    "MSRValue": "0",
4710    "CounterMask": "0",
4711    "Invert": "0",
4712    "AnyThread": "0",
4713    "EdgeDetect": "0",
4714    "PEBS": "0",
4715    "Errata": "null",
4716    "Offcore": "0"
4717  },
4718  {
4719    "EventCode": "0xCE",
4720    "UMask": "0x0",
4721    "EventName": "SIMD_INSTR_RETIRED",
4722    "BriefDescription": "SIMD Instructions retired.",
4723    "PublicDescription": "SIMD Instructions retired.",
4724    "Counter": "0,1",
4725    "SampleAfterValue": "2000000",
4726    "MSRIndex": "0",
4727    "MSRValue": "0",
4728    "CounterMask": "0",
4729    "Invert": "0",
4730    "AnyThread": "0",
4731    "EdgeDetect": "0",
4732    "PEBS": "0",
4733    "Errata": "null",
4734    "Offcore": "0"
4735  },
4736  {
4737    "EventCode": "0xCF",
4738    "UMask": "0x0",
4739    "EventName": "SIMD_SAT_INSTR_RETIRED",
4740    "BriefDescription": "Saturated arithmetic instructions retired.",
4741    "PublicDescription": "Saturated arithmetic instructions retired.",
4742    "Counter": "0,1",
4743    "SampleAfterValue": "2000000",
4744    "MSRIndex": "0",
4745    "MSRValue": "0",
4746    "CounterMask": "0",
4747    "Invert": "0",
4748    "AnyThread": "0",
4749    "EdgeDetect": "0",
4750    "PEBS": "0",
4751    "Errata": "null",
4752    "Offcore": "0"
4753  },
4754  {
4755    "EventCode": "0xDC",
4756    "UMask": "0x2",
4757    "EventName": "RESOURCE_STALLS.DIV_BUSY",
4758    "BriefDescription": "Cycles issue is stalled due to div busy.",
4759    "PublicDescription": "Cycles issue is stalled due to div busy.",
4760    "Counter": "0,1",
4761    "SampleAfterValue": "2000000",
4762    "MSRIndex": "0",
4763    "MSRValue": "0",
4764    "CounterMask": "0",
4765    "Invert": "0",
4766    "AnyThread": "0",
4767    "EdgeDetect": "0",
4768    "PEBS": "0",
4769    "Errata": "null",
4770    "Offcore": "0"
4771  },
4772  {
4773    "EventCode": "0xE0",
4774    "UMask": "0x1",
4775    "EventName": "BR_INST_DECODED",
4776    "BriefDescription": "Branch instructions decoded",
4777    "PublicDescription": "Branch instructions decoded",
4778    "Counter": "0,1",
4779    "SampleAfterValue": "2000000",
4780    "MSRIndex": "0",
4781    "MSRValue": "0",
4782    "CounterMask": "0",
4783    "Invert": "0",
4784    "AnyThread": "0",
4785    "EdgeDetect": "0",
4786    "PEBS": "0",
4787    "Errata": "null",
4788    "Offcore": "0"
4789  },
4790  {
4791    "EventCode": "0xE4",
4792    "UMask": "0x1",
4793    "EventName": "BOGUS_BR",
4794    "BriefDescription": "Bogus branches",
4795    "PublicDescription": "Bogus branches",
4796    "Counter": "0,1",
4797    "SampleAfterValue": "2000000",
4798    "MSRIndex": "0",
4799    "MSRValue": "0",
4800    "CounterMask": "0",
4801    "Invert": "0",
4802    "AnyThread": "0",
4803    "EdgeDetect": "0",
4804    "PEBS": "0",
4805    "Errata": "null",
4806    "Offcore": "0"
4807  },
4808  {
4809    "EventCode": "0xE6",
4810    "UMask": "0x1",
4811    "EventName": "BACLEARS.ANY",
4812    "BriefDescription": "BACLEARS asserted.",
4813    "PublicDescription": "BACLEARS asserted.",
4814    "Counter": "0,1",
4815    "SampleAfterValue": "2000000",
4816    "MSRIndex": "0",
4817    "MSRValue": "0",
4818    "CounterMask": "0",
4819    "Invert": "0",
4820    "AnyThread": "0",
4821    "EdgeDetect": "0",
4822    "PEBS": "0",
4823    "Errata": "null",
4824    "Offcore": "0"
4825  },
4826  {
4827    "EventCode": "0x3",
4828    "UMask": "0x1",
4829    "EventName": "REISSUE.OVERLAP_STORE",
4830    "BriefDescription": "Micro-op reissues on a store-load collision",
4831    "PublicDescription": "Micro-op reissues on a store-load collision",
4832    "Counter": "0,1",
4833    "SampleAfterValue": "200000",
4834    "MSRIndex": "0",
4835    "MSRValue": "0",
4836    "CounterMask": "0",
4837    "Invert": "0",
4838    "AnyThread": "0",
4839    "EdgeDetect": "0",
4840    "PEBS": "0",
4841    "Errata": "null",
4842    "Offcore": "0"
4843  },
4844  {
4845    "EventCode": "0x3",
4846    "UMask": "0x81",
4847    "EventName": "REISSUE.OVERLAP_STORE.AR",
4848    "BriefDescription": "Micro-op reissues on a store-load collision (At Retirement)",
4849    "PublicDescription": "Micro-op reissues on a store-load collision (At Retirement)",
4850    "Counter": "0,1",
4851    "SampleAfterValue": "200000",
4852    "MSRIndex": "0",
4853    "MSRValue": "0",
4854    "CounterMask": "0",
4855    "Invert": "0",
4856    "AnyThread": "0",
4857    "EdgeDetect": "0",
4858    "PEBS": "0",
4859    "Errata": "null",
4860    "Offcore": "0"
4861  }
4862]