1bf21cd93STycho Nightingale /*- 24c87aefeSPatrick Mooney * SPDX-License-Identifier: BSD-3-Clause 34c87aefeSPatrick Mooney * 4bf21cd93STycho Nightingale * Copyright (c) 1991 The Regents of the University of California. 5bf21cd93STycho Nightingale * All rights reserved. 6bf21cd93STycho Nightingale * 7bf21cd93STycho Nightingale * Redistribution and use in source and binary forms, with or without 8bf21cd93STycho Nightingale * modification, are permitted provided that the following conditions 9bf21cd93STycho Nightingale * are met: 10bf21cd93STycho Nightingale * 1. Redistributions of source code must retain the above copyright 11bf21cd93STycho Nightingale * notice, this list of conditions and the following disclaimer. 12bf21cd93STycho Nightingale * 2. Redistributions in binary form must reproduce the above copyright 13bf21cd93STycho Nightingale * notice, this list of conditions and the following disclaimer in the 14bf21cd93STycho Nightingale * documentation and/or other materials provided with the distribution. 154c87aefeSPatrick Mooney * 3. Neither the name of the University nor the names of its contributors 16bf21cd93STycho Nightingale * may be used to endorse or promote products derived from this software 17bf21cd93STycho Nightingale * without specific prior written permission. 18bf21cd93STycho Nightingale * 19bf21cd93STycho Nightingale * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 20bf21cd93STycho Nightingale * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21bf21cd93STycho Nightingale * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22bf21cd93STycho Nightingale * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 23bf21cd93STycho Nightingale * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24bf21cd93STycho Nightingale * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25bf21cd93STycho Nightingale * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26bf21cd93STycho Nightingale * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27bf21cd93STycho Nightingale * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28bf21cd93STycho Nightingale * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29bf21cd93STycho Nightingale * SUCH DAMAGE. 30bf21cd93STycho Nightingale * 31bf21cd93STycho Nightingale * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 324c87aefeSPatrick Mooney * $FreeBSD$ 33bf21cd93STycho Nightingale */ 34bf21cd93STycho Nightingale 35bf21cd93STycho Nightingale #ifndef _MACHINE_SPECIALREG_H_ 36bf21cd93STycho Nightingale #define _MACHINE_SPECIALREG_H_ 37bf21cd93STycho Nightingale 38bf21cd93STycho Nightingale /* 39bf21cd93STycho Nightingale * Bits in 386 special registers: 40bf21cd93STycho Nightingale */ 41bf21cd93STycho Nightingale #define CR0_PE 0x00000001 /* Protected mode Enable */ 42bf21cd93STycho Nightingale #define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 43bf21cd93STycho Nightingale #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 44bf21cd93STycho Nightingale #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 45bf21cd93STycho Nightingale #define CR0_PG 0x80000000 /* PaGing enable */ 46bf21cd93STycho Nightingale 47bf21cd93STycho Nightingale /* 48bf21cd93STycho Nightingale * Bits in 486 special registers: 49bf21cd93STycho Nightingale */ 50bf21cd93STycho Nightingale #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 51bf21cd93STycho Nightingale #define CR0_WP 0x00010000 /* Write Protect (honor page protect in 52bf21cd93STycho Nightingale all modes) */ 53bf21cd93STycho Nightingale #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 54bf21cd93STycho Nightingale #define CR0_NW 0x20000000 /* Not Write-through */ 55bf21cd93STycho Nightingale #define CR0_CD 0x40000000 /* Cache Disable */ 56bf21cd93STycho Nightingale 57bf21cd93STycho Nightingale #define CR3_PCID_SAVE 0x8000000000000000 584c87aefeSPatrick Mooney #define CR3_PCID_MASK 0xfff 59bf21cd93STycho Nightingale 60bf21cd93STycho Nightingale /* 61bf21cd93STycho Nightingale * Bits in PPro special registers 62bf21cd93STycho Nightingale */ 63bf21cd93STycho Nightingale #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 64bf21cd93STycho Nightingale #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 65bf21cd93STycho Nightingale #define CR4_TSD 0x00000004 /* Time stamp disable */ 66bf21cd93STycho Nightingale #define CR4_DE 0x00000008 /* Debugging extensions */ 67bf21cd93STycho Nightingale #define CR4_PSE 0x00000010 /* Page size extensions */ 68bf21cd93STycho Nightingale #define CR4_PAE 0x00000020 /* Physical address extension */ 69bf21cd93STycho Nightingale #define CR4_MCE 0x00000040 /* Machine check enable */ 70bf21cd93STycho Nightingale #define CR4_PGE 0x00000080 /* Page global enable */ 71bf21cd93STycho Nightingale #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 72bf21cd93STycho Nightingale #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 73bf21cd93STycho Nightingale #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 7459d65d31SAndy Fiddaman #define CR4_UMIP 0x00000800 /* User Mode Instruction Prevention */ 7559d65d31SAndy Fiddaman #define CR4_LA57 0x00001000 /* Enable 5-level paging */ 76bf21cd93STycho Nightingale #define CR4_VMXE 0x00002000 /* enable VMX operation (Intel-specific) */ 77bf21cd93STycho Nightingale #define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE accessing instructions */ 78bf21cd93STycho Nightingale #define CR4_PCIDE 0x00020000 /* Enable Context ID */ 79bf21cd93STycho Nightingale #define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */ 80bf21cd93STycho Nightingale #define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevention */ 814c87aefeSPatrick Mooney #define CR4_SMAP 0x00200000 /* Supervisor-Mode Access Prevention */ 824c87aefeSPatrick Mooney #define CR4_PKE 0x00400000 /* Protection Keys Enable */ 83bf21cd93STycho Nightingale 84bf21cd93STycho Nightingale /* 85bf21cd93STycho Nightingale * Bits in AMD64 special registers. EFER is 64 bits wide. 86bf21cd93STycho Nightingale */ 87bf21cd93STycho Nightingale #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */ 88bf21cd93STycho Nightingale #define EFER_LME 0x000000100 /* Long mode enable (R/W) */ 89bf21cd93STycho Nightingale #define EFER_LMA 0x000000400 /* Long mode active (R) */ 90bf21cd93STycho Nightingale #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 91bf21cd93STycho Nightingale #define EFER_SVM 0x000001000 /* SVM enable bit for AMD, reserved for Intel */ 924c87aefeSPatrick Mooney #define EFER_LMSLE 0x000002000 /* Long Mode Segment Limit Enable */ 934c87aefeSPatrick Mooney #define EFER_FFXSR 0x000004000 /* Fast FXSAVE/FSRSTOR */ 944c87aefeSPatrick Mooney #define EFER_TCE 0x000008000 /* Translation Cache Extension */ 9559d65d31SAndy Fiddaman #define EFER_MCOMMIT 0x00020000 /* Enable MCOMMIT (AMD) */ 96bf21cd93STycho Nightingale 97bf21cd93STycho Nightingale /* 98bf21cd93STycho Nightingale * Intel Extended Features registers 99bf21cd93STycho Nightingale */ 100bf21cd93STycho Nightingale #define XCR0 0 /* XFEATURE_ENABLED_MASK register */ 101bf21cd93STycho Nightingale 102bf21cd93STycho Nightingale #define XFEATURE_ENABLED_X87 0x00000001 103bf21cd93STycho Nightingale #define XFEATURE_ENABLED_SSE 0x00000002 104bf21cd93STycho Nightingale #define XFEATURE_ENABLED_YMM_HI128 0x00000004 105bf21cd93STycho Nightingale #define XFEATURE_ENABLED_AVX XFEATURE_ENABLED_YMM_HI128 106bf21cd93STycho Nightingale #define XFEATURE_ENABLED_BNDREGS 0x00000008 107bf21cd93STycho Nightingale #define XFEATURE_ENABLED_BNDCSR 0x00000010 108bf21cd93STycho Nightingale #define XFEATURE_ENABLED_OPMASK 0x00000020 109bf21cd93STycho Nightingale #define XFEATURE_ENABLED_ZMM_HI256 0x00000040 110bf21cd93STycho Nightingale #define XFEATURE_ENABLED_HI16_ZMM 0x00000080 111bf21cd93STycho Nightingale 112bf21cd93STycho Nightingale #define XFEATURE_AVX \ 113bf21cd93STycho Nightingale (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX) 114bf21cd93STycho Nightingale #define XFEATURE_AVX512 \ 115bf21cd93STycho Nightingale (XFEATURE_ENABLED_OPMASK | XFEATURE_ENABLED_ZMM_HI256 | \ 116bf21cd93STycho Nightingale XFEATURE_ENABLED_HI16_ZMM) 117bf21cd93STycho Nightingale #define XFEATURE_MPX \ 118bf21cd93STycho Nightingale (XFEATURE_ENABLED_BNDREGS | XFEATURE_ENABLED_BNDCSR) 119bf21cd93STycho Nightingale 120bf21cd93STycho Nightingale /* 121bf21cd93STycho Nightingale * CPUID instruction features register 122bf21cd93STycho Nightingale */ 123bf21cd93STycho Nightingale #define CPUID_FPU 0x00000001 124bf21cd93STycho Nightingale #define CPUID_VME 0x00000002 125bf21cd93STycho Nightingale #define CPUID_DE 0x00000004 126bf21cd93STycho Nightingale #define CPUID_PSE 0x00000008 127bf21cd93STycho Nightingale #define CPUID_TSC 0x00000010 128bf21cd93STycho Nightingale #define CPUID_MSR 0x00000020 129bf21cd93STycho Nightingale #define CPUID_PAE 0x00000040 130bf21cd93STycho Nightingale #define CPUID_MCE 0x00000080 131bf21cd93STycho Nightingale #define CPUID_CX8 0x00000100 132bf21cd93STycho Nightingale #define CPUID_APIC 0x00000200 133bf21cd93STycho Nightingale #define CPUID_B10 0x00000400 134bf21cd93STycho Nightingale #define CPUID_SEP 0x00000800 135bf21cd93STycho Nightingale #define CPUID_MTRR 0x00001000 136bf21cd93STycho Nightingale #define CPUID_PGE 0x00002000 137bf21cd93STycho Nightingale #define CPUID_MCA 0x00004000 138bf21cd93STycho Nightingale #define CPUID_CMOV 0x00008000 139bf21cd93STycho Nightingale #define CPUID_PAT 0x00010000 140bf21cd93STycho Nightingale #define CPUID_PSE36 0x00020000 141bf21cd93STycho Nightingale #define CPUID_PSN 0x00040000 142bf21cd93STycho Nightingale #define CPUID_CLFSH 0x00080000 143bf21cd93STycho Nightingale #define CPUID_B20 0x00100000 144bf21cd93STycho Nightingale #define CPUID_DS 0x00200000 145bf21cd93STycho Nightingale #define CPUID_ACPI 0x00400000 146bf21cd93STycho Nightingale #define CPUID_MMX 0x00800000 147bf21cd93STycho Nightingale #define CPUID_FXSR 0x01000000 148bf21cd93STycho Nightingale #define CPUID_SSE 0x02000000 149bf21cd93STycho Nightingale #define CPUID_XMM 0x02000000 150bf21cd93STycho Nightingale #define CPUID_SSE2 0x04000000 151bf21cd93STycho Nightingale #define CPUID_SS 0x08000000 152bf21cd93STycho Nightingale #define CPUID_HTT 0x10000000 153bf21cd93STycho Nightingale #define CPUID_TM 0x20000000 154bf21cd93STycho Nightingale #define CPUID_IA64 0x40000000 155bf21cd93STycho Nightingale #define CPUID_PBE 0x80000000 156bf21cd93STycho Nightingale 157bf21cd93STycho Nightingale #define CPUID2_SSE3 0x00000001 158bf21cd93STycho Nightingale #define CPUID2_PCLMULQDQ 0x00000002 159bf21cd93STycho Nightingale #define CPUID2_DTES64 0x00000004 160bf21cd93STycho Nightingale #define CPUID2_MON 0x00000008 161bf21cd93STycho Nightingale #define CPUID2_DS_CPL 0x00000010 162bf21cd93STycho Nightingale #define CPUID2_VMX 0x00000020 163bf21cd93STycho Nightingale #define CPUID2_SMX 0x00000040 164bf21cd93STycho Nightingale #define CPUID2_EST 0x00000080 165bf21cd93STycho Nightingale #define CPUID2_TM2 0x00000100 166bf21cd93STycho Nightingale #define CPUID2_SSSE3 0x00000200 167bf21cd93STycho Nightingale #define CPUID2_CNXTID 0x00000400 1684c87aefeSPatrick Mooney #define CPUID2_SDBG 0x00000800 169bf21cd93STycho Nightingale #define CPUID2_FMA 0x00001000 170bf21cd93STycho Nightingale #define CPUID2_CX16 0x00002000 171bf21cd93STycho Nightingale #define CPUID2_XTPR 0x00004000 172bf21cd93STycho Nightingale #define CPUID2_PDCM 0x00008000 173bf21cd93STycho Nightingale #define CPUID2_PCID 0x00020000 174bf21cd93STycho Nightingale #define CPUID2_DCA 0x00040000 175bf21cd93STycho Nightingale #define CPUID2_SSE41 0x00080000 176bf21cd93STycho Nightingale #define CPUID2_SSE42 0x00100000 177bf21cd93STycho Nightingale #define CPUID2_X2APIC 0x00200000 178bf21cd93STycho Nightingale #define CPUID2_MOVBE 0x00400000 179bf21cd93STycho Nightingale #define CPUID2_POPCNT 0x00800000 180bf21cd93STycho Nightingale #define CPUID2_TSCDLT 0x01000000 181bf21cd93STycho Nightingale #define CPUID2_AESNI 0x02000000 182bf21cd93STycho Nightingale #define CPUID2_XSAVE 0x04000000 183bf21cd93STycho Nightingale #define CPUID2_OSXSAVE 0x08000000 184bf21cd93STycho Nightingale #define CPUID2_AVX 0x10000000 185bf21cd93STycho Nightingale #define CPUID2_F16C 0x20000000 186bf21cd93STycho Nightingale #define CPUID2_RDRAND 0x40000000 187bf21cd93STycho Nightingale #define CPUID2_HV 0x80000000 188bf21cd93STycho Nightingale 1894c87aefeSPatrick Mooney /* Intel Processor Trace CPUID. */ 1904c87aefeSPatrick Mooney 1914c87aefeSPatrick Mooney /* Leaf 0 ebx. */ 1924c87aefeSPatrick Mooney #define CPUPT_CR3 (1 << 0) /* CR3 Filtering Support */ 1934c87aefeSPatrick Mooney #define CPUPT_PSB (1 << 1) /* Configurable PSB and Cycle-Accurate Mode Supported */ 1944c87aefeSPatrick Mooney #define CPUPT_IPF (1 << 2) /* IP Filtering and TraceStop supported */ 1954c87aefeSPatrick Mooney #define CPUPT_MTC (1 << 3) /* MTC Supported */ 1964c87aefeSPatrick Mooney #define CPUPT_PRW (1 << 4) /* PTWRITE Supported */ 1974c87aefeSPatrick Mooney #define CPUPT_PWR (1 << 5) /* Power Event Trace Supported */ 1984c87aefeSPatrick Mooney 1994c87aefeSPatrick Mooney /* Leaf 0 ecx. */ 2004c87aefeSPatrick Mooney #define CPUPT_TOPA (1 << 0) /* ToPA Output Supported */ 2014c87aefeSPatrick Mooney #define CPUPT_TOPA_MULTI (1 << 1) /* ToPA Tables Allow Multiple Output Entries */ 2024c87aefeSPatrick Mooney #define CPUPT_SINGLE (1 << 2) /* Single-Range Output Supported */ 2034c87aefeSPatrick Mooney #define CPUPT_TT_OUT (1 << 3) /* Output to Trace Transport Subsystem Supported */ 2044c87aefeSPatrick Mooney #define CPUPT_LINEAR_IP (1 << 31) /* IP Payloads are Linear IP, otherwise IP is effective */ 2054c87aefeSPatrick Mooney 2064c87aefeSPatrick Mooney /* Leaf 1 eax. */ 2074c87aefeSPatrick Mooney #define CPUPT_NADDR_S 0 /* Number of Address Ranges */ 2084c87aefeSPatrick Mooney #define CPUPT_NADDR_M (0x7 << CPUPT_NADDR_S) 2094c87aefeSPatrick Mooney #define CPUPT_MTC_BITMAP_S 16 /* Bitmap of supported MTC Period Encodings */ 2104c87aefeSPatrick Mooney #define CPUPT_MTC_BITMAP_M (0xffff << CPUPT_MTC_BITMAP_S) 2114c87aefeSPatrick Mooney 2124c87aefeSPatrick Mooney /* Leaf 1 ebx. */ 2134c87aefeSPatrick Mooney #define CPUPT_CT_BITMAP_S 0 /* Bitmap of supported Cycle Threshold values */ 2144c87aefeSPatrick Mooney #define CPUPT_CT_BITMAP_M (0xffff << CPUPT_CT_BITMAP_S) 2154c87aefeSPatrick Mooney #define CPUPT_PFE_BITMAP_S 16 /* Bitmap of supported Configurable PSB Frequency encoding */ 2164c87aefeSPatrick Mooney #define CPUPT_PFE_BITMAP_M (0xffff << CPUPT_PFE_BITMAP_S) 2174c87aefeSPatrick Mooney 218bf21cd93STycho Nightingale /* 219bf21cd93STycho Nightingale * Important bits in the AMD extended cpuid flags 220bf21cd93STycho Nightingale */ 221bf21cd93STycho Nightingale #define AMDID_SYSCALL 0x00000800 222bf21cd93STycho Nightingale #define AMDID_MP 0x00080000 223bf21cd93STycho Nightingale #define AMDID_NX 0x00100000 224bf21cd93STycho Nightingale #define AMDID_EXT_MMX 0x00400000 2254c87aefeSPatrick Mooney #define AMDID_FFXSR 0x02000000 226bf21cd93STycho Nightingale #define AMDID_PAGE1GB 0x04000000 227bf21cd93STycho Nightingale #define AMDID_RDTSCP 0x08000000 228bf21cd93STycho Nightingale #define AMDID_LM 0x20000000 229bf21cd93STycho Nightingale #define AMDID_EXT_3DNOW 0x40000000 230bf21cd93STycho Nightingale #define AMDID_3DNOW 0x80000000 231bf21cd93STycho Nightingale 232bf21cd93STycho Nightingale #define AMDID2_LAHF 0x00000001 233bf21cd93STycho Nightingale #define AMDID2_CMP 0x00000002 234bf21cd93STycho Nightingale #define AMDID2_SVM 0x00000004 235bf21cd93STycho Nightingale #define AMDID2_EXT_APIC 0x00000008 236bf21cd93STycho Nightingale #define AMDID2_CR8 0x00000010 237bf21cd93STycho Nightingale #define AMDID2_ABM 0x00000020 238bf21cd93STycho Nightingale #define AMDID2_SSE4A 0x00000040 239bf21cd93STycho Nightingale #define AMDID2_MAS 0x00000080 240bf21cd93STycho Nightingale #define AMDID2_PREFETCH 0x00000100 241bf21cd93STycho Nightingale #define AMDID2_OSVW 0x00000200 242bf21cd93STycho Nightingale #define AMDID2_IBS 0x00000400 243bf21cd93STycho Nightingale #define AMDID2_XOP 0x00000800 244bf21cd93STycho Nightingale #define AMDID2_SKINIT 0x00001000 245bf21cd93STycho Nightingale #define AMDID2_WDT 0x00002000 246bf21cd93STycho Nightingale #define AMDID2_LWP 0x00008000 247bf21cd93STycho Nightingale #define AMDID2_FMA4 0x00010000 248bf21cd93STycho Nightingale #define AMDID2_TCE 0x00020000 249bf21cd93STycho Nightingale #define AMDID2_NODE_ID 0x00080000 250bf21cd93STycho Nightingale #define AMDID2_TBM 0x00200000 251bf21cd93STycho Nightingale #define AMDID2_TOPOLOGY 0x00400000 252bf21cd93STycho Nightingale #define AMDID2_PCXC 0x00800000 253bf21cd93STycho Nightingale #define AMDID2_PNXC 0x01000000 254bf21cd93STycho Nightingale #define AMDID2_DBE 0x04000000 255bf21cd93STycho Nightingale #define AMDID2_PTSC 0x08000000 256bf21cd93STycho Nightingale #define AMDID2_PTSCEL2I 0x10000000 2574c87aefeSPatrick Mooney #define AMDID2_MWAITX 0x20000000 258bf21cd93STycho Nightingale 259bf21cd93STycho Nightingale /* 260bf21cd93STycho Nightingale * CPUID instruction 1 eax info 261bf21cd93STycho Nightingale */ 262bf21cd93STycho Nightingale #define CPUID_STEPPING 0x0000000f 263bf21cd93STycho Nightingale #define CPUID_MODEL 0x000000f0 264bf21cd93STycho Nightingale #define CPUID_FAMILY 0x00000f00 265bf21cd93STycho Nightingale #define CPUID_EXT_MODEL 0x000f0000 266bf21cd93STycho Nightingale #define CPUID_EXT_FAMILY 0x0ff00000 267bf21cd93STycho Nightingale #ifdef __i386__ 268bf21cd93STycho Nightingale #define CPUID_TO_MODEL(id) \ 269bf21cd93STycho Nightingale ((((id) & CPUID_MODEL) >> 4) | \ 270bf21cd93STycho Nightingale ((((id) & CPUID_FAMILY) >= 0x600) ? \ 271bf21cd93STycho Nightingale (((id) & CPUID_EXT_MODEL) >> 12) : 0)) 272bf21cd93STycho Nightingale #define CPUID_TO_FAMILY(id) \ 273bf21cd93STycho Nightingale ((((id) & CPUID_FAMILY) >> 8) + \ 274bf21cd93STycho Nightingale ((((id) & CPUID_FAMILY) == 0xf00) ? \ 275bf21cd93STycho Nightingale (((id) & CPUID_EXT_FAMILY) >> 20) : 0)) 276bf21cd93STycho Nightingale #else 277bf21cd93STycho Nightingale #define CPUID_TO_MODEL(id) \ 278bf21cd93STycho Nightingale ((((id) & CPUID_MODEL) >> 4) | \ 279bf21cd93STycho Nightingale (((id) & CPUID_EXT_MODEL) >> 12)) 280bf21cd93STycho Nightingale #define CPUID_TO_FAMILY(id) \ 281bf21cd93STycho Nightingale ((((id) & CPUID_FAMILY) >> 8) + \ 282bf21cd93STycho Nightingale (((id) & CPUID_EXT_FAMILY) >> 20)) 283bf21cd93STycho Nightingale #endif 28459d65d31SAndy Fiddaman #define CPUID_TO_STEPPING(id) ((id) & CPUID_STEPPING) 285bf21cd93STycho Nightingale 286bf21cd93STycho Nightingale /* 287bf21cd93STycho Nightingale * CPUID instruction 1 ebx info 288bf21cd93STycho Nightingale */ 289bf21cd93STycho Nightingale #define CPUID_BRAND_INDEX 0x000000ff 290bf21cd93STycho Nightingale #define CPUID_CLFUSH_SIZE 0x0000ff00 291bf21cd93STycho Nightingale #define CPUID_HTT_CORES 0x00ff0000 292bf21cd93STycho Nightingale #define CPUID_LOCAL_APIC_ID 0xff000000 293bf21cd93STycho Nightingale 294bf21cd93STycho Nightingale /* 295bf21cd93STycho Nightingale * CPUID instruction 5 info 296bf21cd93STycho Nightingale */ 297bf21cd93STycho Nightingale #define CPUID5_MON_MIN_SIZE 0x0000ffff /* eax */ 298bf21cd93STycho Nightingale #define CPUID5_MON_MAX_SIZE 0x0000ffff /* ebx */ 299bf21cd93STycho Nightingale #define CPUID5_MON_MWAIT_EXT 0x00000001 /* ecx */ 300bf21cd93STycho Nightingale #define CPUID5_MWAIT_INTRBREAK 0x00000002 /* ecx */ 301bf21cd93STycho Nightingale 302bf21cd93STycho Nightingale /* 303bf21cd93STycho Nightingale * MWAIT cpu power states. Lower 4 bits are sub-states. 304bf21cd93STycho Nightingale */ 305bf21cd93STycho Nightingale #define MWAIT_C0 0xf0 306bf21cd93STycho Nightingale #define MWAIT_C1 0x00 307bf21cd93STycho Nightingale #define MWAIT_C2 0x10 308bf21cd93STycho Nightingale #define MWAIT_C3 0x20 309bf21cd93STycho Nightingale #define MWAIT_C4 0x30 310bf21cd93STycho Nightingale 311bf21cd93STycho Nightingale /* 312bf21cd93STycho Nightingale * MWAIT extensions. 313bf21cd93STycho Nightingale */ 314bf21cd93STycho Nightingale /* Interrupt breaks MWAIT even when masked. */ 315bf21cd93STycho Nightingale #define MWAIT_INTRBREAK 0x00000001 316bf21cd93STycho Nightingale 317bf21cd93STycho Nightingale /* 31859d65d31SAndy Fiddaman * CPUID leaf 6: Thermal and Power management. 319bf21cd93STycho Nightingale */ 32059d65d31SAndy Fiddaman /* Eax. */ 32159d65d31SAndy Fiddaman #define CPUTPM1_SENSOR 0x00000001 32259d65d31SAndy Fiddaman #define CPUTPM1_TURBO 0x00000002 32359d65d31SAndy Fiddaman #define CPUTPM1_ARAT 0x00000004 32459d65d31SAndy Fiddaman #define CPUTPM1_PLN 0x00000010 32559d65d31SAndy Fiddaman #define CPUTPM1_ECMD 0x00000020 32659d65d31SAndy Fiddaman #define CPUTPM1_PTM 0x00000040 32759d65d31SAndy Fiddaman #define CPUTPM1_HWP 0x00000080 32859d65d31SAndy Fiddaman #define CPUTPM1_HWP_NOTIFICATION 0x00000100 32959d65d31SAndy Fiddaman #define CPUTPM1_HWP_ACTIVITY_WINDOW 0x00000200 33059d65d31SAndy Fiddaman #define CPUTPM1_HWP_PERF_PREF 0x00000400 33159d65d31SAndy Fiddaman #define CPUTPM1_HWP_PKG 0x00000800 33259d65d31SAndy Fiddaman #define CPUTPM1_HDC 0x00002000 33359d65d31SAndy Fiddaman #define CPUTPM1_TURBO30 0x00004000 33459d65d31SAndy Fiddaman #define CPUTPM1_HWP_CAPABILITIES 0x00008000 33559d65d31SAndy Fiddaman #define CPUTPM1_HWP_PECI_OVR 0x00010000 33659d65d31SAndy Fiddaman #define CPUTPM1_HWP_FLEXIBLE 0x00020000 33759d65d31SAndy Fiddaman #define CPUTPM1_HWP_FAST_MSR 0x00040000 33859d65d31SAndy Fiddaman #define CPUTPM1_HWP_IGN_IDLE 0x00100000 33959d65d31SAndy Fiddaman 34059d65d31SAndy Fiddaman /* Ebx. */ 34159d65d31SAndy Fiddaman #define CPUTPM_B_NSENSINTTHRESH 0x0000000f 34259d65d31SAndy Fiddaman 34359d65d31SAndy Fiddaman /* Ecx. */ 34459d65d31SAndy Fiddaman #define CPUID_PERF_STAT 0x00000001 34559d65d31SAndy Fiddaman #define CPUID_PERF_BIAS 0x00000008 346bf21cd93STycho Nightingale 347bf21cd93STycho Nightingale /* 348bf21cd93STycho Nightingale * CPUID instruction 0xb ebx info. 349bf21cd93STycho Nightingale */ 350bf21cd93STycho Nightingale #define CPUID_TYPE_INVAL 0 351bf21cd93STycho Nightingale #define CPUID_TYPE_SMT 1 352bf21cd93STycho Nightingale #define CPUID_TYPE_CORE 2 353bf21cd93STycho Nightingale 354bf21cd93STycho Nightingale /* 355bf21cd93STycho Nightingale * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1 356bf21cd93STycho Nightingale */ 357bf21cd93STycho Nightingale #define CPUID_EXTSTATE_XSAVEOPT 0x00000001 358bf21cd93STycho Nightingale #define CPUID_EXTSTATE_XSAVEC 0x00000002 359bf21cd93STycho Nightingale #define CPUID_EXTSTATE_XINUSE 0x00000004 360bf21cd93STycho Nightingale #define CPUID_EXTSTATE_XSAVES 0x00000008 361bf21cd93STycho Nightingale 3624c87aefeSPatrick Mooney /* 3634c87aefeSPatrick Mooney * AMD extended function 8000_0007h ebx info 3644c87aefeSPatrick Mooney */ 3654c87aefeSPatrick Mooney #define AMDRAS_MCA_OF_RECOV 0x00000001 3664c87aefeSPatrick Mooney #define AMDRAS_SUCCOR 0x00000002 3674c87aefeSPatrick Mooney #define AMDRAS_HW_ASSERT 0x00000004 3684c87aefeSPatrick Mooney #define AMDRAS_SCALABLE_MCA 0x00000008 3694c87aefeSPatrick Mooney #define AMDRAS_PFEH_SUPPORT 0x00000010 3704c87aefeSPatrick Mooney 371bf21cd93STycho Nightingale /* 372bf21cd93STycho Nightingale * AMD extended function 8000_0007h edx info 373bf21cd93STycho Nightingale */ 374bf21cd93STycho Nightingale #define AMDPM_TS 0x00000001 375bf21cd93STycho Nightingale #define AMDPM_FID 0x00000002 376bf21cd93STycho Nightingale #define AMDPM_VID 0x00000004 377bf21cd93STycho Nightingale #define AMDPM_TTP 0x00000008 378bf21cd93STycho Nightingale #define AMDPM_TM 0x00000010 379bf21cd93STycho Nightingale #define AMDPM_STC 0x00000020 380bf21cd93STycho Nightingale #define AMDPM_100MHZ_STEPS 0x00000040 381bf21cd93STycho Nightingale #define AMDPM_HW_PSTATE 0x00000080 382bf21cd93STycho Nightingale #define AMDPM_TSC_INVARIANT 0x00000100 383bf21cd93STycho Nightingale #define AMDPM_CPB 0x00000200 384bf21cd93STycho Nightingale 3854c87aefeSPatrick Mooney /* 3864c87aefeSPatrick Mooney * AMD extended function 8000_0008h ebx info (amd_extended_feature_extensions) 3874c87aefeSPatrick Mooney */ 3884c87aefeSPatrick Mooney #define AMDFEID_CLZERO 0x00000001 3894c87aefeSPatrick Mooney #define AMDFEID_IRPERF 0x00000002 3904c87aefeSPatrick Mooney #define AMDFEID_XSAVEERPTR 0x00000004 39159d65d31SAndy Fiddaman #define AMDFEID_RDPRU 0x00000010 39259d65d31SAndy Fiddaman #define AMDFEID_MCOMMIT 0x00000100 39359d65d31SAndy Fiddaman #define AMDFEID_WBNOINVD 0x00000200 3944c87aefeSPatrick Mooney #define AMDFEID_IBPB 0x00001000 3954c87aefeSPatrick Mooney #define AMDFEID_IBRS 0x00004000 3964c87aefeSPatrick Mooney #define AMDFEID_STIBP 0x00008000 3974c87aefeSPatrick Mooney /* The below are only defined if the corresponding base feature above exists. */ 3984c87aefeSPatrick Mooney #define AMDFEID_IBRS_ALWAYSON 0x00010000 3994c87aefeSPatrick Mooney #define AMDFEID_STIBP_ALWAYSON 0x00020000 4004c87aefeSPatrick Mooney #define AMDFEID_PREFER_IBRS 0x00040000 40159d65d31SAndy Fiddaman #define AMDFEID_PPIN 0x00800000 4024c87aefeSPatrick Mooney #define AMDFEID_SSBD 0x01000000 4034c87aefeSPatrick Mooney /* SSBD via MSRC001_011F instead of MSR 0x48: */ 4044c87aefeSPatrick Mooney #define AMDFEID_VIRT_SSBD 0x02000000 4054c87aefeSPatrick Mooney #define AMDFEID_SSB_NO 0x04000000 4064c87aefeSPatrick Mooney 407bf21cd93STycho Nightingale /* 408bf21cd93STycho Nightingale * AMD extended function 8000_0008h ecx info 409bf21cd93STycho Nightingale */ 410bf21cd93STycho Nightingale #define AMDID_CMP_CORES 0x000000ff 411bf21cd93STycho Nightingale #define AMDID_COREID_SIZE 0x0000f000 412bf21cd93STycho Nightingale #define AMDID_COREID_SIZE_SHIFT 12 413bf21cd93STycho Nightingale 414bf21cd93STycho Nightingale /* 415bf21cd93STycho Nightingale * CPUID instruction 7 Structured Extended Features, leaf 0 ebx info 416bf21cd93STycho Nightingale */ 417bf21cd93STycho Nightingale #define CPUID_STDEXT_FSGSBASE 0x00000001 418bf21cd93STycho Nightingale #define CPUID_STDEXT_TSC_ADJUST 0x00000002 4194c87aefeSPatrick Mooney #define CPUID_STDEXT_SGX 0x00000004 420bf21cd93STycho Nightingale #define CPUID_STDEXT_BMI1 0x00000008 421bf21cd93STycho Nightingale #define CPUID_STDEXT_HLE 0x00000010 422bf21cd93STycho Nightingale #define CPUID_STDEXT_AVX2 0x00000020 4234c87aefeSPatrick Mooney #define CPUID_STDEXT_FDP_EXC 0x00000040 424bf21cd93STycho Nightingale #define CPUID_STDEXT_SMEP 0x00000080 425bf21cd93STycho Nightingale #define CPUID_STDEXT_BMI2 0x00000100 426bf21cd93STycho Nightingale #define CPUID_STDEXT_ERMS 0x00000200 427bf21cd93STycho Nightingale #define CPUID_STDEXT_INVPCID 0x00000400 428bf21cd93STycho Nightingale #define CPUID_STDEXT_RTM 0x00000800 4294c87aefeSPatrick Mooney #define CPUID_STDEXT_PQM 0x00001000 4304c87aefeSPatrick Mooney #define CPUID_STDEXT_NFPUSG 0x00002000 431bf21cd93STycho Nightingale #define CPUID_STDEXT_MPX 0x00004000 4324c87aefeSPatrick Mooney #define CPUID_STDEXT_PQE 0x00008000 433bf21cd93STycho Nightingale #define CPUID_STDEXT_AVX512F 0x00010000 4344c87aefeSPatrick Mooney #define CPUID_STDEXT_AVX512DQ 0x00020000 435bf21cd93STycho Nightingale #define CPUID_STDEXT_RDSEED 0x00040000 436bf21cd93STycho Nightingale #define CPUID_STDEXT_ADX 0x00080000 437bf21cd93STycho Nightingale #define CPUID_STDEXT_SMAP 0x00100000 4384c87aefeSPatrick Mooney #define CPUID_STDEXT_AVX512IFMA 0x00200000 43959d65d31SAndy Fiddaman /* Formerly PCOMMIT */ 440bf21cd93STycho Nightingale #define CPUID_STDEXT_CLFLUSHOPT 0x00800000 4414c87aefeSPatrick Mooney #define CPUID_STDEXT_CLWB 0x01000000 442bf21cd93STycho Nightingale #define CPUID_STDEXT_PROCTRACE 0x02000000 443bf21cd93STycho Nightingale #define CPUID_STDEXT_AVX512PF 0x04000000 444bf21cd93STycho Nightingale #define CPUID_STDEXT_AVX512ER 0x08000000 445bf21cd93STycho Nightingale #define CPUID_STDEXT_AVX512CD 0x10000000 446bf21cd93STycho Nightingale #define CPUID_STDEXT_SHA 0x20000000 4474c87aefeSPatrick Mooney #define CPUID_STDEXT_AVX512BW 0x40000000 4484c87aefeSPatrick Mooney #define CPUID_STDEXT_AVX512VL 0x80000000 4494c87aefeSPatrick Mooney 4504c87aefeSPatrick Mooney /* 4514c87aefeSPatrick Mooney * CPUID instruction 7 Structured Extended Features, leaf 0 ecx info 4524c87aefeSPatrick Mooney */ 4534c87aefeSPatrick Mooney #define CPUID_STDEXT2_PREFETCHWT1 0x00000001 4544c87aefeSPatrick Mooney #define CPUID_STDEXT2_AVX512VBMI 0x00000002 4554c87aefeSPatrick Mooney #define CPUID_STDEXT2_UMIP 0x00000004 4564c87aefeSPatrick Mooney #define CPUID_STDEXT2_PKU 0x00000008 4574c87aefeSPatrick Mooney #define CPUID_STDEXT2_OSPKE 0x00000010 4584c87aefeSPatrick Mooney #define CPUID_STDEXT2_WAITPKG 0x00000020 4594c87aefeSPatrick Mooney #define CPUID_STDEXT2_AVX512VBMI2 0x00000040 4604c87aefeSPatrick Mooney #define CPUID_STDEXT2_GFNI 0x00000100 4614c87aefeSPatrick Mooney #define CPUID_STDEXT2_VAES 0x00000200 4624c87aefeSPatrick Mooney #define CPUID_STDEXT2_VPCLMULQDQ 0x00000400 4634c87aefeSPatrick Mooney #define CPUID_STDEXT2_AVX512VNNI 0x00000800 4644c87aefeSPatrick Mooney #define CPUID_STDEXT2_AVX512BITALG 0x00001000 46559d65d31SAndy Fiddaman #define CPUID_STDEXT2_TME 0x00002000 4664c87aefeSPatrick Mooney #define CPUID_STDEXT2_AVX512VPOPCNTDQ 0x00004000 46759d65d31SAndy Fiddaman #define CPUID_STDEXT2_LA57 0x00010000 4684c87aefeSPatrick Mooney #define CPUID_STDEXT2_RDPID 0x00400000 4694c87aefeSPatrick Mooney #define CPUID_STDEXT2_CLDEMOTE 0x02000000 4704c87aefeSPatrick Mooney #define CPUID_STDEXT2_MOVDIRI 0x08000000 47159d65d31SAndy Fiddaman #define CPUID_STDEXT2_MOVDIR64B 0x10000000 4724c87aefeSPatrick Mooney #define CPUID_STDEXT2_ENQCMD 0x20000000 4734c87aefeSPatrick Mooney #define CPUID_STDEXT2_SGXLC 0x40000000 4744c87aefeSPatrick Mooney 4754c87aefeSPatrick Mooney /* 4764c87aefeSPatrick Mooney * CPUID instruction 7 Structured Extended Features, leaf 0 edx info 4774c87aefeSPatrick Mooney */ 4784c87aefeSPatrick Mooney #define CPUID_STDEXT3_AVX5124VNNIW 0x00000004 4794c87aefeSPatrick Mooney #define CPUID_STDEXT3_AVX5124FMAPS 0x00000008 48059d65d31SAndy Fiddaman #define CPUID_STDEXT3_FSRM 0x00000010 4814c87aefeSPatrick Mooney #define CPUID_STDEXT3_AVX512VP2INTERSECT 0x00000100 48259d65d31SAndy Fiddaman #define CPUID_STDEXT3_MCUOPT 0x00000200 4834c87aefeSPatrick Mooney #define CPUID_STDEXT3_MD_CLEAR 0x00000400 4844c87aefeSPatrick Mooney #define CPUID_STDEXT3_TSXFA 0x00002000 4854c87aefeSPatrick Mooney #define CPUID_STDEXT3_PCONFIG 0x00040000 4864c87aefeSPatrick Mooney #define CPUID_STDEXT3_IBPB 0x04000000 4874c87aefeSPatrick Mooney #define CPUID_STDEXT3_STIBP 0x08000000 4884c87aefeSPatrick Mooney #define CPUID_STDEXT3_L1D_FLUSH 0x10000000 4894c87aefeSPatrick Mooney #define CPUID_STDEXT3_ARCH_CAP 0x20000000 4904c87aefeSPatrick Mooney #define CPUID_STDEXT3_CORE_CAP 0x40000000 4914c87aefeSPatrick Mooney #define CPUID_STDEXT3_SSBD 0x80000000 4924c87aefeSPatrick Mooney 4934c87aefeSPatrick Mooney /* MSR IA32_ARCH_CAP(ABILITIES) bits */ 4944c87aefeSPatrick Mooney #define IA32_ARCH_CAP_RDCL_NO 0x00000001 4954c87aefeSPatrick Mooney #define IA32_ARCH_CAP_IBRS_ALL 0x00000002 4964c87aefeSPatrick Mooney #define IA32_ARCH_CAP_RSBA 0x00000004 4974c87aefeSPatrick Mooney #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x00000008 4984c87aefeSPatrick Mooney #define IA32_ARCH_CAP_SSB_NO 0x00000010 4994c87aefeSPatrick Mooney #define IA32_ARCH_CAP_MDS_NO 0x00000020 50059d65d31SAndy Fiddaman #define IA32_ARCH_CAP_IF_PSCHANGE_MC_NO 0x00000040 50159d65d31SAndy Fiddaman #define IA32_ARCH_CAP_TSX_CTRL 0x00000080 50259d65d31SAndy Fiddaman #define IA32_ARCH_CAP_TAA_NO 0x00000100 50359d65d31SAndy Fiddaman 50459d65d31SAndy Fiddaman /* MSR IA32_TSX_CTRL bits */ 50559d65d31SAndy Fiddaman #define IA32_TSX_CTRL_RTM_DISABLE 0x00000001 50659d65d31SAndy Fiddaman #define IA32_TSX_CTRL_TSX_CPUID_CLEAR 0x00000002 507bf21cd93STycho Nightingale 508bf21cd93STycho Nightingale /* 509bf21cd93STycho Nightingale * CPUID manufacturers identifiers 510bf21cd93STycho Nightingale */ 511bf21cd93STycho Nightingale #define AMD_VENDOR_ID "AuthenticAMD" 512bf21cd93STycho Nightingale #define CENTAUR_VENDOR_ID "CentaurHauls" 513bf21cd93STycho Nightingale #define CYRIX_VENDOR_ID "CyrixInstead" 514bf21cd93STycho Nightingale #define INTEL_VENDOR_ID "GenuineIntel" 515bf21cd93STycho Nightingale #define NEXGEN_VENDOR_ID "NexGenDriven" 516bf21cd93STycho Nightingale #define NSC_VENDOR_ID "Geode by NSC" 517bf21cd93STycho Nightingale #define RISE_VENDOR_ID "RiseRiseRise" 518bf21cd93STycho Nightingale #define SIS_VENDOR_ID "SiS SiS SiS " 519bf21cd93STycho Nightingale #define TRANSMETA_VENDOR_ID "GenuineTMx86" 520bf21cd93STycho Nightingale #define UMC_VENDOR_ID "UMC UMC UMC " 52159d65d31SAndy Fiddaman #define HYGON_VENDOR_ID "HygonGenuine" 522bf21cd93STycho Nightingale 523bf21cd93STycho Nightingale /* 524bf21cd93STycho Nightingale * Model-specific registers for the i386 family 525bf21cd93STycho Nightingale */ 526bf21cd93STycho Nightingale #define MSR_P5_MC_ADDR 0x000 527bf21cd93STycho Nightingale #define MSR_P5_MC_TYPE 0x001 528bf21cd93STycho Nightingale #define MSR_TSC 0x010 529bf21cd93STycho Nightingale #define MSR_P5_CESR 0x011 530bf21cd93STycho Nightingale #define MSR_P5_CTR0 0x012 531bf21cd93STycho Nightingale #define MSR_P5_CTR1 0x013 532bf21cd93STycho Nightingale #define MSR_IA32_PLATFORM_ID 0x017 533bf21cd93STycho Nightingale #define MSR_APICBASE 0x01b 534bf21cd93STycho Nightingale #define MSR_EBL_CR_POWERON 0x02a 535bf21cd93STycho Nightingale #define MSR_TEST_CTL 0x033 536bf21cd93STycho Nightingale #define MSR_IA32_FEATURE_CONTROL 0x03a 5374c87aefeSPatrick Mooney #define MSR_IA32_SPEC_CTRL 0x048 5384c87aefeSPatrick Mooney #define MSR_IA32_PRED_CMD 0x049 539bf21cd93STycho Nightingale #define MSR_BIOS_UPDT_TRIG 0x079 540bf21cd93STycho Nightingale #define MSR_BBL_CR_D0 0x088 541bf21cd93STycho Nightingale #define MSR_BBL_CR_D1 0x089 542bf21cd93STycho Nightingale #define MSR_BBL_CR_D2 0x08a 543bf21cd93STycho Nightingale #define MSR_BIOS_SIGN 0x08b 544bf21cd93STycho Nightingale #define MSR_PERFCTR0 0x0c1 545bf21cd93STycho Nightingale #define MSR_PERFCTR1 0x0c2 546bf21cd93STycho Nightingale #define MSR_PLATFORM_INFO 0x0ce 547bf21cd93STycho Nightingale #define MSR_MPERF 0x0e7 548bf21cd93STycho Nightingale #define MSR_APERF 0x0e8 549bf21cd93STycho Nightingale #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 550bf21cd93STycho Nightingale #define MSR_MTRRcap 0x0fe 5514c87aefeSPatrick Mooney #define MSR_IA32_ARCH_CAP 0x10a 5524c87aefeSPatrick Mooney #define MSR_IA32_FLUSH_CMD 0x10b 5534c87aefeSPatrick Mooney #define MSR_TSX_FORCE_ABORT 0x10f 554bf21cd93STycho Nightingale #define MSR_BBL_CR_ADDR 0x116 555bf21cd93STycho Nightingale #define MSR_BBL_CR_DECC 0x118 556bf21cd93STycho Nightingale #define MSR_BBL_CR_CTL 0x119 557bf21cd93STycho Nightingale #define MSR_BBL_CR_TRIG 0x11a 558bf21cd93STycho Nightingale #define MSR_BBL_CR_BUSY 0x11b 559bf21cd93STycho Nightingale #define MSR_BBL_CR_CTL3 0x11e 56059d65d31SAndy Fiddaman #define MSR_IA32_TSX_CTRL 0x122 56159d65d31SAndy Fiddaman #define MSR_IA32_MCU_OPT_CTRL 0x123 56259d65d31SAndy Fiddaman #define MSR_MISC_FEATURE_ENABLES 0x140 563bf21cd93STycho Nightingale #define MSR_SYSENTER_CS_MSR 0x174 564bf21cd93STycho Nightingale #define MSR_SYSENTER_ESP_MSR 0x175 565bf21cd93STycho Nightingale #define MSR_SYSENTER_EIP_MSR 0x176 566bf21cd93STycho Nightingale #define MSR_MCG_CAP 0x179 567bf21cd93STycho Nightingale #define MSR_MCG_STATUS 0x17a 568bf21cd93STycho Nightingale #define MSR_MCG_CTL 0x17b 569bf21cd93STycho Nightingale #define MSR_EVNTSEL0 0x186 570bf21cd93STycho Nightingale #define MSR_EVNTSEL1 0x187 571bf21cd93STycho Nightingale #define MSR_THERM_CONTROL 0x19a 572bf21cd93STycho Nightingale #define MSR_THERM_INTERRUPT 0x19b 573bf21cd93STycho Nightingale #define MSR_THERM_STATUS 0x19c 574bf21cd93STycho Nightingale #define MSR_IA32_MISC_ENABLE 0x1a0 575bf21cd93STycho Nightingale #define MSR_IA32_TEMPERATURE_TARGET 0x1a2 576bf21cd93STycho Nightingale #define MSR_TURBO_RATIO_LIMIT 0x1ad 577bf21cd93STycho Nightingale #define MSR_TURBO_RATIO_LIMIT1 0x1ae 57859d65d31SAndy Fiddaman #define MSR_IA32_ENERGY_PERF_BIAS 0x1b0 579bf21cd93STycho Nightingale #define MSR_DEBUGCTLMSR 0x1d9 580bf21cd93STycho Nightingale #define MSR_LASTBRANCHFROMIP 0x1db 581bf21cd93STycho Nightingale #define MSR_LASTBRANCHTOIP 0x1dc 582bf21cd93STycho Nightingale #define MSR_LASTINTFROMIP 0x1dd 583bf21cd93STycho Nightingale #define MSR_LASTINTTOIP 0x1de 584bf21cd93STycho Nightingale #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 585bf21cd93STycho Nightingale #define MSR_MTRRVarBase 0x200 586bf21cd93STycho Nightingale #define MSR_MTRR64kBase 0x250 587bf21cd93STycho Nightingale #define MSR_MTRR16kBase 0x258 588bf21cd93STycho Nightingale #define MSR_MTRR4kBase 0x268 589bf21cd93STycho Nightingale #define MSR_PAT 0x277 590bf21cd93STycho Nightingale #define MSR_MC0_CTL2 0x280 591bf21cd93STycho Nightingale #define MSR_MTRRdefType 0x2ff 592bf21cd93STycho Nightingale #define MSR_MC0_CTL 0x400 593bf21cd93STycho Nightingale #define MSR_MC0_STATUS 0x401 594bf21cd93STycho Nightingale #define MSR_MC0_ADDR 0x402 595bf21cd93STycho Nightingale #define MSR_MC0_MISC 0x403 596bf21cd93STycho Nightingale #define MSR_MC1_CTL 0x404 597bf21cd93STycho Nightingale #define MSR_MC1_STATUS 0x405 598bf21cd93STycho Nightingale #define MSR_MC1_ADDR 0x406 599bf21cd93STycho Nightingale #define MSR_MC1_MISC 0x407 600bf21cd93STycho Nightingale #define MSR_MC2_CTL 0x408 601bf21cd93STycho Nightingale #define MSR_MC2_STATUS 0x409 602bf21cd93STycho Nightingale #define MSR_MC2_ADDR 0x40a 603bf21cd93STycho Nightingale #define MSR_MC2_MISC 0x40b 604bf21cd93STycho Nightingale #define MSR_MC3_CTL 0x40c 605bf21cd93STycho Nightingale #define MSR_MC3_STATUS 0x40d 606bf21cd93STycho Nightingale #define MSR_MC3_ADDR 0x40e 607bf21cd93STycho Nightingale #define MSR_MC3_MISC 0x40f 608bf21cd93STycho Nightingale #define MSR_MC4_CTL 0x410 609bf21cd93STycho Nightingale #define MSR_MC4_STATUS 0x411 610bf21cd93STycho Nightingale #define MSR_MC4_ADDR 0x412 611bf21cd93STycho Nightingale #define MSR_MC4_MISC 0x413 61259d65d31SAndy Fiddaman #define MSR_MCG_EXT_CTL 0x4d0 613bf21cd93STycho Nightingale #define MSR_RAPL_POWER_UNIT 0x606 614bf21cd93STycho Nightingale #define MSR_PKG_ENERGY_STATUS 0x611 615bf21cd93STycho Nightingale #define MSR_DRAM_ENERGY_STATUS 0x619 616bf21cd93STycho Nightingale #define MSR_PP0_ENERGY_STATUS 0x639 617bf21cd93STycho Nightingale #define MSR_PP1_ENERGY_STATUS 0x641 6184c87aefeSPatrick Mooney #define MSR_PPERF 0x64e 6194c87aefeSPatrick Mooney #define MSR_TSC_DEADLINE 0x6e0 /* Writes are not serializing */ 6204c87aefeSPatrick Mooney #define MSR_IA32_PM_ENABLE 0x770 6214c87aefeSPatrick Mooney #define MSR_IA32_HWP_CAPABILITIES 0x771 6224c87aefeSPatrick Mooney #define MSR_IA32_HWP_REQUEST_PKG 0x772 6234c87aefeSPatrick Mooney #define MSR_IA32_HWP_INTERRUPT 0x773 6244c87aefeSPatrick Mooney #define MSR_IA32_HWP_REQUEST 0x774 6254c87aefeSPatrick Mooney #define MSR_IA32_HWP_STATUS 0x777 626bf21cd93STycho Nightingale 627bf21cd93STycho Nightingale /* 628bf21cd93STycho Nightingale * VMX MSRs 629bf21cd93STycho Nightingale */ 630bf21cd93STycho Nightingale #define MSR_VMX_BASIC 0x480 631bf21cd93STycho Nightingale #define MSR_VMX_PINBASED_CTLS 0x481 632bf21cd93STycho Nightingale #define MSR_VMX_PROCBASED_CTLS 0x482 633bf21cd93STycho Nightingale #define MSR_VMX_EXIT_CTLS 0x483 634bf21cd93STycho Nightingale #define MSR_VMX_ENTRY_CTLS 0x484 635bf21cd93STycho Nightingale #define MSR_VMX_CR0_FIXED0 0x486 636bf21cd93STycho Nightingale #define MSR_VMX_CR0_FIXED1 0x487 637bf21cd93STycho Nightingale #define MSR_VMX_CR4_FIXED0 0x488 638bf21cd93STycho Nightingale #define MSR_VMX_CR4_FIXED1 0x489 639bf21cd93STycho Nightingale #define MSR_VMX_PROCBASED_CTLS2 0x48b 640bf21cd93STycho Nightingale #define MSR_VMX_EPT_VPID_CAP 0x48c 641bf21cd93STycho Nightingale #define MSR_VMX_TRUE_PINBASED_CTLS 0x48d 642bf21cd93STycho Nightingale #define MSR_VMX_TRUE_PROCBASED_CTLS 0x48e 643bf21cd93STycho Nightingale #define MSR_VMX_TRUE_EXIT_CTLS 0x48f 644bf21cd93STycho Nightingale #define MSR_VMX_TRUE_ENTRY_CTLS 0x490 645bf21cd93STycho Nightingale 646bf21cd93STycho Nightingale /* 6474c87aefeSPatrick Mooney * X2APIC MSRs. 6484c87aefeSPatrick Mooney * Writes are not serializing. 649bf21cd93STycho Nightingale */ 6504c87aefeSPatrick Mooney #define MSR_APIC_000 0x800 651bf21cd93STycho Nightingale #define MSR_APIC_ID 0x802 652bf21cd93STycho Nightingale #define MSR_APIC_VERSION 0x803 653bf21cd93STycho Nightingale #define MSR_APIC_TPR 0x808 654bf21cd93STycho Nightingale #define MSR_APIC_EOI 0x80b 655bf21cd93STycho Nightingale #define MSR_APIC_LDR 0x80d 656bf21cd93STycho Nightingale #define MSR_APIC_SVR 0x80f 657bf21cd93STycho Nightingale #define MSR_APIC_ISR0 0x810 658bf21cd93STycho Nightingale #define MSR_APIC_ISR1 0x811 659bf21cd93STycho Nightingale #define MSR_APIC_ISR2 0x812 660bf21cd93STycho Nightingale #define MSR_APIC_ISR3 0x813 661bf21cd93STycho Nightingale #define MSR_APIC_ISR4 0x814 662bf21cd93STycho Nightingale #define MSR_APIC_ISR5 0x815 663bf21cd93STycho Nightingale #define MSR_APIC_ISR6 0x816 664bf21cd93STycho Nightingale #define MSR_APIC_ISR7 0x817 665bf21cd93STycho Nightingale #define MSR_APIC_TMR0 0x818 666bf21cd93STycho Nightingale #define MSR_APIC_IRR0 0x820 667bf21cd93STycho Nightingale #define MSR_APIC_ESR 0x828 668bf21cd93STycho Nightingale #define MSR_APIC_LVT_CMCI 0x82F 669bf21cd93STycho Nightingale #define MSR_APIC_ICR 0x830 670bf21cd93STycho Nightingale #define MSR_APIC_LVT_TIMER 0x832 671bf21cd93STycho Nightingale #define MSR_APIC_LVT_THERMAL 0x833 672bf21cd93STycho Nightingale #define MSR_APIC_LVT_PCINT 0x834 673bf21cd93STycho Nightingale #define MSR_APIC_LVT_LINT0 0x835 674bf21cd93STycho Nightingale #define MSR_APIC_LVT_LINT1 0x836 675bf21cd93STycho Nightingale #define MSR_APIC_LVT_ERROR 0x837 676bf21cd93STycho Nightingale #define MSR_APIC_ICR_TIMER 0x838 677bf21cd93STycho Nightingale #define MSR_APIC_CCR_TIMER 0x839 678bf21cd93STycho Nightingale #define MSR_APIC_DCR_TIMER 0x83e 679bf21cd93STycho Nightingale #define MSR_APIC_SELF_IPI 0x83f 680bf21cd93STycho Nightingale 681bf21cd93STycho Nightingale #define MSR_IA32_XSS 0xda0 682bf21cd93STycho Nightingale 6834c87aefeSPatrick Mooney /* 6844c87aefeSPatrick Mooney * Intel Processor Trace (PT) MSRs. 6854c87aefeSPatrick Mooney */ 6864c87aefeSPatrick Mooney #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 /* Trace Output Base Register (R/W) */ 6874c87aefeSPatrick Mooney #define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x561 /* Trace Output Mask Pointers Register (R/W) */ 6884c87aefeSPatrick Mooney #define MSR_IA32_RTIT_CTL 0x570 /* Trace Control Register (R/W) */ 6894c87aefeSPatrick Mooney #define RTIT_CTL_TRACEEN (1 << 0) 6904c87aefeSPatrick Mooney #define RTIT_CTL_CYCEN (1 << 1) 6914c87aefeSPatrick Mooney #define RTIT_CTL_OS (1 << 2) 6924c87aefeSPatrick Mooney #define RTIT_CTL_USER (1 << 3) 6934c87aefeSPatrick Mooney #define RTIT_CTL_PWREVTEN (1 << 4) 6944c87aefeSPatrick Mooney #define RTIT_CTL_FUPONPTW (1 << 5) 6954c87aefeSPatrick Mooney #define RTIT_CTL_FABRICEN (1 << 6) 6964c87aefeSPatrick Mooney #define RTIT_CTL_CR3FILTER (1 << 7) 6974c87aefeSPatrick Mooney #define RTIT_CTL_TOPA (1 << 8) 6984c87aefeSPatrick Mooney #define RTIT_CTL_MTCEN (1 << 9) 6994c87aefeSPatrick Mooney #define RTIT_CTL_TSCEN (1 << 10) 7004c87aefeSPatrick Mooney #define RTIT_CTL_DISRETC (1 << 11) 7014c87aefeSPatrick Mooney #define RTIT_CTL_PTWEN (1 << 12) 7024c87aefeSPatrick Mooney #define RTIT_CTL_BRANCHEN (1 << 13) 7034c87aefeSPatrick Mooney #define RTIT_CTL_MTC_FREQ_S 14 7044c87aefeSPatrick Mooney #define RTIT_CTL_MTC_FREQ(n) ((n) << RTIT_CTL_MTC_FREQ_S) 7054c87aefeSPatrick Mooney #define RTIT_CTL_MTC_FREQ_M (0xf << RTIT_CTL_MTC_FREQ_S) 7064c87aefeSPatrick Mooney #define RTIT_CTL_CYC_THRESH_S 19 7074c87aefeSPatrick Mooney #define RTIT_CTL_CYC_THRESH_M (0xf << RTIT_CTL_CYC_THRESH_S) 7084c87aefeSPatrick Mooney #define RTIT_CTL_PSB_FREQ_S 24 7094c87aefeSPatrick Mooney #define RTIT_CTL_PSB_FREQ_M (0xf << RTIT_CTL_PSB_FREQ_S) 7104c87aefeSPatrick Mooney #define RTIT_CTL_ADDR_CFG_S(n) (32 + (n) * 4) 7114c87aefeSPatrick Mooney #define RTIT_CTL_ADDR0_CFG_S 32 7124c87aefeSPatrick Mooney #define RTIT_CTL_ADDR0_CFG_M (0xfULL << RTIT_CTL_ADDR0_CFG_S) 7134c87aefeSPatrick Mooney #define RTIT_CTL_ADDR1_CFG_S 36 7144c87aefeSPatrick Mooney #define RTIT_CTL_ADDR1_CFG_M (0xfULL << RTIT_CTL_ADDR1_CFG_S) 7154c87aefeSPatrick Mooney #define RTIT_CTL_ADDR2_CFG_S 40 7164c87aefeSPatrick Mooney #define RTIT_CTL_ADDR2_CFG_M (0xfULL << RTIT_CTL_ADDR2_CFG_S) 7174c87aefeSPatrick Mooney #define RTIT_CTL_ADDR3_CFG_S 44 7184c87aefeSPatrick Mooney #define RTIT_CTL_ADDR3_CFG_M (0xfULL << RTIT_CTL_ADDR3_CFG_S) 7194c87aefeSPatrick Mooney #define MSR_IA32_RTIT_STATUS 0x571 /* Tracing Status Register (R/W) */ 7204c87aefeSPatrick Mooney #define RTIT_STATUS_FILTEREN (1 << 0) 7214c87aefeSPatrick Mooney #define RTIT_STATUS_CONTEXTEN (1 << 1) 7224c87aefeSPatrick Mooney #define RTIT_STATUS_TRIGGEREN (1 << 2) 7234c87aefeSPatrick Mooney #define RTIT_STATUS_ERROR (1 << 4) 7244c87aefeSPatrick Mooney #define RTIT_STATUS_STOPPED (1 << 5) 7254c87aefeSPatrick Mooney #define RTIT_STATUS_PACKETBYTECNT_S 32 7264c87aefeSPatrick Mooney #define RTIT_STATUS_PACKETBYTECNT_M (0x1ffffULL << RTIT_STATUS_PACKETBYTECNT_S) 7274c87aefeSPatrick Mooney #define MSR_IA32_RTIT_CR3_MATCH 0x572 /* Trace Filter CR3 Match Register (R/W) */ 7284c87aefeSPatrick Mooney #define MSR_IA32_RTIT_ADDR_A(n) (0x580 + (n) * 2) 7294c87aefeSPatrick Mooney #define MSR_IA32_RTIT_ADDR_B(n) (0x581 + (n) * 2) 7304c87aefeSPatrick Mooney #define MSR_IA32_RTIT_ADDR0_A 0x580 /* Region 0 Start Address (R/W) */ 7314c87aefeSPatrick Mooney #define MSR_IA32_RTIT_ADDR0_B 0x581 /* Region 0 End Address (R/W) */ 7324c87aefeSPatrick Mooney #define MSR_IA32_RTIT_ADDR1_A 0x582 /* Region 1 Start Address (R/W) */ 7334c87aefeSPatrick Mooney #define MSR_IA32_RTIT_ADDR1_B 0x583 /* Region 1 End Address (R/W) */ 7344c87aefeSPatrick Mooney #define MSR_IA32_RTIT_ADDR2_A 0x584 /* Region 2 Start Address (R/W) */ 7354c87aefeSPatrick Mooney #define MSR_IA32_RTIT_ADDR2_B 0x585 /* Region 2 End Address (R/W) */ 7364c87aefeSPatrick Mooney #define MSR_IA32_RTIT_ADDR3_A 0x586 /* Region 3 Start Address (R/W) */ 7374c87aefeSPatrick Mooney #define MSR_IA32_RTIT_ADDR3_B 0x587 /* Region 3 End Address (R/W) */ 7384c87aefeSPatrick Mooney 7394c87aefeSPatrick Mooney /* Intel Processor Trace Table of Physical Addresses (ToPA). */ 7404c87aefeSPatrick Mooney #define TOPA_SIZE_S 6 7414c87aefeSPatrick Mooney #define TOPA_SIZE_M (0xf << TOPA_SIZE_S) 7424c87aefeSPatrick Mooney #define TOPA_SIZE_4K (0 << TOPA_SIZE_S) 7434c87aefeSPatrick Mooney #define TOPA_SIZE_8K (1 << TOPA_SIZE_S) 7444c87aefeSPatrick Mooney #define TOPA_SIZE_16K (2 << TOPA_SIZE_S) 7454c87aefeSPatrick Mooney #define TOPA_SIZE_32K (3 << TOPA_SIZE_S) 7464c87aefeSPatrick Mooney #define TOPA_SIZE_64K (4 << TOPA_SIZE_S) 7474c87aefeSPatrick Mooney #define TOPA_SIZE_128K (5 << TOPA_SIZE_S) 7484c87aefeSPatrick Mooney #define TOPA_SIZE_256K (6 << TOPA_SIZE_S) 7494c87aefeSPatrick Mooney #define TOPA_SIZE_512K (7 << TOPA_SIZE_S) 7504c87aefeSPatrick Mooney #define TOPA_SIZE_1M (8 << TOPA_SIZE_S) 7514c87aefeSPatrick Mooney #define TOPA_SIZE_2M (9 << TOPA_SIZE_S) 7524c87aefeSPatrick Mooney #define TOPA_SIZE_4M (10 << TOPA_SIZE_S) 7534c87aefeSPatrick Mooney #define TOPA_SIZE_8M (11 << TOPA_SIZE_S) 7544c87aefeSPatrick Mooney #define TOPA_SIZE_16M (12 << TOPA_SIZE_S) 7554c87aefeSPatrick Mooney #define TOPA_SIZE_32M (13 << TOPA_SIZE_S) 7564c87aefeSPatrick Mooney #define TOPA_SIZE_64M (14 << TOPA_SIZE_S) 7574c87aefeSPatrick Mooney #define TOPA_SIZE_128M (15 << TOPA_SIZE_S) 7584c87aefeSPatrick Mooney #define TOPA_STOP (1 << 4) 7594c87aefeSPatrick Mooney #define TOPA_INT (1 << 2) 7604c87aefeSPatrick Mooney #define TOPA_END (1 << 0) 7614c87aefeSPatrick Mooney 762bf21cd93STycho Nightingale /* 763bf21cd93STycho Nightingale * Constants related to MSR's. 764bf21cd93STycho Nightingale */ 765bf21cd93STycho Nightingale #define APICBASE_RESERVED 0x000002ff 766bf21cd93STycho Nightingale #define APICBASE_BSP 0x00000100 767bf21cd93STycho Nightingale #define APICBASE_X2APIC 0x00000400 768bf21cd93STycho Nightingale #define APICBASE_ENABLED 0x00000800 769bf21cd93STycho Nightingale #define APICBASE_ADDRESS 0xfffff000 770bf21cd93STycho Nightingale 771bf21cd93STycho Nightingale /* MSR_IA32_FEATURE_CONTROL related */ 772bf21cd93STycho Nightingale #define IA32_FEATURE_CONTROL_LOCK 0x01 /* lock bit */ 773bf21cd93STycho Nightingale #define IA32_FEATURE_CONTROL_SMX_EN 0x02 /* enable VMX inside SMX */ 774bf21cd93STycho Nightingale #define IA32_FEATURE_CONTROL_VMX_EN 0x04 /* enable VMX outside SMX */ 77559d65d31SAndy Fiddaman #define IA32_FEATURE_CONTROL_LMCE_EN 0x100000 /* enable local MCE */ 776bf21cd93STycho Nightingale 7774c87aefeSPatrick Mooney /* MSR IA32_MISC_ENABLE */ 7784c87aefeSPatrick Mooney #define IA32_MISC_EN_FASTSTR 0x0000000000000001ULL 7794c87aefeSPatrick Mooney #define IA32_MISC_EN_ATCCE 0x0000000000000008ULL 7804c87aefeSPatrick Mooney #define IA32_MISC_EN_PERFMON 0x0000000000000080ULL 7814c87aefeSPatrick Mooney #define IA32_MISC_EN_PEBSU 0x0000000000001000ULL 7824c87aefeSPatrick Mooney #define IA32_MISC_EN_ESSTE 0x0000000000010000ULL 7834c87aefeSPatrick Mooney #define IA32_MISC_EN_MONE 0x0000000000040000ULL 7844c87aefeSPatrick Mooney #define IA32_MISC_EN_LIMCPUID 0x0000000000400000ULL 7854c87aefeSPatrick Mooney #define IA32_MISC_EN_xTPRD 0x0000000000800000ULL 7864c87aefeSPatrick Mooney #define IA32_MISC_EN_XDD 0x0000000400000000ULL 7874c87aefeSPatrick Mooney 7884c87aefeSPatrick Mooney /* 7894c87aefeSPatrick Mooney * IA32_SPEC_CTRL and IA32_PRED_CMD MSRs are described in the Intel' 7904c87aefeSPatrick Mooney * document 336996-001 Speculative Execution Side Channel Mitigations. 7914c87aefeSPatrick Mooney * 7924c87aefeSPatrick Mooney * AMD uses the same MSRs and bit definitions, as described in 111006-B 7934c87aefeSPatrick Mooney * "Indirect Branch Control Extension" and 124441 "Speculative Store Bypass 7944c87aefeSPatrick Mooney * Disable." 7954c87aefeSPatrick Mooney */ 7964c87aefeSPatrick Mooney /* MSR IA32_SPEC_CTRL */ 7974c87aefeSPatrick Mooney #define IA32_SPEC_CTRL_IBRS 0x00000001 7984c87aefeSPatrick Mooney #define IA32_SPEC_CTRL_STIBP 0x00000002 7994c87aefeSPatrick Mooney #define IA32_SPEC_CTRL_SSBD 0x00000004 8004c87aefeSPatrick Mooney 8014c87aefeSPatrick Mooney /* MSR IA32_PRED_CMD */ 8024c87aefeSPatrick Mooney #define IA32_PRED_CMD_IBPB_BARRIER 0x0000000000000001ULL 8034c87aefeSPatrick Mooney 8044c87aefeSPatrick Mooney /* MSR IA32_FLUSH_CMD */ 8054c87aefeSPatrick Mooney #define IA32_FLUSH_CMD_L1D 0x00000001 8064c87aefeSPatrick Mooney 80759d65d31SAndy Fiddaman /* MSR IA32_MCU_OPT_CTRL */ 80859d65d31SAndy Fiddaman #define IA32_RNGDS_MITG_DIS 0x00000001 80959d65d31SAndy Fiddaman 8104c87aefeSPatrick Mooney /* MSR IA32_HWP_CAPABILITIES */ 8114c87aefeSPatrick Mooney #define IA32_HWP_CAPABILITIES_HIGHEST_PERFORMANCE(x) (((x) >> 0) & 0xff) 8124c87aefeSPatrick Mooney #define IA32_HWP_CAPABILITIES_GUARANTEED_PERFORMANCE(x) (((x) >> 8) & 0xff) 8134c87aefeSPatrick Mooney #define IA32_HWP_CAPABILITIES_EFFICIENT_PERFORMANCE(x) (((x) >> 16) & 0xff) 8144c87aefeSPatrick Mooney #define IA32_HWP_CAPABILITIES_LOWEST_PERFORMANCE(x) (((x) >> 24) & 0xff) 8154c87aefeSPatrick Mooney 8164c87aefeSPatrick Mooney /* MSR IA32_HWP_REQUEST */ 8174c87aefeSPatrick Mooney #define IA32_HWP_REQUEST_MINIMUM_VALID (1ULL << 63) 8184c87aefeSPatrick Mooney #define IA32_HWP_REQUEST_MAXIMUM_VALID (1ULL << 62) 8194c87aefeSPatrick Mooney #define IA32_HWP_REQUEST_DESIRED_VALID (1ULL << 61) 8204c87aefeSPatrick Mooney #define IA32_HWP_REQUEST_EPP_VALID (1ULL << 60) 8214c87aefeSPatrick Mooney #define IA32_HWP_REQUEST_ACTIVITY_WINDOW_VALID (1ULL << 59) 8224c87aefeSPatrick Mooney #define IA32_HWP_REQUEST_PACKAGE_CONTROL (1ULL << 42) 8234c87aefeSPatrick Mooney #define IA32_HWP_ACTIVITY_WINDOW (0x3ffULL << 32) 8244c87aefeSPatrick Mooney #define IA32_HWP_REQUEST_ENERGY_PERFORMANCE_PREFERENCE (0xffULL << 24) 8254c87aefeSPatrick Mooney #define IA32_HWP_DESIRED_PERFORMANCE (0xffULL << 16) 8264c87aefeSPatrick Mooney #define IA32_HWP_REQUEST_MAXIMUM_PERFORMANCE (0xffULL << 8) 8274c87aefeSPatrick Mooney #define IA32_HWP_MINIMUM_PERFORMANCE (0xffULL << 0) 8284c87aefeSPatrick Mooney 82959d65d31SAndy Fiddaman /* MSR IA32_ENERGY_PERF_BIAS */ 83059d65d31SAndy Fiddaman #define IA32_ENERGY_PERF_BIAS_POLICY_HINT_MASK (0xfULL << 0) 83159d65d31SAndy Fiddaman 832bf21cd93STycho Nightingale /* 833bf21cd93STycho Nightingale * PAT modes. 834bf21cd93STycho Nightingale */ 835bf21cd93STycho Nightingale #define PAT_UNCACHEABLE 0x00 836bf21cd93STycho Nightingale #define PAT_WRITE_COMBINING 0x01 837bf21cd93STycho Nightingale #define PAT_WRITE_THROUGH 0x04 838bf21cd93STycho Nightingale #define PAT_WRITE_PROTECTED 0x05 839bf21cd93STycho Nightingale #define PAT_WRITE_BACK 0x06 840bf21cd93STycho Nightingale #define PAT_UNCACHED 0x07 841bf21cd93STycho Nightingale #define PAT_VALUE(i, m) ((long long)(m) << (8 * (i))) 842bf21cd93STycho Nightingale #define PAT_MASK(i) PAT_VALUE(i, 0xff) 843bf21cd93STycho Nightingale 844bf21cd93STycho Nightingale /* 845bf21cd93STycho Nightingale * Constants related to MTRRs 846bf21cd93STycho Nightingale */ 847bf21cd93STycho Nightingale #define MTRR_UNCACHEABLE 0x00 848bf21cd93STycho Nightingale #define MTRR_WRITE_COMBINING 0x01 849bf21cd93STycho Nightingale #define MTRR_WRITE_THROUGH 0x04 850bf21cd93STycho Nightingale #define MTRR_WRITE_PROTECTED 0x05 851bf21cd93STycho Nightingale #define MTRR_WRITE_BACK 0x06 852bf21cd93STycho Nightingale #define MTRR_N64K 8 /* numbers of fixed-size entries */ 853bf21cd93STycho Nightingale #define MTRR_N16K 16 854bf21cd93STycho Nightingale #define MTRR_N4K 64 855bf21cd93STycho Nightingale #define MTRR_CAP_WC 0x0000000000000400 856bf21cd93STycho Nightingale #define MTRR_CAP_FIXED 0x0000000000000100 857bf21cd93STycho Nightingale #define MTRR_CAP_VCNT 0x00000000000000ff 858bf21cd93STycho Nightingale #define MTRR_DEF_ENABLE 0x0000000000000800 859bf21cd93STycho Nightingale #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400 860bf21cd93STycho Nightingale #define MTRR_DEF_TYPE 0x00000000000000ff 861bf21cd93STycho Nightingale #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000 862bf21cd93STycho Nightingale #define MTRR_PHYSBASE_TYPE 0x00000000000000ff 863bf21cd93STycho Nightingale #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000 864bf21cd93STycho Nightingale #define MTRR_PHYSMASK_VALID 0x0000000000000800 865bf21cd93STycho Nightingale 866bf21cd93STycho Nightingale /* 867bf21cd93STycho Nightingale * Cyrix configuration registers, accessible as IO ports. 868bf21cd93STycho Nightingale */ 869bf21cd93STycho Nightingale #define CCR0 0xc0 /* Configuration control register 0 */ 870bf21cd93STycho Nightingale #define CCR0_NC0 0x01 /* First 64K of each 1M memory region is 871bf21cd93STycho Nightingale non-cacheable */ 872bf21cd93STycho Nightingale #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 873bf21cd93STycho Nightingale #define CCR0_A20M 0x04 /* Enables A20M# input pin */ 874bf21cd93STycho Nightingale #define CCR0_KEN 0x08 /* Enables KEN# input pin */ 875bf21cd93STycho Nightingale #define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ 876bf21cd93STycho Nightingale #define CCR0_BARB 0x20 /* Flushes internal cache when entering hold 877bf21cd93STycho Nightingale state */ 878bf21cd93STycho Nightingale #define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set 879bf21cd93STycho Nightingale assoc */ 880bf21cd93STycho Nightingale #define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ 881bf21cd93STycho Nightingale 882bf21cd93STycho Nightingale #define CCR1 0xc1 /* Configuration control register 1 */ 883bf21cd93STycho Nightingale #define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ 884bf21cd93STycho Nightingale #define CCR1_SMI 0x02 /* Enables SMM pins */ 885bf21cd93STycho Nightingale #define CCR1_SMAC 0x04 /* System management memory access */ 886bf21cd93STycho Nightingale #define CCR1_MMAC 0x08 /* Main memory access */ 887bf21cd93STycho Nightingale #define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ 888bf21cd93STycho Nightingale #define CCR1_SM3 0x80 /* SMM address space address region 3 */ 889bf21cd93STycho Nightingale 890bf21cd93STycho Nightingale #define CCR2 0xc2 891bf21cd93STycho Nightingale #define CCR2_WB 0x02 /* Enables WB cache interface pins */ 892bf21cd93STycho Nightingale #define CCR2_SADS 0x02 /* Slow ADS */ 893bf21cd93STycho Nightingale #define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ 894bf21cd93STycho Nightingale #define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ 895bf21cd93STycho Nightingale #define CCR2_WT1 0x10 /* WT region 1 */ 896bf21cd93STycho Nightingale #define CCR2_WPR1 0x10 /* Write-protect region 1 */ 897bf21cd93STycho Nightingale #define CCR2_BARB 0x20 /* Flushes write-back cache when entering 898bf21cd93STycho Nightingale hold state. */ 899bf21cd93STycho Nightingale #define CCR2_BWRT 0x40 /* Enables burst write cycles */ 900bf21cd93STycho Nightingale #define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ 901bf21cd93STycho Nightingale 902bf21cd93STycho Nightingale #define CCR3 0xc3 903bf21cd93STycho Nightingale #define CCR3_SMILOCK 0x01 /* SMM register lock */ 904bf21cd93STycho Nightingale #define CCR3_NMI 0x02 /* Enables NMI during SMM */ 905bf21cd93STycho Nightingale #define CCR3_LINBRST 0x04 /* Linear address burst cycles */ 906bf21cd93STycho Nightingale #define CCR3_SMMMODE 0x08 /* SMM Mode */ 907bf21cd93STycho Nightingale #define CCR3_MAPEN0 0x10 /* Enables Map0 */ 908bf21cd93STycho Nightingale #define CCR3_MAPEN1 0x20 /* Enables Map1 */ 909bf21cd93STycho Nightingale #define CCR3_MAPEN2 0x40 /* Enables Map2 */ 910bf21cd93STycho Nightingale #define CCR3_MAPEN3 0x80 /* Enables Map3 */ 911bf21cd93STycho Nightingale 912bf21cd93STycho Nightingale #define CCR4 0xe8 913bf21cd93STycho Nightingale #define CCR4_IOMASK 0x07 914bf21cd93STycho Nightingale #define CCR4_MEM 0x08 /* Enables momory bypassing */ 915bf21cd93STycho Nightingale #define CCR4_DTE 0x10 /* Enables directory table entry cache */ 916bf21cd93STycho Nightingale #define CCR4_FASTFPE 0x20 /* Fast FPU exception */ 917bf21cd93STycho Nightingale #define CCR4_CPUID 0x80 /* Enables CPUID instruction */ 918bf21cd93STycho Nightingale 919bf21cd93STycho Nightingale #define CCR5 0xe9 920bf21cd93STycho Nightingale #define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ 921bf21cd93STycho Nightingale #define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ 922bf21cd93STycho Nightingale #define CCR5_LBR1 0x10 /* Local bus region 1 */ 923bf21cd93STycho Nightingale #define CCR5_ARREN 0x20 /* Enables ARR region */ 924bf21cd93STycho Nightingale 925bf21cd93STycho Nightingale #define CCR6 0xea 926bf21cd93STycho Nightingale 927bf21cd93STycho Nightingale #define CCR7 0xeb 928bf21cd93STycho Nightingale 929bf21cd93STycho Nightingale /* Performance Control Register (5x86 only). */ 930bf21cd93STycho Nightingale #define PCR0 0x20 931bf21cd93STycho Nightingale #define PCR0_RSTK 0x01 /* Enables return stack */ 932bf21cd93STycho Nightingale #define PCR0_BTB 0x02 /* Enables branch target buffer */ 933bf21cd93STycho Nightingale #define PCR0_LOOP 0x04 /* Enables loop */ 934bf21cd93STycho Nightingale #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 935bf21cd93STycho Nightingale serialize pipe. */ 936bf21cd93STycho Nightingale #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 937bf21cd93STycho Nightingale #define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 938bf21cd93STycho Nightingale #define PCR0_LSSER 0x80 /* Disable reorder */ 939bf21cd93STycho Nightingale 940bf21cd93STycho Nightingale /* Device Identification Registers */ 941bf21cd93STycho Nightingale #define DIR0 0xfe 942bf21cd93STycho Nightingale #define DIR1 0xff 943bf21cd93STycho Nightingale 944bf21cd93STycho Nightingale /* 945bf21cd93STycho Nightingale * Machine Check register constants. 946bf21cd93STycho Nightingale */ 947bf21cd93STycho Nightingale #define MCG_CAP_COUNT 0x000000ff 948bf21cd93STycho Nightingale #define MCG_CAP_CTL_P 0x00000100 949bf21cd93STycho Nightingale #define MCG_CAP_EXT_P 0x00000200 950bf21cd93STycho Nightingale #define MCG_CAP_CMCI_P 0x00000400 951bf21cd93STycho Nightingale #define MCG_CAP_TES_P 0x00000800 952bf21cd93STycho Nightingale #define MCG_CAP_EXT_CNT 0x00ff0000 953bf21cd93STycho Nightingale #define MCG_CAP_SER_P 0x01000000 95459d65d31SAndy Fiddaman #define MCG_CAP_EMC_P 0x02000000 95559d65d31SAndy Fiddaman #define MCG_CAP_ELOG_P 0x04000000 95659d65d31SAndy Fiddaman #define MCG_CAP_LMCE_P 0x08000000 957bf21cd93STycho Nightingale #define MCG_STATUS_RIPV 0x00000001 958bf21cd93STycho Nightingale #define MCG_STATUS_EIPV 0x00000002 959bf21cd93STycho Nightingale #define MCG_STATUS_MCIP 0x00000004 96059d65d31SAndy Fiddaman #define MCG_STATUS_LMCS 0x00000008 /* if MCG_CAP_LMCE_P */ 961bf21cd93STycho Nightingale #define MCG_CTL_ENABLE 0xffffffffffffffff 962bf21cd93STycho Nightingale #define MCG_CTL_DISABLE 0x0000000000000000 963bf21cd93STycho Nightingale #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) 964bf21cd93STycho Nightingale #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) 965bf21cd93STycho Nightingale #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) 966bf21cd93STycho Nightingale #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) 967bf21cd93STycho Nightingale #define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */ 968bf21cd93STycho Nightingale #define MC_STATUS_MCA_ERROR 0x000000000000ffff 969bf21cd93STycho Nightingale #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000 970bf21cd93STycho Nightingale #define MC_STATUS_OTHER_INFO 0x01ffffff00000000 971bf21cd93STycho Nightingale #define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */ 972bf21cd93STycho Nightingale #define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */ 973bf21cd93STycho Nightingale #define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */ 974bf21cd93STycho Nightingale #define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */ 975bf21cd93STycho Nightingale #define MC_STATUS_PCC 0x0200000000000000 976bf21cd93STycho Nightingale #define MC_STATUS_ADDRV 0x0400000000000000 977bf21cd93STycho Nightingale #define MC_STATUS_MISCV 0x0800000000000000 978bf21cd93STycho Nightingale #define MC_STATUS_EN 0x1000000000000000 979bf21cd93STycho Nightingale #define MC_STATUS_UC 0x2000000000000000 980bf21cd93STycho Nightingale #define MC_STATUS_OVER 0x4000000000000000 981bf21cd93STycho Nightingale #define MC_STATUS_VAL 0x8000000000000000 982bf21cd93STycho Nightingale #define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */ 983bf21cd93STycho Nightingale #define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */ 98459d65d31SAndy Fiddaman #define MC_MISC_PCIE_RID 0x00000000ffff0000 98559d65d31SAndy Fiddaman #define MC_MISC_PCIE_FUNC 0x0000000000070000 98659d65d31SAndy Fiddaman #define MC_MISC_PCIE_SLOT 0x0000000000f80000 98759d65d31SAndy Fiddaman #define MC_MISC_PCIE_BUS 0x00000000ff000000 98859d65d31SAndy Fiddaman #define MC_MISC_PCIE_SEG 0x000000ff00000000 989bf21cd93STycho Nightingale #define MC_CTL2_THRESHOLD 0x0000000000007fff 990bf21cd93STycho Nightingale #define MC_CTL2_CMCI_EN 0x0000000040000000 9914c87aefeSPatrick Mooney #define MC_AMDNB_BANK 4 9924c87aefeSPatrick Mooney #define MC_MISC_AMD_VAL 0x8000000000000000 /* Counter presence valid */ 9934c87aefeSPatrick Mooney #define MC_MISC_AMD_CNTP 0x4000000000000000 /* Counter present */ 9944c87aefeSPatrick Mooney #define MC_MISC_AMD_LOCK 0x2000000000000000 /* Register locked */ 9954c87aefeSPatrick Mooney #define MC_MISC_AMD_INTP 0x1000000000000000 /* Int. type can generate interrupts */ 9964c87aefeSPatrick Mooney #define MC_MISC_AMD_LVT_MASK 0x00f0000000000000 /* Extended LVT offset */ 9974c87aefeSPatrick Mooney #define MC_MISC_AMD_LVT_SHIFT 52 9984c87aefeSPatrick Mooney #define MC_MISC_AMD_CNTEN 0x0008000000000000 /* Counter enabled */ 9994c87aefeSPatrick Mooney #define MC_MISC_AMD_INT_MASK 0x0006000000000000 /* Interrupt type */ 10004c87aefeSPatrick Mooney #define MC_MISC_AMD_INT_LVT 0x0002000000000000 /* Interrupt via Extended LVT */ 10014c87aefeSPatrick Mooney #define MC_MISC_AMD_INT_SMI 0x0004000000000000 /* SMI */ 10024c87aefeSPatrick Mooney #define MC_MISC_AMD_OVERFLOW 0x0001000000000000 /* Counter overflow */ 10034c87aefeSPatrick Mooney #define MC_MISC_AMD_CNT_MASK 0x00000fff00000000 /* Counter value */ 10044c87aefeSPatrick Mooney #define MC_MISC_AMD_CNT_SHIFT 32 10054c87aefeSPatrick Mooney #define MC_MISC_AMD_CNT_MAX 0xfff 10064c87aefeSPatrick Mooney #define MC_MISC_AMD_PTR_MASK 0x00000000ff000000 /* Pointer to additional registers */ 10074c87aefeSPatrick Mooney #define MC_MISC_AMD_PTR_SHIFT 24 10084c87aefeSPatrick Mooney 10094c87aefeSPatrick Mooney /* AMD Scalable MCA */ 10104c87aefeSPatrick Mooney #define MSR_SMCA_MC0_CTL 0xc0002000 10114c87aefeSPatrick Mooney #define MSR_SMCA_MC0_STATUS 0xc0002001 10124c87aefeSPatrick Mooney #define MSR_SMCA_MC0_ADDR 0xc0002002 10134c87aefeSPatrick Mooney #define MSR_SMCA_MC0_MISC0 0xc0002003 10144c87aefeSPatrick Mooney #define MSR_SMCA_MC_CTL(x) (MSR_SMCA_MC0_CTL + 0x10 * (x)) 10154c87aefeSPatrick Mooney #define MSR_SMCA_MC_STATUS(x) (MSR_SMCA_MC0_STATUS + 0x10 * (x)) 10164c87aefeSPatrick Mooney #define MSR_SMCA_MC_ADDR(x) (MSR_SMCA_MC0_ADDR + 0x10 * (x)) 10174c87aefeSPatrick Mooney #define MSR_SMCA_MC_MISC(x) (MSR_SMCA_MC0_MISC0 + 0x10 * (x)) 1018bf21cd93STycho Nightingale 1019bf21cd93STycho Nightingale /* 1020bf21cd93STycho Nightingale * The following four 3-byte registers control the non-cacheable regions. 1021bf21cd93STycho Nightingale * These registers must be written as three separate bytes. 1022bf21cd93STycho Nightingale * 1023bf21cd93STycho Nightingale * NCRx+0: A31-A24 of starting address 1024bf21cd93STycho Nightingale * NCRx+1: A23-A16 of starting address 1025bf21cd93STycho Nightingale * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 1026bf21cd93STycho Nightingale * 1027bf21cd93STycho Nightingale * The non-cacheable region's starting address must be aligned to the 1028bf21cd93STycho Nightingale * size indicated by the NCR_SIZE_xx field. 1029bf21cd93STycho Nightingale */ 1030bf21cd93STycho Nightingale #define NCR1 0xc4 1031bf21cd93STycho Nightingale #define NCR2 0xc7 1032bf21cd93STycho Nightingale #define NCR3 0xca 1033bf21cd93STycho Nightingale #define NCR4 0xcd 1034bf21cd93STycho Nightingale 1035bf21cd93STycho Nightingale #define NCR_SIZE_0K 0 1036bf21cd93STycho Nightingale #define NCR_SIZE_4K 1 1037bf21cd93STycho Nightingale #define NCR_SIZE_8K 2 1038bf21cd93STycho Nightingale #define NCR_SIZE_16K 3 1039bf21cd93STycho Nightingale #define NCR_SIZE_32K 4 1040bf21cd93STycho Nightingale #define NCR_SIZE_64K 5 1041bf21cd93STycho Nightingale #define NCR_SIZE_128K 6 1042bf21cd93STycho Nightingale #define NCR_SIZE_256K 7 1043bf21cd93STycho Nightingale #define NCR_SIZE_512K 8 1044bf21cd93STycho Nightingale #define NCR_SIZE_1M 9 1045bf21cd93STycho Nightingale #define NCR_SIZE_2M 10 1046bf21cd93STycho Nightingale #define NCR_SIZE_4M 11 1047bf21cd93STycho Nightingale #define NCR_SIZE_8M 12 1048bf21cd93STycho Nightingale #define NCR_SIZE_16M 13 1049bf21cd93STycho Nightingale #define NCR_SIZE_32M 14 1050bf21cd93STycho Nightingale #define NCR_SIZE_4G 15 1051bf21cd93STycho Nightingale 1052bf21cd93STycho Nightingale /* 1053bf21cd93STycho Nightingale * The address region registers are used to specify the location and 1054bf21cd93STycho Nightingale * size for the eight address regions. 1055bf21cd93STycho Nightingale * 1056bf21cd93STycho Nightingale * ARRx + 0: A31-A24 of start address 1057bf21cd93STycho Nightingale * ARRx + 1: A23-A16 of start address 1058bf21cd93STycho Nightingale * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 1059bf21cd93STycho Nightingale */ 1060bf21cd93STycho Nightingale #define ARR0 0xc4 1061bf21cd93STycho Nightingale #define ARR1 0xc7 1062bf21cd93STycho Nightingale #define ARR2 0xca 1063bf21cd93STycho Nightingale #define ARR3 0xcd 1064bf21cd93STycho Nightingale #define ARR4 0xd0 1065bf21cd93STycho Nightingale #define ARR5 0xd3 1066bf21cd93STycho Nightingale #define ARR6 0xd6 1067bf21cd93STycho Nightingale #define ARR7 0xd9 1068bf21cd93STycho Nightingale 1069bf21cd93STycho Nightingale #define ARR_SIZE_0K 0 1070bf21cd93STycho Nightingale #define ARR_SIZE_4K 1 1071bf21cd93STycho Nightingale #define ARR_SIZE_8K 2 1072bf21cd93STycho Nightingale #define ARR_SIZE_16K 3 1073bf21cd93STycho Nightingale #define ARR_SIZE_32K 4 1074bf21cd93STycho Nightingale #define ARR_SIZE_64K 5 1075bf21cd93STycho Nightingale #define ARR_SIZE_128K 6 1076bf21cd93STycho Nightingale #define ARR_SIZE_256K 7 1077bf21cd93STycho Nightingale #define ARR_SIZE_512K 8 1078bf21cd93STycho Nightingale #define ARR_SIZE_1M 9 1079bf21cd93STycho Nightingale #define ARR_SIZE_2M 10 1080bf21cd93STycho Nightingale #define ARR_SIZE_4M 11 1081bf21cd93STycho Nightingale #define ARR_SIZE_8M 12 1082bf21cd93STycho Nightingale #define ARR_SIZE_16M 13 1083bf21cd93STycho Nightingale #define ARR_SIZE_32M 14 1084bf21cd93STycho Nightingale #define ARR_SIZE_4G 15 1085bf21cd93STycho Nightingale 1086bf21cd93STycho Nightingale /* 1087bf21cd93STycho Nightingale * The region control registers specify the attributes associated with 1088bf21cd93STycho Nightingale * the ARRx addres regions. 1089bf21cd93STycho Nightingale */ 1090bf21cd93STycho Nightingale #define RCR0 0xdc 1091bf21cd93STycho Nightingale #define RCR1 0xdd 1092bf21cd93STycho Nightingale #define RCR2 0xde 1093bf21cd93STycho Nightingale #define RCR3 0xdf 1094bf21cd93STycho Nightingale #define RCR4 0xe0 1095bf21cd93STycho Nightingale #define RCR5 0xe1 1096bf21cd93STycho Nightingale #define RCR6 0xe2 1097bf21cd93STycho Nightingale #define RCR7 0xe3 1098bf21cd93STycho Nightingale 1099bf21cd93STycho Nightingale #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 1100bf21cd93STycho Nightingale #define RCR_RCE 0x01 /* Enables caching for ARR7. */ 1101bf21cd93STycho Nightingale #define RCR_WWO 0x02 /* Weak write ordering. */ 1102bf21cd93STycho Nightingale #define RCR_WL 0x04 /* Weak locking. */ 1103bf21cd93STycho Nightingale #define RCR_WG 0x08 /* Write gathering. */ 1104bf21cd93STycho Nightingale #define RCR_WT 0x10 /* Write-through. */ 1105bf21cd93STycho Nightingale #define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 1106bf21cd93STycho Nightingale 1107bf21cd93STycho Nightingale /* AMD Write Allocate Top-Of-Memory and Control Register */ 1108bf21cd93STycho Nightingale #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 1109bf21cd93STycho Nightingale #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 1110bf21cd93STycho Nightingale #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 1111bf21cd93STycho Nightingale 1112bf21cd93STycho Nightingale /* AMD64 MSR's */ 1113bf21cd93STycho Nightingale #define MSR_EFER 0xc0000080 /* extended features */ 1114bf21cd93STycho Nightingale #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */ 1115bf21cd93STycho Nightingale #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */ 1116bf21cd93STycho Nightingale #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */ 1117bf21cd93STycho Nightingale #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */ 1118bf21cd93STycho Nightingale #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */ 1119bf21cd93STycho Nightingale #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */ 1120bf21cd93STycho Nightingale #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */ 11214c87aefeSPatrick Mooney #define MSR_TSC_AUX 0xc0000103 1122bf21cd93STycho Nightingale #define MSR_PERFEVSEL0 0xc0010000 1123bf21cd93STycho Nightingale #define MSR_PERFEVSEL1 0xc0010001 1124bf21cd93STycho Nightingale #define MSR_PERFEVSEL2 0xc0010002 1125bf21cd93STycho Nightingale #define MSR_PERFEVSEL3 0xc0010003 1126bf21cd93STycho Nightingale #define MSR_K7_PERFCTR0 0xc0010004 1127bf21cd93STycho Nightingale #define MSR_K7_PERFCTR1 0xc0010005 1128bf21cd93STycho Nightingale #define MSR_K7_PERFCTR2 0xc0010006 1129bf21cd93STycho Nightingale #define MSR_K7_PERFCTR3 0xc0010007 1130bf21cd93STycho Nightingale #define MSR_SYSCFG 0xc0010010 1131bf21cd93STycho Nightingale #define MSR_HWCR 0xc0010015 1132bf21cd93STycho Nightingale #define MSR_IORRBASE0 0xc0010016 1133bf21cd93STycho Nightingale #define MSR_IORRMASK0 0xc0010017 1134bf21cd93STycho Nightingale #define MSR_IORRBASE1 0xc0010018 1135bf21cd93STycho Nightingale #define MSR_IORRMASK1 0xc0010019 1136bf21cd93STycho Nightingale #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ 1137bf21cd93STycho Nightingale #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ 1138bf21cd93STycho Nightingale #define MSR_NB_CFG1 0xc001001f /* NB configuration 1 */ 11394c87aefeSPatrick Mooney #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ 11404c87aefeSPatrick Mooney #define MSR_MC0_CTL_MASK 0xc0010044 114159d65d31SAndy Fiddaman #define MSR_AMDK8_IPM 0xc0010055 1142bf21cd93STycho Nightingale #define MSR_P_STATE_LIMIT 0xc0010061 /* P-state Current Limit Register */ 1143bf21cd93STycho Nightingale #define MSR_P_STATE_CONTROL 0xc0010062 /* P-state Control Register */ 1144bf21cd93STycho Nightingale #define MSR_P_STATE_STATUS 0xc0010063 /* P-state Status Register */ 1145bf21cd93STycho Nightingale #define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */ 1146bf21cd93STycho Nightingale #define MSR_SMM_ADDR 0xc0010112 /* SMM TSEG base address */ 1147bf21cd93STycho Nightingale #define MSR_SMM_MASK 0xc0010113 /* SMM TSEG address mask */ 11484c87aefeSPatrick Mooney #define MSR_VM_CR 0xc0010114 /* SVM: feature control */ 11494c87aefeSPatrick Mooney #define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */ 1150*717646f7SJordan Paige Hendricks #define MSR_AMD_TSC_RATIO 0xc0000104 /* SVM TSC Ratio */ 11514c87aefeSPatrick Mooney #define MSR_AMD_CPUID07 0xc0011002 /* CPUID 07 %ebx override */ 11524c87aefeSPatrick Mooney #define MSR_EXTFEATURES 0xc0011005 /* Extended CPUID Features override */ 11534c87aefeSPatrick Mooney #define MSR_LS_CFG 0xc0011020 1154bf21cd93STycho Nightingale #define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */ 1155425a8337SPatrick Mooney #define MSR_DE_CFG 0xc0011029 /* Decode Configuration */ 1156bf21cd93STycho Nightingale 1157bf21cd93STycho Nightingale /* MSR_VM_CR related */ 1158bf21cd93STycho Nightingale #define VM_CR_SVMDIS 0x10 /* SVM: disabled by BIOS */ 1159bf21cd93STycho Nightingale 116059d65d31SAndy Fiddaman #define AMDK8_SMIONCMPHALT (1ULL << 27) 116159d65d31SAndy Fiddaman #define AMDK8_C1EONCMPHALT (1ULL << 28) 116259d65d31SAndy Fiddaman 1163bf21cd93STycho Nightingale /* VIA ACE crypto featureset: for via_feature_rng */ 1164bf21cd93STycho Nightingale #define VIA_HAS_RNG 1 /* cpu has RNG */ 1165bf21cd93STycho Nightingale 1166bf21cd93STycho Nightingale /* VIA ACE crypto featureset: for via_feature_xcrypt */ 1167bf21cd93STycho Nightingale #define VIA_HAS_AES 1 /* cpu has AES */ 1168bf21cd93STycho Nightingale #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 1169bf21cd93STycho Nightingale #define VIA_HAS_MM 4 /* cpu has RSA instructions */ 1170bf21cd93STycho Nightingale #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 1171bf21cd93STycho Nightingale 1172bf21cd93STycho Nightingale /* Centaur Extended Feature flags */ 1173bf21cd93STycho Nightingale #define VIA_CPUID_HAS_RNG 0x000004 1174bf21cd93STycho Nightingale #define VIA_CPUID_DO_RNG 0x000008 1175bf21cd93STycho Nightingale #define VIA_CPUID_HAS_ACE 0x000040 1176bf21cd93STycho Nightingale #define VIA_CPUID_DO_ACE 0x000080 1177bf21cd93STycho Nightingale #define VIA_CPUID_HAS_ACE2 0x000100 1178bf21cd93STycho Nightingale #define VIA_CPUID_DO_ACE2 0x000200 1179bf21cd93STycho Nightingale #define VIA_CPUID_HAS_PHE 0x000400 1180bf21cd93STycho Nightingale #define VIA_CPUID_DO_PHE 0x000800 1181bf21cd93STycho Nightingale #define VIA_CPUID_HAS_PMM 0x001000 1182bf21cd93STycho Nightingale #define VIA_CPUID_DO_PMM 0x002000 1183bf21cd93STycho Nightingale 1184bf21cd93STycho Nightingale /* VIA ACE xcrypt-* instruction context control options */ 1185bf21cd93STycho Nightingale #define VIA_CRYPT_CWLO_ROUND_M 0x0000000f 1186bf21cd93STycho Nightingale #define VIA_CRYPT_CWLO_ALG_M 0x00000070 1187bf21cd93STycho Nightingale #define VIA_CRYPT_CWLO_ALG_AES 0x00000000 1188bf21cd93STycho Nightingale #define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 1189bf21cd93STycho Nightingale #define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 1190bf21cd93STycho Nightingale #define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 1191bf21cd93STycho Nightingale #define VIA_CRYPT_CWLO_NORMAL 0x00000000 1192bf21cd93STycho Nightingale #define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 1193bf21cd93STycho Nightingale #define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 1194bf21cd93STycho Nightingale #define VIA_CRYPT_CWLO_DECRYPT 0x00000200 1195bf21cd93STycho Nightingale #define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 1196bf21cd93STycho Nightingale #define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 1197bf21cd93STycho Nightingale #define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 1198bf21cd93STycho Nightingale 1199bf21cd93STycho Nightingale #endif /* !_MACHINE_SPECIALREG_H_ */ 1200