1bf21cd93STycho Nightingale /*- 2bf21cd93STycho Nightingale * Copyright (c) 1993 The Regents of the University of California. 3bf21cd93STycho Nightingale * All rights reserved. 4bf21cd93STycho Nightingale * 5bf21cd93STycho Nightingale * Redistribution and use in source and binary forms, with or without 6bf21cd93STycho Nightingale * modification, are permitted provided that the following conditions 7bf21cd93STycho Nightingale * are met: 8bf21cd93STycho Nightingale * 1. Redistributions of source code must retain the above copyright 9bf21cd93STycho Nightingale * notice, this list of conditions and the following disclaimer. 10bf21cd93STycho Nightingale * 2. Redistributions in binary form must reproduce the above copyright 11bf21cd93STycho Nightingale * notice, this list of conditions and the following disclaimer in the 12bf21cd93STycho Nightingale * documentation and/or other materials provided with the distribution. 13bf21cd93STycho Nightingale * 4. Neither the name of the University nor the names of its contributors 14bf21cd93STycho Nightingale * may be used to endorse or promote products derived from this software 15bf21cd93STycho Nightingale * without specific prior written permission. 16bf21cd93STycho Nightingale * 17bf21cd93STycho Nightingale * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18bf21cd93STycho Nightingale * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19bf21cd93STycho Nightingale * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20bf21cd93STycho Nightingale * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21bf21cd93STycho Nightingale * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22bf21cd93STycho Nightingale * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23bf21cd93STycho Nightingale * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24bf21cd93STycho Nightingale * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25bf21cd93STycho Nightingale * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26bf21cd93STycho Nightingale * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27bf21cd93STycho Nightingale * SUCH DAMAGE. 28bf21cd93STycho Nightingale * 29bf21cd93STycho Nightingale * from: Header: timerreg.h,v 1.2 93/02/28 15:08:58 mccanne Exp 30bf21cd93STycho Nightingale * $FreeBSD: head/sys/dev/ic/i8253reg.h 146215 2005-05-14 10:26:31Z nyan $ 31bf21cd93STycho Nightingale */ 32bf21cd93STycho Nightingale 33bf21cd93STycho Nightingale /* 34bf21cd93STycho Nightingale * Register definitions for the Intel 8253 Programmable Interval Timer. 35bf21cd93STycho Nightingale * 36bf21cd93STycho Nightingale * This chip has three independent 16-bit down counters that can be 37bf21cd93STycho Nightingale * read on the fly. There are three mode registers and three countdown 38bf21cd93STycho Nightingale * registers. The countdown registers are addressed directly, via the 39bf21cd93STycho Nightingale * first three I/O ports. The three mode registers are accessed via 40bf21cd93STycho Nightingale * the fourth I/O port, with two bits in the mode byte indicating the 41bf21cd93STycho Nightingale * register. (Why are hardware interfaces always so braindead?). 42bf21cd93STycho Nightingale * 43bf21cd93STycho Nightingale * To write a value into the countdown register, the mode register 44bf21cd93STycho Nightingale * is first programmed with a command indicating the which byte of 45bf21cd93STycho Nightingale * the two byte register is to be modified. The three possibilities 46bf21cd93STycho Nightingale * are load msb (TMR_MR_MSB), load lsb (TMR_MR_LSB), or load lsb then 47bf21cd93STycho Nightingale * msb (TMR_MR_BOTH). 48bf21cd93STycho Nightingale * 49bf21cd93STycho Nightingale * To read the current value ("on the fly") from the countdown register, 50bf21cd93STycho Nightingale * you write a "latch" command into the mode register, then read the stable 51bf21cd93STycho Nightingale * value from the corresponding I/O port. For example, you write 52bf21cd93STycho Nightingale * TMR_MR_LATCH into the corresponding mode register. Presumably, 53bf21cd93STycho Nightingale * after doing this, a write operation to the I/O port would result 54bf21cd93STycho Nightingale * in undefined behavior (but hopefully not fry the chip). 55bf21cd93STycho Nightingale * Reading in this manner has no side effects. 56bf21cd93STycho Nightingale */ 57bf21cd93STycho Nightingale 58bf21cd93STycho Nightingale /* 59bf21cd93STycho Nightingale * Macros for specifying values to be written into a mode register. 60bf21cd93STycho Nightingale */ 61bf21cd93STycho Nightingale #define TIMER_REG_CNTR0 0 /* timer 0 counter port */ 62bf21cd93STycho Nightingale #define TIMER_REG_CNTR1 1 /* timer 1 counter port */ 63bf21cd93STycho Nightingale #define TIMER_REG_CNTR2 2 /* timer 2 counter port */ 64bf21cd93STycho Nightingale #define TIMER_REG_MODE 3 /* timer mode port */ 65bf21cd93STycho Nightingale #define TIMER_SEL0 0x00 /* select counter 0 */ 66bf21cd93STycho Nightingale #define TIMER_SEL1 0x40 /* select counter 1 */ 67bf21cd93STycho Nightingale #define TIMER_SEL2 0x80 /* select counter 2 */ 68bf21cd93STycho Nightingale #define TIMER_INTTC 0x00 /* mode 0, intr on terminal cnt */ 69bf21cd93STycho Nightingale #define TIMER_ONESHOT 0x02 /* mode 1, one shot */ 70bf21cd93STycho Nightingale #define TIMER_RATEGEN 0x04 /* mode 2, rate generator */ 71bf21cd93STycho Nightingale #define TIMER_SQWAVE 0x06 /* mode 3, square wave */ 72bf21cd93STycho Nightingale #define TIMER_SWSTROBE 0x08 /* mode 4, s/w triggered strobe */ 73bf21cd93STycho Nightingale #define TIMER_HWSTROBE 0x0a /* mode 5, h/w triggered strobe */ 74bf21cd93STycho Nightingale #define TIMER_LATCH 0x00 /* latch counter for reading */ 75bf21cd93STycho Nightingale #define TIMER_LSB 0x10 /* r/w counter LSB */ 76bf21cd93STycho Nightingale #define TIMER_MSB 0x20 /* r/w counter MSB */ 77bf21cd93STycho Nightingale #define TIMER_16BIT 0x30 /* r/w counter 16 bits, LSB first */ 78bf21cd93STycho Nightingale #define TIMER_BCD 0x01 /* count in BCD */ 79