1 /*
2  *
3  * CDDL HEADER START
4  *
5  * The contents of this file are subject to the terms of the
6  * Common Development and Distribution License (the "License").
7  * You may not use this file except in compliance with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
24  * Copyright 2016 Joyent, Inc.
25  */
26 
27 /*
28  * Copyright (c) 2010, Intel Corporation.
29  * All rights reserved.
30  */
31 
32 /*	Copyright (c) 1988 AT&T	*/
33 /*	  All Rights Reserved  	*/
34 
35 #include	"dis_tables.h"
36 
37 /* BEGIN CSTYLED */
38 
39 /*
40  * Disassembly begins in dis_distable, which is equivalent to the One-byte
41  * Opcode Map in the Intel IA32 ISA Reference (page A-6 in my copy).  The
42  * decoding loops then traverse out through the other tables as necessary to
43  * decode a given instruction.
44  *
45  * The behavior of this file can be controlled by one of the following flags:
46  *
47  * 	DIS_TEXT	Include text for disassembly
48  * 	DIS_MEM		Include memory-size calculations
49  *
50  * Either or both of these can be defined.
51  *
52  * This file is not, and will never be, cstyled.  If anything, the tables should
53  * be taken out another tab stop or two so nothing overlaps.
54  */
55 
56 /*
57  * These functions must be provided for the consumer to do disassembly.
58  */
59 #ifdef DIS_TEXT
60 extern char *strncpy(char *, const char *, size_t);
61 extern size_t strlen(const char *);
62 extern int strcmp(const char *, const char *);
63 extern int strncmp(const char *, const char *, size_t);
64 extern size_t strlcat(char *, const char *, size_t);
65 #endif
66 
67 
68 #define		TERM 	0	/* used to indicate that the 'indirect' */
69 				/* field terminates - no pointer.	*/
70 
71 /* Used to decode instructions. */
72 typedef struct	instable {
73 	struct instable	*it_indirect;	/* for decode op codes */
74 	uchar_t		it_adrmode;
75 #ifdef DIS_TEXT
76 	char		it_name[NCPS];
77 	uint_t		it_suffix:1;		/* mnem + "w", "l", or "d" */
78 #endif
79 #ifdef DIS_MEM
80 	uint_t		it_size:16;
81 #endif
82 	uint_t		it_invalid64:1;		/* opcode invalid in amd64 */
83 	uint_t		it_always64:1;		/* 64 bit when in 64 bit mode */
84 	uint_t		it_invalid32:1;		/* invalid in IA32 */
85 	uint_t		it_stackop:1;		/* push/pop stack operation */
86 	uint_t		it_vexwoxmm:1;		/* VEX instructions that don't use XMM/YMM */
87 	uint_t		it_avxsuf:1;		/* AVX suffix required */
88 } instable_t;
89 
90 /*
91  * Instruction formats.
92  */
93 enum {
94 	UNKNOWN,
95 	MRw,
96 	IMlw,
97 	IMw,
98 	IR,
99 	OA,
100 	AO,
101 	MS,
102 	SM,
103 	Mv,
104 	Mw,
105 	M,		/* register or memory */
106 	MG9,		/* register or memory in group 9 (prefix optional) */
107 	Mb,		/* register or memory, always byte sized */
108 	MO,		/* memory only (no registers) */
109 	PREF,
110 	SWAPGS_RDTSCP,
111 	MONITOR_MWAIT,
112 	R,
113 	RA,
114 	SEG,
115 	MR,
116 	RM,
117 	RM_66r,		/* RM, but with a required 0x66 prefix */
118 	IA,
119 	MA,
120 	SD,
121 	AD,
122 	SA,
123 	D,
124 	INM,
125 	SO,
126 	BD,
127 	I,
128 	P,
129 	V,
130 	DSHIFT,		/* for double shift that has an 8-bit immediate */
131 	U,
132 	OVERRIDE,
133 	NORM,		/* instructions w/o ModR/M byte, no memory access */
134 	IMPLMEM,	/* instructions w/o ModR/M byte, implicit mem access */
135 	O,		/* for call	*/
136 	JTAB,		/* jump table 	*/
137 	IMUL,		/* for 186 iimul instr  */
138 	CBW,		/* so data16 can be evaluated for cbw and variants */
139 	MvI,		/* for 186 logicals */
140 	ENTER,		/* for 186 enter instr  */
141 	RMw,		/* for 286 arpl instr */
142 	Ib,		/* for push immediate byte */
143 	F,		/* for 287 instructions */
144 	FF,		/* for 287 instructions */
145 	FFC,		/* for 287 instructions */
146 	DM,		/* 16-bit data */
147 	AM,		/* 16-bit addr */
148 	LSEG,		/* for 3-bit seg reg encoding */
149 	MIb,		/* for 386 logicals */
150 	SREG,		/* for 386 special registers */
151 	PREFIX,		/* a REP instruction prefix */
152 	LOCK,		/* a LOCK instruction prefix */
153 	INT3,		/* The int 3 instruction, which has a fake operand */
154 	INTx,		/* The normal int instruction, with explicit int num */
155 	DSHIFTcl,	/* for double shift that implicitly uses %cl */
156 	CWD,		/* so data16 can be evaluated for cwd and variants */
157 	RET,		/* single immediate 16-bit operand */
158 	MOVZ,		/* for movs and movz, with different size operands */
159 	CRC32,		/* for crc32, with different size operands */
160 	XADDB,		/* for xaddb */
161 	MOVSXZ,		/* AMD64 mov sign extend 32 to 64 bit instruction */
162 	MOVBE,		/* movbe instruction */
163 
164 /*
165  * MMX/SIMD addressing modes.
166  */
167 
168 	MMO,		/* Prefixable MMX/SIMD-Int	mm/mem	-> mm */
169 	MMOIMPL,	/* Prefixable MMX/SIMD-Int	mm	-> mm (mem) */
170 	MMO3P,		/* Prefixable MMX/SIMD-Int	mm	-> r32,imm8 */
171 	MMOM3,		/* Prefixable MMX/SIMD-Int	mm	-> r32 	*/
172 	MMOS,		/* Prefixable MMX/SIMD-Int	mm	-> mm/mem */
173 	MMOMS,		/* Prefixable MMX/SIMD-Int	mm	-> mem */
174 	MMOPM,		/* MMX/SIMD-Int			mm/mem	-> mm,imm8 */
175 	MMOPM_66o,	/* MMX/SIMD-Int 0x66 optional	mm/mem	-> mm,imm8 */
176 	MMOPRM,		/* Prefixable MMX/SIMD-Int	r32/mem	-> mm,imm8 */
177 	MMOSH,		/* Prefixable MMX		mm,imm8	*/
178 	MM,		/* MMX/SIMD-Int			mm/mem	-> mm	*/
179 	MMS,		/* MMX/SIMD-Int			mm	-> mm/mem */
180 	MMSH,		/* MMX				mm,imm8 */
181 	XMMO,		/* Prefixable SIMD		xmm/mem	-> xmm */
182 	XMMOS,		/* Prefixable SIMD		xmm	-> xmm/mem */
183 	XMMOPM,		/* Prefixable SIMD		xmm/mem	w/to xmm,imm8 */
184 	XMMOMX,		/* Prefixable SIMD		mm/mem	-> xmm */
185 	XMMOX3,		/* Prefixable SIMD		xmm	-> r32 */
186 	XMMOXMM,	/* Prefixable SIMD		xmm/mem	-> mm	*/
187 	XMMOM,		/* Prefixable SIMD		xmm	-> mem */
188 	XMMOMS,		/* Prefixable SIMD		mem	-> xmm */
189 	XMM,		/* SIMD 			xmm/mem	-> xmm */
190 	XMM_66r,	/* SIMD 0x66 prefix required	xmm/mem	-> xmm */
191 	XMM_66o,	/* SIMD 0x66 prefix optional 	xmm/mem	-> xmm */
192 	XMMXIMPL,	/* SIMD				xmm	-> xmm (mem) */
193 	XMM3P,		/* SIMD				xmm	-> r32,imm8 */
194 	XMM3PM_66r,	/* SIMD 0x66 prefix required	xmm	-> r32/mem,imm8 */
195 	XMMP,		/* SIMD 			xmm/mem w/to xmm,imm8 */
196 	XMMP_66o,	/* SIMD 0x66 prefix optional	xmm/mem w/to xmm,imm8 */
197 	XMMP_66r,	/* SIMD 0x66 prefix required	xmm/mem w/to xmm,imm8 */
198 	XMMPRM,		/* SIMD 			r32/mem -> xmm,imm8 */
199 	XMMPRM_66r,	/* SIMD 0x66 prefix required	r32/mem -> xmm,imm8 */
200 	XMMS,		/* SIMD				xmm	-> xmm/mem */
201 	XMMM,		/* SIMD 			mem	-> xmm */
202 	XMMM_66r,	/* SIMD	0x66 prefix required	mem	-> xmm */
203 	XMMMS,		/* SIMD				xmm	-> mem */
204 	XMM3MX,		/* SIMD 			r32/mem -> xmm */
205 	XMM3MXS,	/* SIMD 			xmm	-> r32/mem */
206 	XMMSH,		/* SIMD 			xmm,imm8 */
207 	XMMXM3,		/* SIMD 			xmm/mem -> r32 */
208 	XMMX3,		/* SIMD 			xmm	-> r32 */
209 	XMMXMM,		/* SIMD 			xmm/mem	-> mm */
210 	XMMMX,		/* SIMD 			mm	-> xmm */
211 	XMMXM,		/* SIMD 			xmm	-> mm */
212         XMMX2I,		/* SIMD				xmm -> xmm, imm, imm */
213         XMM2I,		/* SIMD				xmm, imm, imm */
214 	XMMFENCE,	/* SIMD lfence or mfence */
215 	XMMSFNC,	/* SIMD sfence (none or mem) */
216 	XGETBV_XSETBV,
217 	VEX_NONE,	/* VEX  no operand */
218 	VEX_MO,		/* VEX	mod_rm		               -> implicit reg */
219 	VEX_RMrX,	/* VEX  VEX.vvvv, mod_rm               -> mod_reg */
220 	VEX_VRMrX,	/* VEX  mod_rm, VEX.vvvv               -> mod_rm */
221 	VEX_RRX,	/* VEX  VEX.vvvv, mod_reg              -> mod_rm */
222 	VEX_RMRX,	/* VEX  VEX.vvvv, mod_rm, imm8[7:4]    -> mod_reg */
223 	VEX_MX,         /* VEX  mod_rm                         -> mod_reg */
224 	VEX_MXI,        /* VEX  mod_rm, imm8                   -> mod_reg */
225 	VEX_XXI,        /* VEX  mod_rm, imm8                   -> VEX.vvvv */
226 	VEX_MR,         /* VEX  mod_rm                         -> mod_reg */
227 	VEX_RRI,        /* VEX  mod_reg, mod_rm                -> implicit(eflags/r32) */
228 	VEX_RX,         /* VEX  mod_reg                        -> mod_rm */
229 	VEX_RR,         /* VEX  mod_rm                         -> mod_reg */
230 	VEX_RRi,        /* VEX  mod_rm, imm8                   -> mod_reg */
231 	VEX_RM,         /* VEX  mod_reg                        -> mod_rm */
232 	VEX_RIM,	/* VEX  mod_reg, imm8                  -> mod_rm */
233 	VEX_RRM,        /* VEX  VEX.vvvv, mod_reg              -> mod_rm */
234 	VEX_RMX,        /* VEX  VEX.vvvv, mod_rm               -> mod_reg */
235 	VEX_SbVM,	/* VEX  SIB, VEX.vvvv                  -> mod_rm */
236 	VMx,		/* vmcall/vmlaunch/vmresume/vmxoff */
237 	VMxo,		/* VMx instruction with optional prefix */
238 	SVM,		/* AMD SVM instructions */
239 	BLS,		/* BLSR, BLSMSK, BLSI */
240 	FMA,		/* FMA instructions, all VEX_RMrX */
241 	ADX		/* ADX instructions, support REX.w, mod_rm->mod_reg */
242 };
243 
244 /*
245  * VEX prefixes
246  */
247 #define VEX_2bytes	0xC5	/* the first byte of two-byte form */
248 #define VEX_3bytes	0xC4	/* the first byte of three-byte form */
249 
250 #define	FILL	0x90	/* Fill byte used for alignment (nop)	*/
251 
252 /*
253 ** Register numbers for the i386
254 */
255 #define	EAX_REGNO 0
256 #define	ECX_REGNO 1
257 #define	EDX_REGNO 2
258 #define	EBX_REGNO 3
259 #define	ESP_REGNO 4
260 #define	EBP_REGNO 5
261 #define	ESI_REGNO 6
262 #define	EDI_REGNO 7
263 
264 /*
265  * modes for immediate values
266  */
267 #define	MODE_NONE	0
268 #define	MODE_IPREL	1	/* signed IP relative value */
269 #define	MODE_SIGNED	2	/* sign extended immediate */
270 #define	MODE_IMPLIED	3	/* constant value implied from opcode */
271 #define	MODE_OFFSET	4	/* offset part of an address */
272 #define	MODE_RIPREL	5	/* like IPREL, but from %rip (amd64) */
273 
274 /*
275  * The letters used in these macros are:
276  *   IND - indirect to another to another table
277  *   "T" - means to Terminate indirections (this is the final opcode)
278  *   "S" - means "operand length suffix required"
279  *   "Sa" - means AVX2 suffix (d/q) required
280  *   "NS" - means "no suffix" which is the operand length suffix of the opcode
281  *   "Z" - means instruction size arg required
282  *   "u" - means the opcode is invalid in IA32 but valid in amd64
283  *   "x" - means the opcode is invalid in amd64, but not IA32
284  *   "y" - means the operand size is always 64 bits in 64 bit mode
285  *   "p" - means push/pop stack operation
286  *   "vr" - means VEX instruction that operates on normal registers, not fpu
287  */
288 
289 #if defined(DIS_TEXT) && defined(DIS_MEM)
290 #define	IND(table)		{(instable_t *)table, 0, "", 0, 0, 0, 0, 0, 0}
291 #define	INDx(table)		{(instable_t *)table, 0, "", 0, 0, 1, 0, 0, 0}
292 #define	TNS(name, amode)	{TERM, amode, name, 0, 0, 0, 0, 0, 0}
293 #define	TNSu(name, amode)	{TERM, amode, name, 0, 0, 0, 0, 1, 0}
294 #define	TNSx(name, amode)	{TERM, amode, name, 0, 0, 1, 0, 0, 0}
295 #define	TNSy(name, amode)	{TERM, amode, name, 0, 0, 0, 1, 0, 0}
296 #define	TNSyp(name, amode)	{TERM, amode, name, 0, 0, 0, 1, 0, 1}
297 #define	TNSZ(name, amode, sz)	{TERM, amode, name, 0, sz, 0, 0, 0, 0}
298 #define	TNSZy(name, amode, sz)	{TERM, amode, name, 0, sz, 0, 1, 0, 0}
299 #define	TNSZvr(name, amode, sz)	{TERM, amode, name, 0, sz, 0, 0, 0, 0, 1}
300 #define	TS(name, amode)		{TERM, amode, name, 1, 0, 0, 0, 0, 0}
301 #define	TSx(name, amode)	{TERM, amode, name, 1, 0, 1, 0, 0, 0}
302 #define	TSy(name, amode)	{TERM, amode, name, 1, 0, 0, 1, 0, 0}
303 #define	TSp(name, amode)	{TERM, amode, name, 1, 0, 0, 0, 0, 1}
304 #define	TSZ(name, amode, sz)	{TERM, amode, name, 1, sz, 0, 0, 0, 0}
305 #define	TSaZ(name, amode, sz)	{TERM, amode, name, 1, sz, 0, 0, 0, 0, 0, 1}
306 #define	TSZx(name, amode, sz)	{TERM, amode, name, 1, sz, 1, 0, 0, 0}
307 #define	TSZy(name, amode, sz)	{TERM, amode, name, 1, sz, 0, 1, 0, 0}
308 #define	INVALID			{TERM, UNKNOWN, "", 0, 0, 0, 0, 0}
309 #elif defined(DIS_TEXT)
310 #define	IND(table)		{(instable_t *)table, 0, "", 0, 0, 0, 0, 0}
311 #define	INDx(table)		{(instable_t *)table, 0, "", 0, 1, 0, 0, 0}
312 #define	TNS(name, amode)	{TERM, amode, name, 0, 0, 0, 0, 0}
313 #define	TNSu(name, amode)	{TERM, amode, name, 0, 0, 0, 1, 0}
314 #define	TNSx(name, amode)	{TERM, amode, name, 0, 1, 0, 0, 0}
315 #define	TNSy(name, amode)	{TERM, amode, name, 0, 0, 1, 0, 0}
316 #define	TNSyp(name, amode)	{TERM, amode, name, 0, 0, 1, 0, 1}
317 #define	TNSZ(name, amode, sz)	{TERM, amode, name, 0, 0, 0, 0, 0}
318 #define	TNSZy(name, amode, sz)	{TERM, amode, name, 0, 0, 1, 0, 0}
319 #define	TNSZvr(name, amode, sz)	{TERM, amode, name, 0, 0, 0, 0, 0, 1}
320 #define	TS(name, amode)		{TERM, amode, name, 1, 0, 0, 0, 0}
321 #define	TSx(name, amode)	{TERM, amode, name, 1, 1, 0, 0, 0}
322 #define	TSy(name, amode)	{TERM, amode, name, 1, 0, 1, 0, 0}
323 #define	TSp(name, amode)	{TERM, amode, name, 1, 0, 0, 0, 1}
324 #define	TSZ(name, amode, sz)	{TERM, amode, name, 1, 0, 0, 0, 0}
325 #define	TSaZ(name, amode, sz)	{TERM, amode, name, 1, 0, 0, 0, 0, 0, 1}
326 #define	TSZx(name, amode, sz)	{TERM, amode, name, 1, 1, 0, 0, 0}
327 #define	TSZy(name, amode, sz)	{TERM, amode, name, 1, 0, 1, 0, 0}
328 #define	INVALID			{TERM, UNKNOWN, "", 0, 0, 0, 0, 0}
329 #elif defined(DIS_MEM)
330 #define	IND(table)		{(instable_t *)table, 0, 0, 0, 0, 0, 0}
331 #define	INDx(table)		{(instable_t *)table, 0, 0, 1, 0, 0, 0}
332 #define	TNS(name, amode)	{TERM, amode,  0, 0, 0, 0, 0}
333 #define	TNSu(name, amode)	{TERM, amode,  0, 0, 0, 1, 0}
334 #define	TNSy(name, amode)	{TERM, amode,  0, 0, 1, 0, 0}
335 #define	TNSyp(name, amode)	{TERM, amode,  0, 0, 1, 0, 1}
336 #define	TNSx(name, amode)	{TERM, amode,  0, 1, 0, 0, 0}
337 #define	TNSZ(name, amode, sz)	{TERM, amode, sz, 0, 0, 0, 0}
338 #define	TNSZy(name, amode, sz)	{TERM, amode, sz, 0, 1, 0, 0}
339 #define	TNSZvr(name, amode, sz)	{TERM, amode, sz, 0, 0, 0, 0, 1}
340 #define	TS(name, amode)		{TERM, amode,  0, 0, 0, 0, 0}
341 #define	TSx(name, amode)	{TERM, amode,  0, 1, 0, 0, 0}
342 #define	TSy(name, amode)	{TERM, amode,  0, 0, 1, 0, 0}
343 #define	TSp(name, amode)	{TERM, amode,  0, 0, 0, 0, 1}
344 #define	TSZ(name, amode, sz)	{TERM, amode, sz, 0, 0, 0, 0}
345 #define	TSaZ(name, amode, sz)	{TERM, amode, sz, 0, 0, 0, 0, 0, 1}
346 #define	TSZx(name, amode, sz)	{TERM, amode, sz, 1, 0, 0, 0}
347 #define	TSZy(name, amode, sz)	{TERM, amode, sz, 0, 1, 0, 0}
348 #define	INVALID			{TERM, UNKNOWN, 0, 0, 0, 0, 0}
349 #else
350 #define	IND(table)		{(instable_t *)table, 0, 0, 0, 0, 0}
351 #define	INDx(table)		{(instable_t *)table, 0, 1, 0, 0, 0}
352 #define	TNS(name, amode)	{TERM, amode,  0, 0, 0, 0}
353 #define	TNSu(name, amode)	{TERM, amode,  0, 0, 1, 0}
354 #define	TNSy(name, amode)	{TERM, amode,  0, 1, 0, 0}
355 #define	TNSyp(name, amode)	{TERM, amode,  0, 1, 0, 1}
356 #define	TNSx(name, amode)	{TERM, amode,  1, 0, 0, 0}
357 #define	TNSZ(name, amode, sz)	{TERM, amode,  0, 0, 0, 0}
358 #define	TNSZy(name, amode, sz)	{TERM, amode,  0, 1, 0, 0}
359 #define	TNSZvr(name, amode, sz)	{TERM, amode,  0, 0, 0, 0, 1}
360 #define	TS(name, amode)		{TERM, amode,  0, 0, 0, 0}
361 #define	TSx(name, amode)	{TERM, amode,  1, 0, 0, 0}
362 #define	TSy(name, amode)	{TERM, amode,  0, 1, 0, 0}
363 #define	TSp(name, amode)	{TERM, amode,  0, 0, 0, 1}
364 #define	TSZ(name, amode, sz)	{TERM, amode,  0, 0, 0, 0}
365 #define	TSaZ(name, amode, sz)	{TERM, amode,  0, 0, 0, 0, 0, 1}
366 #define	TSZx(name, amode, sz)	{TERM, amode,  1, 0, 0, 0}
367 #define	TSZy(name, amode, sz)	{TERM, amode,  0, 1, 0, 0}
368 #define	INVALID			{TERM, UNKNOWN, 0, 0, 0, 0}
369 #endif
370 
371 #ifdef DIS_TEXT
372 /*
373  * this decodes the r_m field for mode's 0, 1, 2 in 16 bit mode
374  */
375 const char *const dis_addr16[3][8] = {
376 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "",
377 									"(%bx)",
378 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di", "(%bp)",
379 									"(%bx)",
380 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "(%bp)",
381 									"(%bx)",
382 };
383 
384 
385 /*
386  * This decodes 32 bit addressing mode r_m field for modes 0, 1, 2
387  */
388 const char *const dis_addr32_mode0[16] = {
389   "(%eax)", "(%ecx)", "(%edx)",  "(%ebx)",  "", "",        "(%esi)",  "(%edi)",
390   "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "",        "(%r14d)", "(%r15d)"
391 };
392 
393 const char *const dis_addr32_mode12[16] = {
394   "(%eax)", "(%ecx)", "(%edx)",  "(%ebx)",  "", "(%ebp)",  "(%esi)",  "(%edi)",
395   "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "(%r13d)", "(%r14d)", "(%r15d)"
396 };
397 
398 /*
399  * This decodes 64 bit addressing mode r_m field for modes 0, 1, 2
400  */
401 const char *const dis_addr64_mode0[16] = {
402  "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "",       "(%rip)", "(%rsi)", "(%rdi)",
403  "(%r8)",  "(%r9)",  "(%r10)", "(%r11)", "(%r12)", "(%rip)", "(%r14)", "(%r15)"
404 };
405 const char *const dis_addr64_mode12[16] = {
406  "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "",       "(%rbp)", "(%rsi)", "(%rdi)",
407  "(%r8)",  "(%r9)",  "(%r10)", "(%r11)", "(%r12)", "(%r13)", "(%r14)", "(%r15)"
408 };
409 
410 /*
411  * decode for scale from SIB byte
412  */
413 const char *const dis_scale_factor[4] = { ")", ",2)", ",4)", ",8)" };
414 
415 /*
416  * decode for scale from VSIB byte, note that we always include the scale factor
417  * to match gas.
418  */
419 const char *const dis_vscale_factor[4] = { ",1)", ",2)", ",4)", ",8)" };
420 
421 /*
422  * register decoding for normal references to registers (ie. not addressing)
423  */
424 const char *const dis_REG8[16] = {
425 	"%al",  "%cl",  "%dl",   "%bl",   "%ah",   "%ch",   "%dh",   "%bh",
426 	"%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
427 };
428 
429 const char *const dis_REG8_REX[16] = {
430 	"%al",  "%cl",  "%dl",   "%bl",   "%spl",  "%bpl",  "%sil",  "%dil",
431 	"%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
432 };
433 
434 const char *const dis_REG16[16] = {
435 	"%ax",  "%cx",  "%dx",   "%bx",   "%sp",   "%bp",   "%si",   "%di",
436 	"%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
437 };
438 
439 const char *const dis_REG32[16] = {
440 	"%eax", "%ecx", "%edx",  "%ebx",  "%esp",  "%ebp",  "%esi",  "%edi",
441 	"%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
442 };
443 
444 const char *const dis_REG64[16] = {
445 	"%rax", "%rcx", "%rdx",  "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
446 	"%r8",  "%r9",  "%r10",  "%r11", "%r12", "%r13", "%r14", "%r15"
447 };
448 
449 const char *const dis_DEBUGREG[16] = {
450 	"%db0", "%db1", "%db2",  "%db3",  "%db4",  "%db5",  "%db6",  "%db7",
451 	"%db8", "%db9", "%db10", "%db11", "%db12", "%db13", "%db14", "%db15"
452 };
453 
454 const char *const dis_CONTROLREG[16] = {
455     "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5?", "%cr6?", "%cr7?",
456     "%cr8", "%cr9?", "%cr10?", "%cr11?", "%cr12?", "%cr13?", "%cr14?", "%cr15?"
457 };
458 
459 const char *const dis_TESTREG[16] = {
460 	"%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7",
461 	"%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7"
462 };
463 
464 const char *const dis_MMREG[16] = {
465 	"%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7",
466 	"%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7"
467 };
468 
469 const char *const dis_XMMREG[16] = {
470     "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7",
471     "%xmm8", "%xmm9", "%xmm10", "%xmm11", "%xmm12", "%xmm13", "%xmm14", "%xmm15"
472 };
473 
474 const char *const dis_YMMREG[16] = {
475     "%ymm0", "%ymm1", "%ymm2", "%ymm3", "%ymm4", "%ymm5", "%ymm6", "%ymm7",
476     "%ymm8", "%ymm9", "%ymm10", "%ymm11", "%ymm12", "%ymm13", "%ymm14", "%ymm15"
477 };
478 
479 const char *const dis_SEGREG[16] = {
480 	"%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>",
481 	"%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>"
482 };
483 
484 /*
485  * SIMD predicate suffixes
486  */
487 const char *const dis_PREDSUFFIX[8] = {
488 	"eq", "lt", "le", "unord", "neq", "nlt", "nle", "ord"
489 };
490 
491 const char *const dis_AVXvgrp7[3][8] = {
492 	/*0	1	2		3		4		5	6		7*/
493 /*71*/	{"",	"",	"vpsrlw",	"",		"vpsraw",	"",	"vpsllw",	""},
494 /*72*/	{"",	"",	"vpsrld",	"",		"vpsrad",	"",	"vpslld",	""},
495 /*73*/	{"",	"",	"vpsrlq",	"vpsrldq",	"",		"",	"vpsllq",	"vpslldq"}
496 };
497 
498 #endif	/* DIS_TEXT */
499 
500 /*
501  *	"decode table" for 64 bit mode MOVSXD instruction (opcode 0x63)
502  */
503 const instable_t dis_opMOVSLD = TNS("movslq",MOVSXZ);
504 
505 /*
506  *	"decode table" for pause and clflush instructions
507  */
508 const instable_t dis_opPause = TNS("pause", NORM);
509 
510 /*
511  *	Decode table for 0x0F00 opcodes
512  */
513 const instable_t dis_op0F00[8] = {
514 
515 /*  [0]  */	TNS("sldt",M),		TNS("str",M),		TNSy("lldt",M), 	TNSy("ltr",M),
516 /*  [4]  */	TNSZ("verr",M,2),	TNSZ("verw",M,2),	INVALID,		INVALID,
517 };
518 
519 
520 /*
521  *	Decode table for 0x0F01 opcodes
522  */
523 const instable_t dis_op0F01[8] = {
524 
525 /*  [0]  */	TNSZ("sgdt",VMx,6),	TNSZ("sidt",MONITOR_MWAIT,6),	TNSZ("lgdt",XGETBV_XSETBV,6),	TNSZ("lidt",SVM,6),
526 /*  [4]  */	TNSZ("smsw",M,2),	INVALID, 		TNSZ("lmsw",M,2),	TNS("invlpg",SWAPGS_RDTSCP),
527 };
528 
529 /*
530  *	Decode table for 0x0F18 opcodes -- SIMD prefetch
531  */
532 const instable_t dis_op0F18[8] = {
533 
534 /*  [0]  */	TNS("prefetchnta",PREF),TNS("prefetcht0",PREF),	TNS("prefetcht1",PREF),	TNS("prefetcht2",PREF),
535 /*  [4]  */	INVALID,		INVALID,		INVALID,		INVALID,
536 };
537 
538 /*
539  * 	Decode table for 0x0FAE opcodes -- SIMD state save/restore
540  */
541 const instable_t dis_op0FAE[8] = {
542 /*  [0]  */	TNSZ("fxsave",M,512),	TNSZ("fxrstor",M,512),	TNS("ldmxcsr",M),	TNS("stmxcsr",M),
543 /*  [4]  */	TNSZ("xsave",M,512),	TNS("lfence",XMMFENCE), TNS("mfence",XMMFENCE),	TNS("sfence",XMMSFNC),
544 };
545 
546 /*
547  *	Decode table for 0x0FBA opcodes
548  */
549 
550 const instable_t dis_op0FBA[8] = {
551 
552 /*  [0]  */	INVALID,		INVALID,		INVALID,		INVALID,
553 /*  [4]  */	TS("bt",MIb),		TS("bts",MIb),		TS("btr",MIb),		TS("btc",MIb),
554 };
555 
556 /*
557  * 	Decode table for 0x0FC7 opcode (group 9)
558  */
559 
560 const instable_t dis_op0FC7[8] = {
561 
562 /*  [0]  */	INVALID,		TNS("cmpxchg8b",M),	INVALID,		INVALID,
563 /*  [4]  */	INVALID,		INVALID,		TNS("vmptrld",MG9),	TNS("vmptrst",MG9),
564 };
565 
566 /*
567  * 	Decode table for 0x0FC7 opcode (group 9) mode 3
568  */
569 
570 const instable_t dis_op0FC7m3[8] = {
571 
572 /*  [0]  */	INVALID,		INVALID,	INVALID,		INVALID,
573 /*  [4]  */	INVALID,		INVALID,	TNS("rdrand",MG9),	TNS("rdseed", MG9),
574 };
575 
576 /*
577  * 	Decode table for 0x0FC7 opcode with 0x66 prefix
578  */
579 
580 const instable_t dis_op660FC7[8] = {
581 
582 /*  [0]  */	INVALID,		INVALID,		INVALID,		INVALID,
583 /*  [4]  */	INVALID,		INVALID,		TNS("vmclear",M),	INVALID,
584 };
585 
586 /*
587  * 	Decode table for 0x0FC7 opcode with 0xF3 prefix
588  */
589 
590 const instable_t dis_opF30FC7[8] = {
591 
592 /*  [0]  */	INVALID,		INVALID,		INVALID,		INVALID,
593 /*  [4]  */	INVALID,		INVALID,		TNS("vmxon",M),		INVALID,
594 };
595 
596 /*
597  *	Decode table for 0x0FC8 opcode -- 486 bswap instruction
598  *
599  *bit pattern: 0000 1111 1100 1reg
600  */
601 const instable_t dis_op0FC8[4] = {
602 /*  [0]  */	TNS("bswap",R),		INVALID,		INVALID,		INVALID,
603 };
604 
605 /*
606  *	Decode table for 0x0F71, 0x0F72, and 0x0F73 opcodes -- MMX instructions
607  */
608 const instable_t dis_op0F7123[4][8] = {
609 {
610 /*  [70].0 */	INVALID,		INVALID,		INVALID,		INVALID,
611 /*      .4 */	INVALID,		INVALID,		INVALID,		INVALID,
612 }, {
613 /*  [71].0 */	INVALID,		INVALID,		TNS("psrlw",MMOSH),	INVALID,
614 /*      .4 */	TNS("psraw",MMOSH),	INVALID,		TNS("psllw",MMOSH),	INVALID,
615 }, {
616 /*  [72].0 */	INVALID,		INVALID,		TNS("psrld",MMOSH),	INVALID,
617 /*      .4 */	TNS("psrad",MMOSH),	INVALID,		TNS("pslld",MMOSH),	INVALID,
618 }, {
619 /*  [73].0 */	INVALID,		INVALID,		TNS("psrlq",MMOSH),	TNS("INVALID",MMOSH),
620 /*      .4 */	INVALID,		INVALID, 		TNS("psllq",MMOSH),	TNS("INVALID",MMOSH),
621 } };
622 
623 /*
624  *	Decode table for SIMD extensions to above 0x0F71-0x0F73 opcodes.
625  */
626 const instable_t dis_opSIMD7123[32] = {
627 /* [70].0 */	INVALID,		INVALID,		INVALID,		INVALID,
628 /*     .4 */	INVALID,		INVALID,		INVALID,		INVALID,
629 
630 /* [71].0 */	INVALID,		INVALID,		TNS("psrlw",XMMSH),	INVALID,
631 /*     .4 */	TNS("psraw",XMMSH),	INVALID,		TNS("psllw",XMMSH),	INVALID,
632 
633 /* [72].0 */	INVALID,		INVALID,		TNS("psrld",XMMSH),	INVALID,
634 /*     .4 */	TNS("psrad",XMMSH),	INVALID,		TNS("pslld",XMMSH),	INVALID,
635 
636 /* [73].0 */	INVALID,		INVALID,		TNS("psrlq",XMMSH),	TNS("psrldq",XMMSH),
637 /*     .4 */	INVALID,		INVALID,		TNS("psllq",XMMSH),	TNS("pslldq",XMMSH),
638 };
639 
640 /*
641  *	SIMD instructions have been wedged into the existing IA32 instruction
642  *	set through the use of prefixes.  That is, while 0xf0 0x58 may be
643  *	addps, 0xf3 0xf0 0x58 (literally, repz addps) is a completely different
644  *	instruction - addss.  At present, three prefixes have been coopted in
645  *	this manner - address size (0x66), repnz (0xf2) and repz (0xf3).  The
646  *	following tables are used to provide the prefixed instruction names.
647  *	The arrays are sparse, but they're fast.
648  */
649 
650 /*
651  *	Decode table for SIMD instructions with the address size (0x66) prefix.
652  */
653 const instable_t dis_opSIMDdata16[256] = {
654 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
655 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
656 /*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
657 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
658 
659 /*  [10]  */	TNSZ("movupd",XMM,16),	TNSZ("movupd",XMMS,16),	TNSZ("movlpd",XMMM,8),	TNSZ("movlpd",XMMMS,8),
660 /*  [14]  */	TNSZ("unpcklpd",XMM,16),TNSZ("unpckhpd",XMM,16),TNSZ("movhpd",XMMM,8),	TNSZ("movhpd",XMMMS,8),
661 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
662 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
663 
664 /*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
665 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
666 /*  [28]  */	TNSZ("movapd",XMM,16),	TNSZ("movapd",XMMS,16),	TNSZ("cvtpi2pd",XMMOMX,8),TNSZ("movntpd",XMMOMS,16),
667 /*  [2C]  */	TNSZ("cvttpd2pi",XMMXMM,16),TNSZ("cvtpd2pi",XMMXMM,16),TNSZ("ucomisd",XMM,8),TNSZ("comisd",XMM,8),
668 
669 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
670 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
671 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
672 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
673 
674 /*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
675 /*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
676 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
677 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
678 
679 /*  [50]  */	TNS("movmskpd",XMMOX3),	TNSZ("sqrtpd",XMM,16),	INVALID,		INVALID,
680 /*  [54]  */	TNSZ("andpd",XMM,16),	TNSZ("andnpd",XMM,16),	TNSZ("orpd",XMM,16),	TNSZ("xorpd",XMM,16),
681 /*  [58]  */	TNSZ("addpd",XMM,16),	TNSZ("mulpd",XMM,16),	TNSZ("cvtpd2ps",XMM,16),TNSZ("cvtps2dq",XMM,16),
682 /*  [5C]  */	TNSZ("subpd",XMM,16),	TNSZ("minpd",XMM,16),	TNSZ("divpd",XMM,16),	TNSZ("maxpd",XMM,16),
683 
684 /*  [60]  */	TNSZ("punpcklbw",XMM,16),TNSZ("punpcklwd",XMM,16),TNSZ("punpckldq",XMM,16),TNSZ("packsswb",XMM,16),
685 /*  [64]  */	TNSZ("pcmpgtb",XMM,16),	TNSZ("pcmpgtw",XMM,16),	TNSZ("pcmpgtd",XMM,16),	TNSZ("packuswb",XMM,16),
686 /*  [68]  */	TNSZ("punpckhbw",XMM,16),TNSZ("punpckhwd",XMM,16),TNSZ("punpckhdq",XMM,16),TNSZ("packssdw",XMM,16),
687 /*  [6C]  */	TNSZ("punpcklqdq",XMM,16),TNSZ("punpckhqdq",XMM,16),TNSZ("movd",XMM3MX,4),TNSZ("movdqa",XMM,16),
688 
689 /*  [70]  */	TNSZ("pshufd",XMMP,16),	INVALID,		INVALID,		INVALID,
690 /*  [74]  */	TNSZ("pcmpeqb",XMM,16),	TNSZ("pcmpeqw",XMM,16),	TNSZ("pcmpeqd",XMM,16),	INVALID,
691 /*  [78]  */	TNSZ("extrq",XMM2I,16),	TNSZ("extrq",XMM,16), INVALID,		INVALID,
692 /*  [7C]  */	TNSZ("haddpd",XMM,16),	TNSZ("hsubpd",XMM,16),	TNSZ("movd",XMM3MXS,4),	TNSZ("movdqa",XMMS,16),
693 
694 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
695 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
696 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
697 /*  [8C]  */	INVALID,		INVALID,		INVALID,		INVALID,
698 
699 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
700 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
701 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
702 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
703 
704 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
705 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
706 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
707 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
708 
709 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
710 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
711 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
712 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
713 
714 /*  [C0]  */	INVALID,		INVALID,		TNSZ("cmppd",XMMP,16),	INVALID,
715 /*  [C4]  */	TNSZ("pinsrw",XMMPRM,2),TNS("pextrw",XMM3P),	TNSZ("shufpd",XMMP,16),	INVALID,
716 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
717 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
718 
719 /*  [D0]  */	TNSZ("addsubpd",XMM,16),TNSZ("psrlw",XMM,16),	TNSZ("psrld",XMM,16),	TNSZ("psrlq",XMM,16),
720 /*  [D4]  */	TNSZ("paddq",XMM,16),	TNSZ("pmullw",XMM,16),	TNSZ("movq",XMMS,8),	TNS("pmovmskb",XMMX3),
721 /*  [D8]  */	TNSZ("psubusb",XMM,16),	TNSZ("psubusw",XMM,16),	TNSZ("pminub",XMM,16),	TNSZ("pand",XMM,16),
722 /*  [DC]  */	TNSZ("paddusb",XMM,16),	TNSZ("paddusw",XMM,16),	TNSZ("pmaxub",XMM,16),	TNSZ("pandn",XMM,16),
723 
724 /*  [E0]  */	TNSZ("pavgb",XMM,16),	TNSZ("psraw",XMM,16),	TNSZ("psrad",XMM,16),	TNSZ("pavgw",XMM,16),
725 /*  [E4]  */	TNSZ("pmulhuw",XMM,16),	TNSZ("pmulhw",XMM,16),	TNSZ("cvttpd2dq",XMM,16),TNSZ("movntdq",XMMS,16),
726 /*  [E8]  */	TNSZ("psubsb",XMM,16),	TNSZ("psubsw",XMM,16),	TNSZ("pminsw",XMM,16),	TNSZ("por",XMM,16),
727 /*  [EC]  */	TNSZ("paddsb",XMM,16),	TNSZ("paddsw",XMM,16),	TNSZ("pmaxsw",XMM,16),	TNSZ("pxor",XMM,16),
728 
729 /*  [F0]  */	INVALID,		TNSZ("psllw",XMM,16),	TNSZ("pslld",XMM,16),	TNSZ("psllq",XMM,16),
730 /*  [F4]  */	TNSZ("pmuludq",XMM,16),	TNSZ("pmaddwd",XMM,16),	TNSZ("psadbw",XMM,16),	TNSZ("maskmovdqu", XMMXIMPL,16),
731 /*  [F8]  */	TNSZ("psubb",XMM,16),	TNSZ("psubw",XMM,16),	TNSZ("psubd",XMM,16),	TNSZ("psubq",XMM,16),
732 /*  [FC]  */	TNSZ("paddb",XMM,16),	TNSZ("paddw",XMM,16),	TNSZ("paddd",XMM,16),	INVALID,
733 };
734 
735 const instable_t dis_opAVX660F[256] = {
736 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
737 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
738 /*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
739 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
740 
741 /*  [10]  */	TNSZ("vmovupd",VEX_MX,16),	TNSZ("vmovupd",VEX_RX,16),	TNSZ("vmovlpd",VEX_RMrX,8),	TNSZ("vmovlpd",VEX_RM,8),
742 /*  [14]  */	TNSZ("vunpcklpd",VEX_RMrX,16),TNSZ("vunpckhpd",VEX_RMrX,16),TNSZ("vmovhpd",VEX_RMrX,8),	TNSZ("vmovhpd",VEX_RM,8),
743 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
744 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
745 
746 /*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
747 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
748 /*  [28]  */	TNSZ("vmovapd",VEX_MX,16),	TNSZ("vmovapd",VEX_RX,16),	INVALID,		TNSZ("vmovntpd",VEX_RM,16),
749 /*  [2C]  */	INVALID,		INVALID,		TNSZ("vucomisd",VEX_MX,8),TNSZ("vcomisd",VEX_MX,8),
750 
751 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
752 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
753 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
754 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
755 
756 /*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
757 /*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
758 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
759 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
760 
761 /*  [50]  */	TNS("vmovmskpd",VEX_MR),	TNSZ("vsqrtpd",VEX_MX,16),	INVALID,		INVALID,
762 /*  [54]  */	TNSZ("vandpd",VEX_RMrX,16),	TNSZ("vandnpd",VEX_RMrX,16),	TNSZ("vorpd",VEX_RMrX,16),	TNSZ("vxorpd",VEX_RMrX,16),
763 /*  [58]  */	TNSZ("vaddpd",VEX_RMrX,16),	TNSZ("vmulpd",VEX_RMrX,16),	TNSZ("vcvtpd2ps",VEX_MX,16),TNSZ("vcvtps2dq",VEX_MX,16),
764 /*  [5C]  */	TNSZ("vsubpd",VEX_RMrX,16),	TNSZ("vminpd",VEX_RMrX,16),	TNSZ("vdivpd",VEX_RMrX,16),	TNSZ("vmaxpd",VEX_RMrX,16),
765 
766 /*  [60]  */	TNSZ("vpunpcklbw",VEX_RMrX,16),TNSZ("vpunpcklwd",VEX_RMrX,16),TNSZ("vpunpckldq",VEX_RMrX,16),TNSZ("vpacksswb",VEX_RMrX,16),
767 /*  [64]  */	TNSZ("vpcmpgtb",VEX_RMrX,16),	TNSZ("vpcmpgtw",VEX_RMrX,16),	TNSZ("vpcmpgtd",VEX_RMrX,16),	TNSZ("vpackuswb",VEX_RMrX,16),
768 /*  [68]  */	TNSZ("vpunpckhbw",VEX_RMrX,16),TNSZ("vpunpckhwd",VEX_RMrX,16),TNSZ("vpunpckhdq",VEX_RMrX,16),TNSZ("vpackssdw",VEX_RMrX,16),
769 /*  [6C]  */	TNSZ("vpunpcklqdq",VEX_RMrX,16),TNSZ("vpunpckhqdq",VEX_RMrX,16),TNSZ("vmovd",VEX_MX,4),TNSZ("vmovdqa",VEX_MX,16),
770 
771 /*  [70]  */	TNSZ("vpshufd",VEX_MXI,16),	TNSZ("vgrp71",VEX_XXI,16),	TNSZ("vgrp72",VEX_XXI,16),		TNSZ("vgrp73",VEX_XXI,16),
772 /*  [74]  */	TNSZ("vpcmpeqb",VEX_RMrX,16),	TNSZ("vpcmpeqw",VEX_RMrX,16),	TNSZ("vpcmpeqd",VEX_RMrX,16),	INVALID,
773 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
774 /*  [7C]  */	TNSZ("vhaddpd",VEX_RMrX,16),	TNSZ("vhsubpd",VEX_RMrX,16),	TNSZ("vmovd",VEX_RR,4),	TNSZ("vmovdqa",VEX_RX,16),
775 
776 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
777 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
778 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
779 /*  [8C]  */	INVALID,		INVALID,		INVALID,		INVALID,
780 
781 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
782 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
783 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
784 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
785 
786 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
787 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
788 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
789 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
790 
791 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
792 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
793 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
794 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
795 
796 /*  [C0]  */	INVALID,		INVALID,		TNSZ("vcmppd",VEX_RMRX,16),	INVALID,
797 /*  [C4]  */	TNSZ("vpinsrw",VEX_RMRX,2),TNS("vpextrw",VEX_MR),	TNSZ("vshufpd",VEX_RMRX,16),	INVALID,
798 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
799 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
800 
801 /*  [D0]  */	TNSZ("vaddsubpd",VEX_RMrX,16),TNSZ("vpsrlw",VEX_RMrX,16),	TNSZ("vpsrld",VEX_RMrX,16),	TNSZ("vpsrlq",VEX_RMrX,16),
802 /*  [D4]  */	TNSZ("vpaddq",VEX_RMrX,16),	TNSZ("vpmullw",VEX_RMrX,16),	TNSZ("vmovq",VEX_RX,8),	TNS("vpmovmskb",VEX_MR),
803 /*  [D8]  */	TNSZ("vpsubusb",VEX_RMrX,16),	TNSZ("vpsubusw",VEX_RMrX,16),	TNSZ("vpminub",VEX_RMrX,16),	TNSZ("vpand",VEX_RMrX,16),
804 /*  [DC]  */	TNSZ("vpaddusb",VEX_RMrX,16),	TNSZ("vpaddusw",VEX_RMrX,16),	TNSZ("vpmaxub",VEX_RMrX,16),	TNSZ("vpandn",VEX_RMrX,16),
805 
806 /*  [E0]  */	TNSZ("vpavgb",VEX_RMrX,16),	TNSZ("vpsraw",VEX_RMrX,16),	TNSZ("vpsrad",VEX_RMrX,16),	TNSZ("vpavgw",VEX_RMrX,16),
807 /*  [E4]  */	TNSZ("vpmulhuw",VEX_RMrX,16),	TNSZ("vpmulhw",VEX_RMrX,16),	TNSZ("vcvttpd2dq",VEX_MX,16),TNSZ("vmovntdq",VEX_RM,16),
808 /*  [E8]  */	TNSZ("vpsubsb",VEX_RMrX,16),	TNSZ("vpsubsw",VEX_RMrX,16),	TNSZ("vpminsw",VEX_RMrX,16),	TNSZ("vpor",VEX_RMrX,16),
809 /*  [EC]  */	TNSZ("vpaddsb",VEX_RMrX,16),	TNSZ("vpaddsw",VEX_RMrX,16),	TNSZ("vpmaxsw",VEX_RMrX,16),	TNSZ("vpxor",VEX_RMrX,16),
810 
811 /*  [F0]  */	INVALID,		TNSZ("vpsllw",VEX_RMrX,16),	TNSZ("vpslld",VEX_RMrX,16),	TNSZ("vpsllq",VEX_RMrX,16),
812 /*  [F4]  */	TNSZ("vpmuludq",VEX_RMrX,16),	TNSZ("vpmaddwd",VEX_RMrX,16),	TNSZ("vpsadbw",VEX_RMrX,16),	TNS("vmaskmovdqu",VEX_MX),
813 /*  [F8]  */	TNSZ("vpsubb",VEX_RMrX,16),	TNSZ("vpsubw",VEX_RMrX,16),	TNSZ("vpsubd",VEX_RMrX,16),	TNSZ("vpsubq",VEX_RMrX,16),
814 /*  [FC]  */	TNSZ("vpaddb",VEX_RMrX,16),	TNSZ("vpaddw",VEX_RMrX,16),	TNSZ("vpaddd",VEX_RMrX,16),	INVALID,
815 };
816 
817 /*
818  *	Decode table for SIMD instructions with the repnz (0xf2) prefix.
819  */
820 const instable_t dis_opSIMDrepnz[256] = {
821 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
822 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
823 /*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
824 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
825 
826 /*  [10]  */	TNSZ("movsd",XMM,8),	TNSZ("movsd",XMMS,8),	TNSZ("movddup",XMM,8),	INVALID,
827 /*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
828 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
829 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
830 
831 /*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
832 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
833 /*  [28]  */	INVALID,		INVALID,		TNSZ("cvtsi2sd",XMM3MX,4),TNSZ("movntsd",XMMMS,8),
834 /*  [2C]  */	TNSZ("cvttsd2si",XMMXM3,8),TNSZ("cvtsd2si",XMMXM3,8),INVALID,		INVALID,
835 
836 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
837 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
838 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
839 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
840 
841 /*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
842 /*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
843 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
844 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
845 
846 /*  [50]  */	INVALID,		TNSZ("sqrtsd",XMM,8),	INVALID,		INVALID,
847 /*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
848 /*  [58]  */	TNSZ("addsd",XMM,8),	TNSZ("mulsd",XMM,8),	TNSZ("cvtsd2ss",XMM,8),	INVALID,
849 /*  [5C]  */	TNSZ("subsd",XMM,8),	TNSZ("minsd",XMM,8),	TNSZ("divsd",XMM,8),	TNSZ("maxsd",XMM,8),
850 
851 /*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
852 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
853 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
854 /*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
855 
856 /*  [70]  */	TNSZ("pshuflw",XMMP,16),INVALID,		INVALID,		INVALID,
857 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
858 /*  [78]  */	TNSZ("insertq",XMMX2I,16),TNSZ("insertq",XMM,8),INVALID,		INVALID,
859 /*  [7C]  */	TNSZ("haddps",XMM,16),	TNSZ("hsubps",XMM,16),	INVALID,		INVALID,
860 
861 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
862 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
863 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
864 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
865 
866 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
867 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
868 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
869 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
870 
871 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
872 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
873 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
874 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
875 
876 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
877 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
878 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
879 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
880 
881 /*  [C0]  */	INVALID,		INVALID,		TNSZ("cmpsd",XMMP,8),	INVALID,
882 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
883 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
884 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
885 
886 /*  [D0]  */	TNSZ("addsubps",XMM,16),INVALID,		INVALID,		INVALID,
887 /*  [D4]  */	INVALID,		INVALID,		TNS("movdq2q",XMMXM),	INVALID,
888 /*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
889 /*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
890 
891 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
892 /*  [E4]  */	INVALID,		INVALID,		TNSZ("cvtpd2dq",XMM,16),INVALID,
893 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
894 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
895 
896 /*  [F0]  */	TNS("lddqu",XMMM),	INVALID,		INVALID,		INVALID,
897 /*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
898 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
899 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
900 };
901 
902 const instable_t dis_opAVXF20F[256] = {
903 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
904 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
905 /*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
906 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
907 
908 /*  [10]  */	TNSZ("vmovsd",VEX_RMrX,8),	TNSZ("vmovsd",VEX_RRX,8),	TNSZ("vmovddup",VEX_MX,8),	INVALID,
909 /*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
910 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
911 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
912 
913 /*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
914 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
915 /*  [28]  */	INVALID,		INVALID,		TNSZ("vcvtsi2sd",VEX_RMrX,4),INVALID,
916 /*  [2C]  */	TNSZ("vcvttsd2si",VEX_MR,8),TNSZ("vcvtsd2si",VEX_MR,8),INVALID,		INVALID,
917 
918 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
919 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
920 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
921 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
922 
923 /*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
924 /*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
925 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
926 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
927 
928 /*  [50]  */	INVALID,		TNSZ("vsqrtsd",VEX_RMrX,8),	INVALID,		INVALID,
929 /*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
930 /*  [58]  */	TNSZ("vaddsd",VEX_RMrX,8),	TNSZ("vmulsd",VEX_RMrX,8),	TNSZ("vcvtsd2ss",VEX_RMrX,8),	INVALID,
931 /*  [5C]  */	TNSZ("vsubsd",VEX_RMrX,8),	TNSZ("vminsd",VEX_RMrX,8),	TNSZ("vdivsd",VEX_RMrX,8),	TNSZ("vmaxsd",VEX_RMrX,8),
932 
933 /*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
934 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
935 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
936 /*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
937 
938 /*  [70]  */	TNSZ("vpshuflw",VEX_MXI,16),INVALID,		INVALID,		INVALID,
939 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
940 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
941 /*  [7C]  */	TNSZ("vhaddps",VEX_RMrX,8),	TNSZ("vhsubps",VEX_RMrX,8),	INVALID,		INVALID,
942 
943 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
944 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
945 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
946 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
947 
948 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
949 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
950 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
951 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
952 
953 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
954 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
955 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
956 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
957 
958 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
959 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
960 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
961 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
962 
963 /*  [C0]  */	INVALID,		INVALID,		TNSZ("vcmpsd",VEX_RMRX,8),	INVALID,
964 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
965 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
966 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
967 
968 /*  [D0]  */	TNSZ("vaddsubps",VEX_RMrX,8),	INVALID,		INVALID,		INVALID,
969 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
970 /*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
971 /*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
972 
973 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
974 /*  [E4]  */	INVALID,		INVALID,		TNSZ("vcvtpd2dq",VEX_MX,16),INVALID,
975 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
976 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
977 
978 /*  [F0]  */	TNSZ("vlddqu",VEX_MX,16),	INVALID,		INVALID,		INVALID,
979 /*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
980 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
981 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
982 };
983 
984 const instable_t dis_opAVXF20F3A[256] = {
985 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
986 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
987 /*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
988 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
989 
990 /*  [10]  */	INVALID,		INVALID,		INVALID,		INVALID,
991 /*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
992 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
993 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
994 
995 /*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
996 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
997 /*  [28]  */	INVALID,		INVALID,		INVALID,		INVALID,
998 /*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
999 
1000 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1001 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1002 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1003 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1004 
1005 /*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1006 /*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
1007 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1008 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1009 
1010 /*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
1011 /*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
1012 /*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
1013 /*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1014 
1015 /*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1016 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1017 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1018 /*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1019 
1020 /*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
1021 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1022 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1023 /*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1024 
1025 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1026 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1027 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1028 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1029 
1030 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1031 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1032 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1033 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1034 
1035 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1036 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1037 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1038 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1039 
1040 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1041 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1042 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1043 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1044 
1045 /*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1046 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1047 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1048 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1049 
1050 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1051 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1052 /*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1053 /*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1054 
1055 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1056 /*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1057 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1058 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1059 
1060 /*  [F0]  */	TNSZvr("rorx",VEX_MXI,6),INVALID,		INVALID,		INVALID,
1061 /*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1062 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1063 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1064 };
1065 
1066 const instable_t dis_opAVXF20F38[256] = {
1067 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1068 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1069 /*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
1070 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1071 
1072 /*  [10]  */	INVALID,		INVALID,		INVALID,		INVALID,
1073 /*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
1074 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1075 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1076 
1077 /*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
1078 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1079 /*  [28]  */	INVALID,		INVALID,		INVALID,		INVALID,
1080 /*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1081 
1082 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1083 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1084 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1085 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1086 
1087 /*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1088 /*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
1089 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1090 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1091 
1092 /*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
1093 /*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
1094 /*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
1095 /*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1096 
1097 /*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1098 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1099 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1100 /*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1101 
1102 /*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
1103 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1104 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1105 /*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1106 
1107 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1108 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1109 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1110 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1111 
1112 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1113 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1114 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1115 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1116 
1117 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1118 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1119 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1120 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1121 
1122 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1123 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1124 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1125 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1126 
1127 /*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1128 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1129 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1130 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1131 
1132 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1133 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1134 /*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1135 /*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1136 
1137 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1138 /*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1139 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1140 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1141 
1142 /*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1143 /*  [F4]  */	INVALID,		TNSZvr("pdep",VEX_RMrX,5),TNSZvr("mulx",VEX_RMrX,5),TNSZvr("shrx",VEX_VRMrX,5),
1144 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1145 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1146 };
1147 
1148 const instable_t dis_opAVXF30F38[256] = {
1149 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1150 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1151 /*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
1152 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1153 
1154 /*  [10]  */	INVALID,		INVALID,		INVALID,		INVALID,
1155 /*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
1156 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1157 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1158 
1159 /*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
1160 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1161 /*  [28]  */	INVALID,		INVALID,		INVALID,		INVALID,
1162 /*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1163 
1164 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1165 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1166 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1167 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1168 
1169 /*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1170 /*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
1171 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1172 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1173 
1174 /*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
1175 /*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
1176 /*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
1177 /*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1178 
1179 /*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1180 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1181 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1182 /*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1183 
1184 /*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
1185 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1186 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1187 /*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1188 
1189 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1190 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1191 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1192 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1193 
1194 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1195 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1196 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1197 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1198 
1199 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1200 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1201 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1202 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1203 
1204 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1205 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1206 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1207 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1208 
1209 /*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1210 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1211 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1212 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1213 
1214 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1215 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1216 /*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1217 /*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1218 
1219 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1220 /*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1221 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1222 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1223 
1224 /*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1225 /*  [F4]  */	INVALID,		TNSZvr("pext",VEX_RMrX,5),INVALID,		TNSZvr("sarx",VEX_VRMrX,5),
1226 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1227 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1228 };
1229 /*
1230  *	Decode table for SIMD instructions with the repz (0xf3) prefix.
1231  */
1232 const instable_t dis_opSIMDrepz[256] = {
1233 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1234 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1235 /*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
1236 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1237 
1238 /*  [10]  */	TNSZ("movss",XMM,4),	TNSZ("movss",XMMS,4),	TNSZ("movsldup",XMM,16),INVALID,
1239 /*  [14]  */	INVALID,		INVALID,		TNSZ("movshdup",XMM,16),INVALID,
1240 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1241 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1242 
1243 /*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
1244 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1245 /*  [28]  */	INVALID,		INVALID,		TNSZ("cvtsi2ss",XMM3MX,4),TNSZ("movntss",XMMMS,4),
1246 /*  [2C]  */	TNSZ("cvttss2si",XMMXM3,4),TNSZ("cvtss2si",XMMXM3,4),INVALID,		INVALID,
1247 
1248 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1249 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1250 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1251 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1252 
1253 /*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1254 /*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
1255 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1256 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1257 
1258 /*  [50]  */	INVALID,		TNSZ("sqrtss",XMM,4),	TNSZ("rsqrtss",XMM,4),	TNSZ("rcpss",XMM,4),
1259 /*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
1260 /*  [58]  */	TNSZ("addss",XMM,4),	TNSZ("mulss",XMM,4),	TNSZ("cvtss2sd",XMM,4),	TNSZ("cvttps2dq",XMM,16),
1261 /*  [5C]  */	TNSZ("subss",XMM,4),	TNSZ("minss",XMM,4),	TNSZ("divss",XMM,4),	TNSZ("maxss",XMM,4),
1262 
1263 /*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1264 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1265 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1266 /*  [6C]  */	INVALID,		INVALID,		INVALID,		TNSZ("movdqu",XMM,16),
1267 
1268 /*  [70]  */	TNSZ("pshufhw",XMMP,16),INVALID,		INVALID,		INVALID,
1269 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1270 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1271 /*  [7C]  */	INVALID,		INVALID,		TNSZ("movq",XMM,8),	TNSZ("movdqu",XMMS,16),
1272 
1273 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1274 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1275 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1276 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1277 
1278 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1279 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1280 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1281 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1282 
1283 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1284 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1285 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1286 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1287 
1288 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1289 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1290 /*  [B8]  */	TS("popcnt",MRw),	INVALID,		INVALID,		INVALID,
1291 /*  [BC]  */	TNSZ("tzcnt",MRw,5),	TS("lzcnt",MRw),	INVALID,		INVALID,
1292 
1293 /*  [C0]  */	INVALID,		INVALID,		TNSZ("cmpss",XMMP,4),	INVALID,
1294 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1295 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1296 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1297 
1298 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1299 /*  [D4]  */	INVALID,		INVALID,		TNS("movq2dq",XMMMX),	INVALID,
1300 /*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1301 /*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1302 
1303 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1304 /*  [E4]  */	INVALID,		INVALID,		TNSZ("cvtdq2pd",XMM,8),	INVALID,
1305 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1306 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1307 
1308 /*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1309 /*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1310 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1311 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1312 };
1313 
1314 const instable_t dis_opAVXF30F[256] = {
1315 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1316 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1317 /*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
1318 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1319 
1320 /*  [10]  */	TNSZ("vmovss",VEX_RMrX,4),	TNSZ("vmovss",VEX_RRX,4),	TNSZ("vmovsldup",VEX_MX,4),	INVALID,
1321 /*  [14]  */	INVALID,		INVALID,		TNSZ("vmovshdup",VEX_MX,4),	INVALID,
1322 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1323 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1324 
1325 /*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
1326 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1327 /*  [28]  */	INVALID,		INVALID,		TNSZ("vcvtsi2ss",VEX_RMrX,4),INVALID,
1328 /*  [2C]  */	TNSZ("vcvttss2si",VEX_MR,4),TNSZ("vcvtss2si",VEX_MR,4),INVALID,		INVALID,
1329 
1330 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1331 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1332 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1333 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1334 
1335 /*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1336 /*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
1337 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1338 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1339 
1340 /*  [50]  */	INVALID,		TNSZ("vsqrtss",VEX_RMrX,4),	TNSZ("vrsqrtss",VEX_RMrX,4),	TNSZ("vrcpss",VEX_RMrX,4),
1341 /*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
1342 /*  [58]  */	TNSZ("vaddss",VEX_RMrX,4),	TNSZ("vmulss",VEX_RMrX,4),	TNSZ("vcvtss2sd",VEX_RMrX,4),	TNSZ("vcvttps2dq",VEX_MX,16),
1343 /*  [5C]  */	TNSZ("vsubss",VEX_RMrX,4),	TNSZ("vminss",VEX_RMrX,4),	TNSZ("vdivss",VEX_RMrX,4),	TNSZ("vmaxss",VEX_RMrX,4),
1344 
1345 /*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1346 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1347 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1348 /*  [6C]  */	INVALID,		INVALID,		INVALID,		TNSZ("vmovdqu",VEX_MX,16),
1349 
1350 /*  [70]  */	TNSZ("vpshufhw",VEX_MXI,16),INVALID,		INVALID,		INVALID,
1351 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1352 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1353 /*  [7C]  */	INVALID,		INVALID,		TNSZ("vmovq",VEX_MX,8),	TNSZ("vmovdqu",VEX_RX,16),
1354 
1355 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1356 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1357 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1358 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1359 
1360 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1361 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1362 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1363 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1364 
1365 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1366 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1367 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1368 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1369 
1370 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1371 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1372 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1373 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1374 
1375 /*  [C0]  */	INVALID,		INVALID,		TNSZ("vcmpss",VEX_RMRX,4),	INVALID,
1376 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1377 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1378 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1379 
1380 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1381 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1382 /*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1383 /*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1384 
1385 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1386 /*  [E4]  */	INVALID,		INVALID,		TNSZ("vcvtdq2pd",VEX_MX,8),	INVALID,
1387 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1388 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1389 
1390 /*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1391 /*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1392 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1393 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1394 };
1395 /*
1396  * The following two tables are used to encode crc32 and movbe
1397  * since they share the same opcodes.
1398  */
1399 const instable_t dis_op0F38F0[2] = {
1400 /*  [00]  */	TNS("crc32b",CRC32),
1401 		TS("movbe",MOVBE),
1402 };
1403 
1404 const instable_t dis_op0F38F1[2] = {
1405 /*  [00]  */	TS("crc32",CRC32),
1406 		TS("movbe",MOVBE),
1407 };
1408 
1409 /*
1410  * The following table is used to distinguish between adox and adcx which share
1411  * the same opcodes.
1412  */
1413 const instable_t dis_op0F38F6[2] = {
1414 /*  [00]  */	TNS("adcx",ADX),
1415 		TNS("adox",ADX),
1416 };
1417 
1418 const instable_t dis_op0F38[256] = {
1419 /*  [00]  */	TNSZ("pshufb",XMM_66o,16),TNSZ("phaddw",XMM_66o,16),TNSZ("phaddd",XMM_66o,16),TNSZ("phaddsw",XMM_66o,16),
1420 /*  [04]  */	TNSZ("pmaddubsw",XMM_66o,16),TNSZ("phsubw",XMM_66o,16),	TNSZ("phsubd",XMM_66o,16),TNSZ("phsubsw",XMM_66o,16),
1421 /*  [08]  */	TNSZ("psignb",XMM_66o,16),TNSZ("psignw",XMM_66o,16),TNSZ("psignd",XMM_66o,16),TNSZ("pmulhrsw",XMM_66o,16),
1422 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1423 
1424 /*  [10]  */	TNSZ("pblendvb",XMM_66r,16),INVALID,		INVALID,		INVALID,
1425 /*  [14]  */	TNSZ("blendvps",XMM_66r,16),TNSZ("blendvpd",XMM_66r,16),INVALID,	TNSZ("ptest",XMM_66r,16),
1426 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1427 /*  [1C]  */	TNSZ("pabsb",XMM_66o,16),TNSZ("pabsw",XMM_66o,16),TNSZ("pabsd",XMM_66o,16),INVALID,
1428 
1429 /*  [20]  */	TNSZ("pmovsxbw",XMM_66r,16),TNSZ("pmovsxbd",XMM_66r,16),TNSZ("pmovsxbq",XMM_66r,16),TNSZ("pmovsxwd",XMM_66r,16),
1430 /*  [24]  */	TNSZ("pmovsxwq",XMM_66r,16),TNSZ("pmovsxdq",XMM_66r,16),INVALID,	INVALID,
1431 /*  [28]  */	TNSZ("pmuldq",XMM_66r,16),TNSZ("pcmpeqq",XMM_66r,16),TNSZ("movntdqa",XMMM_66r,16),TNSZ("packusdw",XMM_66r,16),
1432 /*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1433 
1434 /*  [30]  */	TNSZ("pmovzxbw",XMM_66r,16),TNSZ("pmovzxbd",XMM_66r,16),TNSZ("pmovzxbq",XMM_66r,16),TNSZ("pmovzxwd",XMM_66r,16),
1435 /*  [34]  */	TNSZ("pmovzxwq",XMM_66r,16),TNSZ("pmovzxdq",XMM_66r,16),INVALID,	TNSZ("pcmpgtq",XMM_66r,16),
1436 /*  [38]  */	TNSZ("pminsb",XMM_66r,16),TNSZ("pminsd",XMM_66r,16),TNSZ("pminuw",XMM_66r,16),TNSZ("pminud",XMM_66r,16),
1437 /*  [3C]  */	TNSZ("pmaxsb",XMM_66r,16),TNSZ("pmaxsd",XMM_66r,16),TNSZ("pmaxuw",XMM_66r,16),TNSZ("pmaxud",XMM_66r,16),
1438 
1439 /*  [40]  */	TNSZ("pmulld",XMM_66r,16),TNSZ("phminposuw",XMM_66r,16),INVALID,	INVALID,
1440 /*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
1441 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1442 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1443 
1444 /*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
1445 /*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
1446 /*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
1447 /*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1448 
1449 /*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1450 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1451 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1452 /*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1453 
1454 /*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
1455 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1456 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1457 /*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1458 
1459 /*  [80]  */	TNSy("invept", RM_66r),	TNSy("invvpid", RM_66r),TNSy("invpcid", RM_66r),INVALID,
1460 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1461 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1462 /*  [8C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1463 
1464 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1465 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1466 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1467 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1468 
1469 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1470 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1471 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1472 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1473 
1474 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1475 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1476 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1477 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1478 
1479 /*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1480 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1481 /*  [C8]  */	TNSZ("sha1nexte",XMM,16),TNSZ("sha1msg1",XMM,16),TNSZ("sha1msg2",XMM,16),TNSZ("sha256rnds2",XMM,16),
1482 /*  [CC]  */	TNSZ("sha256msg1",XMM,16),TNSZ("sha256msg2",XMM,16),INVALID,		INVALID,
1483 
1484 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1485 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1486 /*  [D8]  */	INVALID,		INVALID,		INVALID,		TNSZ("aesimc",XMM_66r,16),
1487 /*  [DC]  */	TNSZ("aesenc",XMM_66r,16),TNSZ("aesenclast",XMM_66r,16),TNSZ("aesdec",XMM_66r,16),TNSZ("aesdeclast",XMM_66r,16),
1488 
1489 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1490 /*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1491 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1492 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1493 /*  [F0]  */	IND(dis_op0F38F0),	IND(dis_op0F38F1),	INVALID,		INVALID,
1494 /*  [F4]  */	INVALID,		INVALID,		IND(dis_op0F38F6),	INVALID,
1495 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1496 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1497 };
1498 
1499 const instable_t dis_opAVX660F38[256] = {
1500 /*  [00]  */	TNSZ("vpshufb",VEX_RMrX,16),TNSZ("vphaddw",VEX_RMrX,16),TNSZ("vphaddd",VEX_RMrX,16),TNSZ("vphaddsw",VEX_RMrX,16),
1501 /*  [04]  */	TNSZ("vpmaddubsw",VEX_RMrX,16),TNSZ("vphsubw",VEX_RMrX,16),	TNSZ("vphsubd",VEX_RMrX,16),TNSZ("vphsubsw",VEX_RMrX,16),
1502 /*  [08]  */	TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16),
1503 /*  [0C]  */	TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8),	TNSZ("vtestpd",VEX_RRI,16),
1504 
1505 /*  [10]  */	INVALID,		INVALID,		INVALID,		TNSZ("vcvtph2ps",VEX_MX,16),
1506 /*  [14]  */	INVALID,		INVALID,		TNSZ("vpermps",VEX_RMrX,16),TNSZ("vptest",VEX_RRI,16),
1507 /*  [18]  */	TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID,
1508 /*  [1C]  */	TNSZ("vpabsb",VEX_MX,16),TNSZ("vpabsw",VEX_MX,16),TNSZ("vpabsd",VEX_MX,16),INVALID,
1509 
1510 /*  [20]  */	TNSZ("vpmovsxbw",VEX_MX,16),TNSZ("vpmovsxbd",VEX_MX,16),TNSZ("vpmovsxbq",VEX_MX,16),TNSZ("vpmovsxwd",VEX_MX,16),
1511 /*  [24]  */	TNSZ("vpmovsxwq",VEX_MX,16),TNSZ("vpmovsxdq",VEX_MX,16),INVALID,	INVALID,
1512 /*  [28]  */	TNSZ("vpmuldq",VEX_RMrX,16),TNSZ("vpcmpeqq",VEX_RMrX,16),TNSZ("vmovntdqa",VEX_MX,16),TNSZ("vpackusdw",VEX_RMrX,16),
1513 /*  [2C]  */	TNSZ("vmaskmovps",VEX_RMrX,8),TNSZ("vmaskmovpd",VEX_RMrX,16),TNSZ("vmaskmovps",VEX_RRM,8),TNSZ("vmaskmovpd",VEX_RRM,16),
1514 
1515 /*  [30]  */	TNSZ("vpmovzxbw",VEX_MX,16),TNSZ("vpmovzxbd",VEX_MX,16),TNSZ("vpmovzxbq",VEX_MX,16),TNSZ("vpmovzxwd",VEX_MX,16),
1516 /*  [34]  */	TNSZ("vpmovzxwq",VEX_MX,16),TNSZ("vpmovzxdq",VEX_MX,16),TNSZ("vpermd",VEX_RMrX,16),TNSZ("vpcmpgtq",VEX_RMrX,16),
1517 /*  [38]  */	TNSZ("vpminsb",VEX_RMrX,16),TNSZ("vpminsd",VEX_RMrX,16),TNSZ("vpminuw",VEX_RMrX,16),TNSZ("vpminud",VEX_RMrX,16),
1518 /*  [3C]  */	TNSZ("vpmaxsb",VEX_RMrX,16),TNSZ("vpmaxsd",VEX_RMrX,16),TNSZ("vpmaxuw",VEX_RMrX,16),TNSZ("vpmaxud",VEX_RMrX,16),
1519 
1520 /*  [40]  */	TNSZ("vpmulld",VEX_RMrX,16),TNSZ("vphminposuw",VEX_MX,16),INVALID,	INVALID,
1521 /*  [44]  */	INVALID,		TSaZ("vpsrlv",VEX_RMrX,16),TNSZ("vpsravd",VEX_RMrX,16),TSaZ("vpsllv",VEX_RMrX,16),
1522 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1523 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1524 
1525 /*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
1526 /*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
1527 /*  [58]  */	TNSZ("vpbroadcastd",VEX_MX,16),TNSZ("vpbroadcastq",VEX_MX,16),TNSZ("vbroadcasti128",VEX_MX,16),INVALID,
1528 /*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1529 
1530 /*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1531 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1532 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1533 /*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1534 
1535 /*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
1536 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1537 /*  [78]  */	TNSZ("vpbroadcastb",VEX_MX,16),TNSZ("vpbroadcastw",VEX_MX,16),INVALID,	INVALID,
1538 /*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1539 
1540 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1541 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1542 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1543 /*  [8C]  */	TSaZ("vpmaskmov",VEX_RMrX,16),INVALID,		TSaZ("vpmaskmov",VEX_RRM,16),INVALID,
1544 
1545 /*  [90]  */	TNSZ("vpgatherd",VEX_SbVM,16),TNSZ("vpgatherq",VEX_SbVM,16),TNSZ("vgatherdp",VEX_SbVM,16),TNSZ("vgatherqp",VEX_SbVM,16),
1546 /*  [94]  */	INVALID,		INVALID,		TNSZ("vfmaddsub132p",FMA,16),TNSZ("vfmsubadd132p",FMA,16),
1547 /*  [98]  */	TNSZ("vfmadd132p",FMA,16),TNSZ("vfmadd132s",FMA,16),TNSZ("vfmsub132p",FMA,16),TNSZ("vfmsub132s",FMA,16),
1548 /*  [9C]  */	TNSZ("vfnmadd132p",FMA,16),TNSZ("vfnmadd132s",FMA,16),TNSZ("vfnmsub132p",FMA,16),TNSZ("vfnmsub132s",FMA,16),
1549 
1550 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1551 /*  [A4]  */	INVALID,		INVALID,		TNSZ("vfmaddsub213p",FMA,16),TNSZ("vfmsubadd213p",FMA,16),
1552 /*  [A8]  */	TNSZ("vfmadd213p",FMA,16),TNSZ("vfmadd213s",FMA,16),TNSZ("vfmsub213p",FMA,16),TNSZ("vfmsub213s",FMA,16),
1553 /*  [AC]  */	TNSZ("vfnmadd213p",FMA,16),TNSZ("vfnmadd213s",FMA,16),TNSZ("vfnmsub213p",FMA,16),TNSZ("vfnmsub213s",FMA,16),
1554 
1555 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1556 /*  [B4]  */	INVALID,		INVALID,		TNSZ("vfmaddsub231p",FMA,16),TNSZ("vfmsubadd231p",FMA,16),
1557 /*  [B8]  */	TNSZ("vfmadd231p",FMA,16),TNSZ("vfmadd231s",FMA,16),TNSZ("vfmsub231p",FMA,16),TNSZ("vfmsub231s",FMA,16),
1558 /*  [BC]  */	TNSZ("vfnmadd231p",FMA,16),TNSZ("vfnmadd231s",FMA,16),TNSZ("vfnmsub231p",FMA,16),TNSZ("vfnmsub231s",FMA,16),
1559 
1560 /*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1561 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1562 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1563 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1564 
1565 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1566 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1567 /*  [D8]  */	INVALID,		INVALID,		INVALID,		TNSZ("vaesimc",VEX_MX,16),
1568 /*  [DC]  */	TNSZ("vaesenc",VEX_RMrX,16),TNSZ("vaesenclast",VEX_RMrX,16),TNSZ("vaesdec",VEX_RMrX,16),TNSZ("vaesdeclast",VEX_RMrX,16),
1569 
1570 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1571 /*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1572 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1573 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1574 /*  [F0]  */	IND(dis_op0F38F0),	IND(dis_op0F38F1),	INVALID,		INVALID,
1575 /*  [F4]  */	INVALID,		INVALID,		INVALID,		TNSZvr("shlx",VEX_VRMrX,5),
1576 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1577 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1578 };
1579 
1580 const instable_t dis_op0F3A[256] = {
1581 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1582 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1583 /*  [08]  */	TNSZ("roundps",XMMP_66r,16),TNSZ("roundpd",XMMP_66r,16),TNSZ("roundss",XMMP_66r,16),TNSZ("roundsd",XMMP_66r,16),
1584 /*  [0C]  */	TNSZ("blendps",XMMP_66r,16),TNSZ("blendpd",XMMP_66r,16),TNSZ("pblendw",XMMP_66r,16),TNSZ("palignr",XMMP_66o,16),
1585 
1586 /*  [10]  */	INVALID,		INVALID,		INVALID,		INVALID,
1587 /*  [14]  */	TNSZ("pextrb",XMM3PM_66r,8),TNSZ("pextrw",XMM3PM_66r,16),TSZ("pextr",XMM3PM_66r,16),TNSZ("extractps",XMM3PM_66r,16),
1588 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1589 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1590 
1591 /*  [20]  */	TNSZ("pinsrb",XMMPRM_66r,8),TNSZ("insertps",XMMP_66r,16),TSZ("pinsr",XMMPRM_66r,16),INVALID,
1592 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1593 /*  [28]  */	INVALID,		INVALID,		INVALID,		INVALID,
1594 /*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1595 
1596 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1597 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1598 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1599 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1600 
1601 /*  [40]  */	TNSZ("dpps",XMMP_66r,16),TNSZ("dppd",XMMP_66r,16),TNSZ("mpsadbw",XMMP_66r,16),INVALID,
1602 /*  [44]  */	TNSZ("pclmulqdq",XMMP_66r,16),INVALID,		INVALID,		INVALID,
1603 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1604 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1605 
1606 /*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
1607 /*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
1608 /*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
1609 /*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1610 
1611 /*  [60]  */	TNSZ("pcmpestrm",XMMP_66r,16),TNSZ("pcmpestri",XMMP_66r,16),TNSZ("pcmpistrm",XMMP_66r,16),TNSZ("pcmpistri",XMMP_66r,16),
1612 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1613 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1614 /*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1615 
1616 /*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
1617 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1618 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1619 /*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1620 
1621 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1622 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1623 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1624 /*  [8C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1625 
1626 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1627 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1628 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1629 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1630 
1631 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1632 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1633 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1634 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1635 
1636 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1637 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1638 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1639 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1640 
1641 /*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1642 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1643 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1644 /*  [CC]  */	TNSZ("sha1rnds4",XMMP,16),INVALID,		INVALID,		INVALID,
1645 
1646 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1647 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1648 /*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1649 /*  [DC]  */	INVALID,		INVALID,		INVALID,		TNSZ("aeskeygenassist",XMMP_66r,16),
1650 
1651 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1652 /*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1653 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1654 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1655 
1656 /*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1657 /*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1658 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1659 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1660 };
1661 
1662 const instable_t dis_opAVX660F3A[256] = {
1663 /*  [00]  */	TNSZ("vpermq",VEX_MXI,16),TNSZ("vpermpd",VEX_MXI,16),TNSZ("vpblendd",VEX_RMRX,16),INVALID,
1664 /*  [04]  */	TNSZ("vpermilps",VEX_MXI,8),TNSZ("vpermilpd",VEX_MXI,16),TNSZ("vperm2f128",VEX_RMRX,16),INVALID,
1665 /*  [08]  */	TNSZ("vroundps",VEX_MXI,16),TNSZ("vroundpd",VEX_MXI,16),TNSZ("vroundss",VEX_RMRX,16),TNSZ("vroundsd",VEX_RMRX,16),
1666 /*  [0C]  */	TNSZ("vblendps",VEX_RMRX,16),TNSZ("vblendpd",VEX_RMRX,16),TNSZ("vpblendw",VEX_RMRX,16),TNSZ("vpalignr",VEX_RMRX,16),
1667 
1668 /*  [10]  */	INVALID,		INVALID,		INVALID,		INVALID,
1669 /*  [14]  */	TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16),
1670 /*  [18]  */	TNSZ("vinsertf128",VEX_RMRX,16),TNSZ("vextractf128",VEX_RX,16),INVALID,		INVALID,
1671 /*  [1C]  */	INVALID,		TNSZ("vcvtps2ph",VEX_RX,16),		INVALID,		INVALID,
1672 
1673 /*  [20]  */	TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID,
1674 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1675 /*  [28]  */	INVALID,		INVALID,		INVALID,		INVALID,
1676 /*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1677 
1678 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1679 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1680 /*  [38]  */	TNSZ("vinserti128",VEX_RMRX,16),TNSZ("vextracti128",VEX_RIM,16),INVALID,		INVALID,
1681 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1682 
1683 /*  [40]  */	TNSZ("vdpps",VEX_RMRX,16),TNSZ("vdppd",VEX_RMRX,16),TNSZ("vmpsadbw",VEX_RMRX,16),INVALID,
1684 /*  [44]  */	TNSZ("vpclmulqdq",VEX_RMRX,16),INVALID,		TNSZ("vperm2i128",VEX_RMRX,16),INVALID,
1685 /*  [48]  */	INVALID,		INVALID,		TNSZ("vblendvps",VEX_RMRX,8),	TNSZ("vblendvpd",VEX_RMRX,16),
1686 /*  [4C]  */	TNSZ("vpblendvb",VEX_RMRX,16),INVALID,		INVALID,		INVALID,
1687 
1688 /*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
1689 /*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
1690 /*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
1691 /*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1692 
1693 /*  [60]  */	TNSZ("vpcmpestrm",VEX_MXI,16),TNSZ("vpcmpestri",VEX_MXI,16),TNSZ("vpcmpistrm",VEX_MXI,16),TNSZ("vpcmpistri",VEX_MXI,16),
1694 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1695 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1696 /*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1697 
1698 /*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
1699 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1700 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1701 /*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1702 
1703 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1704 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1705 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1706 /*  [8C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1707 
1708 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1709 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1710 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1711 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1712 
1713 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1714 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1715 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1716 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1717 
1718 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1719 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1720 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1721 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1722 
1723 /*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1724 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1725 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1726 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1727 
1728 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1729 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1730 /*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1731 /*  [DC]  */	INVALID,		INVALID,		INVALID,		TNSZ("vaeskeygenassist",VEX_MXI,16),
1732 
1733 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1734 /*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1735 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1736 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1737 
1738 /*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1739 /*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1740 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1741 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1742 };
1743 
1744 /*
1745  * 	Decode table for 0x0F0D which uses the first byte of the mod_rm to
1746  * 	indicate a sub-code.
1747  */
1748 const instable_t dis_op0F0D[8] = {
1749 /*  [00]  */	INVALID,		TNS("prefetchw",PREF),	TNS("prefetchwt1",PREF),INVALID,
1750 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1751 };
1752 
1753 /*
1754  *	Decode table for 0x0F opcodes
1755  */
1756 
1757 const instable_t dis_op0F[16][16] = {
1758 {
1759 /*  [00]  */	IND(dis_op0F00),	IND(dis_op0F01),	TNS("lar",MR),		TNS("lsl",MR),
1760 /*  [04]  */	INVALID,		TNS("syscall",NORM),	TNS("clts",NORM),	TNS("sysret",NORM),
1761 /*  [08]  */	TNS("invd",NORM),	TNS("wbinvd",NORM),	INVALID,		TNS("ud2",NORM),
1762 /*  [0C]  */	INVALID,		IND(dis_op0F0D),	INVALID,		INVALID,
1763 }, {
1764 /*  [10]  */	TNSZ("movups",XMMO,16),	TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8),	TNSZ("movlps",XMMOS,8),
1765 /*  [14]  */	TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8),
1766 /*  [18]  */	IND(dis_op0F18),	INVALID,		INVALID,		INVALID,
1767 /*  [1C]  */	INVALID,		INVALID,		INVALID,		TS("nop",Mw),
1768 }, {
1769 /*  [20]  */	TSy("mov",SREG),	TSy("mov",SREG),	TSy("mov",SREG),	TSy("mov",SREG),
1770 /*  [24]  */	TSx("mov",SREG),	INVALID,		TSx("mov",SREG),	INVALID,
1771 /*  [28]  */	TNSZ("movaps",XMMO,16),	TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16),
1772 /*  [2C]  */	TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4),
1773 }, {
1774 /*  [30]  */	TNS("wrmsr",NORM),	TNS("rdtsc",NORM),	TNS("rdmsr",NORM),	TNS("rdpmc",NORM),
1775 /*  [34]  */	TNSx("sysenter",NORM),	TNSx("sysexit",NORM),	INVALID,		INVALID,
1776 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1777 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1778 }, {
1779 /*  [40]  */	TS("cmovx.o",MR),	TS("cmovx.no",MR),	TS("cmovx.b",MR),	TS("cmovx.ae",MR),
1780 /*  [44]  */	TS("cmovx.e",MR),	TS("cmovx.ne",MR),	TS("cmovx.be",MR),	TS("cmovx.a",MR),
1781 /*  [48]  */	TS("cmovx.s",MR),	TS("cmovx.ns",MR),	TS("cmovx.pe",MR),	TS("cmovx.po",MR),
1782 /*  [4C]  */	TS("cmovx.l",MR),	TS("cmovx.ge",MR),	TS("cmovx.le",MR),	TS("cmovx.g",MR),
1783 }, {
1784 /*  [50]  */	TNS("movmskps",XMMOX3),	TNSZ("sqrtps",XMMO,16),	TNSZ("rsqrtps",XMMO,16),TNSZ("rcpps",XMMO,16),
1785 /*  [54]  */	TNSZ("andps",XMMO,16),	TNSZ("andnps",XMMO,16),	TNSZ("orps",XMMO,16),	TNSZ("xorps",XMMO,16),
1786 /*  [58]  */	TNSZ("addps",XMMO,16),	TNSZ("mulps",XMMO,16),	TNSZ("cvtps2pd",XMMO,8),TNSZ("cvtdq2ps",XMMO,16),
1787 /*  [5C]  */	TNSZ("subps",XMMO,16),	TNSZ("minps",XMMO,16),	TNSZ("divps",XMMO,16),	TNSZ("maxps",XMMO,16),
1788 }, {
1789 /*  [60]  */	TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8),
1790 /*  [64]  */	TNSZ("pcmpgtb",MMO,8),	TNSZ("pcmpgtw",MMO,8),	TNSZ("pcmpgtd",MMO,8),	TNSZ("packuswb",MMO,8),
1791 /*  [68]  */	TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8),
1792 /*  [6C]  */	TNSZ("INVALID",MMO,0),	TNSZ("INVALID",MMO,0),	TNSZ("movd",MMO,4),	TNSZ("movq",MMO,8),
1793 }, {
1794 /*  [70]  */	TNSZ("pshufw",MMOPM,8),	TNS("psrXXX",MR),	TNS("psrXXX",MR),	TNS("psrXXX",MR),
1795 /*  [74]  */	TNSZ("pcmpeqb",MMO,8),	TNSZ("pcmpeqw",MMO,8),	TNSZ("pcmpeqd",MMO,8),	TNS("emms",NORM),
1796 /*  [78]  */	TNSy("vmread",RM),	TNSy("vmwrite",MR),	INVALID,		INVALID,
1797 /*  [7C]  */	INVALID,		INVALID,		TNSZ("movd",MMOS,4),	TNSZ("movq",MMOS,8),
1798 }, {
1799 /*  [80]  */	TNS("jo",D),		TNS("jno",D),		TNS("jb",D),		TNS("jae",D),
1800 /*  [84]  */	TNS("je",D),		TNS("jne",D),		TNS("jbe",D),		TNS("ja",D),
1801 /*  [88]  */	TNS("js",D),		TNS("jns",D),		TNS("jp",D),		TNS("jnp",D),
1802 /*  [8C]  */	TNS("jl",D),		TNS("jge",D),		TNS("jle",D),		TNS("jg",D),
1803 }, {
1804 /*  [90]  */	TNS("seto",Mb),		TNS("setno",Mb),	TNS("setb",Mb),		TNS("setae",Mb),
1805 /*  [94]  */	TNS("sete",Mb),		TNS("setne",Mb),	TNS("setbe",Mb),	TNS("seta",Mb),
1806 /*  [98]  */	TNS("sets",Mb),		TNS("setns",Mb),	TNS("setp",Mb),		TNS("setnp",Mb),
1807 /*  [9C]  */	TNS("setl",Mb),		TNS("setge",Mb),	TNS("setle",Mb),	TNS("setg",Mb),
1808 }, {
1809 /*  [A0]  */	TSp("push",LSEG),	TSp("pop",LSEG),	TNS("cpuid",NORM),	TS("bt",RMw),
1810 /*  [A4]  */	TS("shld",DSHIFT),	TS("shld",DSHIFTcl),	INVALID,		INVALID,
1811 /*  [A8]  */	TSp("push",LSEG),	TSp("pop",LSEG),	TNS("rsm",NORM),	TS("bts",RMw),
1812 /*  [AC]  */	TS("shrd",DSHIFT),	TS("shrd",DSHIFTcl),	IND(dis_op0FAE),	TS("imul",MRw),
1813 }, {
1814 /*  [B0]  */	TNS("cmpxchgb",RMw),	TS("cmpxchg",RMw),	TS("lss",MR),		TS("btr",RMw),
1815 /*  [B4]  */	TS("lfs",MR),		TS("lgs",MR),		TS("movzb",MOVZ),	TNS("movzwl",MOVZ),
1816 /*  [B8]  */	TNS("INVALID",MRw),	INVALID,		IND(dis_op0FBA),	TS("btc",RMw),
1817 /*  [BC]  */	TS("bsf",MRw),		TS("bsr",MRw),		TS("movsb",MOVZ),	TNS("movswl",MOVZ),
1818 }, {
1819 /*  [C0]  */	TNS("xaddb",XADDB),	TS("xadd",RMw),		TNSZ("cmpps",XMMOPM,16),TNS("movnti",RM),
1820 /*  [C4]  */	TNSZ("pinsrw",MMOPRM,2),TNS("pextrw",MMO3P), 	TNSZ("shufps",XMMOPM,16),IND(dis_op0FC7),
1821 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1822 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1823 }, {
1824 /*  [D0]  */	INVALID,		TNSZ("psrlw",MMO,8),	TNSZ("psrld",MMO,8),	TNSZ("psrlq",MMO,8),
1825 /*  [D4]  */	TNSZ("paddq",MMO,8),	TNSZ("pmullw",MMO,8),	TNSZ("INVALID",MMO,0),	TNS("pmovmskb",MMOM3),
1826 /*  [D8]  */	TNSZ("psubusb",MMO,8),	TNSZ("psubusw",MMO,8),	TNSZ("pminub",MMO,8),	TNSZ("pand",MMO,8),
1827 /*  [DC]  */	TNSZ("paddusb",MMO,8),	TNSZ("paddusw",MMO,8),	TNSZ("pmaxub",MMO,8),	TNSZ("pandn",MMO,8),
1828 }, {
1829 /*  [E0]  */	TNSZ("pavgb",MMO,8),	TNSZ("psraw",MMO,8),	TNSZ("psrad",MMO,8),	TNSZ("pavgw",MMO,8),
1830 /*  [E4]  */	TNSZ("pmulhuw",MMO,8),	TNSZ("pmulhw",MMO,8),	TNS("INVALID",XMMO),	TNSZ("movntq",MMOMS,8),
1831 /*  [E8]  */	TNSZ("psubsb",MMO,8),	TNSZ("psubsw",MMO,8),	TNSZ("pminsw",MMO,8),	TNSZ("por",MMO,8),
1832 /*  [EC]  */	TNSZ("paddsb",MMO,8),	TNSZ("paddsw",MMO,8),	TNSZ("pmaxsw",MMO,8),	TNSZ("pxor",MMO,8),
1833 }, {
1834 /*  [F0]  */	INVALID,		TNSZ("psllw",MMO,8),	TNSZ("pslld",MMO,8),	TNSZ("psllq",MMO,8),
1835 /*  [F4]  */	TNSZ("pmuludq",MMO,8),	TNSZ("pmaddwd",MMO,8),	TNSZ("psadbw",MMO,8),	TNSZ("maskmovq",MMOIMPL,8),
1836 /*  [F8]  */	TNSZ("psubb",MMO,8),	TNSZ("psubw",MMO,8),	TNSZ("psubd",MMO,8),	TNSZ("psubq",MMO,8),
1837 /*  [FC]  */	TNSZ("paddb",MMO,8),	TNSZ("paddw",MMO,8),	TNSZ("paddd",MMO,8),	INVALID,
1838 } };
1839 
1840 const instable_t dis_opAVX0F[16][16] = {
1841 {
1842 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1843 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1844 /*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
1845 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1846 }, {
1847 /*  [10]  */	TNSZ("vmovups",VEX_MX,16),	TNSZ("vmovups",VEX_RM,16),TNSZ("vmovlps",VEX_RMrX,8),	TNSZ("vmovlps",VEX_RM,8),
1848 /*  [14]  */	TNSZ("vunpcklps",VEX_RMrX,16),TNSZ("vunpckhps",VEX_RMrX,16),TNSZ("vmovhps",VEX_RMrX,8),TNSZ("vmovhps",VEX_RM,8),
1849 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1850 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1851 }, {
1852 /*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
1853 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1854 /*  [28]  */	TNSZ("vmovaps",VEX_MX,16),	TNSZ("vmovaps",VEX_RX,16),INVALID,		TNSZ("vmovntps",VEX_RM,16),
1855 /*  [2C]  */	INVALID,		INVALID,		TNSZ("vucomiss",VEX_MX,4),TNSZ("vcomiss",VEX_MX,4),
1856 }, {
1857 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1858 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1859 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1860 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1861 }, {
1862 /*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1863 /*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
1864 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1865 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1866 }, {
1867 /*  [50]  */	TNS("vmovmskps",VEX_MR),	TNSZ("vsqrtps",VEX_MX,16),	TNSZ("vrsqrtps",VEX_MX,16),TNSZ("vrcpps",VEX_MX,16),
1868 /*  [54]  */	TNSZ("vandps",VEX_RMrX,16),	TNSZ("vandnps",VEX_RMrX,16),	TNSZ("vorps",VEX_RMrX,16),	TNSZ("vxorps",VEX_RMrX,16),
1869 /*  [58]  */	TNSZ("vaddps",VEX_RMrX,16),	TNSZ("vmulps",VEX_RMrX,16),	TNSZ("vcvtps2pd",VEX_MX,8),TNSZ("vcvtdq2ps",VEX_MX,16),
1870 /*  [5C]  */	TNSZ("vsubps",VEX_RMrX,16),	TNSZ("vminps",VEX_RMrX,16),	TNSZ("vdivps",VEX_RMrX,16),	TNSZ("vmaxps",VEX_RMrX,16),
1871 }, {
1872 /*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1873 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1874 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1875 /*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1876 }, {
1877 /*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
1878 /*  [74]  */	INVALID,		INVALID,		INVALID,		TNS("vzeroupper", VEX_NONE),
1879 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1880 /*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1881 }, {
1882 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1883 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1884 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1885 /*  [8C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1886 }, {
1887 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1888 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1889 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1890 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1891 }, {
1892 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1893 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1894 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1895 /*  [AC]  */	INVALID,		INVALID,		TNSZ("vldmxcsr",VEX_MO,2),		INVALID,
1896 }, {
1897 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1898 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1899 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1900 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1901 }, {
1902 /*  [C0]  */	INVALID,		INVALID,		TNSZ("vcmpps",VEX_RMRX,16),INVALID,
1903 /*  [C4]  */	INVALID,		INVALID,	 	TNSZ("vshufps",VEX_RMRX,16),INVALID,
1904 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1905 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1906 }, {
1907 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1908 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1909 /*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1910 /*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1911 }, {
1912 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1913 /*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1914 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1915 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1916 }, {
1917 /*  [F0]  */	INVALID,		INVALID,		TNSZvr("andn",VEX_RMrX,5),TNSZvr("bls",BLS,5),
1918 /*  [F4]  */	INVALID,		TNSZvr("bzhi",VEX_VRMrX,5),INVALID,		TNSZvr("bextr",VEX_VRMrX,5),
1919 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1920 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1921 } };
1922 
1923 /*
1924  *	Decode table for 0x80 opcodes
1925  */
1926 
1927 const instable_t dis_op80[8] = {
1928 
1929 /*  [0]  */	TNS("addb",IMlw),	TNS("orb",IMw),		TNS("adcb",IMlw),	TNS("sbbb",IMlw),
1930 /*  [4]  */	TNS("andb",IMw),	TNS("subb",IMlw),	TNS("xorb",IMw),	TNS("cmpb",IMlw),
1931 };
1932 
1933 
1934 /*
1935  *	Decode table for 0x81 opcodes.
1936  */
1937 
1938 const instable_t dis_op81[8] = {
1939 
1940 /*  [0]  */	TS("add",IMlw),		TS("or",IMw),		TS("adc",IMlw),		TS("sbb",IMlw),
1941 /*  [4]  */	TS("and",IMw),		TS("sub",IMlw),		TS("xor",IMw),		TS("cmp",IMlw),
1942 };
1943 
1944 
1945 /*
1946  *	Decode table for 0x82 opcodes.
1947  */
1948 
1949 const instable_t dis_op82[8] = {
1950 
1951 /*  [0]  */	TNSx("addb",IMlw),	TNSx("orb",IMlw),	TNSx("adcb",IMlw),	TNSx("sbbb",IMlw),
1952 /*  [4]  */	TNSx("andb",IMlw),	TNSx("subb",IMlw),	TNSx("xorb",IMlw),	TNSx("cmpb",IMlw),
1953 };
1954 /*
1955  *	Decode table for 0x83 opcodes.
1956  */
1957 
1958 const instable_t dis_op83[8] = {
1959 
1960 /*  [0]  */	TS("add",IMlw),		TS("or",IMlw),		TS("adc",IMlw),		TS("sbb",IMlw),
1961 /*  [4]  */	TS("and",IMlw),		TS("sub",IMlw),		TS("xor",IMlw),		TS("cmp",IMlw),
1962 };
1963 
1964 /*
1965  *	Decode table for 0xC0 opcodes.
1966  */
1967 
1968 const instable_t dis_opC0[8] = {
1969 
1970 /*  [0]  */	TNS("rolb",MvI),	TNS("rorb",MvI),	TNS("rclb",MvI),	TNS("rcrb",MvI),
1971 /*  [4]  */	TNS("shlb",MvI),	TNS("shrb",MvI),	INVALID,		TNS("sarb",MvI),
1972 };
1973 
1974 /*
1975  *	Decode table for 0xD0 opcodes.
1976  */
1977 
1978 const instable_t dis_opD0[8] = {
1979 
1980 /*  [0]  */	TNS("rolb",Mv),		TNS("rorb",Mv),		TNS("rclb",Mv),		TNS("rcrb",Mv),
1981 /*  [4]  */	TNS("shlb",Mv),		TNS("shrb",Mv),		TNS("salb",Mv),		TNS("sarb",Mv),
1982 };
1983 
1984 /*
1985  *	Decode table for 0xC1 opcodes.
1986  *	186 instruction set
1987  */
1988 
1989 const instable_t dis_opC1[8] = {
1990 
1991 /*  [0]  */	TS("rol",MvI),		TS("ror",MvI),		TS("rcl",MvI),		TS("rcr",MvI),
1992 /*  [4]  */	TS("shl",MvI),		TS("shr",MvI),		TS("sal",MvI),		TS("sar",MvI),
1993 };
1994 
1995 /*
1996  *	Decode table for 0xD1 opcodes.
1997  */
1998 
1999 const instable_t dis_opD1[8] = {
2000 
2001 /*  [0]  */	TS("rol",Mv),		TS("ror",Mv),		TS("rcl",Mv),		TS("rcr",Mv),
2002 /*  [4]  */	TS("shl",Mv),		TS("shr",Mv),		TS("sal",Mv),		TS("sar",Mv),
2003 };
2004 
2005 
2006 /*
2007  *	Decode table for 0xD2 opcodes.
2008  */
2009 
2010 const instable_t dis_opD2[8] = {
2011 
2012 /*  [0]  */	TNS("rolb",Mv),		TNS("rorb",Mv),		TNS("rclb",Mv),		TNS("rcrb",Mv),
2013 /*  [4]  */	TNS("shlb",Mv),		TNS("shrb",Mv),		TNS("salb",Mv),		TNS("sarb",Mv),
2014 };
2015 /*
2016  *	Decode table for 0xD3 opcodes.
2017  */
2018 
2019 const instable_t dis_opD3[8] = {
2020 
2021 /*  [0]  */	TS("rol",Mv),		TS("ror",Mv),		TS("rcl",Mv),		TS("rcr",Mv),
2022 /*  [4]  */	TS("shl",Mv),		TS("shr",Mv),		TS("salb",Mv),		TS("sar",Mv),
2023 };
2024 
2025 
2026 /*
2027  *	Decode table for 0xF6 opcodes.
2028  */
2029 
2030 const instable_t dis_opF6[8] = {
2031 
2032 /*  [0]  */	TNS("testb",IMw),	TNS("testb",IMw),	TNS("notb",Mw),		TNS("negb",Mw),
2033 /*  [4]  */	TNS("mulb",MA),		TNS("imulb",MA),	TNS("divb",MA),		TNS("idivb",MA),
2034 };
2035 
2036 
2037 /*
2038  *	Decode table for 0xF7 opcodes.
2039  */
2040 
2041 const instable_t dis_opF7[8] = {
2042 
2043 /*  [0]  */	TS("test",IMw),		TS("test",IMw),		TS("not",Mw),		TS("neg",Mw),
2044 /*  [4]  */	TS("mul",MA),		TS("imul",MA),		TS("div",MA),		TS("idiv",MA),
2045 };
2046 
2047 
2048 /*
2049  *	Decode table for 0xFE opcodes.
2050  */
2051 
2052 const instable_t dis_opFE[8] = {
2053 
2054 /*  [0]  */	TNS("incb",Mw),		TNS("decb",Mw),		INVALID,		INVALID,
2055 /*  [4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2056 };
2057 /*
2058  *	Decode table for 0xFF opcodes.
2059  */
2060 
2061 const instable_t dis_opFF[8] = {
2062 
2063 /*  [0]  */	TS("inc",Mw),		TS("dec",Mw),		TNSyp("call",INM),	TNS("lcall",INM),
2064 /*  [4]  */	TNSy("jmp",INM),	TNS("ljmp",INM),	TSp("push",M),		INVALID,
2065 };
2066 
2067 /* for 287 instructions, which are a mess to decode */
2068 
2069 const instable_t dis_opFP1n2[8][8] = {
2070 {
2071 /* bit pattern:	1101 1xxx MODxx xR/M */
2072 /*  [0,0] */	TNS("fadds",M),		TNS("fmuls",M),		TNS("fcoms",M),		TNS("fcomps",M),
2073 /*  [0,4] */	TNS("fsubs",M),		TNS("fsubrs",M),	TNS("fdivs",M),		TNS("fdivrs",M),
2074 }, {
2075 /*  [1,0]  */	TNS("flds",M),		INVALID,		TNS("fsts",M),		TNS("fstps",M),
2076 /*  [1,4]  */	TNSZ("fldenv",M,28),	TNSZ("fldcw",M,2),	TNSZ("fnstenv",M,28),	TNSZ("fnstcw",M,2),
2077 }, {
2078 /*  [2,0]  */	TNS("fiaddl",M),	TNS("fimull",M),	TNS("ficoml",M),	TNS("ficompl",M),
2079 /*  [2,4]  */	TNS("fisubl",M),	TNS("fisubrl",M),	TNS("fidivl",M),	TNS("fidivrl",M),
2080 }, {
2081 /*  [3,0]  */	TNS("fildl",M),		TNSZ("tisttpl",M,4),	TNS("fistl",M),		TNS("fistpl",M),
2082 /*  [3,4]  */	INVALID,		TNSZ("fldt",M,10),	INVALID,		TNSZ("fstpt",M,10),
2083 }, {
2084 /*  [4,0]  */	TNSZ("faddl",M,8),	TNSZ("fmull",M,8),	TNSZ("fcoml",M,8),	TNSZ("fcompl",M,8),
2085 /*  [4,1]  */	TNSZ("fsubl",M,8),	TNSZ("fsubrl",M,8),	TNSZ("fdivl",M,8),	TNSZ("fdivrl",M,8),
2086 }, {
2087 /*  [5,0]  */	TNSZ("fldl",M,8),	TNSZ("fisttpll",M,8),	TNSZ("fstl",M,8),	TNSZ("fstpl",M,8),
2088 /*  [5,4]  */	TNSZ("frstor",M,108),	INVALID,		TNSZ("fnsave",M,108),	TNSZ("fnstsw",M,2),
2089 }, {
2090 /*  [6,0]  */	TNSZ("fiadd",M,2),	TNSZ("fimul",M,2),	TNSZ("ficom",M,2),	TNSZ("ficomp",M,2),
2091 /*  [6,4]  */	TNSZ("fisub",M,2),	TNSZ("fisubr",M,2),	TNSZ("fidiv",M,2),	TNSZ("fidivr",M,2),
2092 }, {
2093 /*  [7,0]  */	TNSZ("fild",M,2),	TNSZ("fisttp",M,2),	TNSZ("fist",M,2),	TNSZ("fistp",M,2),
2094 /*  [7,4]  */	TNSZ("fbld",M,10),	TNSZ("fildll",M,8),	TNSZ("fbstp",M,10),	TNSZ("fistpll",M,8),
2095 } };
2096 
2097 const instable_t dis_opFP3[8][8] = {
2098 {
2099 /* bit  pattern:	1101 1xxx 11xx xREG */
2100 /*  [0,0]  */	TNS("fadd",FF),		TNS("fmul",FF),		TNS("fcom",F),		TNS("fcomp",F),
2101 /*  [0,4]  */	TNS("fsub",FF),		TNS("fsubr",FF),	TNS("fdiv",FF),		TNS("fdivr",FF),
2102 }, {
2103 /*  [1,0]  */	TNS("fld",F),		TNS("fxch",F),		TNS("fnop",NORM),	TNS("fstp",F),
2104 /*  [1,4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2105 }, {
2106 /*  [2,0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2107 /*  [2,4]  */	INVALID,		TNS("fucompp",NORM),	INVALID,		INVALID,
2108 }, {
2109 /*  [3,0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2110 /*  [3,4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2111 }, {
2112 /*  [4,0]  */	TNS("fadd",FF),		TNS("fmul",FF),		TNS("fcom",F),		TNS("fcomp",F),
2113 /*  [4,4]  */	TNS("fsub",FF),		TNS("fsubr",FF),	TNS("fdiv",FF),		TNS("fdivr",FF),
2114 }, {
2115 /*  [5,0]  */	TNS("ffree",F),		TNS("fxch",F),		TNS("fst",F),		TNS("fstp",F),
2116 /*  [5,4]  */	TNS("fucom",F),		TNS("fucomp",F),	INVALID,		INVALID,
2117 }, {
2118 /*  [6,0]  */	TNS("faddp",FF),	TNS("fmulp",FF),	TNS("fcomp",F),		TNS("fcompp",NORM),
2119 /*  [6,4]  */	TNS("fsubp",FF),	TNS("fsubrp",FF),	TNS("fdivp",FF),	TNS("fdivrp",FF),
2120 }, {
2121 /*  [7,0]  */	TNS("ffreep",F),		TNS("fxch",F),		TNS("fstp",F),		TNS("fstp",F),
2122 /*  [7,4]  */	TNS("fnstsw",M),	TNS("fucomip",FFC),	TNS("fcomip",FFC),	INVALID,
2123 } };
2124 
2125 const instable_t dis_opFP4[4][8] = {
2126 {
2127 /* bit pattern:	1101 1001 111x xxxx */
2128 /*  [0,0]  */	TNS("fchs",NORM),	TNS("fabs",NORM),	INVALID,		INVALID,
2129 /*  [0,4]  */	TNS("ftst",NORM),	TNS("fxam",NORM),	TNS("ftstp",NORM),	INVALID,
2130 }, {
2131 /*  [1,0]  */	TNS("fld1",NORM),	TNS("fldl2t",NORM),	TNS("fldl2e",NORM),	TNS("fldpi",NORM),
2132 /*  [1,4]  */	TNS("fldlg2",NORM),	TNS("fldln2",NORM),	TNS("fldz",NORM),	INVALID,
2133 }, {
2134 /*  [2,0]  */	TNS("f2xm1",NORM),	TNS("fyl2x",NORM),	TNS("fptan",NORM),	TNS("fpatan",NORM),
2135 /*  [2,4]  */	TNS("fxtract",NORM),	TNS("fprem1",NORM),	TNS("fdecstp",NORM),	TNS("fincstp",NORM),
2136 }, {
2137 /*  [3,0]  */	TNS("fprem",NORM),	TNS("fyl2xp1",NORM),	TNS("fsqrt",NORM),	TNS("fsincos",NORM),
2138 /*  [3,4]  */	TNS("frndint",NORM),	TNS("fscale",NORM),	TNS("fsin",NORM),	TNS("fcos",NORM),
2139 } };
2140 
2141 const instable_t dis_opFP5[8] = {
2142 /* bit pattern:	1101 1011 111x xxxx */
2143 /*  [0]  */	TNS("feni",NORM),	TNS("fdisi",NORM),	TNS("fnclex",NORM),	TNS("fninit",NORM),
2144 /*  [4]  */	TNS("fsetpm",NORM),	TNS("frstpm",NORM),	INVALID,		INVALID,
2145 };
2146 
2147 const instable_t dis_opFP6[8] = {
2148 /* bit pattern:	1101 1011 11yy yxxx */
2149 /*  [00]  */	TNS("fcmov.nb",FF),	TNS("fcmov.ne",FF),	TNS("fcmov.nbe",FF),	TNS("fcmov.nu",FF),
2150 /*  [04]  */	INVALID,		TNS("fucomi",F),	TNS("fcomi",F),		INVALID,
2151 };
2152 
2153 const instable_t dis_opFP7[8] = {
2154 /* bit pattern:	1101 1010 11yy yxxx */
2155 /*  [00]  */	TNS("fcmov.b",FF),	TNS("fcmov.e",FF),	TNS("fcmov.be",FF),	TNS("fcmov.u",FF),
2156 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
2157 };
2158 
2159 /*
2160  *	Main decode table for the op codes.  The first two nibbles
2161  *	will be used as an index into the table.  If there is a
2162  *	a need to further decode an instruction, the array to be
2163  *	referenced is indicated with the other two entries being
2164  *	empty.
2165  */
2166 
2167 const instable_t dis_distable[16][16] = {
2168 {
2169 /* [0,0] */	TNS("addb",RMw),	TS("add",RMw),		TNS("addb",MRw),	TS("add",MRw),
2170 /* [0,4] */	TNS("addb",IA),		TS("add",IA),		TSx("push",SEG),	TSx("pop",SEG),
2171 /* [0,8] */	TNS("orb",RMw),		TS("or",RMw),		TNS("orb",MRw),		TS("or",MRw),
2172 /* [0,C] */	TNS("orb",IA),		TS("or",IA),		TSx("push",SEG),	IND(dis_op0F),
2173 }, {
2174 /* [1,0] */	TNS("adcb",RMw),	TS("adc",RMw),		TNS("adcb",MRw),	TS("adc",MRw),
2175 /* [1,4] */	TNS("adcb",IA),		TS("adc",IA),		TSx("push",SEG),	TSx("pop",SEG),
2176 /* [1,8] */	TNS("sbbb",RMw),	TS("sbb",RMw),		TNS("sbbb",MRw),	TS("sbb",MRw),
2177 /* [1,C] */	TNS("sbbb",IA),		TS("sbb",IA),		TSx("push",SEG),	TSx("pop",SEG),
2178 }, {
2179 /* [2,0] */	TNS("andb",RMw),	TS("and",RMw),		TNS("andb",MRw),	TS("and",MRw),
2180 /* [2,4] */	TNS("andb",IA),		TS("and",IA),		TNSx("%es:",OVERRIDE),	TNSx("daa",NORM),
2181 /* [2,8] */	TNS("subb",RMw),	TS("sub",RMw),		TNS("subb",MRw),	TS("sub",MRw),
2182 /* [2,C] */	TNS("subb",IA),		TS("sub",IA),		TNS("%cs:",OVERRIDE),	TNSx("das",NORM),
2183 }, {
2184 /* [3,0] */	TNS("xorb",RMw),	TS("xor",RMw),		TNS("xorb",MRw),	TS("xor",MRw),
2185 /* [3,4] */	TNS("xorb",IA),		TS("xor",IA),		TNSx("%ss:",OVERRIDE),	TNSx("aaa",NORM),
2186 /* [3,8] */	TNS("cmpb",RMw),	TS("cmp",RMw),		TNS("cmpb",MRw),	TS("cmp",MRw),
2187 /* [3,C] */	TNS("cmpb",IA),		TS("cmp",IA),		TNSx("%ds:",OVERRIDE),	TNSx("aas",NORM),
2188 }, {
2189 /* [4,0] */	TSx("inc",R),		TSx("inc",R),		TSx("inc",R),		TSx("inc",R),
2190 /* [4,4] */	TSx("inc",R),		TSx("inc",R),		TSx("inc",R),		TSx("inc",R),
2191 /* [4,8] */	TSx("dec",R),		TSx("dec",R),		TSx("dec",R),		TSx("dec",R),
2192 /* [4,C] */	TSx("dec",R),		TSx("dec",R),		TSx("dec",R),		TSx("dec",R),
2193 }, {
2194 /* [5,0] */	TSp("push",R),		TSp("push",R),		TSp("push",R),		TSp("push",R),
2195 /* [5,4] */	TSp("push",R),		TSp("push",R),		TSp("push",R),		TSp("push",R),
2196 /* [5,8] */	TSp("pop",R),		TSp("pop",R),		TSp("pop",R),		TSp("pop",R),
2197 /* [5,C] */	TSp("pop",R),		TSp("pop",R),		TSp("pop",R),		TSp("pop",R),
2198 }, {
2199 /* [6,0] */	TSZx("pusha",IMPLMEM,28),TSZx("popa",IMPLMEM,28), TSx("bound",MR),	TNS("arpl",RMw),
2200 /* [6,4] */	TNS("%fs:",OVERRIDE),	TNS("%gs:",OVERRIDE),	TNS("data16",DM),	TNS("addr16",AM),
2201 /* [6,8] */	TSp("push",I),		TS("imul",IMUL),	TSp("push",Ib),	TS("imul",IMUL),
2202 /* [6,C] */	TNSZ("insb",IMPLMEM,1),	TSZ("ins",IMPLMEM,4),	TNSZ("outsb",IMPLMEM,1),TSZ("outs",IMPLMEM,4),
2203 }, {
2204 /* [7,0] */	TNSy("jo",BD),		TNSy("jno",BD),		TNSy("jb",BD),		TNSy("jae",BD),
2205 /* [7,4] */	TNSy("je",BD),		TNSy("jne",BD),		TNSy("jbe",BD),		TNSy("ja",BD),
2206 /* [7,8] */	TNSy("js",BD),		TNSy("jns",BD),		TNSy("jp",BD),		TNSy("jnp",BD),
2207 /* [7,C] */	TNSy("jl",BD),		TNSy("jge",BD),		TNSy("jle",BD),		TNSy("jg",BD),
2208 }, {
2209 /* [8,0] */	IND(dis_op80),		IND(dis_op81),		INDx(dis_op82),		IND(dis_op83),
2210 /* [8,4] */	TNS("testb",RMw),	TS("test",RMw),		TNS("xchgb",RMw),	TS("xchg",RMw),
2211 /* [8,8] */	TNS("movb",RMw),	TS("mov",RMw),		TNS("movb",MRw),	TS("mov",MRw),
2212 /* [8,C] */	TNS("movw",SM),		TS("lea",MR),		TNS("movw",MS),		TSp("pop",M),
2213 }, {
2214 /* [9,0] */	TNS("nop",NORM),	TS("xchg",RA),		TS("xchg",RA),		TS("xchg",RA),
2215 /* [9,4] */	TS("xchg",RA),		TS("xchg",RA),		TS("xchg",RA),		TS("xchg",RA),
2216 /* [9,8] */	TNS("cXtX",CBW),	TNS("cXtX",CWD),	TNSx("lcall",SO),	TNS("fwait",NORM),
2217 /* [9,C] */	TSZy("pushf",IMPLMEM,4),TSZy("popf",IMPLMEM,4),	TNS("sahf",NORM),	TNS("lahf",NORM),
2218 }, {
2219 /* [A,0] */	TNS("movb",OA),		TS("mov",OA),		TNS("movb",AO),		TS("mov",AO),
2220 /* [A,4] */	TNSZ("movsb",SD,1),	TS("movs",SD),		TNSZ("cmpsb",SD,1),	TS("cmps",SD),
2221 /* [A,8] */	TNS("testb",IA),	TS("test",IA),		TNS("stosb",AD),	TS("stos",AD),
2222 /* [A,C] */	TNS("lodsb",SA),	TS("lods",SA),		TNS("scasb",AD),	TS("scas",AD),
2223 }, {
2224 /* [B,0] */	TNS("movb",IR),		TNS("movb",IR),		TNS("movb",IR),		TNS("movb",IR),
2225 /* [B,4] */	TNS("movb",IR),		TNS("movb",IR),		TNS("movb",IR),		TNS("movb",IR),
2226 /* [B,8] */	TS("mov",IR),		TS("mov",IR),		TS("mov",IR),		TS("mov",IR),
2227 /* [B,C] */	TS("mov",IR),		TS("mov",IR),		TS("mov",IR),		TS("mov",IR),
2228 }, {
2229 /* [C,0] */	IND(dis_opC0),		IND(dis_opC1), 		TNSyp("ret",RET),	TNSyp("ret",NORM),
2230 /* [C,4] */	TNSx("les",MR),		TNSx("lds",MR),		TNS("movb",IMw),	TS("mov",IMw),
2231 /* [C,8] */	TNSyp("enter",ENTER),	TNSyp("leave",NORM),	TNS("lret",RET),	TNS("lret",NORM),
2232 /* [C,C] */	TNS("int",INT3),	TNS("int",INTx),	TNSx("into",NORM),	TNS("iret",NORM),
2233 }, {
2234 /* [D,0] */	IND(dis_opD0),		IND(dis_opD1),		IND(dis_opD2),		IND(dis_opD3),
2235 /* [D,4] */	TNSx("aam",U),		TNSx("aad",U),		TNSx("falc",NORM),	TNSZ("xlat",IMPLMEM,1),
2236 
2237 /* 287 instructions.  Note that although the indirect field		*/
2238 /* indicates opFP1n2 for further decoding, this is not necessarily	*/
2239 /* the case since the opFP arrays are not partitioned according to key1	*/
2240 /* and key2.  opFP1n2 is given only to indicate that we haven't		*/
2241 /* finished decoding the instruction.					*/
2242 /* [D,8] */	IND(dis_opFP1n2),	IND(dis_opFP1n2),	IND(dis_opFP1n2),	IND(dis_opFP1n2),
2243 /* [D,C] */	IND(dis_opFP1n2),	IND(dis_opFP1n2),	IND(dis_opFP1n2),	IND(dis_opFP1n2),
2244 }, {
2245 /* [E,0] */	TNSy("loopnz",BD),	TNSy("loopz",BD),	TNSy("loop",BD),	TNSy("jcxz",BD),
2246 /* [E,4] */	TNS("inb",P),		TS("in",P),		TNS("outb",P),		TS("out",P),
2247 /* [E,8] */	TNSyp("call",D),	TNSy("jmp",D),		TNSx("ljmp",SO),		TNSy("jmp",BD),
2248 /* [E,C] */	TNS("inb",V),		TS("in",V),		TNS("outb",V),		TS("out",V),
2249 }, {
2250 /* [F,0] */	TNS("lock",LOCK),	TNS("icebp", NORM),	TNS("repnz",PREFIX),	TNS("repz",PREFIX),
2251 /* [F,4] */	TNS("hlt",NORM),	TNS("cmc",NORM),	IND(dis_opF6),		IND(dis_opF7),
2252 /* [F,8] */	TNS("clc",NORM),	TNS("stc",NORM),	TNS("cli",NORM),	TNS("sti",NORM),
2253 /* [F,C] */	TNS("cld",NORM),	TNS("std",NORM),	IND(dis_opFE),		IND(dis_opFF),
2254 } };
2255 
2256 /* END CSTYLED */
2257 
2258 /*
2259  * common functions to decode and disassemble an x86 or amd64 instruction
2260  */
2261 
2262 /*
2263  * These are the individual fields of a REX prefix. Note that a REX
2264  * prefix with none of these set is still needed to:
2265  *	- use the MOVSXD (sign extend 32 to 64 bits) instruction
2266  *	- access the %sil, %dil, %bpl, %spl registers
2267  */
2268 #define	REX_W 0x08	/* 64 bit operand size when set */
2269 #define	REX_R 0x04	/* high order bit extension of ModRM reg field */
2270 #define	REX_X 0x02	/* high order bit extension of SIB index field */
2271 #define	REX_B 0x01	/* extends ModRM r_m, SIB base, or opcode reg */
2272 
2273 /*
2274  * These are the individual fields of a VEX prefix.
2275  */
2276 #define	VEX_R 0x08	/* REX.R in 1's complement form */
2277 #define	VEX_X 0x04	/* REX.X in 1's complement form */
2278 #define	VEX_B 0x02	/* REX.B in 1's complement form */
2279 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector */
2280 #define	VEX_L 0x04
2281 #define	VEX_W 0x08	/* opcode specific, use like REX.W */
2282 #define	VEX_m 0x1F	/* VEX m-mmmm field */
2283 #define	VEX_v 0x78	/* VEX register specifier */
2284 #define	VEX_p 0x03	/* VEX pp field, opcode extension */
2285 
2286 /* VEX m-mmmm field, only used by three bytes prefix */
2287 #define	VEX_m_0F 0x01   /* implied 0F leading opcode byte */
2288 #define	VEX_m_0F38 0x02 /* implied 0F 38 leading opcode byte */
2289 #define	VEX_m_0F3A 0x03 /* implied 0F 3A leading opcode byte */
2290 
2291 /* VEX pp field, providing equivalent functionality of a SIMD prefix */
2292 #define	VEX_p_66 0x01
2293 #define	VEX_p_F3 0x02
2294 #define	VEX_p_F2 0x03
2295 
2296 /*
2297  * Even in 64 bit mode, usually only 4 byte immediate operands are supported.
2298  */
2299 static int isize[] = {1, 2, 4, 4};
2300 static int isize64[] = {1, 2, 4, 8};
2301 
2302 /*
2303  * Just a bunch of useful macros.
2304  */
2305 #define	WBIT(x)	(x & 0x1)		/* to get w bit	*/
2306 #define	REGNO(x) (x & 0x7)		/* to get 3 bit register */
2307 #define	VBIT(x)	((x)>>1 & 0x1)		/* to get 'v' bit */
2308 #define	OPSIZE(osize, wbit) ((wbit) ? isize[osize] : 1)
2309 #define	OPSIZE64(osize, wbit) ((wbit) ? isize64[osize] : 1)
2310 
2311 #define	REG_ONLY 3	/* mode to indicate a register operand (not memory) */
2312 
2313 #define	BYTE_OPND	0	/* w-bit value indicating byte register */
2314 #define	LONG_OPND	1	/* w-bit value indicating opnd_size register */
2315 #define	MM_OPND		2	/* "value" used to indicate a mmx reg */
2316 #define	XMM_OPND	3	/* "value" used to indicate a xmm reg */
2317 #define	SEG_OPND	4	/* "value" used to indicate a segment reg */
2318 #define	CONTROL_OPND	5	/* "value" used to indicate a control reg */
2319 #define	DEBUG_OPND	6	/* "value" used to indicate a debug reg */
2320 #define	TEST_OPND	7	/* "value" used to indicate a test reg */
2321 #define	WORD_OPND	8	/* w-bit value indicating word size reg */
2322 #define	YMM_OPND	9	/* "value" used to indicate a ymm reg */
2323 
2324 /*
2325  * The AVX2 gather instructions are a bit of a mess. While there's a pattern,
2326  * there's not really a consistent scheme that we can use to know what the mode
2327  * is supposed to be for a given type. Various instructions, like VPGATHERDD,
2328  * always match the value of VEX_L. Other instructions like VPGATHERDQ, have
2329  * some registers match VEX_L, but the VSIB is always XMM.
2330  *
2331  * The simplest way to deal with this is to just define a table based on the
2332  * instruction opcodes, which are 0x90-0x93, so we subtract 0x90 to index into
2333  * them.
2334  *
2335  * We further have to subdivide this based on the value of VEX_W and the value
2336  * of VEX_L. The array is constructed to be indexed as:
2337  * 	[opcode - 0x90][VEX_W][VEX_L].
2338  */
2339 /* w = 0, 0x90 */
2340 typedef struct dis_gather_regs {
2341 	uint_t dgr_arg0;	/* src reg */
2342 	uint_t dgr_arg1;	/* vsib reg */
2343 	uint_t dgr_arg2;	/* dst reg */
2344 	char   *dgr_suffix;	/* suffix to append */
2345 } dis_gather_regs_t;
2346 
2347 static dis_gather_regs_t dis_vgather[4][2][2] = {
2348 	{
2349 		/* op 0x90, W.0 */
2350 		{
2351 			{ XMM_OPND, XMM_OPND, XMM_OPND, "d" },
2352 			{ YMM_OPND, YMM_OPND, YMM_OPND, "d" }
2353 		},
2354 		/* op 0x90, W.1 */
2355 		{
2356 			{ XMM_OPND, XMM_OPND, XMM_OPND, "q" },
2357 			{ YMM_OPND, XMM_OPND, YMM_OPND, "q" }
2358 		}
2359 	},
2360 	{
2361 		/* op 0x91, W.0 */
2362 		{
2363 			{ XMM_OPND, XMM_OPND, XMM_OPND, "d" },
2364 			{ XMM_OPND, YMM_OPND, XMM_OPND, "d" },
2365 		},
2366 		/* op 0x91, W.1 */
2367 		{
2368 			{ XMM_OPND, XMM_OPND, XMM_OPND, "q" },
2369 			{ YMM_OPND, YMM_OPND, YMM_OPND, "q" },
2370 		}
2371 	},
2372 	{
2373 		/* op 0x92, W.0 */
2374 		{
2375 			{ XMM_OPND, XMM_OPND, XMM_OPND, "s" },
2376 			{ YMM_OPND, YMM_OPND, YMM_OPND, "s" }
2377 		},
2378 		/* op 0x92, W.1 */
2379 		{
2380 			{ XMM_OPND, XMM_OPND, XMM_OPND, "d" },
2381 			{ YMM_OPND, XMM_OPND, YMM_OPND, "d" }
2382 		}
2383 	},
2384 	{
2385 		/* op 0x93, W.0 */
2386 		{
2387 			{ XMM_OPND, XMM_OPND, XMM_OPND, "s" },
2388 			{ XMM_OPND, YMM_OPND, XMM_OPND, "s" }
2389 		},
2390 		/* op 0x93, W.1 */
2391 		{
2392 			{ XMM_OPND, XMM_OPND, XMM_OPND, "d" },
2393 			{ YMM_OPND, YMM_OPND, YMM_OPND, "d" }
2394 		}
2395 	}
2396 };
2397 
2398 /*
2399  * Get the next byte and separate the op code into the high and low nibbles.
2400  */
2401 static int
2402 dtrace_get_opcode(dis86_t *x, uint_t *high, uint_t *low)
2403 {
2404 	int byte;
2405 
2406 	/*
2407 	 * x86 instructions have a maximum length of 15 bytes.  Bail out if
2408 	 * we try to read more.
2409 	 */
2410 	if (x->d86_len >= 15)
2411 		return (x->d86_error = 1);
2412 
2413 	if (x->d86_error)
2414 		return (1);
2415 	byte = x->d86_get_byte(x->d86_data);
2416 	if (byte < 0)
2417 		return (x->d86_error = 1);
2418 	x->d86_bytes[x->d86_len++] = byte;
2419 	*low = byte & 0xf;		/* ----xxxx low 4 bits */
2420 	*high = byte >> 4 & 0xf;	/* xxxx---- bits 7 to 4 */
2421 	return (0);
2422 }
2423 
2424 /*
2425  * Get and decode an SIB (scaled index base) byte
2426  */
2427 static void
2428 dtrace_get_SIB(dis86_t *x, uint_t *ss, uint_t *index, uint_t *base)
2429 {
2430 	int byte;
2431 
2432 	if (x->d86_error)
2433 		return;
2434 
2435 	byte = x->d86_get_byte(x->d86_data);
2436 	if (byte < 0) {
2437 		x->d86_error = 1;
2438 		return;
2439 	}
2440 	x->d86_bytes[x->d86_len++] = byte;
2441 
2442 	*base = byte & 0x7;
2443 	*index = (byte >> 3) & 0x7;
2444 	*ss = (byte >> 6) & 0x3;
2445 }
2446 
2447 /*
2448  * Get the byte following the op code and separate it into the
2449  * mode, register, and r/m fields.
2450  */
2451 static void
2452 dtrace_get_modrm(dis86_t *x, uint_t *mode, uint_t *reg, uint_t *r_m)
2453 {
2454 	if (x->d86_got_modrm == 0) {
2455 		if (x->d86_rmindex == -1)
2456 			x->d86_rmindex = x->d86_len;
2457 		dtrace_get_SIB(x, mode, reg, r_m);
2458 		x->d86_got_modrm = 1;
2459 	}
2460 }
2461 
2462 /*
2463  * Adjust register selection based on any REX prefix bits present.
2464  */
2465 /*ARGSUSED*/
2466 static void
2467 dtrace_rex_adjust(uint_t rex_prefix, uint_t mode, uint_t *reg, uint_t *r_m)
2468 {
2469 	if (reg != NULL && r_m == NULL) {
2470 		if (rex_prefix & REX_B)
2471 			*reg += 8;
2472 	} else {
2473 		if (reg != NULL && (REX_R & rex_prefix) != 0)
2474 			*reg += 8;
2475 		if (r_m != NULL && (REX_B & rex_prefix) != 0)
2476 			*r_m += 8;
2477 	}
2478 }
2479 
2480 /*
2481  * Adjust register selection based on any VEX prefix bits present.
2482  * Notes: VEX.R, VEX.X and VEX.B use the inverted form compared with REX prefix
2483  */
2484 /*ARGSUSED*/
2485 static void
2486 dtrace_vex_adjust(uint_t vex_byte1, uint_t mode, uint_t *reg, uint_t *r_m)
2487 {
2488 	if (reg != NULL && r_m == NULL) {
2489 		if (!(vex_byte1 & VEX_B))
2490 			*reg += 8;
2491 	} else {
2492 		if (reg != NULL && ((VEX_R & vex_byte1) == 0))
2493 			*reg += 8;
2494 		if (r_m != NULL && ((VEX_B & vex_byte1) == 0))
2495 			*r_m += 8;
2496 	}
2497 }
2498 
2499 /*
2500  * Get an immediate operand of the given size, with sign extension.
2501  */
2502 static void
2503 dtrace_imm_opnd(dis86_t *x, int wbit, int size, int opindex)
2504 {
2505 	int i;
2506 	int byte;
2507 	int valsize;
2508 
2509 	if (x->d86_numopnds < opindex + 1)
2510 		x->d86_numopnds = opindex + 1;
2511 
2512 	switch (wbit) {
2513 	case BYTE_OPND:
2514 		valsize = 1;
2515 		break;
2516 	case LONG_OPND:
2517 		if (x->d86_opnd_size == SIZE16)
2518 			valsize = 2;
2519 		else if (x->d86_opnd_size == SIZE32)
2520 			valsize = 4;
2521 		else
2522 			valsize = 8;
2523 		break;
2524 	case MM_OPND:
2525 	case XMM_OPND:
2526 	case YMM_OPND:
2527 	case SEG_OPND:
2528 	case CONTROL_OPND:
2529 	case DEBUG_OPND:
2530 	case TEST_OPND:
2531 		valsize = size;
2532 		break;
2533 	case WORD_OPND:
2534 		valsize = 2;
2535 		break;
2536 	}
2537 	if (valsize < size)
2538 		valsize = size;
2539 
2540 	if (x->d86_error)
2541 		return;
2542 	x->d86_opnd[opindex].d86_value = 0;
2543 	for (i = 0; i < size; ++i) {
2544 		byte = x->d86_get_byte(x->d86_data);
2545 		if (byte < 0) {
2546 			x->d86_error = 1;
2547 			return;
2548 		}
2549 		x->d86_bytes[x->d86_len++] = byte;
2550 		x->d86_opnd[opindex].d86_value |= (uint64_t)byte << (i * 8);
2551 	}
2552 	/* Do sign extension */
2553 	if (x->d86_bytes[x->d86_len - 1] & 0x80) {
2554 		for (; i < sizeof (uint64_t); i++)
2555 			x->d86_opnd[opindex].d86_value |=
2556 			    (uint64_t)0xff << (i * 8);
2557 	}
2558 #ifdef DIS_TEXT
2559 	x->d86_opnd[opindex].d86_mode = MODE_SIGNED;
2560 	x->d86_opnd[opindex].d86_value_size = valsize;
2561 	x->d86_imm_bytes += size;
2562 #endif
2563 }
2564 
2565 /*
2566  * Get an ip relative operand of the given size, with sign extension.
2567  */
2568 static void
2569 dtrace_disp_opnd(dis86_t *x, int wbit, int size, int opindex)
2570 {
2571 	dtrace_imm_opnd(x, wbit, size, opindex);
2572 #ifdef DIS_TEXT
2573 	x->d86_opnd[opindex].d86_mode = MODE_IPREL;
2574 #endif
2575 }
2576 
2577 /*
2578  * Check to see if there is a segment override prefix pending.
2579  * If so, print it in the current 'operand' location and set
2580  * the override flag back to false.
2581  */
2582 /*ARGSUSED*/
2583 static void
2584 dtrace_check_override(dis86_t *x, int opindex)
2585 {
2586 #ifdef DIS_TEXT
2587 	if (x->d86_seg_prefix) {
2588 		(void) strlcat(x->d86_opnd[opindex].d86_prefix,
2589 		    x->d86_seg_prefix, PFIXLEN);
2590 	}
2591 #endif
2592 	x->d86_seg_prefix = NULL;
2593 }
2594 
2595 
2596 /*
2597  * Process a single instruction Register or Memory operand.
2598  *
2599  * mode = addressing mode from ModRM byte
2600  * r_m = r_m (or reg if mode == 3) field from ModRM byte
2601  * wbit = indicates which register (8bit, 16bit, ... MMX, etc.) set to use.
2602  * o = index of operand that we are processing (0, 1 or 2)
2603  *
2604  * the value of reg or r_m must have already been adjusted for any REX prefix.
2605  */
2606 /*ARGSUSED*/
2607 static void
2608 dtrace_get_operand(dis86_t *x, uint_t mode, uint_t r_m, int wbit, int opindex)
2609 {
2610 	int have_SIB = 0;	/* flag presence of scale-index-byte */
2611 	uint_t ss;		/* scale-factor from opcode */
2612 	uint_t index;		/* index register number */
2613 	uint_t base;		/* base register number */
2614 	int dispsize;   	/* size of displacement in bytes */
2615 #ifdef DIS_TEXT
2616 	char *opnd = x->d86_opnd[opindex].d86_opnd;
2617 #endif
2618 
2619 	if (x->d86_numopnds < opindex + 1)
2620 		x->d86_numopnds = opindex + 1;
2621 
2622 	if (x->d86_error)
2623 		return;
2624 
2625 	/*
2626 	 * first handle a simple register
2627 	 */
2628 	if (mode == REG_ONLY) {
2629 #ifdef DIS_TEXT
2630 		switch (wbit) {
2631 		case MM_OPND:
2632 			(void) strlcat(opnd, dis_MMREG[r_m], OPLEN);
2633 			break;
2634 		case XMM_OPND:
2635 			(void) strlcat(opnd, dis_XMMREG[r_m], OPLEN);
2636 			break;
2637 		case YMM_OPND:
2638 			(void) strlcat(opnd, dis_YMMREG[r_m], OPLEN);
2639 			break;
2640 		case SEG_OPND:
2641 			(void) strlcat(opnd, dis_SEGREG[r_m], OPLEN);
2642 			break;
2643 		case CONTROL_OPND:
2644 			(void) strlcat(opnd, dis_CONTROLREG[r_m], OPLEN);
2645 			break;
2646 		case DEBUG_OPND:
2647 			(void) strlcat(opnd, dis_DEBUGREG[r_m], OPLEN);
2648 			break;
2649 		case TEST_OPND:
2650 			(void) strlcat(opnd, dis_TESTREG[r_m], OPLEN);
2651 			break;
2652 		case BYTE_OPND:
2653 			if (x->d86_rex_prefix == 0)
2654 				(void) strlcat(opnd, dis_REG8[r_m], OPLEN);
2655 			else
2656 				(void) strlcat(opnd, dis_REG8_REX[r_m], OPLEN);
2657 			break;
2658 		case WORD_OPND:
2659 			(void) strlcat(opnd, dis_REG16[r_m], OPLEN);
2660 			break;
2661 		case LONG_OPND:
2662 			if (x->d86_opnd_size == SIZE16)
2663 				(void) strlcat(opnd, dis_REG16[r_m], OPLEN);
2664 			else if (x->d86_opnd_size == SIZE32)
2665 				(void) strlcat(opnd, dis_REG32[r_m], OPLEN);
2666 			else
2667 				(void) strlcat(opnd, dis_REG64[r_m], OPLEN);
2668 			break;
2669 		}
2670 #endif /* DIS_TEXT */
2671 		return;
2672 	}
2673 
2674 	/*
2675 	 * if symbolic representation, skip override prefix, if any
2676 	 */
2677 	dtrace_check_override(x, opindex);
2678 
2679 	/*
2680 	 * Handle 16 bit memory references first, since they decode
2681 	 * the mode values more simply.
2682 	 * mode 1 is r_m + 8 bit displacement
2683 	 * mode 2 is r_m + 16 bit displacement
2684 	 * mode 0 is just r_m, unless r_m is 6 which is 16 bit disp
2685 	 */
2686 	if (x->d86_addr_size == SIZE16) {
2687 		if ((mode == 0 && r_m == 6) || mode == 2)
2688 			dtrace_imm_opnd(x, WORD_OPND, 2, opindex);
2689 		else if (mode == 1)
2690 			dtrace_imm_opnd(x, BYTE_OPND, 1, opindex);
2691 #ifdef DIS_TEXT
2692 		if (mode == 0 && r_m == 6)
2693 			x->d86_opnd[opindex].d86_mode = MODE_SIGNED;
2694 		else if (mode == 0)
2695 			x->d86_opnd[opindex].d86_mode = MODE_NONE;
2696 		else
2697 			x->d86_opnd[opindex].d86_mode = MODE_OFFSET;
2698 		(void) strlcat(opnd, dis_addr16[mode][r_m], OPLEN);
2699 #endif
2700 		return;
2701 	}
2702 
2703 	/*
2704 	 * 32 and 64 bit addressing modes are more complex since they
2705 	 * can involve an SIB (scaled index and base) byte to decode.
2706 	 */
2707 	if (r_m == ESP_REGNO || r_m == ESP_REGNO + 8) {
2708 		have_SIB = 1;
2709 		dtrace_get_SIB(x, &ss, &index, &base);
2710 		if (x->d86_error)
2711 			return;
2712 		if (base != 5 || mode != 0)
2713 			if (x->d86_rex_prefix & REX_B)
2714 				base += 8;
2715 		if (x->d86_rex_prefix & REX_X)
2716 			index += 8;
2717 	} else {
2718 		base = r_m;
2719 	}
2720 
2721 	/*
2722 	 * Compute the displacement size and get its bytes
2723 	 */
2724 	dispsize = 0;
2725 
2726 	if (mode == 1)
2727 		dispsize = 1;
2728 	else if (mode == 2)
2729 		dispsize = 4;
2730 	else if ((r_m & 7) == EBP_REGNO ||
2731 	    (have_SIB && (base & 7) == EBP_REGNO))
2732 		dispsize = 4;
2733 
2734 	if (dispsize > 0) {
2735 		dtrace_imm_opnd(x, dispsize == 4 ? LONG_OPND : BYTE_OPND,
2736 		    dispsize, opindex);
2737 		if (x->d86_error)
2738 			return;
2739 	}
2740 
2741 #ifdef DIS_TEXT
2742 	if (dispsize > 0)
2743 		x->d86_opnd[opindex].d86_mode = MODE_OFFSET;
2744 
2745 	if (have_SIB == 0) {
2746 		if (x->d86_mode == SIZE32) {
2747 			if (mode == 0)
2748 				(void) strlcat(opnd, dis_addr32_mode0[r_m],
2749 				    OPLEN);
2750 			else
2751 				(void) strlcat(opnd, dis_addr32_mode12[r_m],
2752 				    OPLEN);
2753 		} else {
2754 			if (mode == 0) {
2755 				(void) strlcat(opnd, dis_addr64_mode0[r_m],
2756 				    OPLEN);
2757 				if (r_m == 5) {
2758 					x->d86_opnd[opindex].d86_mode =
2759 					    MODE_RIPREL;
2760 				}
2761 			} else {
2762 				(void) strlcat(opnd, dis_addr64_mode12[r_m],
2763 				    OPLEN);
2764 			}
2765 		}
2766 	} else {
2767 		uint_t need_paren = 0;
2768 		char **regs;
2769 		char **bregs;
2770 		const char *const *sf;
2771 		if (x->d86_mode == SIZE32) /* NOTE this is not addr_size! */
2772 			regs = (char **)dis_REG32;
2773 		else
2774 			regs = (char **)dis_REG64;
2775 
2776 		if (x->d86_vsib != 0) {
2777 			if (wbit == YMM_OPND) /* NOTE this is not addr_size! */
2778 				bregs = (char **)dis_YMMREG;
2779 			else
2780 				bregs = (char **)dis_XMMREG;
2781 			sf = dis_vscale_factor;
2782 		} else {
2783 			bregs = regs;
2784 			sf = dis_scale_factor;
2785 		}
2786 
2787 		/*
2788 		 * print the base (if any)
2789 		 */
2790 		if (base == EBP_REGNO && mode == 0) {
2791 			if (index != ESP_REGNO || x->d86_vsib != 0) {
2792 				(void) strlcat(opnd, "(", OPLEN);
2793 				need_paren = 1;
2794 			}
2795 		} else {
2796 			(void) strlcat(opnd, "(", OPLEN);
2797 			(void) strlcat(opnd, regs[base], OPLEN);
2798 			need_paren = 1;
2799 		}
2800 
2801 		/*
2802 		 * print the index (if any)
2803 		 */
2804 		if (index != ESP_REGNO || x->d86_vsib) {
2805 			(void) strlcat(opnd, ",", OPLEN);
2806 			(void) strlcat(opnd, bregs[index], OPLEN);
2807 			(void) strlcat(opnd, sf[ss], OPLEN);
2808 		} else
2809 			if (need_paren)
2810 				(void) strlcat(opnd, ")", OPLEN);
2811 	}
2812 #endif
2813 }
2814 
2815 /*
2816  * Operand sequence for standard instruction involving one register
2817  * and one register/memory operand.
2818  * wbit indicates a byte(0) or opnd_size(1) operation
2819  * vbit indicates direction (0 for "opcode r,r_m") or (1 for "opcode r_m, r")
2820  */
2821 #define	STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, vbit)  {	\
2822 		dtrace_get_modrm(x, &mode, &reg, &r_m);			\
2823 		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);	\
2824 		dtrace_get_operand(x, mode, r_m, wbit, vbit);		\
2825 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 1 - vbit);	\
2826 }
2827 
2828 /*
2829  * Similar to above, but allows for the two operands to be of different
2830  * classes (ie. wbit).
2831  *	wbit is for the r_m operand
2832  *	w2 is for the reg operand
2833  */
2834 #define	MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, w2, vbit)	{	\
2835 		dtrace_get_modrm(x, &mode, &reg, &r_m);			\
2836 		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);	\
2837 		dtrace_get_operand(x, mode, r_m, wbit, vbit);		\
2838 		dtrace_get_operand(x, REG_ONLY, reg, w2, 1 - vbit);	\
2839 }
2840 
2841 /*
2842  * Similar, but for 2 operands plus an immediate.
2843  * vbit indicates direction
2844  * 	0 for "opcode imm, r, r_m" or
2845  *	1 for "opcode imm, r_m, r"
2846  */
2847 #define	THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize, vbit) { \
2848 		dtrace_get_modrm(x, &mode, &reg, &r_m);			\
2849 		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);	\
2850 		dtrace_get_operand(x, mode, r_m, wbit, 2-vbit);		\
2851 		dtrace_get_operand(x, REG_ONLY, reg, w2, 1+vbit);	\
2852 		dtrace_imm_opnd(x, wbit, immsize, 0);			\
2853 }
2854 
2855 /*
2856  * Similar, but for 2 operands plus two immediates.
2857  */
2858 #define	FOUROPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize) { \
2859 		dtrace_get_modrm(x, &mode, &reg, &r_m);			\
2860 		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);	\
2861 		dtrace_get_operand(x, mode, r_m, wbit, 2);		\
2862 		dtrace_get_operand(x, REG_ONLY, reg, w2, 3);		\
2863 		dtrace_imm_opnd(x, wbit, immsize, 1);			\
2864 		dtrace_imm_opnd(x, wbit, immsize, 0);			\
2865 }
2866 
2867 /*
2868  * 1 operands plus two immediates.
2869  */
2870 #define	ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, wbit, immsize) { \
2871 		dtrace_get_modrm(x, &mode, &reg, &r_m);			\
2872 		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);	\
2873 		dtrace_get_operand(x, mode, r_m, wbit, 2);		\
2874 		dtrace_imm_opnd(x, wbit, immsize, 1);			\
2875 		dtrace_imm_opnd(x, wbit, immsize, 0);			\
2876 }
2877 
2878 /*
2879  * Dissassemble a single x86 or amd64 instruction.
2880  *
2881  * Mode determines the default operating mode (SIZE16, SIZE32 or SIZE64)
2882  * for interpreting instructions.
2883  *
2884  * returns non-zero for bad opcode
2885  */
2886 int
2887 dtrace_disx86(dis86_t *x, uint_t cpu_mode)
2888 {
2889 	instable_t *dp;		/* decode table being used */
2890 #ifdef DIS_TEXT
2891 	uint_t i;
2892 #endif
2893 #ifdef DIS_MEM
2894 	uint_t nomem = 0;
2895 #define	NOMEM	(nomem = 1)
2896 #else
2897 #define	NOMEM	/* nothing */
2898 #endif
2899 	uint_t opnd_size;	/* SIZE16, SIZE32 or SIZE64 */
2900 	uint_t addr_size;	/* SIZE16, SIZE32 or SIZE64 */
2901 	uint_t wbit;		/* opcode wbit, 0 is 8 bit, !0 for opnd_size */
2902 	uint_t w2;		/* wbit value for second operand */
2903 	uint_t vbit;
2904 	uint_t mode = 0;	/* mode value from ModRM byte */
2905 	uint_t reg;		/* reg value from ModRM byte */
2906 	uint_t r_m;		/* r_m value from ModRM byte */
2907 
2908 	uint_t opcode1;		/* high nibble of 1st byte */
2909 	uint_t opcode2;		/* low nibble of 1st byte */
2910 	uint_t opcode3;		/* extra opcode bits usually from ModRM byte */
2911 	uint_t opcode4;		/* high nibble of 2nd byte */
2912 	uint_t opcode5;		/* low nibble of 2nd byte */
2913 	uint_t opcode6;		/* high nibble of 3rd byte */
2914 	uint_t opcode7;		/* low nibble of 3rd byte */
2915 	uint_t opcode_bytes = 1;
2916 
2917 	/*
2918 	 * legacy prefixes come in 5 flavors, you should have only one of each
2919 	 */
2920 	uint_t	opnd_size_prefix = 0;
2921 	uint_t	addr_size_prefix = 0;
2922 	uint_t	segment_prefix = 0;
2923 	uint_t	lock_prefix = 0;
2924 	uint_t	rep_prefix = 0;
2925 	uint_t	rex_prefix = 0;	/* amd64 register extension prefix */
2926 
2927 	/*
2928 	 * Intel VEX instruction encoding prefix and fields
2929 	 */
2930 
2931 	/* 0xC4 means 3 bytes prefix, 0xC5 means 2 bytes prefix */
2932 	uint_t vex_prefix = 0;
2933 
2934 	/*
2935 	 * VEX prefix byte 1, includes vex.r, vex.x and vex.b
2936 	 * (for 3 bytes prefix)
2937 	 */
2938 	uint_t vex_byte1 = 0;
2939 
2940 	/*
2941 	 * For 32-bit mode, it should prefetch the next byte to
2942 	 * distinguish between AVX and les/lds
2943 	 */
2944 	uint_t vex_prefetch = 0;
2945 
2946 	uint_t vex_m = 0;
2947 	uint_t vex_v = 0;
2948 	uint_t vex_p = 0;
2949 	uint_t vex_R = 1;
2950 	uint_t vex_X = 1;
2951 	uint_t vex_B = 1;
2952 	uint_t vex_W = 0;
2953 	uint_t vex_L;
2954 	dis_gather_regs_t *vreg;
2955 
2956 #ifdef	DIS_TEXT
2957 	/* Instruction name for BLS* family of instructions */
2958 	char *blsinstr;
2959 #endif
2960 
2961 	size_t	off;
2962 
2963 	instable_t dp_mmx;
2964 
2965 	x->d86_len = 0;
2966 	x->d86_rmindex = -1;
2967 	x->d86_error = 0;
2968 #ifdef DIS_TEXT
2969 	x->d86_numopnds = 0;
2970 	x->d86_seg_prefix = NULL;
2971 	x->d86_mnem[0] = 0;
2972 	for (i = 0; i < 4; ++i) {
2973 		x->d86_opnd[i].d86_opnd[0] = 0;
2974 		x->d86_opnd[i].d86_prefix[0] = 0;
2975 		x->d86_opnd[i].d86_value_size = 0;
2976 		x->d86_opnd[i].d86_value = 0;
2977 		x->d86_opnd[i].d86_mode = MODE_NONE;
2978 	}
2979 #endif
2980 	x->d86_rex_prefix = 0;
2981 	x->d86_got_modrm = 0;
2982 	x->d86_memsize = 0;
2983 	x->d86_vsib = 0;
2984 
2985 	if (cpu_mode == SIZE16) {
2986 		opnd_size = SIZE16;
2987 		addr_size = SIZE16;
2988 	} else if (cpu_mode == SIZE32) {
2989 		opnd_size = SIZE32;
2990 		addr_size = SIZE32;
2991 	} else {
2992 		opnd_size = SIZE32;
2993 		addr_size = SIZE64;
2994 	}
2995 
2996 	/*
2997 	 * Get one opcode byte and check for zero padding that follows
2998 	 * jump tables.
2999 	 */
3000 	if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3001 		goto error;
3002 
3003 	if (opcode1 == 0 && opcode2 == 0 &&
3004 	    x->d86_check_func != NULL && x->d86_check_func(x->d86_data)) {
3005 #ifdef DIS_TEXT
3006 		(void) strncpy(x->d86_mnem, ".byte\t0", OPLEN);
3007 #endif
3008 		goto done;
3009 	}
3010 
3011 	/*
3012 	 * Gather up legacy x86 prefix bytes.
3013 	 */
3014 	for (;;) {
3015 		uint_t *which_prefix = NULL;
3016 
3017 		dp = (instable_t *)&dis_distable[opcode1][opcode2];
3018 
3019 		switch (dp->it_adrmode) {
3020 		case PREFIX:
3021 			which_prefix = &rep_prefix;
3022 			break;
3023 		case LOCK:
3024 			which_prefix = &lock_prefix;
3025 			break;
3026 		case OVERRIDE:
3027 			which_prefix = &segment_prefix;
3028 #ifdef DIS_TEXT
3029 			x->d86_seg_prefix = (char *)dp->it_name;
3030 #endif
3031 			if (dp->it_invalid64 && cpu_mode == SIZE64)
3032 				goto error;
3033 			break;
3034 		case AM:
3035 			which_prefix = &addr_size_prefix;
3036 			break;
3037 		case DM:
3038 			which_prefix = &opnd_size_prefix;
3039 			break;
3040 		}
3041 		if (which_prefix == NULL)
3042 			break;
3043 		*which_prefix = (opcode1 << 4) | opcode2;
3044 		if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3045 			goto error;
3046 	}
3047 
3048 	/*
3049 	 * Handle amd64 mode PREFIX values.
3050 	 * Some of the segment prefixes are no-ops. (only FS/GS actually work)
3051 	 * We might have a REX prefix (opcodes 0x40-0x4f)
3052 	 */
3053 	if (cpu_mode == SIZE64) {
3054 		if (segment_prefix != 0x64 && segment_prefix != 0x65)
3055 			segment_prefix = 0;
3056 
3057 		if (opcode1 == 0x4) {
3058 			rex_prefix = (opcode1 << 4) | opcode2;
3059 			if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3060 				goto error;
3061 			dp = (instable_t *)&dis_distable[opcode1][opcode2];
3062 		} else if (opcode1 == 0xC &&
3063 		    (opcode2 == 0x4 || opcode2 == 0x5)) {
3064 			/* AVX instructions */
3065 			vex_prefix = (opcode1 << 4) | opcode2;
3066 			x->d86_rex_prefix = 0x40;
3067 		}
3068 	} else if (opcode1 == 0xC && (opcode2 == 0x4 || opcode2 == 0x5)) {
3069 		/* LDS, LES or AVX */
3070 		dtrace_get_modrm(x, &mode, &reg, &r_m);
3071 		vex_prefetch = 1;
3072 
3073 		if (mode == REG_ONLY) {
3074 			/* AVX */
3075 			vex_prefix = (opcode1 << 4) | opcode2;
3076 			x->d86_rex_prefix = 0x40;
3077 			opcode3 = (((mode << 3) | reg)>>1) & 0x0F;
3078 			opcode4 = ((reg << 3) | r_m) & 0x0F;
3079 		}
3080 	}
3081 
3082 	if (vex_prefix == VEX_2bytes) {
3083 		if (!vex_prefetch) {
3084 			if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0)
3085 				goto error;
3086 		}
3087 		vex_R = ((opcode3 & VEX_R) & 0x0F) >> 3;
3088 		vex_L = ((opcode4 & VEX_L) & 0x0F) >> 2;
3089 		vex_v = (((opcode3 << 4) | opcode4) & VEX_v) >> 3;
3090 		vex_p = opcode4 & VEX_p;
3091 		/*
3092 		 * The vex.x and vex.b bits are not defined in two bytes
3093 		 * mode vex prefix, their default values are 1
3094 		 */
3095 		vex_byte1 = (opcode3 & VEX_R) | VEX_X | VEX_B;
3096 
3097 		if (vex_R == 0)
3098 			x->d86_rex_prefix |= REX_R;
3099 
3100 		if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3101 			goto error;
3102 
3103 		switch (vex_p) {
3104 			case VEX_p_66:
3105 				dp = (instable_t *)
3106 				    &dis_opAVX660F[(opcode1 << 4) | opcode2];
3107 				break;
3108 			case VEX_p_F3:
3109 				dp = (instable_t *)
3110 				    &dis_opAVXF30F[(opcode1 << 4) | opcode2];
3111 				break;
3112 			case VEX_p_F2:
3113 				dp = (instable_t *)
3114 				    &dis_opAVXF20F [(opcode1 << 4) | opcode2];
3115 				break;
3116 			default:
3117 				dp = (instable_t *)
3118 				    &dis_opAVX0F[opcode1][opcode2];
3119 
3120 		}
3121 
3122 	} else if (vex_prefix == VEX_3bytes) {
3123 		if (!vex_prefetch) {
3124 			if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0)
3125 				goto error;
3126 		}
3127 		vex_R = (opcode3 & VEX_R) >> 3;
3128 		vex_X = (opcode3 & VEX_X) >> 2;
3129 		vex_B = (opcode3 & VEX_B) >> 1;
3130 		vex_m = (((opcode3 << 4) | opcode4) & VEX_m);
3131 		vex_byte1 = opcode3 & (VEX_R | VEX_X | VEX_B);
3132 
3133 		if (vex_R == 0)
3134 			x->d86_rex_prefix |= REX_R;
3135 		if (vex_X == 0)
3136 			x->d86_rex_prefix |= REX_X;
3137 		if (vex_B == 0)
3138 			x->d86_rex_prefix |= REX_B;
3139 
3140 		if (dtrace_get_opcode(x, &opcode5, &opcode6) != 0)
3141 			goto error;
3142 		vex_W = (opcode5 & VEX_W) >> 3;
3143 		vex_L = (opcode6 & VEX_L) >> 2;
3144 		vex_v = (((opcode5 << 4) | opcode6) & VEX_v) >> 3;
3145 		vex_p = opcode6 & VEX_p;
3146 
3147 		if (vex_W)
3148 			x->d86_rex_prefix |= REX_W;
3149 
3150 		/* Only these three vex_m values valid; others are reserved */
3151 		if ((vex_m != VEX_m_0F) && (vex_m != VEX_m_0F38) &&
3152 		    (vex_m != VEX_m_0F3A))
3153 			goto error;
3154 
3155 		if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3156 			goto error;
3157 
3158 		switch (vex_p) {
3159 			case VEX_p_66:
3160 				if (vex_m == VEX_m_0F) {
3161 					dp = (instable_t *)
3162 					    &dis_opAVX660F
3163 					    [(opcode1 << 4) | opcode2];
3164 				} else if (vex_m == VEX_m_0F38) {
3165 					dp = (instable_t *)
3166 					    &dis_opAVX660F38
3167 					    [(opcode1 << 4) | opcode2];
3168 				} else if (vex_m == VEX_m_0F3A) {
3169 					dp = (instable_t *)
3170 					    &dis_opAVX660F3A
3171 					    [(opcode1 << 4) | opcode2];
3172 				} else {
3173 					goto error;
3174 				}
3175 				break;
3176 			case VEX_p_F3:
3177 				if (vex_m == VEX_m_0F) {
3178 					dp = (instable_t *)
3179 					    &dis_opAVXF30F
3180 					    [(opcode1 << 4) | opcode2];
3181 				} else if (vex_m == VEX_m_0F38) {
3182 					dp = (instable_t *)
3183 					    &dis_opAVXF30F38
3184 					    [(opcode1 << 4) | opcode2];
3185 				} else {
3186 					goto error;
3187 				}
3188 				break;
3189 			case VEX_p_F2:
3190 				if (vex_m == VEX_m_0F) {
3191 					dp = (instable_t *)
3192 					    &dis_opAVXF20F
3193 					    [(opcode1 << 4) | opcode2];
3194 				} else if (vex_m == VEX_m_0F3A) {
3195 					dp = (instable_t *)
3196 					    &dis_opAVXF20F3A
3197 					    [(opcode1 << 4) | opcode2];
3198 				} else if (vex_m == VEX_m_0F38) {
3199 					dp = (instable_t *)
3200 					    &dis_opAVXF20F38
3201 					    [(opcode1 << 4) | opcode2];
3202 				} else {
3203 					goto error;
3204 				}
3205 				break;
3206 			default:
3207 				dp = (instable_t *)
3208 				    &dis_opAVX0F[opcode1][opcode2];
3209 
3210 		}
3211 	}
3212 	if (vex_prefix) {
3213 		if (dp->it_vexwoxmm) {
3214 			wbit = LONG_OPND;
3215 		} else {
3216 			if (vex_L)
3217 				wbit = YMM_OPND;
3218 			else
3219 				wbit = XMM_OPND;
3220 		}
3221 	}
3222 
3223 	/*
3224 	 * Deal with selection of operand and address size now.
3225 	 * Note that the REX.W bit being set causes opnd_size_prefix to be
3226 	 * ignored.
3227 	 */
3228 	if (cpu_mode == SIZE64) {
3229 		if ((rex_prefix & REX_W) || vex_W)
3230 			opnd_size = SIZE64;
3231 		else if (opnd_size_prefix)
3232 			opnd_size = SIZE16;
3233 
3234 		if (addr_size_prefix)
3235 			addr_size = SIZE32;
3236 	} else if (cpu_mode == SIZE32) {
3237 		if (opnd_size_prefix)
3238 			opnd_size = SIZE16;
3239 		if (addr_size_prefix)
3240 			addr_size = SIZE16;
3241 	} else {
3242 		if (opnd_size_prefix)
3243 			opnd_size = SIZE32;
3244 		if (addr_size_prefix)
3245 			addr_size = SIZE32;
3246 	}
3247 	/*
3248 	 * The pause instruction - a repz'd nop.  This doesn't fit
3249 	 * with any of the other prefix goop added for SSE, so we'll
3250 	 * special-case it here.
3251 	 */
3252 	if (rep_prefix == 0xf3 && opcode1 == 0x9 && opcode2 == 0x0) {
3253 		rep_prefix = 0;
3254 		dp = (instable_t *)&dis_opPause;
3255 	}
3256 
3257 	/*
3258 	 * Some 386 instructions have 2 bytes of opcode before the mod_r/m
3259 	 * byte so we may need to perform a table indirection.
3260 	 */
3261 	if (dp->it_indirect == (instable_t *)dis_op0F) {
3262 		if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0)
3263 			goto error;
3264 		opcode_bytes = 2;
3265 		if (opcode4 == 0x7 && opcode5 >= 0x1 && opcode5 <= 0x3) {
3266 			uint_t	subcode;
3267 
3268 			if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
3269 				goto error;
3270 			opcode_bytes = 3;
3271 			subcode = ((opcode6 & 0x3) << 1) |
3272 			    ((opcode7 & 0x8) >> 3);
3273 			dp = (instable_t *)&dis_op0F7123[opcode5][subcode];
3274 		} else if ((opcode4 == 0xc) && (opcode5 >= 0x8)) {
3275 			dp = (instable_t *)&dis_op0FC8[0];
3276 		} else if ((opcode4 == 0x3) && (opcode5 == 0xA)) {
3277 			opcode_bytes = 3;
3278 			if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
3279 				goto error;
3280 			if (opnd_size == SIZE16)
3281 				opnd_size = SIZE32;
3282 
3283 			dp = (instable_t *)&dis_op0F3A[(opcode6<<4)|opcode7];
3284 #ifdef DIS_TEXT
3285 			if (strcmp(dp->it_name, "INVALID") == 0)
3286 				goto error;
3287 #endif
3288 			switch (dp->it_adrmode) {
3289 				case XMMP:
3290 					break;
3291 				case XMMP_66r:
3292 				case XMMPRM_66r:
3293 				case XMM3PM_66r:
3294 					if (opnd_size_prefix == 0) {
3295 						goto error;
3296 					}
3297 					break;
3298 				case XMMP_66o:
3299 					if (opnd_size_prefix == 0) {
3300 						/* SSSE3 MMX instructions */
3301 						dp_mmx = *dp;
3302 						dp = &dp_mmx;
3303 						dp->it_adrmode = MMOPM_66o;
3304 #ifdef	DIS_MEM
3305 						dp->it_size = 8;
3306 #endif
3307 					}
3308 					break;
3309 				default:
3310 					goto error;
3311 			}
3312 		} else if ((opcode4 == 0x3) && (opcode5 == 0x8)) {
3313 			opcode_bytes = 3;
3314 			if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
3315 				goto error;
3316 			dp = (instable_t *)&dis_op0F38[(opcode6<<4)|opcode7];
3317 
3318 			/*
3319 			 * Both crc32 and movbe have the same 3rd opcode
3320 			 * byte of either 0xF0 or 0xF1, so we use another
3321 			 * indirection to distinguish between the two.
3322 			 */
3323 			if (dp->it_indirect == (instable_t *)dis_op0F38F0 ||
3324 			    dp->it_indirect == (instable_t *)dis_op0F38F1) {
3325 
3326 				dp = dp->it_indirect;
3327 				if (rep_prefix != 0xF2) {
3328 					/* It is movbe */
3329 					dp++;
3330 				}
3331 			}
3332 
3333 			/*
3334 			 * The adx family of instructions (adcx and adox)
3335 			 * continue the classic Intel tradition of abusing
3336 			 * arbitrary prefixes without actually meaning the
3337 			 * prefix bit. Therefore, if we find either the
3338 			 * opnd_size_prefix or rep_prefix we end up zeroing it
3339 			 * out after making our determination so as to ensure
3340 			 * that we don't get confused and accidentally print
3341 			 * repz prefixes and the like on these instructions.
3342 			 *
3343 			 * In addition, these instructions are actually much
3344 			 * closer to AVX instructions in semantics. Importantly,
3345 			 * they always default to having 32-bit operands.
3346 			 * However, if the CPU is in 64-bit mode, then and only
3347 			 * then, does it use REX.w promotes things to 64-bits
3348 			 * and REX.r allows 64-bit mode to use register r8-r15.
3349 			 */
3350 			if (dp->it_indirect == (instable_t *)dis_op0F38F6) {
3351 				dp = dp->it_indirect;
3352 				if (opnd_size_prefix == 0 &&
3353 				    rep_prefix == 0xf3) {
3354 					/* It is adox */
3355 					dp++;
3356 				} else if (opnd_size_prefix != 0x66 &&
3357 				    rep_prefix != 0) {
3358 					/* It isn't adcx */
3359 					goto error;
3360 				}
3361 				opnd_size_prefix = 0;
3362 				rep_prefix = 0;
3363 				opnd_size = SIZE32;
3364 				if (rex_prefix & REX_W)
3365 					opnd_size = SIZE64;
3366 			}
3367 
3368 #ifdef DIS_TEXT
3369 			if (strcmp(dp->it_name, "INVALID") == 0)
3370 				goto error;
3371 #endif
3372 			switch (dp->it_adrmode) {
3373 				case ADX:
3374 				case XMM:
3375 					break;
3376 				case RM_66r:
3377 				case XMM_66r:
3378 				case XMMM_66r:
3379 					if (opnd_size_prefix == 0) {
3380 						goto error;
3381 					}
3382 					break;
3383 				case XMM_66o:
3384 					if (opnd_size_prefix == 0) {
3385 						/* SSSE3 MMX instructions */
3386 						dp_mmx = *dp;
3387 						dp = &dp_mmx;
3388 						dp->it_adrmode = MM;
3389 #ifdef	DIS_MEM
3390 						dp->it_size = 8;
3391 #endif
3392 					}
3393 					break;
3394 				case CRC32:
3395 					if (rep_prefix != 0xF2) {
3396 						goto error;
3397 					}
3398 					rep_prefix = 0;
3399 					break;
3400 				case MOVBE:
3401 					if (rep_prefix != 0x0) {
3402 						goto error;
3403 					}
3404 					break;
3405 				default:
3406 					goto error;
3407 			}
3408 		} else {
3409 			dp = (instable_t *)&dis_op0F[opcode4][opcode5];
3410 		}
3411 	}
3412 
3413 	/*
3414 	 * If still not at a TERM decode entry, then a ModRM byte
3415 	 * exists and its fields further decode the instruction.
3416 	 */
3417 	x->d86_got_modrm = 0;
3418 	if (dp->it_indirect != TERM) {
3419 		dtrace_get_modrm(x, &mode, &opcode3, &r_m);
3420 		if (x->d86_error)
3421 			goto error;
3422 		reg = opcode3;
3423 
3424 		/*
3425 		 * decode 287 instructions (D8-DF) from opcodeN
3426 		 */
3427 		if (opcode1 == 0xD && opcode2 >= 0x8) {
3428 			if (opcode2 == 0xB && mode == 0x3 && opcode3 == 4)
3429 				dp = (instable_t *)&dis_opFP5[r_m];
3430 			else if (opcode2 == 0xA && mode == 0x3 && opcode3 < 4)
3431 				dp = (instable_t *)&dis_opFP7[opcode3];
3432 			else if (opcode2 == 0xB && mode == 0x3)
3433 				dp = (instable_t *)&dis_opFP6[opcode3];
3434 			else if (opcode2 == 0x9 && mode == 0x3 && opcode3 >= 4)
3435 				dp = (instable_t *)&dis_opFP4[opcode3 - 4][r_m];
3436 			else if (mode == 0x3)
3437 				dp = (instable_t *)
3438 				    &dis_opFP3[opcode2 - 8][opcode3];
3439 			else
3440 				dp = (instable_t *)
3441 				    &dis_opFP1n2[opcode2 - 8][opcode3];
3442 		} else {
3443 			dp = (instable_t *)dp->it_indirect + opcode3;
3444 		}
3445 	}
3446 
3447 	/*
3448 	 * In amd64 bit mode, ARPL opcode is changed to MOVSXD
3449 	 * (sign extend 32bit to 64 bit)
3450 	 */
3451 	if ((vex_prefix == 0) && cpu_mode == SIZE64 &&
3452 	    opcode1 == 0x6 && opcode2 == 0x3)
3453 		dp = (instable_t *)&dis_opMOVSLD;
3454 
3455 	/*
3456 	 * at this point we should have a correct (or invalid) opcode
3457 	 */
3458 	if (cpu_mode == SIZE64 && dp->it_invalid64 ||
3459 	    cpu_mode != SIZE64 && dp->it_invalid32)
3460 		goto error;
3461 	if (dp->it_indirect != TERM)
3462 		goto error;
3463 
3464 	/*
3465 	 * Deal with MMX/SSE opcodes which are changed by prefixes. Note, we do
3466 	 * need to include UNKNOWN below, as we may have instructions that
3467 	 * actually have a prefix, but don't exist in any other form.
3468 	 */
3469 	switch (dp->it_adrmode) {
3470 	case UNKNOWN:
3471 	case MMO:
3472 	case MMOIMPL:
3473 	case MMO3P:
3474 	case MMOM3:
3475 	case MMOMS:
3476 	case MMOPM:
3477 	case MMOPRM:
3478 	case MMOS:
3479 	case XMMO:
3480 	case XMMOM:
3481 	case XMMOMS:
3482 	case XMMOPM:
3483 	case XMMOS:
3484 	case XMMOMX:
3485 	case XMMOX3:
3486 	case XMMOXMM:
3487 		/*
3488 		 * This is horrible.  Some SIMD instructions take the
3489 		 * form 0x0F 0x?? ..., which is easily decoded using the
3490 		 * existing tables.  Other SIMD instructions use various
3491 		 * prefix bytes to overload existing instructions.  For
3492 		 * Example, addps is F0, 58, whereas addss is F3 (repz),
3493 		 * F0, 58.  Presumably someone got a raise for this.
3494 		 *
3495 		 * If we see one of the instructions which can be
3496 		 * modified in this way (if we've got one of the SIMDO*
3497 		 * address modes), we'll check to see if the last prefix
3498 		 * was a repz.  If it was, we strip the prefix from the
3499 		 * mnemonic, and we indirect using the dis_opSIMDrepz
3500 		 * table.
3501 		 */
3502 
3503 		/*
3504 		 * Calculate our offset in dis_op0F
3505 		 */
3506 		if ((uintptr_t)dp - (uintptr_t)dis_op0F > sizeof (dis_op0F))
3507 			goto error;
3508 
3509 		off = ((uintptr_t)dp - (uintptr_t)dis_op0F) /
3510 		    sizeof (instable_t);
3511 
3512 		/*
3513 		 * Rewrite if this instruction used one of the magic prefixes.
3514 		 */
3515 		if (rep_prefix) {
3516 			if (rep_prefix == 0xf2)
3517 				dp = (instable_t *)&dis_opSIMDrepnz[off];
3518 			else
3519 				dp = (instable_t *)&dis_opSIMDrepz[off];
3520 			rep_prefix = 0;
3521 		} else if (opnd_size_prefix) {
3522 			dp = (instable_t *)&dis_opSIMDdata16[off];
3523 			opnd_size_prefix = 0;
3524 			if (opnd_size == SIZE16)
3525 				opnd_size = SIZE32;
3526 		}
3527 		break;
3528 
3529 	case MG9:
3530 		/*
3531 		 * More horribleness: the group 9 (0xF0 0xC7) instructions are
3532 		 * allowed an optional prefix of 0x66 or 0xF3.  This is similar
3533 		 * to the SIMD business described above, but with a different
3534 		 * addressing mode (and an indirect table), so we deal with it
3535 		 * separately (if similarly).
3536 		 *
3537 		 * Intel further complicated this with the release of Ivy Bridge
3538 		 * where they overloaded these instructions based on the ModR/M
3539 		 * bytes. The VMX instructions have a mode of 0 since they are
3540 		 * memory instructions but rdrand instructions have a mode of
3541 		 * 0b11 (REG_ONLY) because they only operate on registers. While
3542 		 * there are different prefix formats, for now it is sufficient
3543 		 * to use a single different table.
3544 		 */
3545 
3546 		/*
3547 		 * Calculate our offset in dis_op0FC7 (the group 9 table)
3548 		 */
3549 		if ((uintptr_t)dp - (uintptr_t)dis_op0FC7 > sizeof (dis_op0FC7))
3550 			goto error;
3551 
3552 		off = ((uintptr_t)dp - (uintptr_t)dis_op0FC7) /
3553 		    sizeof (instable_t);
3554 
3555 		/*
3556 		 * If we have a mode of 0b11 then we have to rewrite this.
3557 		 */
3558 		dtrace_get_modrm(x, &mode, &reg, &r_m);
3559 		if (mode == REG_ONLY) {
3560 			dp = (instable_t *)&dis_op0FC7m3[off];
3561 			break;
3562 		}
3563 
3564 		/*
3565 		 * Rewrite if this instruction used one of the magic prefixes.
3566 		 */
3567 		if (rep_prefix) {
3568 			if (rep_prefix == 0xf3)
3569 				dp = (instable_t *)&dis_opF30FC7[off];
3570 			else
3571 				goto error;
3572 			rep_prefix = 0;
3573 		} else if (opnd_size_prefix) {
3574 			dp = (instable_t *)&dis_op660FC7[off];
3575 			opnd_size_prefix = 0;
3576 			if (opnd_size == SIZE16)
3577 				opnd_size = SIZE32;
3578 		}
3579 		break;
3580 
3581 
3582 	case MMOSH:
3583 		/*
3584 		 * As with the "normal" SIMD instructions, the MMX
3585 		 * shuffle instructions are overloaded.  These
3586 		 * instructions, however, are special in that they use
3587 		 * an extra byte, and thus an extra table.  As of this
3588 		 * writing, they only use the opnd_size prefix.
3589 		 */
3590 
3591 		/*
3592 		 * Calculate our offset in dis_op0F7123
3593 		 */
3594 		if ((uintptr_t)dp - (uintptr_t)dis_op0F7123 >
3595 		    sizeof (dis_op0F7123))
3596 			goto error;
3597 
3598 		if (opnd_size_prefix) {
3599 			off = ((uintptr_t)dp - (uintptr_t)dis_op0F7123) /
3600 			    sizeof (instable_t);
3601 			dp = (instable_t *)&dis_opSIMD7123[off];
3602 			opnd_size_prefix = 0;
3603 			if (opnd_size == SIZE16)
3604 				opnd_size = SIZE32;
3605 		}
3606 		break;
3607 	case MRw:
3608 		if (rep_prefix) {
3609 			if (rep_prefix == 0xf3) {
3610 
3611 				/*
3612 				 * Calculate our offset in dis_op0F
3613 				 */
3614 				if ((uintptr_t)dp - (uintptr_t)dis_op0F
3615 				    > sizeof (dis_op0F))
3616 					goto error;
3617 
3618 				off = ((uintptr_t)dp - (uintptr_t)dis_op0F) /
3619 				    sizeof (instable_t);
3620 
3621 				dp = (instable_t *)&dis_opSIMDrepz[off];
3622 				rep_prefix = 0;
3623 			} else {
3624 				goto error;
3625 			}
3626 		}
3627 		break;
3628 	}
3629 
3630 	/*
3631 	 * In 64 bit mode, some opcodes automatically use opnd_size == SIZE64.
3632 	 */
3633 	if (cpu_mode == SIZE64)
3634 		if (dp->it_always64 || (opnd_size == SIZE32 && dp->it_stackop))
3635 			opnd_size = SIZE64;
3636 
3637 #ifdef DIS_TEXT
3638 	/*
3639 	 * At this point most instructions can format the opcode mnemonic
3640 	 * including the prefixes.
3641 	 */
3642 	if (lock_prefix)
3643 		(void) strlcat(x->d86_mnem, "lock ", OPLEN);
3644 
3645 	if (rep_prefix == 0xf2)
3646 		(void) strlcat(x->d86_mnem, "repnz ", OPLEN);
3647 	else if (rep_prefix == 0xf3)
3648 		(void) strlcat(x->d86_mnem, "repz ", OPLEN);
3649 
3650 	if (cpu_mode == SIZE64 && addr_size_prefix)
3651 		(void) strlcat(x->d86_mnem, "addr32 ", OPLEN);
3652 
3653 	if (dp->it_adrmode != CBW &&
3654 	    dp->it_adrmode != CWD &&
3655 	    dp->it_adrmode != XMMSFNC) {
3656 		if (strcmp(dp->it_name, "INVALID") == 0)
3657 			goto error;
3658 		(void) strlcat(x->d86_mnem, dp->it_name, OPLEN);
3659 		if (dp->it_avxsuf && dp->it_suffix) {
3660 			(void) strlcat(x->d86_mnem, vex_W != 0 ? "q" : "d",
3661 			    OPLEN);
3662 		} else if (dp->it_suffix) {
3663 			char *types[] = {"", "w", "l", "q"};
3664 			if (opcode_bytes == 2 && opcode4 == 4) {
3665 				/* It's a cmovx.yy. Replace the suffix x */
3666 				for (i = 5; i < OPLEN; i++) {
3667 					if (x->d86_mnem[i] == '.')
3668 						break;
3669 				}
3670 				x->d86_mnem[i - 1] = *types[opnd_size];
3671 			} else if ((opnd_size == 2) && (opcode_bytes == 3) &&
3672 			    ((opcode6 == 1 && opcode7 == 6) ||
3673 			    (opcode6 == 2 && opcode7 == 2))) {
3674 				/*
3675 				 * To handle PINSRD and PEXTRD
3676 				 */
3677 				(void) strlcat(x->d86_mnem, "d", OPLEN);
3678 			} else {
3679 				(void) strlcat(x->d86_mnem, types[opnd_size],
3680 				    OPLEN);
3681 			}
3682 		}
3683 	}
3684 #endif
3685 
3686 	/*
3687 	 * Process operands based on the addressing modes.
3688 	 */
3689 	x->d86_mode = cpu_mode;
3690 	/*
3691 	 * In vex mode the rex_prefix has no meaning
3692 	 */
3693 	if (!vex_prefix)
3694 		x->d86_rex_prefix = rex_prefix;
3695 	x->d86_opnd_size = opnd_size;
3696 	x->d86_addr_size = addr_size;
3697 	vbit = 0;		/* initialize for mem/reg -> reg */
3698 	switch (dp->it_adrmode) {
3699 		/*
3700 		 * amd64 instruction to sign extend 32 bit reg/mem operands
3701 		 * into 64 bit register values
3702 		 */
3703 	case MOVSXZ:
3704 #ifdef DIS_TEXT
3705 		if (rex_prefix == 0)
3706 			(void) strncpy(x->d86_mnem, "movzld", OPLEN);
3707 #endif
3708 		dtrace_get_modrm(x, &mode, &reg, &r_m);
3709 		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
3710 		x->d86_opnd_size = SIZE64;
3711 		dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
3712 		x->d86_opnd_size = opnd_size = SIZE32;
3713 		wbit = LONG_OPND;
3714 		dtrace_get_operand(x, mode, r_m, wbit, 0);
3715 		break;
3716 
3717 		/*
3718 		 * movsbl movsbw movsbq (0x0FBE) or movswl movswq (0x0FBF)
3719 		 * movzbl movzbw movzbq (0x0FB6) or movzwl movzwq (0x0FB7)
3720 		 * wbit lives in 2nd byte, note that operands
3721 		 * are different sized
3722 		 */
3723 	case MOVZ:
3724 		if (rex_prefix & REX_W) {
3725 			/* target register size = 64 bit */
3726 			x->d86_mnem[5] = 'q';
3727 		}
3728 		dtrace_get_modrm(x, &mode, &reg, &r_m);
3729 		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
3730 		dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
3731 		x->d86_opnd_size = opnd_size = SIZE16;
3732 		wbit = WBIT(opcode5);
3733 		dtrace_get_operand(x, mode, r_m, wbit, 0);
3734 		break;
3735 	case CRC32:
3736 		opnd_size = SIZE32;
3737 		if (rex_prefix & REX_W)
3738 			opnd_size = SIZE64;
3739 		x->d86_opnd_size = opnd_size;
3740 
3741 		dtrace_get_modrm(x, &mode, &reg, &r_m);
3742 		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
3743 		dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
3744 		wbit = WBIT(opcode7);
3745 		if (opnd_size_prefix)
3746 			x->d86_opnd_size = opnd_size = SIZE16;
3747 		dtrace_get_operand(x, mode, r_m, wbit, 0);
3748 		break;
3749 	case MOVBE:
3750 		opnd_size = SIZE32;
3751 		if (rex_prefix & REX_W)
3752 			opnd_size = SIZE64;
3753 		x->d86_opnd_size = opnd_size;
3754 
3755 		dtrace_get_modrm(x, &mode, &reg, &r_m);
3756 		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
3757 		wbit = WBIT(opcode7);
3758 		if (opnd_size_prefix)
3759 			x->d86_opnd_size = opnd_size = SIZE16;
3760 		if (wbit) {
3761 			/* reg -> mem */
3762 			dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);
3763 			dtrace_get_operand(x, mode, r_m, wbit, 1);
3764 		} else {
3765 			/* mem -> reg */
3766 			dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
3767 			dtrace_get_operand(x, mode, r_m, wbit, 0);
3768 		}
3769 		break;
3770 
3771 	/*
3772 	 * imul instruction, with either 8-bit or longer immediate
3773 	 * opcode 0x6B for byte, sign-extended displacement, 0x69 for word(s)
3774 	 */
3775 	case IMUL:
3776 		wbit = LONG_OPND;
3777 		THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND,
3778 		    OPSIZE(opnd_size, opcode2 == 0x9), 1);
3779 		break;
3780 
3781 	/* memory or register operand to register, with 'w' bit	*/
3782 	case MRw:
3783 	case ADX:
3784 		wbit = WBIT(opcode2);
3785 		STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
3786 		break;
3787 
3788 	/* register to memory or register operand, with 'w' bit	*/
3789 	/* arpl happens to fit here also because it is odd */
3790 	case RMw:
3791 		if (opcode_bytes == 2)
3792 			wbit = WBIT(opcode5);
3793 		else
3794 			wbit = WBIT(opcode2);
3795 		STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
3796 		break;
3797 
3798 	/* xaddb instruction */
3799 	case XADDB:
3800 		wbit = 0;
3801 		STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
3802 		break;
3803 
3804 	/* MMX register to memory or register operand		*/
3805 	case MMS:
3806 	case MMOS:
3807 #ifdef DIS_TEXT
3808 		wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND;
3809 #else
3810 		wbit = LONG_OPND;
3811 #endif
3812 		MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1);
3813 		break;
3814 
3815 	/* MMX register to memory */
3816 	case MMOMS:
3817 		dtrace_get_modrm(x, &mode, &reg, &r_m);
3818 		if (mode == REG_ONLY)
3819 			goto error;
3820 		wbit = MM_OPND;
3821 		MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1);
3822 		break;
3823 
3824 	/* Double shift. Has immediate operand specifying the shift. */
3825 	case DSHIFT:
3826 		wbit = LONG_OPND;
3827 		dtrace_get_modrm(x, &mode, &reg, &r_m);
3828 		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
3829 		dtrace_get_operand(x, mode, r_m, wbit, 2);
3830 		dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
3831 		dtrace_imm_opnd(x, wbit, 1, 0);
3832 		break;
3833 
3834 	/*
3835 	 * Double shift. With no immediate operand, specifies using %cl.
3836 	 */
3837 	case DSHIFTcl:
3838 		wbit = LONG_OPND;
3839 		STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
3840 		break;
3841 
3842 	/* immediate to memory or register operand */
3843 	case IMlw:
3844 		wbit = WBIT(opcode2);
3845 		dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3846 		dtrace_get_operand(x, mode, r_m, wbit, 1);
3847 		/*
3848 		 * Have long immediate for opcode 0x81, but not 0x80 nor 0x83
3849 		 */
3850 		dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, opcode2 == 1), 0);
3851 		break;
3852 
3853 	/* immediate to memory or register operand with the	*/
3854 	/* 'w' bit present					*/
3855 	case IMw:
3856 		wbit = WBIT(opcode2);
3857 		dtrace_get_modrm(x, &mode, &reg, &r_m);
3858 		dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3859 		dtrace_get_operand(x, mode, r_m, wbit, 1);
3860 		dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0);
3861 		break;
3862 
3863 	/* immediate to register with register in low 3 bits	*/
3864 	/* of op code						*/
3865 	case IR:
3866 		/* w-bit here (with regs) is bit 3 */
3867 		wbit = opcode2 >>3 & 0x1;
3868 		reg = REGNO(opcode2);
3869 		dtrace_rex_adjust(rex_prefix, mode, &reg, NULL);
3870 		mode = REG_ONLY;
3871 		r_m = reg;
3872 		dtrace_get_operand(x, mode, r_m, wbit, 1);
3873 		dtrace_imm_opnd(x, wbit, OPSIZE64(opnd_size, wbit), 0);
3874 		break;
3875 
3876 	/* MMX immediate shift of register */
3877 	case MMSH:
3878 	case MMOSH:
3879 		wbit = MM_OPND;
3880 		goto mm_shift;	/* in next case */
3881 
3882 	/* SIMD immediate shift of register */
3883 	case XMMSH:
3884 		wbit = XMM_OPND;
3885 mm_shift:
3886 		reg = REGNO(opcode7);
3887 		dtrace_rex_adjust(rex_prefix, mode, &reg, NULL);
3888 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
3889 		dtrace_imm_opnd(x, wbit, 1, 0);
3890 		NOMEM;
3891 		break;
3892 
3893 	/* accumulator to memory operand */
3894 	case AO:
3895 		vbit = 1;
3896 		/*FALLTHROUGH*/
3897 
3898 	/* memory operand to accumulator */
3899 	case OA:
3900 		wbit = WBIT(opcode2);
3901 		dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1 - vbit);
3902 		dtrace_imm_opnd(x, wbit, OPSIZE64(addr_size, LONG_OPND), vbit);
3903 #ifdef DIS_TEXT
3904 		x->d86_opnd[vbit].d86_mode = MODE_OFFSET;
3905 #endif
3906 		break;
3907 
3908 
3909 	/* segment register to memory or register operand */
3910 	case SM:
3911 		vbit = 1;
3912 		/*FALLTHROUGH*/
3913 
3914 	/* memory or register operand to segment register */
3915 	case MS:
3916 		dtrace_get_modrm(x, &mode, &reg, &r_m);
3917 		dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3918 		dtrace_get_operand(x, mode, r_m, LONG_OPND, vbit);
3919 		dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 1 - vbit);
3920 		break;
3921 
3922 	/*
3923 	 * rotate or shift instructions, which may shift by 1 or
3924 	 * consult the cl register, depending on the 'v' bit
3925 	 */
3926 	case Mv:
3927 		vbit = VBIT(opcode2);
3928 		wbit = WBIT(opcode2);
3929 		dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3930 		dtrace_get_operand(x, mode, r_m, wbit, 1);
3931 #ifdef DIS_TEXT
3932 		if (vbit) {
3933 			(void) strlcat(x->d86_opnd[0].d86_opnd, "%cl", OPLEN);
3934 		} else {
3935 			x->d86_opnd[0].d86_mode = MODE_SIGNED;
3936 			x->d86_opnd[0].d86_value_size = 1;
3937 			x->d86_opnd[0].d86_value = 1;
3938 		}
3939 #endif
3940 		break;
3941 	/*
3942 	 * immediate rotate or shift instructions
3943 	 */
3944 	case MvI:
3945 		wbit = WBIT(opcode2);
3946 normal_imm_mem:
3947 		dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3948 		dtrace_get_operand(x, mode, r_m, wbit, 1);
3949 		dtrace_imm_opnd(x, wbit, 1, 0);
3950 		break;
3951 
3952 	/* bit test instructions */
3953 	case MIb:
3954 		wbit = LONG_OPND;
3955 		goto normal_imm_mem;
3956 
3957 	/* single memory or register operand with 'w' bit present */
3958 	case Mw:
3959 		wbit = WBIT(opcode2);
3960 just_mem:
3961 		dtrace_get_modrm(x, &mode, &reg, &r_m);
3962 		dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3963 		dtrace_get_operand(x, mode, r_m, wbit, 0);
3964 		break;
3965 
3966 	case SWAPGS_RDTSCP:
3967 		if (cpu_mode == SIZE64 && mode == 3 && r_m == 0) {
3968 #ifdef DIS_TEXT
3969 			(void) strncpy(x->d86_mnem, "swapgs", OPLEN);
3970 #endif
3971 			NOMEM;
3972 			break;
3973 		} else if (mode == 3 && r_m == 1) {
3974 #ifdef DIS_TEXT
3975 			(void) strncpy(x->d86_mnem, "rdtscp", OPLEN);
3976 #endif
3977 			NOMEM;
3978 			break;
3979 		}
3980 
3981 		/*FALLTHROUGH*/
3982 
3983 	/* prefetch instruction - memory operand, but no memory acess */
3984 	case PREF:
3985 		NOMEM;
3986 		/*FALLTHROUGH*/
3987 
3988 	/* single memory or register operand */
3989 	case M:
3990 	case MG9:
3991 		wbit = LONG_OPND;
3992 		goto just_mem;
3993 
3994 	/* single memory or register byte operand */
3995 	case Mb:
3996 		wbit = BYTE_OPND;
3997 		goto just_mem;
3998 
3999 	case VMx:
4000 		if (mode == 3) {
4001 #ifdef DIS_TEXT
4002 			char *vminstr;
4003 
4004 			switch (r_m) {
4005 			case 1:
4006 				vminstr = "vmcall";
4007 				break;
4008 			case 2:
4009 				vminstr = "vmlaunch";
4010 				break;
4011 			case 3:
4012 				vminstr = "vmresume";
4013 				break;
4014 			case 4:
4015 				vminstr = "vmxoff";
4016 				break;
4017 			default:
4018 				goto error;
4019 			}
4020 
4021 			(void) strncpy(x->d86_mnem, vminstr, OPLEN);
4022 #else
4023 			if (r_m < 1 || r_m > 4)
4024 				goto error;
4025 #endif
4026 
4027 			NOMEM;
4028 			break;
4029 		}
4030 		/*FALLTHROUGH*/
4031 	case SVM:
4032 		if (mode == 3) {
4033 #if DIS_TEXT
4034 			char *vinstr;
4035 
4036 			switch (r_m) {
4037 			case 0:
4038 				vinstr = "vmrun";
4039 				break;
4040 			case 1:
4041 				vinstr = "vmmcall";
4042 				break;
4043 			case 2:
4044 				vinstr = "vmload";
4045 				break;
4046 			case 3:
4047 				vinstr = "vmsave";
4048 				break;
4049 			case 4:
4050 				vinstr = "stgi";
4051 				break;
4052 			case 5:
4053 				vinstr = "clgi";
4054 				break;
4055 			case 6:
4056 				vinstr = "skinit";
4057 				break;
4058 			case 7:
4059 				vinstr = "invlpga";
4060 				break;
4061 			}
4062 
4063 			(void) strncpy(x->d86_mnem, vinstr, OPLEN);
4064 #endif
4065 			NOMEM;
4066 			break;
4067 		}
4068 		/*FALLTHROUGH*/
4069 	case MONITOR_MWAIT:
4070 		if (mode == 3) {
4071 			if (r_m == 0) {
4072 #ifdef DIS_TEXT
4073 				(void) strncpy(x->d86_mnem, "monitor", OPLEN);
4074 #endif
4075 				NOMEM;
4076 				break;
4077 			} else if (r_m == 1) {
4078 #ifdef DIS_TEXT
4079 				(void) strncpy(x->d86_mnem, "mwait", OPLEN);
4080 #endif
4081 				NOMEM;
4082 				break;
4083 			} else if (r_m == 2) {
4084 #ifdef DIS_TEXT
4085 				(void) strncpy(x->d86_mnem, "clac", OPLEN);
4086 #endif
4087 				NOMEM;
4088 				break;
4089 			} else if (r_m == 3) {
4090 #ifdef DIS_TEXT
4091 				(void) strncpy(x->d86_mnem, "stac", OPLEN);
4092 #endif
4093 				NOMEM;
4094 				break;
4095 			} else {
4096 				goto error;
4097 			}
4098 		}
4099 		/*FALLTHROUGH*/
4100 	case XGETBV_XSETBV:
4101 		if (mode == 3) {
4102 			if (r_m == 0) {
4103 #ifdef DIS_TEXT
4104 				(void) strncpy(x->d86_mnem, "xgetbv", OPLEN);
4105 #endif
4106 				NOMEM;
4107 				break;
4108 			} else if (r_m == 1) {
4109 #ifdef DIS_TEXT
4110 				(void) strncpy(x->d86_mnem, "xsetbv", OPLEN);
4111 #endif
4112 				NOMEM;
4113 				break;
4114 			} else {
4115 				goto error;
4116 			}
4117 
4118 		}
4119 		/*FALLTHROUGH*/
4120 	case MO:
4121 		/* Similar to M, but only memory (no direct registers) */
4122 		wbit = LONG_OPND;
4123 		dtrace_get_modrm(x, &mode, &reg, &r_m);
4124 		if (mode == 3)
4125 			goto error;
4126 		dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
4127 		dtrace_get_operand(x, mode, r_m, wbit, 0);
4128 		break;
4129 
4130 	/* move special register to register or reverse if vbit */
4131 	case SREG:
4132 		switch (opcode5) {
4133 
4134 		case 2:
4135 			vbit = 1;
4136 			/*FALLTHROUGH*/
4137 		case 0:
4138 			wbit = CONTROL_OPND;
4139 			break;
4140 
4141 		case 3:
4142 			vbit = 1;
4143 			/*FALLTHROUGH*/
4144 		case 1:
4145 			wbit = DEBUG_OPND;
4146 			break;
4147 
4148 		case 6:
4149 			vbit = 1;
4150 			/*FALLTHROUGH*/
4151 		case 4:
4152 			wbit = TEST_OPND;
4153 			break;
4154 
4155 		}
4156 		dtrace_get_modrm(x, &mode, &reg, &r_m);
4157 		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
4158 		dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit);
4159 		dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 1 - vbit);
4160 		NOMEM;
4161 		break;
4162 
4163 	/*
4164 	 * single register operand with register in the low 3
4165 	 * bits of op code
4166 	 */
4167 	case R:
4168 		if (opcode_bytes == 2)
4169 			reg = REGNO(opcode5);
4170 		else
4171 			reg = REGNO(opcode2);
4172 		dtrace_rex_adjust(rex_prefix, mode, &reg, NULL);
4173 		dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);
4174 		NOMEM;
4175 		break;
4176 
4177 	/*
4178 	 * register to accumulator with register in the low 3
4179 	 * bits of op code, xchg instructions
4180 	 */
4181 	case RA:
4182 		NOMEM;
4183 		reg = REGNO(opcode2);
4184 		dtrace_rex_adjust(rex_prefix, mode, &reg, NULL);
4185 		dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);
4186 		dtrace_get_operand(x, REG_ONLY, EAX_REGNO, LONG_OPND, 1);
4187 		break;
4188 
4189 	/*
4190 	 * single segment register operand, with register in
4191 	 * bits 3-4 of op code byte
4192 	 */
4193 	case SEG:
4194 		NOMEM;
4195 		reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x3;
4196 		dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0);
4197 		break;
4198 
4199 	/*
4200 	 * single segment register operand, with register in
4201 	 * bits 3-5 of op code
4202 	 */
4203 	case LSEG:
4204 		NOMEM;
4205 		/* long seg reg from opcode */
4206 		reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x7;
4207 		dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0);
4208 		break;
4209 
4210 	/* memory or register operand to register */
4211 	case MR:
4212 		if (vex_prefetch)
4213 			x->d86_got_modrm = 1;
4214 		wbit = LONG_OPND;
4215 		STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
4216 		break;
4217 
4218 	case RM:
4219 	case RM_66r:
4220 		wbit = LONG_OPND;
4221 		STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
4222 		break;
4223 
4224 	/* MMX/SIMD-Int memory or mm reg to mm reg		*/
4225 	case MM:
4226 	case MMO:
4227 #ifdef DIS_TEXT
4228 		wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND;
4229 #else
4230 		wbit = LONG_OPND;
4231 #endif
4232 		MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0);
4233 		break;
4234 
4235 	case MMOIMPL:
4236 #ifdef DIS_TEXT
4237 		wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND;
4238 #else
4239 		wbit = LONG_OPND;
4240 #endif
4241 		dtrace_get_modrm(x, &mode, &reg, &r_m);
4242 		if (mode != REG_ONLY)
4243 			goto error;
4244 
4245 		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
4246 		dtrace_get_operand(x, mode, r_m, wbit, 0);
4247 		dtrace_get_operand(x, REG_ONLY, reg, MM_OPND, 1);
4248 		mode = 0;	/* change for memory access size... */
4249 		break;
4250 
4251 	/* MMX/SIMD-Int and SIMD-FP predicated mm reg to r32 */
4252 	case MMO3P:
4253 		wbit = MM_OPND;
4254 		goto xmm3p;
4255 	case XMM3P:
4256 		wbit = XMM_OPND;
4257 xmm3p:
4258 		dtrace_get_modrm(x, &mode, &reg, &r_m);
4259 		if (mode != REG_ONLY)
4260 			goto error;
4261 
4262 		THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 1,
4263 		    1);
4264 		NOMEM;
4265 		break;
4266 
4267 	case XMM3PM_66r:
4268 		THREEOPERAND(x, mode, reg, r_m, rex_prefix, LONG_OPND, XMM_OPND,
4269 		    1, 0);
4270 		break;
4271 
4272 	/* MMX/SIMD-Int predicated r32/mem to mm reg */
4273 	case MMOPRM:
4274 		wbit = LONG_OPND;
4275 		w2 = MM_OPND;
4276 		goto xmmprm;
4277 	case XMMPRM:
4278 	case XMMPRM_66r:
4279 		wbit = LONG_OPND;
4280 		w2 = XMM_OPND;
4281 xmmprm:
4282 		THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, 1, 1);
4283 		break;
4284 
4285 	/* MMX/SIMD-Int predicated mm/mem to mm reg */
4286 	case MMOPM:
4287 	case MMOPM_66o:
4288 		wbit = w2 = MM_OPND;
4289 		goto xmmprm;
4290 
4291 	/* MMX/SIMD-Int mm reg to r32 */
4292 	case MMOM3:
4293 		NOMEM;
4294 		dtrace_get_modrm(x, &mode, &reg, &r_m);
4295 		if (mode != REG_ONLY)
4296 			goto error;
4297 		wbit = MM_OPND;
4298 		MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0);
4299 		break;
4300 
4301 	/* SIMD memory or xmm reg operand to xmm reg		*/
4302 	case XMM:
4303 	case XMM_66o:
4304 	case XMM_66r:
4305 	case XMMO:
4306 	case XMMXIMPL:
4307 		wbit = XMM_OPND;
4308 		STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
4309 
4310 		if (dp->it_adrmode == XMMXIMPL && mode != REG_ONLY)
4311 			goto error;
4312 
4313 #ifdef DIS_TEXT
4314 		/*
4315 		 * movlps and movhlps share opcodes.  They differ in the
4316 		 * addressing modes allowed for their operands.
4317 		 * movhps and movlhps behave similarly.
4318 		 */
4319 		if (mode == REG_ONLY) {
4320 			if (strcmp(dp->it_name, "movlps") == 0)
4321 				(void) strncpy(x->d86_mnem, "movhlps", OPLEN);
4322 			else if (strcmp(dp->it_name, "movhps") == 0)
4323 				(void) strncpy(x->d86_mnem, "movlhps", OPLEN);
4324 		}
4325 #endif
4326 		if (dp->it_adrmode == XMMXIMPL)
4327 			mode = 0;	/* change for memory access size... */
4328 		break;
4329 
4330 	/* SIMD xmm reg to memory or xmm reg */
4331 	case XMMS:
4332 	case XMMOS:
4333 	case XMMMS:
4334 	case XMMOMS:
4335 		dtrace_get_modrm(x, &mode, &reg, &r_m);
4336 #ifdef DIS_TEXT
4337 		if ((strcmp(dp->it_name, "movlps") == 0 ||
4338 		    strcmp(dp->it_name, "movhps") == 0 ||
4339 		    strcmp(dp->it_name, "movntps") == 0) &&
4340 		    mode == REG_ONLY)
4341 			goto error;
4342 #endif
4343 		wbit = XMM_OPND;
4344 		MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1);
4345 		break;
4346 
4347 	/* SIMD memory to xmm reg */
4348 	case XMMM:
4349 	case XMMM_66r:
4350 	case XMMOM:
4351 		wbit = XMM_OPND;
4352 		dtrace_get_modrm(x, &mode, &reg, &r_m);
4353 #ifdef DIS_TEXT
4354 		if (mode == REG_ONLY) {
4355 			if (strcmp(dp->it_name, "movhps") == 0)
4356 				(void) strncpy(x->d86_mnem, "movlhps", OPLEN);
4357 			else
4358 				goto error;
4359 		}
4360 #endif
4361 		MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0);
4362 		break;
4363 
4364 	/* SIMD memory or r32 to xmm reg			*/
4365 	case XMM3MX:
4366 		wbit = LONG_OPND;
4367 		MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0);
4368 		break;
4369 
4370 	case XMM3MXS:
4371 		wbit = LONG_OPND;
4372 		MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1);
4373 		break;
4374 
4375 	/* SIMD memory or mm reg to xmm reg			*/
4376 	case XMMOMX:
4377 	/* SIMD mm to xmm */
4378 	case XMMMX:
4379 		wbit = MM_OPND;
4380 		MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0);
4381 		break;
4382 
4383 	/* SIMD memory or xmm reg to mm reg			*/
4384 	case XMMXMM:
4385 	case XMMOXMM:
4386 	case XMMXM:
4387 		wbit = XMM_OPND;
4388 		MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0);
4389 		break;
4390 
4391 
4392 	/* SIMD memory or xmm reg to r32			*/
4393 	case XMMXM3:
4394 		wbit = XMM_OPND;
4395 		MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0);
4396 		break;
4397 
4398 	/* SIMD xmm to r32					*/
4399 	case XMMX3:
4400 	case XMMOX3:
4401 		dtrace_get_modrm(x, &mode, &reg, &r_m);
4402 		if (mode != REG_ONLY)
4403 			goto error;
4404 		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
4405 		dtrace_get_operand(x, mode, r_m, XMM_OPND, 0);
4406 		dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
4407 		NOMEM;
4408 		break;
4409 
4410 	/* SIMD predicated memory or xmm reg with/to xmm reg */
4411 	case XMMP:
4412 	case XMMP_66r:
4413 	case XMMP_66o:
4414 	case XMMOPM:
4415 		wbit = XMM_OPND;
4416 		THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1,
4417 		    1);
4418 
4419 #ifdef DIS_TEXT
4420 		/*
4421 		 * cmpps and cmpss vary their instruction name based
4422 		 * on the value of imm8.  Other XMMP instructions,
4423 		 * such as shufps, require explicit specification of
4424 		 * the predicate.
4425 		 */
4426 		if (dp->it_name[0] == 'c' &&
4427 		    dp->it_name[1] == 'm' &&
4428 		    dp->it_name[2] == 'p' &&
4429 		    strlen(dp->it_name) == 5) {
4430 			uchar_t pred = x->d86_opnd[0].d86_value & 0xff;
4431 
4432 			if (pred >= (sizeof (dis_PREDSUFFIX) / sizeof (char *)))
4433 				goto error;
4434 
4435 			(void) strncpy(x->d86_mnem, "cmp", OPLEN);
4436 			(void) strlcat(x->d86_mnem, dis_PREDSUFFIX[pred],
4437 			    OPLEN);
4438 			(void) strlcat(x->d86_mnem,
4439 			    dp->it_name + strlen(dp->it_name) - 2,
4440 			    OPLEN);
4441 			x->d86_opnd[0] = x->d86_opnd[1];
4442 			x->d86_opnd[1] = x->d86_opnd[2];
4443 			x->d86_numopnds = 2;
4444 		}
4445 #endif
4446 		break;
4447 
4448 	case XMMX2I:
4449 		FOUROPERAND(x, mode, reg, r_m, rex_prefix, XMM_OPND, XMM_OPND,
4450 		    1);
4451 		NOMEM;
4452 		break;
4453 
4454 	case XMM2I:
4455 		ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, XMM_OPND, 1);
4456 		NOMEM;
4457 		break;
4458 
4459 	/* immediate operand to accumulator */
4460 	case IA:
4461 		wbit = WBIT(opcode2);
4462 		dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1);
4463 		dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0);
4464 		NOMEM;
4465 		break;
4466 
4467 	/* memory or register operand to accumulator */
4468 	case MA:
4469 		wbit = WBIT(opcode2);
4470 		dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
4471 		dtrace_get_operand(x, mode, r_m, wbit, 0);
4472 		break;
4473 
4474 	/* si register to di register used to reference memory		*/
4475 	case SD:
4476 #ifdef DIS_TEXT
4477 		dtrace_check_override(x, 0);
4478 		x->d86_numopnds = 2;
4479 		if (addr_size == SIZE64) {
4480 			(void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)",
4481 			    OPLEN);
4482 			(void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)",
4483 			    OPLEN);
4484 		} else if (addr_size == SIZE32) {
4485 			(void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)",
4486 			    OPLEN);
4487 			(void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)",
4488 			    OPLEN);
4489 		} else {
4490 			(void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)",
4491 			    OPLEN);
4492 			(void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)",
4493 			    OPLEN);
4494 		}
4495 #endif
4496 		wbit = LONG_OPND;
4497 		break;
4498 
4499 	/* accumulator to di register				*/
4500 	case AD:
4501 		wbit = WBIT(opcode2);
4502 #ifdef DIS_TEXT
4503 		dtrace_check_override(x, 1);
4504 		x->d86_numopnds = 2;
4505 		dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 0);
4506 		if (addr_size == SIZE64)
4507 			(void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)",
4508 			    OPLEN);
4509 		else if (addr_size == SIZE32)
4510 			(void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)",
4511 			    OPLEN);
4512 		else
4513 			(void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)",
4514 			    OPLEN);
4515 #endif
4516 		break;
4517 
4518 	/* si register to accumulator				*/
4519 	case SA:
4520 		wbit = WBIT(opcode2);
4521 #ifdef DIS_TEXT
4522 		dtrace_check_override(x, 0);
4523 		x->d86_numopnds = 2;
4524 		if (addr_size == SIZE64)
4525 			(void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)",
4526 			    OPLEN);
4527 		else if (addr_size == SIZE32)
4528 			(void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)",
4529 			    OPLEN);
4530 		else
4531 			(void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)",
4532 			    OPLEN);
4533 		dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1);
4534 #endif
4535 		break;
4536 
4537 	/*
4538 	 * single operand, a 16/32 bit displacement
4539 	 */
4540 	case D:
4541 		wbit = LONG_OPND;
4542 		dtrace_disp_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0);
4543 		NOMEM;
4544 		break;
4545 
4546 	/* jmp/call indirect to memory or register operand		*/
4547 	case INM:
4548 #ifdef DIS_TEXT
4549 		(void) strlcat(x->d86_opnd[0].d86_prefix, "*", OPLEN);
4550 #endif
4551 		dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
4552 		dtrace_get_operand(x, mode, r_m, LONG_OPND, 0);
4553 		wbit = LONG_OPND;
4554 		break;
4555 
4556 	/*
4557 	 * for long jumps and long calls -- a new code segment
4558 	 * register and an offset in IP -- stored in object
4559 	 * code in reverse order. Note - not valid in amd64
4560 	 */
4561 	case SO:
4562 		dtrace_check_override(x, 1);
4563 		wbit = LONG_OPND;
4564 		dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 1);
4565 #ifdef DIS_TEXT
4566 		x->d86_opnd[1].d86_mode = MODE_SIGNED;
4567 #endif
4568 		/* will now get segment operand */
4569 		dtrace_imm_opnd(x, wbit, 2, 0);
4570 		break;
4571 
4572 	/*
4573 	 * jmp/call. single operand, 8 bit displacement.
4574 	 * added to current EIP in 'compofff'
4575 	 */
4576 	case BD:
4577 		dtrace_disp_opnd(x, BYTE_OPND, 1, 0);
4578 		NOMEM;
4579 		break;
4580 
4581 	/* single 32/16 bit immediate operand			*/
4582 	case I:
4583 		wbit = LONG_OPND;
4584 		dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0);
4585 		break;
4586 
4587 	/* single 8 bit immediate operand			*/
4588 	case Ib:
4589 		wbit = LONG_OPND;
4590 		dtrace_imm_opnd(x, wbit, 1, 0);
4591 		break;
4592 
4593 	case ENTER:
4594 		wbit = LONG_OPND;
4595 		dtrace_imm_opnd(x, wbit, 2, 0);
4596 		dtrace_imm_opnd(x, wbit, 1, 1);
4597 		switch (opnd_size) {
4598 		case SIZE64:
4599 			x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 8;
4600 			break;
4601 		case SIZE32:
4602 			x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 4;
4603 			break;
4604 		case SIZE16:
4605 			x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 2;
4606 			break;
4607 		}
4608 
4609 		break;
4610 
4611 	/* 16-bit immediate operand */
4612 	case RET:
4613 		wbit = LONG_OPND;
4614 		dtrace_imm_opnd(x, wbit, 2, 0);
4615 		break;
4616 
4617 	/* single 8 bit port operand				*/
4618 	case P:
4619 		dtrace_check_override(x, 0);
4620 		dtrace_imm_opnd(x, BYTE_OPND, 1, 0);
4621 		NOMEM;
4622 		break;
4623 
4624 	/* single operand, dx register (variable port instruction) */
4625 	case V:
4626 		x->d86_numopnds = 1;
4627 		dtrace_check_override(x, 0);
4628 #ifdef DIS_TEXT
4629 		(void) strlcat(x->d86_opnd[0].d86_opnd, "(%dx)", OPLEN);
4630 #endif
4631 		NOMEM;
4632 		break;
4633 
4634 	/*
4635 	 * The int instruction, which has two forms:
4636 	 * int 3 (breakpoint) or
4637 	 * int n, where n is indicated in the subsequent
4638 	 * byte (format Ib).  The int 3 instruction (opcode 0xCC),
4639 	 * where, although the 3 looks  like an operand,
4640 	 * it is implied by the opcode. It must be converted
4641 	 * to the correct base and output.
4642 	 */
4643 	case INT3:
4644 #ifdef DIS_TEXT
4645 		x->d86_numopnds = 1;
4646 		x->d86_opnd[0].d86_mode = MODE_SIGNED;
4647 		x->d86_opnd[0].d86_value_size = 1;
4648 		x->d86_opnd[0].d86_value = 3;
4649 #endif
4650 		NOMEM;
4651 		break;
4652 
4653 	/* single 8 bit immediate operand			*/
4654 	case INTx:
4655 		dtrace_imm_opnd(x, BYTE_OPND, 1, 0);
4656 		NOMEM;
4657 		break;
4658 
4659 	/* an unused byte must be discarded */
4660 	case U:
4661 		if (x->d86_get_byte(x->d86_data) < 0)
4662 			goto error;
4663 		x->d86_len++;
4664 		NOMEM;
4665 		break;
4666 
4667 	case CBW:
4668 #ifdef DIS_TEXT
4669 		if (opnd_size == SIZE16)
4670 			(void) strlcat(x->d86_mnem, "cbtw", OPLEN);
4671 		else if (opnd_size == SIZE32)
4672 			(void) strlcat(x->d86_mnem, "cwtl", OPLEN);
4673 		else
4674 			(void) strlcat(x->d86_mnem, "cltq", OPLEN);
4675 #endif
4676 		wbit = LONG_OPND;
4677 		NOMEM;
4678 		break;
4679 
4680 	case CWD:
4681 #ifdef DIS_TEXT
4682 		if (opnd_size == SIZE16)
4683 			(void) strlcat(x->d86_mnem, "cwtd", OPLEN);
4684 		else if (opnd_size == SIZE32)
4685 			(void) strlcat(x->d86_mnem, "cltd", OPLEN);
4686 		else
4687 			(void) strlcat(x->d86_mnem, "cqtd", OPLEN);
4688 #endif
4689 		wbit = LONG_OPND;
4690 		NOMEM;
4691 		break;
4692 
4693 	case XMMSFNC:
4694 		/*
4695 		 * sfence is sfence if mode is REG_ONLY.  If mode isn't
4696 		 * REG_ONLY, mnemonic should be 'clflush'.
4697 		 */
4698 		dtrace_get_modrm(x, &mode, &reg, &r_m);
4699 
4700 		/* sfence doesn't take operands */
4701 #ifdef DIS_TEXT
4702 		if (mode == REG_ONLY) {
4703 			(void) strlcat(x->d86_mnem, "sfence", OPLEN);
4704 		} else {
4705 			(void) strlcat(x->d86_mnem, "clflush", OPLEN);
4706 			dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
4707 			dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0);
4708 			NOMEM;
4709 		}
4710 #else
4711 		if (mode != REG_ONLY) {
4712 			dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
4713 			dtrace_get_operand(x, mode, r_m, LONG_OPND, 0);
4714 			NOMEM;
4715 		}
4716 #endif
4717 		break;
4718 
4719 	/*
4720 	 * no disassembly, the mnemonic was all there was so go on
4721 	 */
4722 	case NORM:
4723 		if (dp->it_invalid32 && cpu_mode != SIZE64)
4724 			goto error;
4725 		NOMEM;
4726 		/*FALLTHROUGH*/
4727 	case IMPLMEM:
4728 		break;
4729 
4730 	case XMMFENCE:
4731 		/*
4732 		 * XRSTOR and LFENCE share the same opcode but differ in mode
4733 		 */
4734 		dtrace_get_modrm(x, &mode, &reg, &r_m);
4735 
4736 		if (mode == REG_ONLY) {
4737 			/*
4738 			 * Only the following exact byte sequences are allowed:
4739 			 *
4740 			 * 	0f ae e8	lfence
4741 			 * 	0f ae f0	mfence
4742 			 */
4743 			if ((uint8_t)x->d86_bytes[x->d86_len - 1] != 0xe8 &&
4744 			    (uint8_t)x->d86_bytes[x->d86_len - 1] != 0xf0)
4745 				goto error;
4746 		} else {
4747 #ifdef DIS_TEXT
4748 			(void) strncpy(x->d86_mnem, "xrstor", OPLEN);
4749 #endif
4750 			dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
4751 			dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0);
4752 		}
4753 		break;
4754 
4755 	/* float reg */
4756 	case F:
4757 #ifdef DIS_TEXT
4758 		x->d86_numopnds = 1;
4759 		(void) strlcat(x->d86_opnd[0].d86_opnd, "%st(X)", OPLEN);
4760 		x->d86_opnd[0].d86_opnd[4] = r_m + '0';
4761 #endif
4762 		NOMEM;
4763 		break;
4764 
4765 	/* float reg to float reg, with ret bit present */
4766 	case FF:
4767 		vbit = opcode2 >> 2 & 0x1;	/* vbit = 1: st -> st(i) */
4768 		/*FALLTHROUGH*/
4769 	case FFC:				/* case for vbit always = 0 */
4770 #ifdef DIS_TEXT
4771 		x->d86_numopnds = 2;
4772 		(void) strlcat(x->d86_opnd[1 - vbit].d86_opnd, "%st", OPLEN);
4773 		(void) strlcat(x->d86_opnd[vbit].d86_opnd, "%st(X)", OPLEN);
4774 		x->d86_opnd[vbit].d86_opnd[4] = r_m + '0';
4775 #endif
4776 		NOMEM;
4777 		break;
4778 
4779 	/* AVX instructions */
4780 	case VEX_MO:
4781 		/* op(ModR/M.r/m) */
4782 		x->d86_numopnds = 1;
4783 		dtrace_get_modrm(x, &mode, &reg, &r_m);
4784 #ifdef DIS_TEXT
4785 		if ((dp == &dis_opAVX0F[0xA][0xE]) && (reg == 3))
4786 			(void) strncpy(x->d86_mnem, "vstmxcsr", OPLEN);
4787 #endif
4788 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
4789 		dtrace_get_operand(x, mode, r_m, wbit, 0);
4790 		break;
4791 	case VEX_RMrX:
4792 	case FMA:
4793 		/* ModR/M.reg := op(VEX.vvvv, ModR/M.r/m) */
4794 		x->d86_numopnds = 3;
4795 		dtrace_get_modrm(x, &mode, &reg, &r_m);
4796 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
4797 
4798 		/*
4799 		 * In classic Intel fashion, the opcodes for all of the FMA
4800 		 * instructions all have two possible mnemonics which vary by
4801 		 * one letter, which is selected based on the value of the wbit.
4802 		 * When wbit is one, they have the 'd' suffix and when 'wbit' is
4803 		 * 0, they have the 's' suffix. Otherwise, the FMA instructions
4804 		 * are all a standard VEX_RMrX.
4805 		 */
4806 #ifdef DIS_TEXT
4807 		if (dp->it_adrmode == FMA) {
4808 			size_t len = strlen(dp->it_name);
4809 			(void) strncpy(x->d86_mnem, dp->it_name, OPLEN);
4810 			if (len + 1 < OPLEN) {
4811 				(void) strncpy(x->d86_mnem + len,
4812 				    vex_W != 0 ? "d" : "s", OPLEN - len);
4813 			}
4814 		}
4815 #endif
4816 
4817 		if (mode != REG_ONLY) {
4818 			if ((dp == &dis_opAVXF20F[0x10]) ||
4819 			    (dp == &dis_opAVXF30F[0x10])) {
4820 				/* vmovsd <m64>, <xmm> */
4821 				/* or vmovss <m64>, <xmm> */
4822 				x->d86_numopnds = 2;
4823 				goto L_VEX_MX;
4824 			}
4825 		}
4826 
4827 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
4828 		/*
4829 		 * VEX prefix uses the 1's complement form to encode the
4830 		 * XMM/YMM regs
4831 		 */
4832 		dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
4833 
4834 		if ((dp == &dis_opAVXF20F[0x2A]) ||
4835 		    (dp == &dis_opAVXF30F[0x2A])) {
4836 			/*
4837 			 * vcvtsi2si </r,m>, <xmm>, <xmm> or vcvtsi2ss </r,m>,
4838 			 * <xmm>, <xmm>
4839 			 */
4840 			wbit = LONG_OPND;
4841 		}
4842 #ifdef DIS_TEXT
4843 		else if ((mode == REG_ONLY) &&
4844 		    (dp == &dis_opAVX0F[0x1][0x6])) {	/* vmovlhps */
4845 			(void) strncpy(x->d86_mnem, "vmovlhps", OPLEN);
4846 		} else if ((mode == REG_ONLY) &&
4847 		    (dp == &dis_opAVX0F[0x1][0x2])) {	/* vmovhlps */
4848 			(void) strncpy(x->d86_mnem, "vmovhlps", OPLEN);
4849 		}
4850 #endif
4851 		dtrace_get_operand(x, mode, r_m, wbit, 0);
4852 
4853 		break;
4854 
4855 	case VEX_VRMrX:
4856 		/* ModR/M.reg := op(MODR/M.r/m, VEX.vvvv) */
4857 		x->d86_numopnds = 3;
4858 		dtrace_get_modrm(x, &mode, &reg, &r_m);
4859 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
4860 
4861 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
4862 		/*
4863 		 * VEX prefix uses the 1's complement form to encode the
4864 		 * XMM/YMM regs
4865 		 */
4866 		dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 0);
4867 
4868 		dtrace_get_operand(x, mode, r_m, wbit, 1);
4869 		break;
4870 
4871 	case VEX_SbVM:
4872 		/* ModR/M.reg := op(MODR/M.r/m, VSIB, VEX.vvvv) */
4873 		x->d86_numopnds = 3;
4874 		x->d86_vsib = 1;
4875 
4876 		/*
4877 		 * All instructions that use VSIB are currently a mess. See the
4878 		 * comment around the dis_gather_regs_t structure definition.
4879 		 */
4880 
4881 		vreg = &dis_vgather[opcode2][vex_W][vex_L];
4882 
4883 #ifdef DIS_TEXT
4884 		(void) strncpy(x->d86_mnem, dp->it_name, OPLEN);
4885 		(void) strlcat(x->d86_mnem + strlen(dp->it_name),
4886 		    vreg->dgr_suffix, OPLEN - strlen(dp->it_name));
4887 #endif
4888 
4889 		dtrace_get_modrm(x, &mode, &reg, &r_m);
4890 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
4891 
4892 		dtrace_get_operand(x, REG_ONLY, reg, vreg->dgr_arg2, 2);
4893 		/*
4894 		 * VEX prefix uses the 1's complement form to encode the
4895 		 * XMM/YMM regs
4896 		 */
4897 		dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), vreg->dgr_arg0,
4898 		    0);
4899 		dtrace_get_operand(x, mode, r_m, vreg->dgr_arg1, 1);
4900 		break;
4901 
4902 	case VEX_RRX:
4903 		/* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */
4904 		x->d86_numopnds = 3;
4905 
4906 		dtrace_get_modrm(x, &mode, &reg, &r_m);
4907 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
4908 
4909 		if (mode != REG_ONLY) {
4910 			if ((dp == &dis_opAVXF20F[0x11]) ||
4911 			    (dp == &dis_opAVXF30F[0x11])) {
4912 				/* vmovsd <xmm>, <m64> */
4913 				/* or vmovss <xmm>, <m64> */
4914 				x->d86_numopnds = 2;
4915 				goto L_VEX_RM;
4916 			}
4917 		}
4918 
4919 		dtrace_get_operand(x, mode, r_m, wbit, 2);
4920 		dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
4921 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
4922 		break;
4923 
4924 	case VEX_RMRX:
4925 		/* ModR/M.reg := op(VEX.vvvv, ModR/M.r_m, imm8[7:4]) */
4926 		x->d86_numopnds = 4;
4927 
4928 		dtrace_get_modrm(x, &mode, &reg, &r_m);
4929 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
4930 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 3);
4931 		dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2);
4932 		if (dp == &dis_opAVX660F3A[0x18]) {
4933 			/* vinsertf128 <imm8>, <xmm>, <ymm>, <ymm> */
4934 			dtrace_get_operand(x, mode, r_m, XMM_OPND, 1);
4935 		} else if ((dp == &dis_opAVX660F3A[0x20]) ||
4936 		    (dp == & dis_opAVX660F[0xC4])) {
4937 			/* vpinsrb <imm8>, <reg/mm>, <xmm>, <xmm> */
4938 			/* or vpinsrw <imm8>, <reg/mm>, <xmm>, <xmm> */
4939 			dtrace_get_operand(x, mode, r_m, LONG_OPND, 1);
4940 		} else if (dp == &dis_opAVX660F3A[0x22]) {
4941 			/* vpinsrd/q <imm8>, <reg/mm>, <xmm>, <xmm> */
4942 #ifdef DIS_TEXT
4943 			if (vex_W)
4944 				x->d86_mnem[6] = 'q';
4945 #endif
4946 			dtrace_get_operand(x, mode, r_m, LONG_OPND, 1);
4947 		} else {
4948 			dtrace_get_operand(x, mode, r_m, wbit, 1);
4949 		}
4950 
4951 		/* one byte immediate number */
4952 		dtrace_imm_opnd(x, wbit, 1, 0);
4953 
4954 		/* vblendvpd, vblendvps, vblendvb use the imm encode the regs */
4955 		if ((dp == &dis_opAVX660F3A[0x4A]) ||
4956 		    (dp == &dis_opAVX660F3A[0x4B]) ||
4957 		    (dp == &dis_opAVX660F3A[0x4C])) {
4958 #ifdef DIS_TEXT
4959 			int regnum = (x->d86_opnd[0].d86_value & 0xF0) >> 4;
4960 #endif
4961 			x->d86_opnd[0].d86_mode = MODE_NONE;
4962 #ifdef DIS_TEXT
4963 			if (vex_L)
4964 				(void) strncpy(x->d86_opnd[0].d86_opnd,
4965 				    dis_YMMREG[regnum], OPLEN);
4966 			else
4967 				(void) strncpy(x->d86_opnd[0].d86_opnd,
4968 				    dis_XMMREG[regnum], OPLEN);
4969 #endif
4970 		}
4971 		break;
4972 
4973 	case VEX_MX:
4974 		/* ModR/M.reg := op(ModR/M.rm) */
4975 		x->d86_numopnds = 2;
4976 
4977 		dtrace_get_modrm(x, &mode, &reg, &r_m);
4978 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
4979 L_VEX_MX:
4980 
4981 		if ((dp == &dis_opAVXF20F[0xE6]) ||
4982 		    (dp == &dis_opAVX660F[0x5A]) ||
4983 		    (dp == &dis_opAVX660F[0xE6])) {
4984 			/* vcvtpd2dq <ymm>, <xmm> */
4985 			/* or vcvtpd2ps <ymm>, <xmm> */
4986 			/* or vcvttpd2dq <ymm>, <xmm> */
4987 			dtrace_get_operand(x, REG_ONLY, reg, XMM_OPND, 1);
4988 			dtrace_get_operand(x, mode, r_m, wbit, 0);
4989 		} else if ((dp == &dis_opAVXF30F[0xE6]) ||
4990 		    (dp == &dis_opAVX0F[0x5][0xA]) ||
4991 		    (dp == &dis_opAVX660F38[0x13]) ||
4992 		    (dp == &dis_opAVX660F38[0x18]) ||
4993 		    (dp == &dis_opAVX660F38[0x19]) ||
4994 		    (dp == &dis_opAVX660F38[0x58]) ||
4995 		    (dp == &dis_opAVX660F38[0x78]) ||
4996 		    (dp == &dis_opAVX660F38[0x79]) ||
4997 		    (dp == &dis_opAVX660F38[0x59])) {
4998 			/* vcvtdq2pd <xmm>, <ymm> */
4999 			/* or vcvtps2pd <xmm>, <ymm> */
5000 			/* or vcvtph2ps <xmm>, <ymm> */
5001 			/* or vbroadcasts* <xmm>, <ymm> */
5002 			dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5003 			dtrace_get_operand(x, mode, r_m, XMM_OPND, 0);
5004 		} else if (dp == &dis_opAVX660F[0x6E]) {
5005 			/* vmovd/q <reg/mem 32/64>, <xmm> */
5006 #ifdef DIS_TEXT
5007 			if (vex_W)
5008 				x->d86_mnem[4] = 'q';
5009 #endif
5010 			dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5011 			dtrace_get_operand(x, mode, r_m, LONG_OPND, 0);
5012 		} else {
5013 			dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5014 			dtrace_get_operand(x, mode, r_m, wbit, 0);
5015 		}
5016 
5017 		break;
5018 
5019 	case VEX_MXI:
5020 		/* ModR/M.reg := op(ModR/M.rm, imm8) */
5021 		x->d86_numopnds = 3;
5022 
5023 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5024 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5025 
5026 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
5027 		dtrace_get_operand(x, mode, r_m, wbit, 1);
5028 
5029 		/* one byte immediate number */
5030 		dtrace_imm_opnd(x, wbit, 1, 0);
5031 		break;
5032 
5033 	case VEX_XXI:
5034 		/* VEX.vvvv := op(ModR/M.rm, imm8) */
5035 		x->d86_numopnds = 3;
5036 
5037 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5038 #ifdef DIS_TEXT
5039 		(void) strncpy(x->d86_mnem, dis_AVXvgrp7[opcode2 - 1][reg],
5040 		    OPLEN);
5041 #endif
5042 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5043 
5044 		dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2);
5045 		dtrace_get_operand(x, REG_ONLY, r_m, wbit, 1);
5046 
5047 		/* one byte immediate number */
5048 		dtrace_imm_opnd(x, wbit, 1, 0);
5049 		break;
5050 
5051 	case VEX_MR:
5052 		/* ModR/M.reg (reg32/64) := op(ModR/M.rm) */
5053 		if (dp == &dis_opAVX660F[0xC5]) {
5054 			/* vpextrw <imm8>, <xmm>, <reg> */
5055 			x->d86_numopnds = 2;
5056 			vbit = 2;
5057 		} else {
5058 			x->d86_numopnds = 2;
5059 			vbit = 1;
5060 		}
5061 
5062 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5063 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5064 		dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, vbit);
5065 		dtrace_get_operand(x, mode, r_m, wbit, vbit - 1);
5066 
5067 		if (vbit == 2)
5068 			dtrace_imm_opnd(x, wbit, 1, 0);
5069 
5070 		break;
5071 
5072 	case VEX_RRI:
5073 		/* implicit(eflags/r32) := op(ModR/M.reg, ModR/M.rm) */
5074 		x->d86_numopnds = 2;
5075 
5076 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5077 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5078 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5079 		dtrace_get_operand(x, mode, r_m, wbit, 0);
5080 		break;
5081 
5082 	case VEX_RX:
5083 		/* ModR/M.rm := op(ModR/M.reg) */
5084 		/* vextractf128 || vcvtps2ph */
5085 		if (dp == &dis_opAVX660F3A[0x19] ||
5086 		    dp == &dis_opAVX660F3A[0x1d]) {
5087 			x->d86_numopnds = 3;
5088 
5089 			dtrace_get_modrm(x, &mode, &reg, &r_m);
5090 			dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5091 
5092 			dtrace_get_operand(x, mode, r_m, XMM_OPND, 2);
5093 			dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5094 
5095 			/* one byte immediate number */
5096 			dtrace_imm_opnd(x, wbit, 1, 0);
5097 			break;
5098 		}
5099 
5100 		x->d86_numopnds = 2;
5101 
5102 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5103 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5104 		dtrace_get_operand(x, mode, r_m, wbit, 1);
5105 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
5106 		break;
5107 
5108 	case VEX_RR:
5109 		/* ModR/M.rm := op(ModR/M.reg) */
5110 		x->d86_numopnds = 2;
5111 
5112 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5113 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5114 
5115 		if (dp == &dis_opAVX660F[0x7E]) {
5116 			/* vmovd/q <reg/mem 32/64>, <xmm> */
5117 #ifdef DIS_TEXT
5118 			if (vex_W)
5119 				x->d86_mnem[4] = 'q';
5120 #endif
5121 			dtrace_get_operand(x, mode, r_m, LONG_OPND, 1);
5122 		} else
5123 			dtrace_get_operand(x, mode, r_m, wbit, 1);
5124 
5125 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
5126 		break;
5127 
5128 	case VEX_RRi:
5129 		/* ModR/M.rm := op(ModR/M.reg, imm) */
5130 		x->d86_numopnds = 3;
5131 
5132 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5133 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5134 
5135 #ifdef DIS_TEXT
5136 		if (dp == &dis_opAVX660F3A[0x16]) {
5137 			/* vpextrd/q <imm>, <xmm>, <reg/mem 32/64> */
5138 			if (vex_W)
5139 				x->d86_mnem[6] = 'q';
5140 		}
5141 #endif
5142 		dtrace_get_operand(x, mode, r_m, LONG_OPND, 2);
5143 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5144 
5145 		/* one byte immediate number */
5146 		dtrace_imm_opnd(x, wbit, 1, 0);
5147 		break;
5148 	case VEX_RIM:
5149 		/* ModR/M.rm := op(ModR/M.reg, imm) */
5150 		x->d86_numopnds = 3;
5151 
5152 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5153 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5154 
5155 		dtrace_get_operand(x, mode, r_m, XMM_OPND, 2);
5156 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5157 		/* one byte immediate number */
5158 		dtrace_imm_opnd(x, wbit, 1, 0);
5159 		break;
5160 
5161 	case VEX_RM:
5162 		/* ModR/M.rm := op(ModR/M.reg) */
5163 		if (dp == &dis_opAVX660F3A[0x17]) {	/* vextractps */
5164 			x->d86_numopnds = 3;
5165 
5166 			dtrace_get_modrm(x, &mode, &reg, &r_m);
5167 			dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5168 
5169 			dtrace_get_operand(x, mode, r_m, LONG_OPND, 2);
5170 			dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5171 			/* one byte immediate number */
5172 			dtrace_imm_opnd(x, wbit, 1, 0);
5173 			break;
5174 		}
5175 		x->d86_numopnds = 2;
5176 
5177 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5178 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5179 L_VEX_RM:
5180 		vbit = 1;
5181 		dtrace_get_operand(x, mode, r_m, wbit, vbit);
5182 		dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit - 1);
5183 
5184 		break;
5185 
5186 	case VEX_RRM:
5187 		/* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */
5188 		x->d86_numopnds = 3;
5189 
5190 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5191 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5192 		dtrace_get_operand(x, mode, r_m, wbit, 2);
5193 		/* VEX use the 1's complement form encode the XMM/YMM regs */
5194 		dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
5195 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
5196 		break;
5197 
5198 	case VEX_RMX:
5199 		/* ModR/M.reg := op(VEX.vvvv, ModR/M.rm) */
5200 		x->d86_numopnds = 3;
5201 
5202 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5203 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5204 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
5205 		dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
5206 		dtrace_get_operand(x, REG_ONLY, r_m, wbit, 0);
5207 		break;
5208 
5209 	case VEX_NONE:
5210 #ifdef DIS_TEXT
5211 		if (vex_L)
5212 			(void) strncpy(x->d86_mnem, "vzeroall", OPLEN);
5213 #endif
5214 		break;
5215 	case BLS: {
5216 
5217 		/*
5218 		 * The BLS instructions are VEX instructions that are based on
5219 		 * VEX.0F38.F3; however, they are considered special group 17
5220 		 * and like everything else, they use the bits in 3-5 of the
5221 		 * MOD R/M to determine the sub instruction. Unlike many others
5222 		 * like the VMX instructions, these are valid both for memory
5223 		 * and register forms.
5224 		 */
5225 
5226 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5227 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5228 
5229 		switch (reg) {
5230 		case 1:
5231 #ifdef	DIS_TEXT
5232 			blsinstr = "blsr";
5233 #endif
5234 			break;
5235 		case 2:
5236 #ifdef	DIS_TEXT
5237 			blsinstr = "blsmsk";
5238 #endif
5239 			break;
5240 		case 3:
5241 #ifdef	DIS_TEXT
5242 			blsinstr = "blsi";
5243 #endif
5244 			break;
5245 		default:
5246 			goto error;
5247 		}
5248 
5249 		x->d86_numopnds = 2;
5250 #ifdef DIS_TEXT
5251 		(void) strncpy(x->d86_mnem, blsinstr, OPLEN);
5252 #endif
5253 		dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
5254 		dtrace_get_operand(x, mode, r_m, wbit, 0);
5255 		break;
5256 	}
5257 	/* an invalid op code */
5258 	case AM:
5259 	case DM:
5260 	case OVERRIDE:
5261 	case PREFIX:
5262 	case UNKNOWN:
5263 		NOMEM;
5264 	default:
5265 		goto error;
5266 	} /* end switch */
5267 	if (x->d86_error)
5268 		goto error;
5269 
5270 done:
5271 #ifdef DIS_MEM
5272 	/*
5273 	 * compute the size of any memory accessed by the instruction
5274 	 */
5275 	if (x->d86_memsize != 0) {
5276 		return (0);
5277 	} else if (dp->it_stackop) {
5278 		switch (opnd_size) {
5279 		case SIZE16:
5280 			x->d86_memsize = 2;
5281 			break;
5282 		case SIZE32:
5283 			x->d86_memsize = 4;
5284 			break;
5285 		case SIZE64:
5286 			x->d86_memsize = 8;
5287 			break;
5288 		}
5289 	} else if (nomem || mode == REG_ONLY) {
5290 		x->d86_memsize = 0;
5291 
5292 	} else if (dp->it_size != 0) {
5293 		/*
5294 		 * In 64 bit mode descriptor table entries
5295 		 * go up to 10 bytes and popf/pushf are always 8 bytes
5296 		 */
5297 		if (x->d86_mode == SIZE64 && dp->it_size == 6)
5298 			x->d86_memsize = 10;
5299 		else if (x->d86_mode == SIZE64 && opcode1 == 0x9 &&
5300 		    (opcode2 == 0xc || opcode2 == 0xd))
5301 			x->d86_memsize = 8;
5302 		else
5303 			x->d86_memsize = dp->it_size;
5304 
5305 	} else if (wbit == 0) {
5306 		x->d86_memsize = 1;
5307 
5308 	} else if (wbit == LONG_OPND) {
5309 		if (opnd_size == SIZE64)
5310 			x->d86_memsize = 8;
5311 		else if (opnd_size == SIZE32)
5312 			x->d86_memsize = 4;
5313 		else
5314 			x->d86_memsize = 2;
5315 
5316 	} else if (wbit == SEG_OPND) {
5317 		x->d86_memsize = 4;
5318 
5319 	} else {
5320 		x->d86_memsize = 8;
5321 	}
5322 #endif
5323 	return (0);
5324 
5325 error:
5326 #ifdef DIS_TEXT
5327 	(void) strlcat(x->d86_mnem, "undef", OPLEN);
5328 #endif
5329 	return (1);
5330 }
5331 
5332 #ifdef DIS_TEXT
5333 
5334 /*
5335  * Some instructions should have immediate operands printed
5336  * as unsigned integers. We compare against this table.
5337  */
5338 static char *unsigned_ops[] = {
5339 	"or", "and", "xor", "test", "in", "out", "lcall", "ljmp",
5340 	"rcr", "rcl", "ror", "rol", "shl", "shr", "sal", "psr", "psl",
5341 	0
5342 };
5343 
5344 
5345 static int
5346 isunsigned_op(char *opcode)
5347 {
5348 	char *where;
5349 	int i;
5350 	int is_unsigned = 0;
5351 
5352 	/*
5353 	 * Work back to start of last mnemonic, since we may have
5354 	 * prefixes on some opcodes.
5355 	 */
5356 	where = opcode + strlen(opcode) - 1;
5357 	while (where > opcode && *where != ' ')
5358 		--where;
5359 	if (*where == ' ')
5360 		++where;
5361 
5362 	for (i = 0; unsigned_ops[i]; ++i) {
5363 		if (strncmp(where, unsigned_ops[i],
5364 		    strlen(unsigned_ops[i])))
5365 			continue;
5366 		is_unsigned = 1;
5367 		break;
5368 	}
5369 	return (is_unsigned);
5370 }
5371 
5372 /*
5373  * Print a numeric immediate into end of buf, maximum length buflen.
5374  * The immediate may be an address or a displacement.  Mask is set
5375  * for address size.  If the immediate is a "small negative", or
5376  * if it's a negative displacement of any magnitude, print as -<absval>.
5377  * Respect the "octal" flag.  "Small negative" is defined as "in the
5378  * interval [NEG_LIMIT, 0)".
5379  *
5380  * Also, "isunsigned_op()" instructions never print negatives.
5381  *
5382  * Return whether we decided to print a negative value or not.
5383  */
5384 
5385 #define	NEG_LIMIT	-255
5386 enum {IMM, DISP};
5387 enum {POS, TRY_NEG};
5388 
5389 static int
5390 print_imm(dis86_t *dis, uint64_t usv, uint64_t mask, char *buf,
5391     size_t buflen, int disp, int try_neg)
5392 {
5393 	int curlen;
5394 	int64_t sv = (int64_t)usv;
5395 	int octal = dis->d86_flags & DIS_F_OCTAL;
5396 
5397 	curlen = strlen(buf);
5398 
5399 	if (try_neg == TRY_NEG && sv < 0 &&
5400 	    (disp || sv >= NEG_LIMIT) &&
5401 	    !isunsigned_op(dis->d86_mnem)) {
5402 		dis->d86_sprintf_func(buf + curlen, buflen - curlen,
5403 		    octal ? "-0%llo" : "-0x%llx", (-sv) & mask);
5404 		return (1);
5405 	} else {
5406 		if (disp == DISP)
5407 			dis->d86_sprintf_func(buf + curlen, buflen - curlen,
5408 			    octal ? "+0%llo" : "+0x%llx", usv & mask);
5409 		else
5410 			dis->d86_sprintf_func(buf + curlen, buflen - curlen,
5411 			    octal ? "0%llo" : "0x%llx", usv & mask);
5412 		return (0);
5413 
5414 	}
5415 }
5416 
5417 
5418 static int
5419 log2(int size)
5420 {
5421 	switch (size) {
5422 	case 1: return (0);
5423 	case 2: return (1);
5424 	case 4: return (2);
5425 	case 8: return (3);
5426 	}
5427 	return (0);
5428 }
5429 
5430 /* ARGSUSED */
5431 void
5432 dtrace_disx86_str(dis86_t *dis, uint_t mode, uint64_t pc, char *buf,
5433     size_t buflen)
5434 {
5435 	uint64_t reltgt = 0;
5436 	uint64_t tgt = 0;
5437 	int curlen;
5438 	int (*lookup)(void *, uint64_t, char *, size_t);
5439 	int i;
5440 	int64_t sv;
5441 	uint64_t usv, mask, save_mask, save_usv;
5442 	static uint64_t masks[] =
5443 	    {0xffU, 0xffffU, 0xffffffffU, 0xffffffffffffffffULL};
5444 	save_usv = 0;
5445 
5446 	dis->d86_sprintf_func(buf, buflen, "%-6s ", dis->d86_mnem);
5447 
5448 	/*
5449 	 * For PC-relative jumps, the pc is really the next pc after executing
5450 	 * this instruction, so increment it appropriately.
5451 	 */
5452 	pc += dis->d86_len;
5453 
5454 	for (i = 0; i < dis->d86_numopnds; i++) {
5455 		d86opnd_t *op = &dis->d86_opnd[i];
5456 
5457 		if (i != 0)
5458 			(void) strlcat(buf, ",", buflen);
5459 
5460 		(void) strlcat(buf, op->d86_prefix, buflen);
5461 
5462 		/*
5463 		 * sv is for the signed, possibly-truncated immediate or
5464 		 * displacement; usv retains the original size and
5465 		 * unsignedness for symbol lookup.
5466 		 */
5467 
5468 		sv = usv = op->d86_value;
5469 
5470 		/*
5471 		 * About masks: for immediates that represent
5472 		 * addresses, the appropriate display size is
5473 		 * the effective address size of the instruction.
5474 		 * This includes MODE_OFFSET, MODE_IPREL, and
5475 		 * MODE_RIPREL.  Immediates that are simply
5476 		 * immediate values should display in the operand's
5477 		 * size, however, since they don't represent addresses.
5478 		 */
5479 
5480 		/* d86_addr_size is SIZEnn, which is log2(real size) */
5481 		mask = masks[dis->d86_addr_size];
5482 
5483 		/* d86_value_size and d86_imm_bytes are in bytes */
5484 		if (op->d86_mode == MODE_SIGNED ||
5485 		    op->d86_mode == MODE_IMPLIED)
5486 			mask = masks[log2(op->d86_value_size)];
5487 
5488 		switch (op->d86_mode) {
5489 
5490 		case MODE_NONE:
5491 
5492 			(void) strlcat(buf, op->d86_opnd, buflen);
5493 			break;
5494 
5495 		case MODE_SIGNED:
5496 		case MODE_IMPLIED:
5497 		case MODE_OFFSET:
5498 
5499 			tgt = usv;
5500 
5501 			if (dis->d86_seg_prefix)
5502 				(void) strlcat(buf, dis->d86_seg_prefix,
5503 				    buflen);
5504 
5505 			if (op->d86_mode == MODE_SIGNED ||
5506 			    op->d86_mode == MODE_IMPLIED) {
5507 				(void) strlcat(buf, "$", buflen);
5508 			}
5509 
5510 			if (print_imm(dis, usv, mask, buf, buflen,
5511 			    IMM, TRY_NEG) &&
5512 			    (op->d86_mode == MODE_SIGNED ||
5513 			    op->d86_mode == MODE_IMPLIED)) {
5514 
5515 				/*
5516 				 * We printed a negative value for an
5517 				 * immediate that wasn't a
5518 				 * displacement.  Note that fact so we can
5519 				 * print the positive value as an
5520 				 * annotation.
5521 				 */
5522 
5523 				save_usv = usv;
5524 				save_mask = mask;
5525 			}
5526 			(void) strlcat(buf, op->d86_opnd, buflen);
5527 
5528 			break;
5529 
5530 		case MODE_IPREL:
5531 		case MODE_RIPREL:
5532 
5533 			reltgt = pc + sv;
5534 
5535 			switch (mode) {
5536 			case SIZE16:
5537 				reltgt = (uint16_t)reltgt;
5538 				break;
5539 			case SIZE32:
5540 				reltgt = (uint32_t)reltgt;
5541 				break;
5542 			}
5543 
5544 			(void) print_imm(dis, usv, mask, buf, buflen,
5545 			    DISP, TRY_NEG);
5546 
5547 			if (op->d86_mode == MODE_RIPREL)
5548 				(void) strlcat(buf, "(%rip)", buflen);
5549 			break;
5550 		}
5551 	}
5552 
5553 	/*
5554 	 * The symbol lookups may result in false positives,
5555 	 * particularly on object files, where small numbers may match
5556 	 * the 0-relative non-relocated addresses of symbols.
5557 	 */
5558 
5559 	lookup = dis->d86_sym_lookup;
5560 	if (tgt != 0) {
5561 		if ((dis->d86_flags & DIS_F_NOIMMSYM) == 0 &&
5562 		    lookup(dis->d86_data, tgt, NULL, 0) == 0) {
5563 			(void) strlcat(buf, "\t<", buflen);
5564 			curlen = strlen(buf);
5565 			lookup(dis->d86_data, tgt, buf + curlen,
5566 			    buflen - curlen);
5567 			(void) strlcat(buf, ">", buflen);
5568 		}
5569 
5570 		/*
5571 		 * If we printed a negative immediate above, print the
5572 		 * positive in case our heuristic was unhelpful
5573 		 */
5574 		if (save_usv) {
5575 			(void) strlcat(buf, "\t<", buflen);
5576 			(void) print_imm(dis, save_usv, save_mask, buf, buflen,
5577 			    IMM, POS);
5578 			(void) strlcat(buf, ">", buflen);
5579 		}
5580 	}
5581 
5582 	if (reltgt != 0) {
5583 		/* Print symbol or effective address for reltgt */
5584 
5585 		(void) strlcat(buf, "\t<", buflen);
5586 		curlen = strlen(buf);
5587 		lookup(dis->d86_data, reltgt, buf + curlen,
5588 		    buflen - curlen);
5589 		(void) strlcat(buf, ">", buflen);
5590 	}
5591 }
5592 
5593 #endif /* DIS_TEXT */
5594