1 /*
2  *
3  * CDDL HEADER START
4  *
5  * The contents of this file are subject to the terms of the
6  * Common Development and Distribution License (the "License").
7  * You may not use this file except in compliance with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
24  * Copyright 2019 Joyent, Inc.
25  * Copyright 2020 Robert Mustacchi
26  */
27 
28 /*
29  * Copyright (c) 2010, Intel Corporation.
30  * All rights reserved.
31  */
32 
33 /*	Copyright (c) 1988 AT&T	*/
34 /*	  All Rights Reserved	*/
35 
36 #include	"dis_tables.h"
37 
38 /* BEGIN CSTYLED */
39 
40 /*
41  * Disassembly begins in dis_distable, which is equivalent to the One-byte
42  * Opcode Map in the Intel IA32 ISA Reference (page A-6 in my copy).  The
43  * decoding loops then traverse out through the other tables as necessary to
44  * decode a given instruction.
45  *
46  * The behavior of this file can be controlled by one of the following flags:
47  *
48  *	DIS_TEXT	Include text for disassembly
49  *	DIS_MEM		Include memory-size calculations
50  *
51  * Either or both of these can be defined.
52  *
53  * This file is not, and will never be, cstyled.  If anything, the tables should
54  * be taken out another tab stop or two so nothing overlaps.
55  */
56 
57 /*
58  * These functions must be provided for the consumer to do disassembly.
59  */
60 #ifdef DIS_TEXT
61 extern char *strncpy(char *, const char *, size_t);
62 extern size_t strlen(const char *);
63 extern int strcmp(const char *, const char *);
64 extern int strncmp(const char *, const char *, size_t);
65 extern size_t strlcat(char *, const char *, size_t);
66 #endif
67 
68 
69 #define		TERM	0	/* used to indicate that the 'indirect' */
70 				/* field terminates - no pointer.	*/
71 
72 /* Used to decode instructions. */
73 typedef struct	instable {
74 	struct instable	*it_indirect;	/* for decode op codes */
75 	uchar_t		it_adrmode;
76 #ifdef DIS_TEXT
77 	char		it_name[NCPS];
78 	uint_t		it_suffix:1;		/* mnem + "w", "l", or "d" */
79 #endif
80 #ifdef DIS_MEM
81 	uint_t		it_size:16;
82 #endif
83 	uint_t		it_invalid64:1;		/* opcode invalid in amd64 */
84 	uint_t		it_always64:1;		/* 64 bit when in 64 bit mode */
85 	uint_t		it_invalid32:1;		/* invalid in IA32 */
86 	uint_t		it_stackop:1;		/* push/pop stack operation */
87 	uint_t		it_vexwoxmm:1;		/* VEX instructions that don't use XMM/YMM */
88 	uint_t		it_avxsuf:2;		/* AVX2/AVX512 suffix rqd. */
89 	uint_t		it_vexopmask:1;		/* VEX inst. that use opmask */
90 } instable_t;
91 
92 /*
93  * Instruction formats.
94  */
95 enum {
96 	UNKNOWN,
97 	MRw,
98 	IMlw,
99 	IMw,
100 	IR,
101 	OA,
102 	AO,
103 	MS,
104 	SM,
105 	Mv,
106 	Mw,
107 	M,		/* register or memory */
108 	MG9,		/* register or memory in group 9 (prefix optional) */
109 	Mb,		/* register or memory, always byte sized */
110 	MO,		/* memory only (no registers) */
111 	PREF,
112 	SWAPGS_RDTSCP,
113 	MONITOR_MWAIT,
114 	R,
115 	RA,
116 	SEG,
117 	MR,
118 	RM,
119 	RM_66r,		/* RM, but with a required 0x66 prefix */
120 	IA,
121 	MA,
122 	SD,
123 	AD,
124 	SA,
125 	D,
126 	INM,
127 	SO,
128 	BD,
129 	I,
130 	P,
131 	V,
132 	DSHIFT,		/* for double shift that has an 8-bit immediate */
133 	U,
134 	OVERRIDE,
135 	NORM,		/* instructions w/o ModR/M byte, no memory access */
136 	IMPLMEM,	/* instructions w/o ModR/M byte, implicit mem access */
137 	O,		/* for call	*/
138 	JTAB,		/* jump table	*/
139 	IMUL,		/* for 186 iimul instr  */
140 	CBW,		/* so data16 can be evaluated for cbw and variants */
141 	MvI,		/* for 186 logicals */
142 	ENTER,		/* for 186 enter instr  */
143 	RMw,		/* for 286 arpl instr */
144 	Ib,		/* for push immediate byte */
145 	F,		/* for 287 instructions */
146 	FF,		/* for 287 instructions */
147 	FFC,		/* for 287 instructions */
148 	DM,		/* 16-bit data */
149 	AM,		/* 16-bit addr */
150 	LSEG,		/* for 3-bit seg reg encoding */
151 	MIb,		/* for 386 logicals */
152 	SREG,		/* for 386 special registers */
153 	PREFIX,		/* a REP instruction prefix */
154 	LOCK,		/* a LOCK instruction prefix */
155 	INT3,		/* The int 3 instruction, which has a fake operand */
156 	INTx,		/* The normal int instruction, with explicit int num */
157 	DSHIFTcl,	/* for double shift that implicitly uses %cl */
158 	CWD,		/* so data16 can be evaluated for cwd and variants */
159 	RET,		/* single immediate 16-bit operand */
160 	MOVZ,		/* for movs and movz, with different size operands */
161 	CRC32,		/* for crc32, with different size operands */
162 	XADDB,		/* for xaddb */
163 	MOVSXZ,		/* AMD64 mov sign extend 32 to 64 bit instruction */
164 	MOVBE,		/* movbe instruction */
165 
166 /*
167  * MMX/SIMD addressing modes.
168  */
169 
170 	MMO,		/* Prefixable MMX/SIMD-Int	mm/mem	-> mm */
171 	MMOIMPL,	/* Prefixable MMX/SIMD-Int	mm	-> mm (mem) */
172 	MMO3P,		/* Prefixable MMX/SIMD-Int	mm	-> r32,imm8 */
173 	MMOM3,		/* Prefixable MMX/SIMD-Int	mm	-> r32	*/
174 	MMOS,		/* Prefixable MMX/SIMD-Int	mm	-> mm/mem */
175 	MMOMS,		/* Prefixable MMX/SIMD-Int	mm	-> mem */
176 	MMOPM,		/* MMX/SIMD-Int			mm/mem	-> mm,imm8 */
177 	MMOPM_66o,	/* MMX/SIMD-Int 0x66 optional	mm/mem	-> mm,imm8 */
178 	MMOPRM,		/* Prefixable MMX/SIMD-Int	r32/mem	-> mm,imm8 */
179 	MMOSH,		/* Prefixable MMX		mm,imm8	*/
180 	MM,		/* MMX/SIMD-Int			mm/mem	-> mm	*/
181 	MMS,		/* MMX/SIMD-Int			mm	-> mm/mem */
182 	MMSH,		/* MMX				mm,imm8 */
183 	XMMO,		/* Prefixable SIMD		xmm/mem	-> xmm */
184 	XMMOS,		/* Prefixable SIMD		xmm	-> xmm/mem */
185 	XMMOPM,		/* Prefixable SIMD		xmm/mem	w/to xmm,imm8 */
186 	XMMOMX,		/* Prefixable SIMD		mm/mem	-> xmm */
187 	XMMOX3,		/* Prefixable SIMD		xmm	-> r32 */
188 	XMMOXMM,	/* Prefixable SIMD		xmm/mem	-> mm	*/
189 	XMMOM,		/* Prefixable SIMD		xmm	-> mem */
190 	XMMOMS,		/* Prefixable SIMD		mem	-> xmm */
191 	XMM,		/* SIMD				xmm/mem	-> xmm */
192 	XMM_66r,	/* SIMD 0x66 prefix required	xmm/mem	-> xmm */
193 	XMM_66o,	/* SIMD 0x66 prefix optional	xmm/mem	-> xmm */
194 	XMMXIMPL,	/* SIMD				xmm	-> xmm (mem) */
195 	XMM3P,		/* SIMD				xmm	-> r32,imm8 */
196 	XMM3PM_66r,	/* SIMD 0x66 prefix required	xmm	-> r32/mem,imm8 */
197 	XMMP,		/* SIMD				xmm/mem w/to xmm,imm8 */
198 	XMMP_66o,	/* SIMD 0x66 prefix optional	xmm/mem w/to xmm,imm8 */
199 	XMMP_66r,	/* SIMD 0x66 prefix required	xmm/mem w/to xmm,imm8 */
200 	XMMPRM,		/* SIMD				r32/mem -> xmm,imm8 */
201 	XMMPRM_66r,	/* SIMD 0x66 prefix required	r32/mem -> xmm,imm8 */
202 	XMMS,		/* SIMD				xmm	-> xmm/mem */
203 	XMMM,		/* SIMD				mem	-> xmm */
204 	XMMM_66r,	/* SIMD	0x66 prefix required	mem	-> xmm */
205 	XMMMS,		/* SIMD				xmm	-> mem */
206 	XMM3MX,		/* SIMD				r32/mem -> xmm */
207 	XMM3MXS,	/* SIMD				xmm	-> r32/mem */
208 	XMMSH,		/* SIMD				xmm,imm8 */
209 	XMMXM3,		/* SIMD				xmm/mem -> r32 */
210 	XMMX3,		/* SIMD				xmm	-> r32 */
211 	XMMXMM,		/* SIMD				xmm/mem	-> mm */
212 	XMMMX,		/* SIMD				mm	-> xmm */
213 	XMMXM,		/* SIMD				xmm	-> mm */
214 	XMMX2I,		/* SIMD				xmm -> xmm, imm, imm */
215 	XMM2I,		/* SIMD				xmm, imm, imm */
216 	XMMFENCE,	/* SIMD lfence or mfence */
217 	XMMSFNC,	/* SIMD sfence (none or mem) */
218 	FSGS,		/* FSGSBASE if reg */
219 	XGETBV_XSETBV,
220 	VEX_NONE,	/* VEX  no operand */
221 	VEX_MO,		/* VEX	mod_rm		               -> implicit reg */
222 	VEX_RMrX,	/* VEX  VEX.vvvv, mod_rm               -> mod_reg */
223 	VEX_VRMrX,	/* VEX  mod_rm, VEX.vvvv               -> mod_rm */
224 	VEX_RRX,	/* VEX  VEX.vvvv, mod_reg              -> mod_rm */
225 	VEX_RMRX,	/* VEX  VEX.vvvv, mod_rm, imm8[7:4]    -> mod_reg */
226 	VEX_MX,		/* VEX  mod_rm                         -> mod_reg */
227 	VEX_MXI,	/* VEX  mod_rm, imm8                   -> mod_reg */
228 	VEX_XXI,	/* VEX  mod_rm, imm8                   -> VEX.vvvv */
229 	VEX_MR,		/* VEX  mod_rm                         -> mod_reg */
230 	VEX_RRI,	/* VEX  mod_reg, mod_rm                -> implicit(eflags/r32) */
231 	VEX_RX,		/* VEX  mod_reg                        -> mod_rm */
232 	VEX_KRR,	/* VEX  mod_rm                         -> mod_reg */
233 	VEX_KMR,	/* VEX  mod_reg                        -> mod_rm */
234 	VEX_KRM,	/* VEX  mod_rm                         -> mod_reg */
235 	VEX_RR,		/* VEX  mod_rm                         -> mod_reg */
236 	VEX_RRi,	/* VEX  mod_rm, imm8                   -> mod_reg */
237 	VEX_RM,		/* VEX  mod_reg                        -> mod_rm */
238 	VEX_RIM,	/* VEX  mod_reg, imm8                  -> mod_rm */
239 	VEX_RRM,	/* VEX  VEX.vvvv, mod_reg              -> mod_rm */
240 	VEX_RMX,	/* VEX  VEX.vvvv, mod_rm               -> mod_reg */
241 	VEX_SbVM,	/* VEX  SIB, VEX.vvvv                  -> mod_rm */
242 	VMx,		/* vmcall/vmlaunch/vmresume/vmxoff */
243 	VMxo,		/* VMx instruction with optional prefix */
244 	SVM,		/* AMD SVM instructions */
245 	BLS,		/* BLSR, BLSMSK, BLSI */
246 	FMA,		/* FMA instructions, all VEX_RMrX */
247 	ADX,		/* ADX instructions, support REX.w, mod_rm->mod_reg */
248 	EVEX_RX,	/* EVEX  mod_reg                      -> mod_rm */
249 	EVEX_MX,	/* EVEX  mod_rm                       -> mod_reg */
250 	EVEX_RMrX,	/* EVEX  EVEX.vvvv, mod_rm            -> mod_reg */
251 	EVEX_RMRX	/* EVEX  EVEX.vvvv, mod_rm, imm8      -> mod_reg */
252 };
253 
254 /*
255  * VEX prefixes
256  */
257 #define VEX_2bytes	0xC5	/* the first byte of two-byte form */
258 #define VEX_3bytes	0xC4	/* the first byte of three-byte form */
259 
260 #define	FILL	0x90	/* Fill byte used for alignment (nop)	*/
261 
262 /*
263 ** Register numbers for the i386
264 */
265 #define	EAX_REGNO 0
266 #define	ECX_REGNO 1
267 #define	EDX_REGNO 2
268 #define	EBX_REGNO 3
269 #define	ESP_REGNO 4
270 #define	EBP_REGNO 5
271 #define	ESI_REGNO 6
272 #define	EDI_REGNO 7
273 
274 /*
275  * modes for immediate values
276  */
277 #define	MODE_NONE	0
278 #define	MODE_IPREL	1	/* signed IP relative value */
279 #define	MODE_SIGNED	2	/* sign extended immediate */
280 #define	MODE_IMPLIED	3	/* constant value implied from opcode */
281 #define	MODE_OFFSET	4	/* offset part of an address */
282 #define	MODE_RIPREL	5	/* like IPREL, but from %rip (amd64) */
283 
284 /*
285  * The letters used in these macros are:
286  *   IND - indirect to another to another table
287  *   "T" - means to Terminate indirections (this is the final opcode)
288  *   "S" - means "operand length suffix required"
289  *   "Sa" - means AVX2 suffix (q/d) required
290  *   "Sq" - means AVX512 suffix (q/d) required
291  *   "Sd" - means AVX512 suffix (d/s) required
292  *   "NS" - means "no suffix" which is the operand length suffix of the opcode
293  *   "Z" - means instruction size arg required
294  *   "u" - means the opcode is invalid in IA32 but valid in amd64
295  *   "x" - means the opcode is invalid in amd64, but not IA32
296  *   "y" - means the operand size is always 64 bits in 64 bit mode
297  *   "p" - means push/pop stack operation
298  *   "vr" - means VEX instruction that operates on normal registers, not fpu
299  *   "vo" - means VEX instruction that operates on opmask registers, not fpu
300  */
301 
302 #define	AVS2	(uint_t)1	/* it_avxsuf: AVX2 q/d suffix handling */
303 #define	AVS5Q	(uint_t)2	/* it_avxsuf: AVX512 q/d suffix handling */
304 #define	AVS5D	(uint_t)3	/* it_avxsuf: AVX512 d/s suffix handling */
305 
306 #if defined(DIS_TEXT) && defined(DIS_MEM)
307 #define	IND(table)		{(instable_t *)table, 0, "", 0, 0, 0, 0, 0, 0}
308 #define	INDx(table)		{(instable_t *)table, 0, "", 0, 0, 1, 0, 0, 0}
309 #define	TNS(name, amode)	{TERM, amode, name, 0, 0, 0, 0, 0, 0}
310 #define	TNSu(name, amode)	{TERM, amode, name, 0, 0, 0, 0, 1, 0}
311 #define	TNSx(name, amode)	{TERM, amode, name, 0, 0, 1, 0, 0, 0}
312 #define	TNSy(name, amode)	{TERM, amode, name, 0, 0, 0, 1, 0, 0}
313 #define	TNSyp(name, amode)	{TERM, amode, name, 0, 0, 0, 1, 0, 1}
314 #define	TNSZ(name, amode, sz)	{TERM, amode, name, 0, sz, 0, 0, 0, 0}
315 #define	TNSZy(name, amode, sz)	{TERM, amode, name, 0, sz, 0, 1, 0, 0}
316 #define	TNSZvr(name, amode, sz)	{TERM, amode, name, 0, sz, 0, 0, 0, 0, 1}
317 #define	TSvo(name, amode)	{TERM, amode, name, 1,  0, 0, 0, 0, 0, 0, 0, 1}
318 #define	TS(name, amode)		{TERM, amode, name, 1, 0, 0, 0, 0, 0}
319 #define	TSx(name, amode)	{TERM, amode, name, 1, 0, 1, 0, 0, 0}
320 #define	TSy(name, amode)	{TERM, amode, name, 1, 0, 0, 1, 0, 0}
321 #define	TSp(name, amode)	{TERM, amode, name, 1, 0, 0, 0, 0, 1}
322 #define	TSZ(name, amode, sz)	{TERM, amode, name, 1, sz, 0, 0, 0, 0}
323 #define	TSaZ(name, amode, sz)	{TERM, amode, name, 1, sz, 0, 0, 0, 0, 0, AVS2}
324 #define	TSq(name, amode)	{TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, AVS5Q}
325 #define	TSd(name, amode)	{TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, AVS5D}
326 #define	TSZx(name, amode, sz)	{TERM, amode, name, 1, sz, 1, 0, 0, 0}
327 #define	TSZy(name, amode, sz)	{TERM, amode, name, 1, sz, 0, 1, 0, 0}
328 #define	INVALID			{TERM, UNKNOWN, "", 0, 0, 0, 0, 0}
329 #elif defined(DIS_TEXT)
330 #define	IND(table)		{(instable_t *)table, 0, "", 0, 0, 0, 0, 0}
331 #define	INDx(table)		{(instable_t *)table, 0, "", 0, 1, 0, 0, 0}
332 #define	TNS(name, amode)	{TERM, amode, name, 0, 0, 0, 0, 0}
333 #define	TNSu(name, amode)	{TERM, amode, name, 0, 0, 0, 1, 0}
334 #define	TNSx(name, amode)	{TERM, amode, name, 0, 1, 0, 0, 0}
335 #define	TNSy(name, amode)	{TERM, amode, name, 0, 0, 1, 0, 0}
336 #define	TNSyp(name, amode)	{TERM, amode, name, 0, 0, 1, 0, 1}
337 #define	TNSZ(name, amode, sz)	{TERM, amode, name, 0, 0, 0, 0, 0}
338 #define	TNSZy(name, amode, sz)	{TERM, amode, name, 0, 0, 1, 0, 0}
339 #define	TNSZvr(name, amode, sz)	{TERM, amode, name, 0, 0, 0, 0, 0, 1}
340 #define	TSvo(name, amode)	{TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 1}
341 #define	TS(name, amode)		{TERM, amode, name, 1, 0, 0, 0, 0}
342 #define	TSx(name, amode)	{TERM, amode, name, 1, 1, 0, 0, 0}
343 #define	TSy(name, amode)	{TERM, amode, name, 1, 0, 1, 0, 0}
344 #define	TSp(name, amode)	{TERM, amode, name, 1, 0, 0, 0, 1}
345 #define	TSZ(name, amode, sz)	{TERM, amode, name, 1, 0, 0, 0, 0}
346 #define	TSaZ(name, amode, sz)	{TERM, amode, name, 1, 0, 0, 0, 0, 0, AVS2}
347 #define	TSq(name, amode)	{TERM, amode, name, 0, 0, 0, 0, 0, 0, AVS5Q}
348 #define	TSZx(name, amode, sz)	{TERM, amode, name, 1, 1, 0, 0, 0}
349 #define	TSZy(name, amode, sz)	{TERM, amode, name, 1, 0, 1, 0, 0}
350 #define	INVALID			{TERM, UNKNOWN, "", 0, 0, 0, 0, 0}
351 #elif defined(DIS_MEM)
352 #define	IND(table)		{(instable_t *)table, 0, 0, 0, 0, 0, 0}
353 #define	INDx(table)		{(instable_t *)table, 0, 0, 1, 0, 0, 0}
354 #define	TNS(name, amode)	{TERM, amode,  0, 0, 0, 0, 0}
355 #define	TNSu(name, amode)	{TERM, amode,  0, 0, 0, 1, 0}
356 #define	TNSy(name, amode)	{TERM, amode,  0, 0, 1, 0, 0}
357 #define	TNSyp(name, amode)	{TERM, amode,  0, 0, 1, 0, 1}
358 #define	TNSx(name, amode)	{TERM, amode,  0, 1, 0, 0, 0}
359 #define	TNSZ(name, amode, sz)	{TERM, amode, sz, 0, 0, 0, 0}
360 #define	TNSZy(name, amode, sz)	{TERM, amode, sz, 0, 1, 0, 0}
361 #define	TNSZvr(name, amode, sz)	{TERM, amode, sz, 0, 0, 0, 0, 1}
362 #define	TSvo(name, amode)	{TERM, amode,  0, 0, 0, 0, 0, 0, 0, 1}
363 #define	TS(name, amode)		{TERM, amode,  0, 0, 0, 0, 0}
364 #define	TSx(name, amode)	{TERM, amode,  0, 1, 0, 0, 0}
365 #define	TSy(name, amode)	{TERM, amode,  0, 0, 1, 0, 0}
366 #define	TSp(name, amode)	{TERM, amode,  0, 0, 0, 0, 1}
367 #define	TSZ(name, amode, sz)	{TERM, amode, sz, 0, 0, 0, 0}
368 #define	TSaZ(name, amode, sz)	{TERM, amode, sz, 0, 0, 0, 0, 0, AVS2}
369 #define	TSq(name, amode)	{TERM, amode, 0, 0, 0, 0, 0, 0, AVS5Q}
370 #define	TSZx(name, amode, sz)	{TERM, amode, sz, 1, 0, 0, 0}
371 #define	TSZy(name, amode, sz)	{TERM, amode, sz, 0, 1, 0, 0}
372 #define	INVALID			{TERM, UNKNOWN, 0, 0, 0, 0, 0}
373 #else
374 #define	IND(table)		{(instable_t *)table, 0, 0, 0, 0, 0}
375 #define	INDx(table)		{(instable_t *)table, 0, 1, 0, 0, 0}
376 #define	TNS(name, amode)	{TERM, amode,  0, 0, 0, 0}
377 #define	TNSu(name, amode)	{TERM, amode,  0, 0, 1, 0}
378 #define	TNSy(name, amode)	{TERM, amode,  0, 1, 0, 0}
379 #define	TNSyp(name, amode)	{TERM, amode,  0, 1, 0, 1}
380 #define	TNSx(name, amode)	{TERM, amode,  1, 0, 0, 0}
381 #define	TNSZ(name, amode, sz)	{TERM, amode,  0, 0, 0, 0}
382 #define	TNSZy(name, amode, sz)	{TERM, amode,  0, 1, 0, 0}
383 #define	TNSZvr(name, amode, sz)	{TERM, amode,  0, 0, 0, 0, 1}
384 #define	TSvo(name, amode)	{TERM, amode,  0, 0, 0, 0, 0, 0, 1}
385 #define	TS(name, amode)		{TERM, amode,  0, 0, 0, 0}
386 #define	TSx(name, amode)	{TERM, amode,  1, 0, 0, 0}
387 #define	TSy(name, amode)	{TERM, amode,  0, 1, 0, 0}
388 #define	TSp(name, amode)	{TERM, amode,  0, 0, 0, 1}
389 #define	TSZ(name, amode, sz)	{TERM, amode,  0, 0, 0, 0}
390 #define	TSaZ(name, amode, sz)	{TERM, amode,  0, 0, 0, 0, 0, AVS2}
391 #define	TSq(name, amode)	{TERM, amode,  0, 0, 0, 0, 0, AVS5Q}
392 #define	TSd(name, amode)	{TERM, amode,  0, 0, 0, 0, 0, AVS5D}
393 #define	TSZx(name, amode, sz)	{TERM, amode,  1, 0, 0, 0}
394 #define	TSZy(name, amode, sz)	{TERM, amode,  0, 1, 0, 0}
395 #define	INVALID			{TERM, UNKNOWN, 0, 0, 0, 0}
396 #endif
397 
398 #ifdef DIS_TEXT
399 /*
400  * this decodes the r_m field for mode's 0, 1, 2 in 16 bit mode
401  */
402 const char *const dis_addr16[3][8] = {
403 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "",
404 									"(%bx)",
405 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di", "(%bp)",
406 									"(%bx)",
407 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "(%bp)",
408 									"(%bx)",
409 };
410 
411 
412 /*
413  * This decodes 32 bit addressing mode r_m field for modes 0, 1, 2
414  */
415 const char *const dis_addr32_mode0[16] = {
416   "(%eax)", "(%ecx)", "(%edx)",  "(%ebx)",  "", "",        "(%esi)",  "(%edi)",
417   "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "",        "(%r14d)", "(%r15d)"
418 };
419 
420 const char *const dis_addr32_mode12[16] = {
421   "(%eax)", "(%ecx)", "(%edx)",  "(%ebx)",  "", "(%ebp)",  "(%esi)",  "(%edi)",
422   "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "(%r13d)", "(%r14d)", "(%r15d)"
423 };
424 
425 /*
426  * This decodes 64 bit addressing mode r_m field for modes 0, 1, 2
427  */
428 const char *const dis_addr64_mode0[16] = {
429  "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "",       "(%rip)", "(%rsi)", "(%rdi)",
430  "(%r8)",  "(%r9)",  "(%r10)", "(%r11)", "(%r12)", "(%rip)", "(%r14)", "(%r15)"
431 };
432 const char *const dis_addr64_mode12[16] = {
433  "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "",       "(%rbp)", "(%rsi)", "(%rdi)",
434  "(%r8)",  "(%r9)",  "(%r10)", "(%r11)", "(%r12)", "(%r13)", "(%r14)", "(%r15)"
435 };
436 
437 /*
438  * decode for scale from SIB byte
439  */
440 const char *const dis_scale_factor[4] = { ")", ",2)", ",4)", ",8)" };
441 
442 /*
443  * decode for scale from VSIB byte, note that we always include the scale factor
444  * to match gas.
445  */
446 const char *const dis_vscale_factor[4] = { ",1)", ",2)", ",4)", ",8)" };
447 
448 /*
449  * register decoding for normal references to registers (ie. not addressing)
450  */
451 const char *const dis_REG8[16] = {
452 	"%al",  "%cl",  "%dl",   "%bl",   "%ah",   "%ch",   "%dh",   "%bh",
453 	"%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
454 };
455 
456 const char *const dis_REG8_REX[16] = {
457 	"%al",  "%cl",  "%dl",   "%bl",   "%spl",  "%bpl",  "%sil",  "%dil",
458 	"%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
459 };
460 
461 const char *const dis_REG16[16] = {
462 	"%ax",  "%cx",  "%dx",   "%bx",   "%sp",   "%bp",   "%si",   "%di",
463 	"%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
464 };
465 
466 const char *const dis_REG32[16] = {
467 	"%eax", "%ecx", "%edx",  "%ebx",  "%esp",  "%ebp",  "%esi",  "%edi",
468 	"%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
469 };
470 
471 const char *const dis_REG64[16] = {
472 	"%rax", "%rcx", "%rdx",  "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
473 	"%r8",  "%r9",  "%r10",  "%r11", "%r12", "%r13", "%r14", "%r15"
474 };
475 
476 const char *const dis_DEBUGREG[16] = {
477 	"%db0", "%db1", "%db2",  "%db3",  "%db4",  "%db5",  "%db6",  "%db7",
478 	"%db8", "%db9", "%db10", "%db11", "%db12", "%db13", "%db14", "%db15"
479 };
480 
481 const char *const dis_CONTROLREG[16] = {
482     "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5?", "%cr6?", "%cr7?",
483     "%cr8", "%cr9?", "%cr10?", "%cr11?", "%cr12?", "%cr13?", "%cr14?", "%cr15?"
484 };
485 
486 const char *const dis_TESTREG[16] = {
487 	"%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7",
488 	"%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7"
489 };
490 
491 const char *const dis_MMREG[16] = {
492 	"%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7",
493 	"%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7"
494 };
495 
496 const char *const dis_XMMREG[32] = {
497     "%xmm0", "%xmm1", "%xmm2", "%xmm3",
498     "%xmm4", "%xmm5", "%xmm6", "%xmm7",
499     "%xmm8", "%xmm9", "%xmm10", "%xmm11",
500     "%xmm12", "%xmm13", "%xmm14", "%xmm15",
501     "%xmm16", "%xmm17", "%xmm18", "%xmm19",
502     "%xmm20", "%xmm21", "%xmm22", "%xmm23",
503     "%xmm24", "%xmm25", "%xmm26", "%xmm27",
504     "%xmm28", "%xmm29", "%xmm30", "%xmm31",
505 };
506 
507 const char *const dis_YMMREG[32] = {
508     "%ymm0", "%ymm1", "%ymm2", "%ymm3",
509     "%ymm4", "%ymm5", "%ymm6", "%ymm7",
510     "%ymm8", "%ymm9", "%ymm10", "%ymm11",
511     "%ymm12", "%ymm13", "%ymm14", "%ymm15",
512     "%ymm16", "%ymm17", "%ymm18", "%ymm19",
513     "%ymm20", "%ymm21", "%ymm22", "%ymm23",
514     "%ymm24", "%ymm25", "%ymm26", "%ymm27",
515     "%ymm28", "%ymm29", "%ymm30", "%ymm31",
516 };
517 
518 const char *const dis_ZMMREG[32] = {
519     "%zmm0", "%zmm1", "%zmm2", "%zmm3",
520     "%zmm4", "%zmm5", "%zmm6", "%zmm7",
521     "%zmm8", "%zmm9", "%zmm10", "%zmm11",
522     "%zmm12", "%zmm13", "%zmm14", "%zmm15",
523     "%zmm16", "%zmm17", "%zmm18", "%zmm19",
524     "%zmm20", "%zmm21", "%zmm22", "%zmm23",
525     "%zmm24", "%zmm25", "%zmm26", "%zmm27",
526     "%zmm28", "%zmm29", "%zmm30", "%zmm31",
527 };
528 
529 const char *const dis_KOPMASKREG[8] = {
530     "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
531 };
532 
533 const char *const dis_SEGREG[16] = {
534 	"%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>",
535 	"%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>"
536 };
537 
538 /*
539  * SIMD predicate suffixes
540  */
541 const char *const dis_PREDSUFFIX[8] = {
542 	"eq", "lt", "le", "unord", "neq", "nlt", "nle", "ord"
543 };
544 
545 const char *const dis_AVXvgrp7[3][8] = {
546 	/*0	1	2		3		4		5	6		7*/
547 /*71*/	{"",	"",	"vpsrlw",	"",		"vpsraw",	"",	"vpsllw",	""},
548 /*72*/	{"",	"",	"vpsrld",	"",		"vpsrad",	"",	"vpslld",	""},
549 /*73*/	{"",	"",	"vpsrlq",	"vpsrldq",	"",		"",	"vpsllq",	"vpslldq"}
550 };
551 
552 #endif	/* DIS_TEXT */
553 
554 /*
555  *	"decode table" for 64 bit mode MOVSXD instruction (opcode 0x63)
556  */
557 const instable_t dis_opMOVSLD = TNS("movslq",MOVSXZ);
558 
559 /*
560  *	"decode table" for pause and clflush instructions
561  */
562 const instable_t dis_opPause = TNS("pause", NORM);
563 
564 /*
565  *	"decode table" for wbnoinvd instruction
566  */
567 const instable_t dis_opWbnoinvd = TNS("wbnoinvd", NORM);
568 
569 /*
570  *	Decode table for 0x0F00 opcodes
571  */
572 const instable_t dis_op0F00[8] = {
573 
574 /*  [0]  */	TNS("sldt",M),		TNS("str",M),		TNSy("lldt",M),		TNSy("ltr",M),
575 /*  [4]  */	TNSZ("verr",M,2),	TNSZ("verw",M,2),	INVALID,		INVALID,
576 };
577 
578 
579 /*
580  *	Decode table for 0x0F01 opcodes
581  */
582 const instable_t dis_op0F01[8] = {
583 
584 /*  [0]  */	TNSZ("sgdt",VMx,6),	TNSZ("sidt",MONITOR_MWAIT,6),	TNSZ("lgdt",XGETBV_XSETBV,6),	TNSZ("lidt",SVM,6),
585 /*  [4]  */	TNSZ("smsw",M,2),	INVALID,		TNSZ("lmsw",M,2),	TNS("invlpg",SWAPGS_RDTSCP),
586 };
587 
588 /*
589  *	Decode table for 0x0F18 opcodes -- SIMD prefetch
590  */
591 const instable_t dis_op0F18[8] = {
592 
593 /*  [0]  */	TNS("prefetchnta",PREF),TNS("prefetcht0",PREF),	TNS("prefetcht1",PREF),	TNS("prefetcht2",PREF),
594 /*  [4]  */	INVALID,		INVALID,		INVALID,		INVALID,
595 };
596 
597 /*
598  *	Decode table for 0x0FAE opcodes -- SIMD state save/restore
599  */
600 const instable_t dis_op0FAE[8] = {
601 /*  [0]  */	TNSZ("fxsave",FSGS,512),TNSZ("fxrstor",FSGS,512),TNS("ldmxcsr",FSGS),	TNS("stmxcsr",FSGS),
602 /*  [4]  */	TNSZ("xsave",M,512),	TNS("lfence",XMMFENCE), TNS("mfence",XMMFENCE),	TNS("sfence",XMMSFNC),
603 };
604 
605 /*
606  *	Decode table for 0xF30FAE opcodes -- FSGSBASE
607  */
608 const instable_t dis_opF30FAE[8] = {
609 /*  [0]  */	TNSx("rdfsbase",FSGS),	TNSx("rdgsbase",FSGS),	TNSx("wrfsbase",FSGS),	TNSx("wrgsbase",FSGS),
610 /*  [4]  */	INVALID,		INVALID,		INVALID,		INVALID,
611 };
612 
613 /*
614  *	Decode table for 0x0FBA opcodes
615  */
616 
617 const instable_t dis_op0FBA[8] = {
618 
619 /*  [0]  */	INVALID,		INVALID,		INVALID,		INVALID,
620 /*  [4]  */	TS("bt",MIb),		TS("bts",MIb),		TS("btr",MIb),		TS("btc",MIb),
621 };
622 
623 /*
624  *	Decode table for 0x0FC7 opcode (group 9)
625  */
626 
627 const instable_t dis_op0FC7[8] = {
628 
629 /*  [0]  */	INVALID,		TNS("cmpxchg8b",M),	INVALID,		TNS("xrstors",MG9),
630 /*  [4]  */	TNS("xsavec",MG9),	TNS("xsaves",MG9),		TNS("vmptrld",MG9),	TNS("vmptrst",MG9),
631 };
632 
633 /*
634  *	Decode table for 0x0FC7 opcode (group 9) mode 3
635  */
636 
637 const instable_t dis_op0FC7m3[8] = {
638 
639 /*  [0]  */	INVALID,		INVALID,	INVALID,		INVALID,
640 /*  [4]  */	INVALID,		INVALID,	TNS("rdrand",MG9),	TNS("rdseed", MG9),
641 };
642 
643 /*
644  *	Decode table for 0x0FC7 opcode with 0x66 prefix
645  */
646 
647 const instable_t dis_op660FC7[8] = {
648 
649 /*  [0]  */	INVALID,		INVALID,		INVALID,		INVALID,
650 /*  [4]  */	INVALID,		INVALID,		TNS("vmclear",M),	INVALID,
651 };
652 
653 /*
654  *	Decode table for 0x0FC7 opcode with 0xF3 prefix
655  */
656 
657 const instable_t dis_opF30FC7[8] = {
658 
659 /*  [0]  */	INVALID,		INVALID,		INVALID,		INVALID,
660 /*  [4]  */	INVALID,		INVALID,		TNS("vmxon",M),		INVALID,
661 };
662 
663 /*
664  *	Decode table for 0x0FC8 opcode -- 486 bswap instruction
665  *
666  *bit pattern: 0000 1111 1100 1reg
667  */
668 const instable_t dis_op0FC8[4] = {
669 /*  [0]  */	TNS("bswap",R),		INVALID,		INVALID,		INVALID,
670 };
671 
672 /*
673  *	Decode table for 0x0F71, 0x0F72, and 0x0F73 opcodes -- MMX instructions
674  */
675 const instable_t dis_op0F7123[4][8] = {
676 {
677 /*  [70].0 */	INVALID,		INVALID,		INVALID,		INVALID,
678 /*      .4 */	INVALID,		INVALID,		INVALID,		INVALID,
679 }, {
680 /*  [71].0 */	INVALID,		INVALID,		TNS("psrlw",MMOSH),	INVALID,
681 /*      .4 */	TNS("psraw",MMOSH),	INVALID,		TNS("psllw",MMOSH),	INVALID,
682 }, {
683 /*  [72].0 */	INVALID,		INVALID,		TNS("psrld",MMOSH),	INVALID,
684 /*      .4 */	TNS("psrad",MMOSH),	INVALID,		TNS("pslld",MMOSH),	INVALID,
685 }, {
686 /*  [73].0 */	INVALID,		INVALID,		TNS("psrlq",MMOSH),	TNS("INVALID",MMOSH),
687 /*      .4 */	INVALID,		INVALID,		TNS("psllq",MMOSH),	TNS("INVALID",MMOSH),
688 } };
689 
690 /*
691  *	Decode table for SIMD extensions to above 0x0F71-0x0F73 opcodes.
692  */
693 const instable_t dis_opSIMD7123[32] = {
694 /* [70].0 */	INVALID,		INVALID,		INVALID,		INVALID,
695 /*     .4 */	INVALID,		INVALID,		INVALID,		INVALID,
696 
697 /* [71].0 */	INVALID,		INVALID,		TNS("psrlw",XMMSH),	INVALID,
698 /*     .4 */	TNS("psraw",XMMSH),	INVALID,		TNS("psllw",XMMSH),	INVALID,
699 
700 /* [72].0 */	INVALID,		INVALID,		TNS("psrld",XMMSH),	INVALID,
701 /*     .4 */	TNS("psrad",XMMSH),	INVALID,		TNS("pslld",XMMSH),	INVALID,
702 
703 /* [73].0 */	INVALID,		INVALID,		TNS("psrlq",XMMSH),	TNS("psrldq",XMMSH),
704 /*     .4 */	INVALID,		INVALID,		TNS("psllq",XMMSH),	TNS("pslldq",XMMSH),
705 };
706 
707 /*
708  *	SIMD instructions have been wedged into the existing IA32 instruction
709  *	set through the use of prefixes.  That is, while 0xf0 0x58 may be
710  *	addps, 0xf3 0xf0 0x58 (literally, repz addps) is a completely different
711  *	instruction - addss.  At present, three prefixes have been coopted in
712  *	this manner - address size (0x66), repnz (0xf2) and repz (0xf3).  The
713  *	following tables are used to provide the prefixed instruction names.
714  *	The arrays are sparse, but they're fast.
715  */
716 
717 /*
718  *	Decode table for SIMD instructions with the address size (0x66) prefix.
719  */
720 const instable_t dis_opSIMDdata16[256] = {
721 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
722 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
723 /*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
724 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
725 
726 /*  [10]  */	TNSZ("movupd",XMM,16),	TNSZ("movupd",XMMS,16),	TNSZ("movlpd",XMMM,8),	TNSZ("movlpd",XMMMS,8),
727 /*  [14]  */	TNSZ("unpcklpd",XMM,16),TNSZ("unpckhpd",XMM,16),TNSZ("movhpd",XMMM,8),	TNSZ("movhpd",XMMMS,8),
728 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
729 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
730 
731 /*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
732 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
733 /*  [28]  */	TNSZ("movapd",XMM,16),	TNSZ("movapd",XMMS,16),	TNSZ("cvtpi2pd",XMMOMX,8),TNSZ("movntpd",XMMOMS,16),
734 /*  [2C]  */	TNSZ("cvttpd2pi",XMMXMM,16),TNSZ("cvtpd2pi",XMMXMM,16),TNSZ("ucomisd",XMM,8),TNSZ("comisd",XMM,8),
735 
736 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
737 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
738 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
739 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
740 
741 /*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
742 /*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
743 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
744 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
745 
746 /*  [50]  */	TNS("movmskpd",XMMOX3),	TNSZ("sqrtpd",XMM,16),	INVALID,		INVALID,
747 /*  [54]  */	TNSZ("andpd",XMM,16),	TNSZ("andnpd",XMM,16),	TNSZ("orpd",XMM,16),	TNSZ("xorpd",XMM,16),
748 /*  [58]  */	TNSZ("addpd",XMM,16),	TNSZ("mulpd",XMM,16),	TNSZ("cvtpd2ps",XMM,16),TNSZ("cvtps2dq",XMM,16),
749 /*  [5C]  */	TNSZ("subpd",XMM,16),	TNSZ("minpd",XMM,16),	TNSZ("divpd",XMM,16),	TNSZ("maxpd",XMM,16),
750 
751 /*  [60]  */	TNSZ("punpcklbw",XMM,16),TNSZ("punpcklwd",XMM,16),TNSZ("punpckldq",XMM,16),TNSZ("packsswb",XMM,16),
752 /*  [64]  */	TNSZ("pcmpgtb",XMM,16),	TNSZ("pcmpgtw",XMM,16),	TNSZ("pcmpgtd",XMM,16),	TNSZ("packuswb",XMM,16),
753 /*  [68]  */	TNSZ("punpckhbw",XMM,16),TNSZ("punpckhwd",XMM,16),TNSZ("punpckhdq",XMM,16),TNSZ("packssdw",XMM,16),
754 /*  [6C]  */	TNSZ("punpcklqdq",XMM,16),TNSZ("punpckhqdq",XMM,16),TNSZ("movd",XMM3MX,4),TNSZ("movdqa",XMM,16),
755 
756 /*  [70]  */	TNSZ("pshufd",XMMP,16),	INVALID,		INVALID,		INVALID,
757 /*  [74]  */	TNSZ("pcmpeqb",XMM,16),	TNSZ("pcmpeqw",XMM,16),	TNSZ("pcmpeqd",XMM,16),	INVALID,
758 /*  [78]  */	TNSZ("extrq",XMM2I,16),	TNSZ("extrq",XMM,16), INVALID,		INVALID,
759 /*  [7C]  */	TNSZ("haddpd",XMM,16),	TNSZ("hsubpd",XMM,16),	TNSZ("movd",XMM3MXS,4),	TNSZ("movdqa",XMMS,16),
760 
761 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
762 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
763 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
764 /*  [8C]  */	INVALID,		INVALID,		INVALID,		INVALID,
765 
766 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
767 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
768 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
769 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
770 
771 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
772 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
773 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
774 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
775 
776 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
777 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
778 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
779 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
780 
781 /*  [C0]  */	INVALID,		INVALID,		TNSZ("cmppd",XMMP,16),	INVALID,
782 /*  [C4]  */	TNSZ("pinsrw",XMMPRM,2),TNS("pextrw",XMM3P),	TNSZ("shufpd",XMMP,16),	INVALID,
783 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
784 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
785 
786 /*  [D0]  */	TNSZ("addsubpd",XMM,16),TNSZ("psrlw",XMM,16),	TNSZ("psrld",XMM,16),	TNSZ("psrlq",XMM,16),
787 /*  [D4]  */	TNSZ("paddq",XMM,16),	TNSZ("pmullw",XMM,16),	TNSZ("movq",XMMS,8),	TNS("pmovmskb",XMMX3),
788 /*  [D8]  */	TNSZ("psubusb",XMM,16),	TNSZ("psubusw",XMM,16),	TNSZ("pminub",XMM,16),	TNSZ("pand",XMM,16),
789 /*  [DC]  */	TNSZ("paddusb",XMM,16),	TNSZ("paddusw",XMM,16),	TNSZ("pmaxub",XMM,16),	TNSZ("pandn",XMM,16),
790 
791 /*  [E0]  */	TNSZ("pavgb",XMM,16),	TNSZ("psraw",XMM,16),	TNSZ("psrad",XMM,16),	TNSZ("pavgw",XMM,16),
792 /*  [E4]  */	TNSZ("pmulhuw",XMM,16),	TNSZ("pmulhw",XMM,16),	TNSZ("cvttpd2dq",XMM,16),TNSZ("movntdq",XMMS,16),
793 /*  [E8]  */	TNSZ("psubsb",XMM,16),	TNSZ("psubsw",XMM,16),	TNSZ("pminsw",XMM,16),	TNSZ("por",XMM,16),
794 /*  [EC]  */	TNSZ("paddsb",XMM,16),	TNSZ("paddsw",XMM,16),	TNSZ("pmaxsw",XMM,16),	TNSZ("pxor",XMM,16),
795 
796 /*  [F0]  */	INVALID,		TNSZ("psllw",XMM,16),	TNSZ("pslld",XMM,16),	TNSZ("psllq",XMM,16),
797 /*  [F4]  */	TNSZ("pmuludq",XMM,16),	TNSZ("pmaddwd",XMM,16),	TNSZ("psadbw",XMM,16),	TNSZ("maskmovdqu", XMMXIMPL,16),
798 /*  [F8]  */	TNSZ("psubb",XMM,16),	TNSZ("psubw",XMM,16),	TNSZ("psubd",XMM,16),	TNSZ("psubq",XMM,16),
799 /*  [FC]  */	TNSZ("paddb",XMM,16),	TNSZ("paddw",XMM,16),	TNSZ("paddd",XMM,16),	INVALID,
800 };
801 
802 const instable_t dis_opAVX660F[256] = {
803 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
804 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
805 /*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
806 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
807 
808 /*  [10]  */	TNSZ("vmovupd",VEX_MX,16),	TNSZ("vmovupd",VEX_RX,16),	TNSZ("vmovlpd",VEX_RMrX,8),	TNSZ("vmovlpd",VEX_RM,8),
809 /*  [14]  */	TNSZ("vunpcklpd",VEX_RMrX,16),TNSZ("vunpckhpd",VEX_RMrX,16),TNSZ("vmovhpd",VEX_RMrX,8),	TNSZ("vmovhpd",VEX_RM,8),
810 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
811 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
812 
813 /*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
814 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
815 /*  [28]  */	TNSZ("vmovapd",VEX_MX,16),	TNSZ("vmovapd",VEX_RX,16),	INVALID,		TNSZ("vmovntpd",VEX_RM,16),
816 /*  [2C]  */	INVALID,		INVALID,		TNSZ("vucomisd",VEX_MX,8),TNSZ("vcomisd",VEX_MX,8),
817 
818 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
819 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
820 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
821 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
822 
823 /*  [40]  */	INVALID,		TSvo("kand",VEX_RMX),	TSvo("kandn",VEX_RMX),		INVALID,
824 /*  [44]  */	TSvo("knot",VEX_MX),	TSvo("kor",VEX_RMX),	TSvo("kxnor",VEX_RMX),		TSvo("kxor",VEX_RMX),
825 /*  [48]  */	INVALID,		INVALID,		TSvo("kadd",VEX_RMX),		TSvo("kunpck",VEX_RMX),
826 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
827 
828 /*  [50]  */	TNS("vmovmskpd",VEX_MR),	TNSZ("vsqrtpd",VEX_MX,16),	INVALID,		INVALID,
829 /*  [54]  */	TNSZ("vandpd",VEX_RMrX,16),	TNSZ("vandnpd",VEX_RMrX,16),	TNSZ("vorpd",VEX_RMrX,16),	TNSZ("vxorpd",VEX_RMrX,16),
830 /*  [58]  */	TNSZ("vaddpd",VEX_RMrX,16),	TNSZ("vmulpd",VEX_RMrX,16),	TNSZ("vcvtpd2ps",VEX_MX,16),TNSZ("vcvtps2dq",VEX_MX,16),
831 /*  [5C]  */	TNSZ("vsubpd",VEX_RMrX,16),	TNSZ("vminpd",VEX_RMrX,16),	TNSZ("vdivpd",VEX_RMrX,16),	TNSZ("vmaxpd",VEX_RMrX,16),
832 
833 /*  [60]  */	TNSZ("vpunpcklbw",VEX_RMrX,16),TNSZ("vpunpcklwd",VEX_RMrX,16),TNSZ("vpunpckldq",VEX_RMrX,16),TNSZ("vpacksswb",VEX_RMrX,16),
834 /*  [64]  */	TNSZ("vpcmpgtb",VEX_RMrX,16),	TNSZ("vpcmpgtw",VEX_RMrX,16),	TNSZ("vpcmpgtd",VEX_RMrX,16),	TNSZ("vpackuswb",VEX_RMrX,16),
835 /*  [68]  */	TNSZ("vpunpckhbw",VEX_RMrX,16),TNSZ("vpunpckhwd",VEX_RMrX,16),TNSZ("vpunpckhdq",VEX_RMrX,16),TNSZ("vpackssdw",VEX_RMrX,16),
836 /*  [6C]  */	TNSZ("vpunpcklqdq",VEX_RMrX,16),TNSZ("vpunpckhqdq",VEX_RMrX,16),TNSZ("vmovd",VEX_MX,4),TNSZ("vmovdqa",VEX_MX,16),
837 
838 /*  [70]  */	TNSZ("vpshufd",VEX_MXI,16),	TNSZ("vgrp71",VEX_XXI,16),	TNSZ("vgrp72",VEX_XXI,16),		TNSZ("vgrp73",VEX_XXI,16),
839 /*  [74]  */	TNSZ("vpcmpeqb",VEX_RMrX,16),	TNSZ("vpcmpeqw",VEX_RMrX,16),	TNSZ("vpcmpeqd",VEX_RMrX,16),	INVALID,
840 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
841 /*  [7C]  */	TNSZ("vhaddpd",VEX_RMrX,16),	TNSZ("vhsubpd",VEX_RMrX,16),	TNSZ("vmovd",VEX_RR,4),	TNSZ("vmovdqa",VEX_RX,16),
842 
843 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
844 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
845 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
846 /*  [8C]  */	INVALID,		INVALID,		INVALID,		INVALID,
847 
848 /*  [90]  */	TSvo("kmov",VEX_KRM),	TSvo("kmov",VEX_KMR),	TSvo("kmov",VEX_KRR),		TSvo("kmov",VEX_MR),
849 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
850 /*  [98]  */	TSvo("kortest",VEX_MX),	TSvo("ktest",VEX_MX),	INVALID,		INVALID,
851 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
852 
853 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
854 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
855 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
856 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
857 
858 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
859 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
860 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
861 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
862 
863 /*  [C0]  */	INVALID,		INVALID,		TNSZ("vcmppd",VEX_RMRX,16),	INVALID,
864 /*  [C4]  */	TNSZ("vpinsrw",VEX_RMRX,2),TNS("vpextrw",VEX_MR),	TNSZ("vshufpd",VEX_RMRX,16),	INVALID,
865 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
866 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
867 
868 /*  [D0]  */	TNSZ("vaddsubpd",VEX_RMrX,16),TNSZ("vpsrlw",VEX_RMrX,16),	TNSZ("vpsrld",VEX_RMrX,16),	TNSZ("vpsrlq",VEX_RMrX,16),
869 /*  [D4]  */	TNSZ("vpaddq",VEX_RMrX,16),	TNSZ("vpmullw",VEX_RMrX,16),	TNSZ("vmovq",VEX_RX,8),	TNS("vpmovmskb",VEX_MR),
870 /*  [D8]  */	TNSZ("vpsubusb",VEX_RMrX,16),	TNSZ("vpsubusw",VEX_RMrX,16),	TNSZ("vpminub",VEX_RMrX,16),	TNSZ("vpand",VEX_RMrX,16),
871 /*  [DC]  */	TNSZ("vpaddusb",VEX_RMrX,16),	TNSZ("vpaddusw",VEX_RMrX,16),	TNSZ("vpmaxub",VEX_RMrX,16),	TNSZ("vpandn",VEX_RMrX,16),
872 
873 /*  [E0]  */	TNSZ("vpavgb",VEX_RMrX,16),	TNSZ("vpsraw",VEX_RMrX,16),	TNSZ("vpsrad",VEX_RMrX,16),	TNSZ("vpavgw",VEX_RMrX,16),
874 /*  [E4]  */	TNSZ("vpmulhuw",VEX_RMrX,16),	TNSZ("vpmulhw",VEX_RMrX,16),	TNSZ("vcvttpd2dq",VEX_MX,16),TNSZ("vmovntdq",VEX_RM,16),
875 /*  [E8]  */	TNSZ("vpsubsb",VEX_RMrX,16),	TNSZ("vpsubsw",VEX_RMrX,16),	TNSZ("vpminsw",VEX_RMrX,16),	TNSZ("vpor",VEX_RMrX,16),
876 /*  [EC]  */	TNSZ("vpaddsb",VEX_RMrX,16),	TNSZ("vpaddsw",VEX_RMrX,16),	TNSZ("vpmaxsw",VEX_RMrX,16),	TNSZ("vpxor",VEX_RMrX,16),
877 
878 /*  [F0]  */	INVALID,		TNSZ("vpsllw",VEX_RMrX,16),	TNSZ("vpslld",VEX_RMrX,16),	TNSZ("vpsllq",VEX_RMrX,16),
879 /*  [F4]  */	TNSZ("vpmuludq",VEX_RMrX,16),	TNSZ("vpmaddwd",VEX_RMrX,16),	TNSZ("vpsadbw",VEX_RMrX,16),	TNS("vmaskmovdqu",VEX_MX),
880 /*  [F8]  */	TNSZ("vpsubb",VEX_RMrX,16),	TNSZ("vpsubw",VEX_RMrX,16),	TNSZ("vpsubd",VEX_RMrX,16),	TNSZ("vpsubq",VEX_RMrX,16),
881 /*  [FC]  */	TNSZ("vpaddb",VEX_RMrX,16),	TNSZ("vpaddw",VEX_RMrX,16),	TNSZ("vpaddd",VEX_RMrX,16),	INVALID,
882 };
883 
884 /*
885  *	Decode table for SIMD instructions with the repnz (0xf2) prefix.
886  */
887 const instable_t dis_opSIMDrepnz[256] = {
888 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
889 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
890 /*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
891 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
892 
893 /*  [10]  */	TNSZ("movsd",XMM,8),	TNSZ("movsd",XMMS,8),	TNSZ("movddup",XMM,8),	INVALID,
894 /*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
895 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
896 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
897 
898 /*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
899 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
900 /*  [28]  */	INVALID,		INVALID,		TNSZ("cvtsi2sd",XMM3MX,4),TNSZ("movntsd",XMMMS,8),
901 /*  [2C]  */	TNSZ("cvttsd2si",XMMXM3,8),TNSZ("cvtsd2si",XMMXM3,8),INVALID,		INVALID,
902 
903 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
904 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
905 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
906 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
907 
908 /*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
909 /*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
910 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
911 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
912 
913 /*  [50]  */	INVALID,		TNSZ("sqrtsd",XMM,8),	INVALID,		INVALID,
914 /*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
915 /*  [58]  */	TNSZ("addsd",XMM,8),	TNSZ("mulsd",XMM,8),	TNSZ("cvtsd2ss",XMM,8),	INVALID,
916 /*  [5C]  */	TNSZ("subsd",XMM,8),	TNSZ("minsd",XMM,8),	TNSZ("divsd",XMM,8),	TNSZ("maxsd",XMM,8),
917 
918 /*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
919 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
920 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
921 /*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
922 
923 /*  [70]  */	TNSZ("pshuflw",XMMP,16),INVALID,		INVALID,		INVALID,
924 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
925 /*  [78]  */	TNSZ("insertq",XMMX2I,16),TNSZ("insertq",XMM,8),INVALID,		INVALID,
926 /*  [7C]  */	TNSZ("haddps",XMM,16),	TNSZ("hsubps",XMM,16),	INVALID,		INVALID,
927 
928 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
929 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
930 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
931 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
932 
933 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
934 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
935 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
936 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
937 
938 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
939 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
940 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
941 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
942 
943 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
944 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
945 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
946 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
947 
948 /*  [C0]  */	INVALID,		INVALID,		TNSZ("cmpsd",XMMP,8),	INVALID,
949 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
950 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
951 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
952 
953 /*  [D0]  */	TNSZ("addsubps",XMM,16),INVALID,		INVALID,		INVALID,
954 /*  [D4]  */	INVALID,		INVALID,		TNS("movdq2q",XMMXM),	INVALID,
955 /*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
956 /*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
957 
958 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
959 /*  [E4]  */	INVALID,		INVALID,		TNSZ("cvtpd2dq",XMM,16),INVALID,
960 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
961 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
962 
963 /*  [F0]  */	TNS("lddqu",XMMM),	INVALID,		INVALID,		INVALID,
964 /*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
965 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
966 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
967 };
968 
969 const instable_t dis_opAVXF20F[256] = {
970 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
971 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
972 /*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
973 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
974 
975 /*  [10]  */	TNSZ("vmovsd",VEX_RMrX,8),	TNSZ("vmovsd",VEX_RRX,8),	TNSZ("vmovddup",VEX_MX,8),	INVALID,
976 /*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
977 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
978 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
979 
980 /*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
981 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
982 /*  [28]  */	INVALID,		INVALID,		TNSZ("vcvtsi2sd",VEX_RMrX,4),INVALID,
983 /*  [2C]  */	TNSZ("vcvttsd2si",VEX_MR,8),TNSZ("vcvtsd2si",VEX_MR,8),INVALID,		INVALID,
984 
985 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
986 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
987 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
988 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
989 
990 /*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
991 /*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
992 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
993 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
994 
995 /*  [50]  */	INVALID,		TNSZ("vsqrtsd",VEX_RMrX,8),	INVALID,		INVALID,
996 /*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
997 /*  [58]  */	TNSZ("vaddsd",VEX_RMrX,8),	TNSZ("vmulsd",VEX_RMrX,8),	TNSZ("vcvtsd2ss",VEX_RMrX,8),	INVALID,
998 /*  [5C]  */	TNSZ("vsubsd",VEX_RMrX,8),	TNSZ("vminsd",VEX_RMrX,8),	TNSZ("vdivsd",VEX_RMrX,8),	TNSZ("vmaxsd",VEX_RMrX,8),
999 
1000 /*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1001 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1002 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1003 /*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1004 
1005 /*  [70]  */	TNSZ("vpshuflw",VEX_MXI,16),INVALID,		INVALID,		INVALID,
1006 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1007 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1008 /*  [7C]  */	TNSZ("vhaddps",VEX_RMrX,8),	TNSZ("vhsubps",VEX_RMrX,8),	INVALID,		INVALID,
1009 
1010 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1011 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1012 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1013 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1014 
1015 /*  [90]  */	INVALID,		INVALID,		TSvo("kmov",VEX_KRR),		TSvo("kmov",VEX_MR),
1016 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1017 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1018 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1019 
1020 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1021 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1022 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1023 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1024 
1025 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1026 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1027 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1028 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1029 
1030 /*  [C0]  */	INVALID,		INVALID,		TNSZ("vcmpsd",VEX_RMRX,8),	INVALID,
1031 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1032 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1033 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1034 
1035 /*  [D0]  */	TNSZ("vaddsubps",VEX_RMrX,8),	INVALID,		INVALID,		INVALID,
1036 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1037 /*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1038 /*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1039 
1040 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1041 /*  [E4]  */	INVALID,		INVALID,		TNSZ("vcvtpd2dq",VEX_MX,16),INVALID,
1042 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1043 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1044 
1045 /*  [F0]  */	TNSZ("vlddqu",VEX_MX,16),	INVALID,		INVALID,		INVALID,
1046 /*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1047 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1048 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1049 };
1050 
1051 const instable_t dis_opAVXF20F3A[256] = {
1052 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1053 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1054 /*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
1055 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1056 
1057 /*  [10]  */	INVALID,		INVALID,		INVALID,		INVALID,
1058 /*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
1059 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1060 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1061 
1062 /*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
1063 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1064 /*  [28]  */	INVALID,		INVALID,		INVALID,		INVALID,
1065 /*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1066 
1067 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1068 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1069 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1070 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1071 
1072 /*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1073 /*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
1074 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1075 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1076 
1077 /*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
1078 /*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
1079 /*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
1080 /*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1081 
1082 /*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1083 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1084 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1085 /*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1086 
1087 /*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
1088 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1089 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1090 /*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1091 
1092 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1093 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1094 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1095 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1096 
1097 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1098 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1099 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1100 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1101 
1102 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1103 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1104 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1105 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1106 
1107 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1108 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1109 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1110 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1111 
1112 /*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1113 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1114 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1115 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1116 
1117 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1118 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1119 /*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1120 /*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1121 
1122 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1123 /*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1124 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1125 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1126 
1127 /*  [F0]  */	TNSZvr("rorx",VEX_MXI,6),INVALID,		INVALID,		INVALID,
1128 /*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1129 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1130 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1131 };
1132 
1133 const instable_t dis_opAVXF20F38[256] = {
1134 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1135 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1136 /*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
1137 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1138 
1139 /*  [10]  */	INVALID,		INVALID,		INVALID,		INVALID,
1140 /*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
1141 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1142 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1143 
1144 /*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
1145 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1146 /*  [28]  */	INVALID,		INVALID,		INVALID,		INVALID,
1147 /*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1148 
1149 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1150 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1151 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1152 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1153 
1154 /*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1155 /*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
1156 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1157 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1158 
1159 /*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
1160 /*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
1161 /*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
1162 /*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1163 
1164 /*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1165 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1166 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1167 /*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1168 
1169 /*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
1170 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1171 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1172 /*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1173 
1174 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1175 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1176 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1177 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1178 
1179 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1180 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1181 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1182 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1183 
1184 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1185 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1186 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1187 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1188 
1189 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1190 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1191 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1192 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1193 
1194 /*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1195 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1196 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1197 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1198 
1199 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1200 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1201 /*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1202 /*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1203 
1204 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1205 /*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1206 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1207 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1208 
1209 /*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1210 /*  [F4]  */	INVALID,		TNSZvr("pdep",VEX_RMrX,5),TNSZvr("mulx",VEX_RMrX,5),TNSZvr("shrx",VEX_VRMrX,5),
1211 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1212 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1213 };
1214 
1215 const instable_t dis_opAVXF30F38[256] = {
1216 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1217 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1218 /*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
1219 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1220 
1221 /*  [10]  */	INVALID,		INVALID,		INVALID,		INVALID,
1222 /*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
1223 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1224 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1225 
1226 /*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
1227 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1228 /*  [28]  */	INVALID,		INVALID,		INVALID,		INVALID,
1229 /*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1230 
1231 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1232 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1233 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1234 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1235 
1236 /*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1237 /*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
1238 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1239 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1240 
1241 /*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
1242 /*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
1243 /*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
1244 /*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1245 
1246 /*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1247 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1248 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1249 /*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1250 
1251 /*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
1252 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1253 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1254 /*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1255 
1256 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1257 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1258 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1259 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1260 
1261 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1262 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1263 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1264 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1265 
1266 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1267 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1268 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1269 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1270 
1271 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1272 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1273 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1274 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1275 
1276 /*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1277 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1278 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1279 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1280 
1281 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1282 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1283 /*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1284 /*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1285 
1286 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1287 /*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1288 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1289 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1290 
1291 /*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1292 /*  [F4]  */	INVALID,		TNSZvr("pext",VEX_RMrX,5),INVALID,		TNSZvr("sarx",VEX_VRMrX,5),
1293 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1294 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1295 };
1296 /*
1297  *	Decode table for SIMD instructions with the repz (0xf3) prefix.
1298  */
1299 const instable_t dis_opSIMDrepz[256] = {
1300 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1301 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1302 /*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
1303 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1304 
1305 /*  [10]  */	TNSZ("movss",XMM,4),	TNSZ("movss",XMMS,4),	TNSZ("movsldup",XMM,16),INVALID,
1306 /*  [14]  */	INVALID,		INVALID,		TNSZ("movshdup",XMM,16),INVALID,
1307 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1308 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1309 
1310 /*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
1311 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1312 /*  [28]  */	INVALID,		INVALID,		TNSZ("cvtsi2ss",XMM3MX,4),TNSZ("movntss",XMMMS,4),
1313 /*  [2C]  */	TNSZ("cvttss2si",XMMXM3,4),TNSZ("cvtss2si",XMMXM3,4),INVALID,		INVALID,
1314 
1315 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1316 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1317 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1318 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1319 
1320 /*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1321 /*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
1322 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1323 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1324 
1325 /*  [50]  */	INVALID,		TNSZ("sqrtss",XMM,4),	TNSZ("rsqrtss",XMM,4),	TNSZ("rcpss",XMM,4),
1326 /*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
1327 /*  [58]  */	TNSZ("addss",XMM,4),	TNSZ("mulss",XMM,4),	TNSZ("cvtss2sd",XMM,4),	TNSZ("cvttps2dq",XMM,16),
1328 /*  [5C]  */	TNSZ("subss",XMM,4),	TNSZ("minss",XMM,4),	TNSZ("divss",XMM,4),	TNSZ("maxss",XMM,4),
1329 
1330 /*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1331 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1332 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1333 /*  [6C]  */	INVALID,		INVALID,		INVALID,		TNSZ("movdqu",XMM,16),
1334 
1335 /*  [70]  */	TNSZ("pshufhw",XMMP,16),INVALID,		INVALID,		INVALID,
1336 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1337 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1338 /*  [7C]  */	INVALID,		INVALID,		TNSZ("movq",XMM,8),	TNSZ("movdqu",XMMS,16),
1339 
1340 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1341 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1342 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1343 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1344 
1345 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1346 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1347 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1348 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1349 
1350 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1351 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1352 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1353 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1354 
1355 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1356 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1357 /*  [B8]  */	TS("popcnt",MRw),	INVALID,		INVALID,		INVALID,
1358 /*  [BC]  */	TNSZ("tzcnt",MRw,5),	TS("lzcnt",MRw),	INVALID,		INVALID,
1359 
1360 /*  [C0]  */	INVALID,		INVALID,		TNSZ("cmpss",XMMP,4),	INVALID,
1361 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1362 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1363 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1364 
1365 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1366 /*  [D4]  */	INVALID,		INVALID,		TNS("movq2dq",XMMMX),	INVALID,
1367 /*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1368 /*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1369 
1370 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1371 /*  [E4]  */	INVALID,		INVALID,		TNSZ("cvtdq2pd",XMM,8),	INVALID,
1372 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1373 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1374 
1375 /*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1376 /*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1377 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1378 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1379 };
1380 
1381 const instable_t dis_opAVXF30F[256] = {
1382 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1383 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1384 /*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
1385 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1386 
1387 /*  [10]  */	TNSZ("vmovss",VEX_RMrX,4),	TNSZ("vmovss",VEX_RRX,4),	TNSZ("vmovsldup",VEX_MX,4),	INVALID,
1388 /*  [14]  */	INVALID,		INVALID,		TNSZ("vmovshdup",VEX_MX,4),	INVALID,
1389 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1390 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1391 
1392 /*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
1393 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1394 /*  [28]  */	INVALID,		INVALID,		TNSZ("vcvtsi2ss",VEX_RMrX,4),INVALID,
1395 /*  [2C]  */	TNSZ("vcvttss2si",VEX_MR,4),TNSZ("vcvtss2si",VEX_MR,4),INVALID,		INVALID,
1396 
1397 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1398 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1399 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1400 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1401 
1402 /*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1403 /*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
1404 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1405 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1406 
1407 /*  [50]  */	INVALID,		TNSZ("vsqrtss",VEX_RMrX,4),	TNSZ("vrsqrtss",VEX_RMrX,4),	TNSZ("vrcpss",VEX_RMrX,4),
1408 /*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
1409 /*  [58]  */	TNSZ("vaddss",VEX_RMrX,4),	TNSZ("vmulss",VEX_RMrX,4),	TNSZ("vcvtss2sd",VEX_RMrX,4),	TNSZ("vcvttps2dq",VEX_MX,16),
1410 /*  [5C]  */	TNSZ("vsubss",VEX_RMrX,4),	TNSZ("vminss",VEX_RMrX,4),	TNSZ("vdivss",VEX_RMrX,4),	TNSZ("vmaxss",VEX_RMrX,4),
1411 
1412 /*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1413 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1414 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1415 /*  [6C]  */	INVALID,		INVALID,		INVALID,		TNSZ("vmovdqu",VEX_MX,16),
1416 
1417 /*  [70]  */	TNSZ("vpshufhw",VEX_MXI,16),INVALID,		INVALID,		INVALID,
1418 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1419 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1420 /*  [7C]  */	INVALID,		INVALID,		TNSZ("vmovq",VEX_MX,8),	TNSZ("vmovdqu",VEX_RX,16),
1421 
1422 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1423 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1424 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1425 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1426 
1427 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1428 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1429 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1430 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1431 
1432 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1433 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1434 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1435 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1436 
1437 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1438 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1439 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1440 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1441 
1442 /*  [C0]  */	INVALID,		INVALID,		TNSZ("vcmpss",VEX_RMRX,4),	INVALID,
1443 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1444 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1445 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1446 
1447 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1448 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1449 /*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1450 /*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1451 
1452 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1453 /*  [E4]  */	INVALID,		INVALID,		TNSZ("vcvtdq2pd",VEX_MX,8),	INVALID,
1454 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1455 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1456 
1457 /*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1458 /*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1459 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1460 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1461 };
1462 
1463 /*
1464  * Table for instructions with an EVEX prefix followed by 0F.
1465  */
1466 const instable_t dis_opEVEX0F[256] = {
1467 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1468 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1469 /*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
1470 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1471 
1472 /*  [10]  */	TNS("vmovups",EVEX_MX),	TNS("vmovups",EVEX_RX),	INVALID,		INVALID,
1473 /*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
1474 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1475 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1476 
1477 /*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
1478 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1479 /*  [28]  */	TNS("vmovaps",EVEX_MX),	TNS("vmovaps",EVEX_RX),	INVALID,		INVALID,
1480 /*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1481 
1482 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1483 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1484 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1485 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1486 
1487 /*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1488 /*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
1489 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1490 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1491 
1492 /*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
1493 /*  [54]  */	TNS("vandps",EVEX_RMrX),TNS("vandnps",EVEX_RMrX),TNS("vorps",EVEX_RMrX),TNS("vxorps",EVEX_RMrX),
1494 /*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
1495 /*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1496 
1497 /*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1498 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1499 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1500 /*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1501 
1502 /*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
1503 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1504 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1505 /*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1506 
1507 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1508 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1509 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1510 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1511 
1512 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1513 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1514 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1515 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1516 
1517 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1518 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1519 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1520 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1521 
1522 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1523 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1524 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1525 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1526 
1527 /*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1528 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1529 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1530 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1531 
1532 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1533 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1534 /*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1535 /*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1536 
1537 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1538 /*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1539 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1540 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1541 
1542 /*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1543 /*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1544 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1545 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1546 };
1547 
1548 /*
1549  * Decode tables for EVEX 66 0F
1550  */
1551 const instable_t dis_opEVEX660F[256] = {
1552 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1553 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1554 /*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
1555 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1556 
1557 /*  [10]  */	TNS("vmovupd",EVEX_MX),	TNS("vmovupd",EVEX_RX),	INVALID,		INVALID,
1558 /*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
1559 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1560 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1561 
1562 /*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
1563 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1564 /*  [28]  */	TNS("vmovapd",EVEX_MX),	TNS("vmovapd",EVEX_RX),	INVALID,		INVALID,
1565 /*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1566 
1567 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1568 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1569 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1570 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1571 
1572 /*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1573 /*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
1574 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1575 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1576 
1577 /*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
1578 /*  [54]  */	TNS("vandpd",EVEX_RMrX),TNS("vandnpd",EVEX_RMrX),TNS("vorpd",EVEX_RMrX),TNS("vxorpd",EVEX_RMrX),
1579 /*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
1580 /*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1581 
1582 /*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1583 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1584 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1585 /*  [6C]  */	INVALID,		INVALID,		INVALID,		TNS("vmovdqa",EVEX_MX),
1586 
1587 /*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
1588 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1589 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1590 /*  [7C]  */	INVALID,		INVALID,		INVALID,		TNS("vmovdqa",EVEX_RX),
1591 
1592 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1593 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1594 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1595 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1596 
1597 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1598 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1599 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1600 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1601 
1602 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1603 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1604 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1605 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1606 
1607 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1608 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1609 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1610 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1611 
1612 /*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1613 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1614 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1615 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1616 
1617 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1618 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1619 /*  [D8]  */	INVALID,		INVALID,		INVALID,		TSq("vpand",EVEX_RMrX),
1620 /*  [DC]  */	INVALID,		INVALID,		INVALID,		TSq("vpandn",EVEX_RMrX),
1621 
1622 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1623 /*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1624 /*  [E8]  */	INVALID,		INVALID,		INVALID,		TSq("vpor",EVEX_RMrX),
1625 /*  [EC]  */	INVALID,		INVALID,		INVALID,		TSq("vpxor",EVEX_RMrX),
1626 
1627 /*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1628 /*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1629 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1630 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1631 };
1632 
1633 const instable_t dis_opEVEX660F38[256] = {
1634 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1635 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1636 /*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
1637 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1638 
1639 /*  [10]  */	INVALID,		INVALID,		INVALID,		INVALID,
1640 /*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
1641 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1642 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1643 
1644 /*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
1645 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1646 /*  [28]  */	INVALID,		INVALID,		INVALID,		INVALID,
1647 /*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1648 
1649 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1650 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1651 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1652 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1653 
1654 /*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1655 /*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
1656 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1657 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1658 
1659 /*  [50]  */	TNSZ("vpdpbusd",EVEX_RMrX,16),TNSZ("vpdpbusds",EVEX_RMrX,16),TNSZ("vpdpwssd",EVEX_RMrX,16),TNSZ("vpdpwssds",EVEX_RMrX,16),
1660 /*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
1661 /*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
1662 /*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1663 
1664 /*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1665 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1666 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1667 /*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1668 
1669 /*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
1670 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1671 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1672 /*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1673 
1674 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1675 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1676 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1677 /*  [8C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1678 
1679 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1680 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1681 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1682 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1683 
1684 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1685 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1686 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1687 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1688 
1689 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1690 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1691 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1692 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1693 
1694 /*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1695 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1696 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1697 /*  [CC]  */	INVALID,		INVALID,		INVALID,		TNS("vgf2p8mulb",EVEX_RMrX),
1698 
1699 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1700 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1701 /*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1702 /*  [DC]  */	TNSZ("vaesenc",EVEX_RMrX,16),TNSZ("vaesenclast",EVEX_RMrX,16),TNSZ("vaesdec",EVEX_RMrX,16),TNSZ("vaesdeclast",EVEX_RMrX,16),
1703 
1704 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1705 /*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1706 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1707 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1708 
1709 /*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1710 /*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1711 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1712 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1713 };
1714 
1715 const instable_t dis_opEVEX660F3A[256] = {
1716 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1717 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1718 /*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
1719 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1720 
1721 /*  [10]  */	INVALID,		INVALID,		INVALID,		INVALID,
1722 /*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
1723 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1724 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1725 
1726 /*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
1727 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1728 /*  [28]  */	INVALID,		INVALID,		INVALID,		INVALID,
1729 /*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1730 
1731 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1732 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1733 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1734 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1735 
1736 /*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1737 /*  [44]  */	TNSZ("vpclmulqdq",EVEX_RMRX,16),INVALID,		INVALID,		INVALID,
1738 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1739 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1740 
1741 /*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
1742 /*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
1743 /*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
1744 /*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1745 
1746 /*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1747 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1748 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1749 /*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1750 
1751 /*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
1752 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1753 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1754 /*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1755 
1756 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1757 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1758 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1759 /*  [8C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1760 
1761 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1762 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1763 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1764 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1765 
1766 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1767 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1768 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1769 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1770 
1771 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1772 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1773 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1774 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1775 
1776 /*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1777 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1778 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1779 /*  [CC]  */	INVALID,		INVALID,		TNS("vgf2p8affineqb",EVEX_RMRX),TNS("vgf2p8affineinvqb",EVEX_RMRX),
1780 
1781 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1782 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1783 /*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1784 /*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1785 
1786 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1787 /*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1788 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1789 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1790 
1791 /*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1792 /*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1793 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1794 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1795 };
1796 
1797 
1798 const instable_t dis_opEVEXF20F[256] = {
1799 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1800 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1801 /*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
1802 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1803 
1804 /*  [10]  */	INVALID,		INVALID,		INVALID,		INVALID,
1805 /*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
1806 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1807 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1808 
1809 /*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
1810 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1811 /*  [28]  */	INVALID,		INVALID,		INVALID,		INVALID,
1812 /*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1813 
1814 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1815 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1816 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1817 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1818 
1819 /*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1820 /*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
1821 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1822 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1823 
1824 /*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
1825 /*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
1826 /*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
1827 /*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1828 
1829 /*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1830 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1831 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1832 /*  [6C]  */	INVALID,		INVALID,		INVALID,		TNS("vmovdqu",EVEX_MX),
1833 
1834 /*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
1835 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1836 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1837 /*  [7C]  */	INVALID,		INVALID,		INVALID,		TNS("vmovdqu",EVEX_RX),
1838 
1839 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1840 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1841 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1842 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1843 
1844 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1845 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1846 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1847 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1848 
1849 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1850 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1851 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1852 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1853 
1854 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1855 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1856 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1857 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1858 
1859 /*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1860 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1861 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1862 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1863 
1864 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1865 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1866 /*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1867 /*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1868 
1869 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1870 /*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1871 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1872 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1873 
1874 /*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1875 /*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1876 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1877 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1878 };
1879 
1880 const instable_t dis_opEVEXF30F[256] = {
1881 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1882 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1883 /*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
1884 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1885 
1886 /*  [10]  */	INVALID,		INVALID,		INVALID,		INVALID,
1887 /*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
1888 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1889 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1890 
1891 /*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
1892 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1893 /*  [28]  */	INVALID,		INVALID,		INVALID,		INVALID,
1894 /*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1895 
1896 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1897 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1898 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1899 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1900 
1901 /*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1902 /*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
1903 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1904 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1905 
1906 /*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
1907 /*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
1908 /*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
1909 /*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1910 
1911 /*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1912 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1913 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1914 /*  [6C]  */	INVALID,		INVALID,		INVALID,		TNS("vmovdqu",EVEX_MX),
1915 
1916 /*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
1917 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1918 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1919 /*  [7C]  */	INVALID,		INVALID,		INVALID,		TNS("vmovdqu",EVEX_RX),
1920 
1921 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1922 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1923 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1924 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1925 
1926 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1927 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1928 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1929 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1930 
1931 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1932 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1933 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1934 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1935 
1936 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1937 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1938 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1939 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1940 
1941 /*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1942 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1943 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1944 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1945 
1946 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1947 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1948 /*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1949 /*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1950 
1951 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1952 /*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1953 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1954 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1955 
1956 /*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1957 /*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1958 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1959 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1960 };
1961 /*
1962  * The following two tables are used to encode crc32 and movbe
1963  * since they share the same opcodes.
1964  */
1965 const instable_t dis_op0F38F0[2] = {
1966 /*  [00]  */	TNS("crc32b",CRC32),
1967 		TS("movbe",MOVBE),
1968 };
1969 
1970 const instable_t dis_op0F38F1[2] = {
1971 /*  [00]  */	TS("crc32",CRC32),
1972 		TS("movbe",MOVBE),
1973 };
1974 
1975 /*
1976  * The following table is used to distinguish between adox and adcx which share
1977  * the same opcodes.
1978  */
1979 const instable_t dis_op0F38F6[2] = {
1980 /*  [00]  */	TNS("adcx",ADX),
1981 		TNS("adox",ADX),
1982 };
1983 
1984 const instable_t dis_op0F38[256] = {
1985 /*  [00]  */	TNSZ("pshufb",XMM_66o,16),TNSZ("phaddw",XMM_66o,16),TNSZ("phaddd",XMM_66o,16),TNSZ("phaddsw",XMM_66o,16),
1986 /*  [04]  */	TNSZ("pmaddubsw",XMM_66o,16),TNSZ("phsubw",XMM_66o,16),	TNSZ("phsubd",XMM_66o,16),TNSZ("phsubsw",XMM_66o,16),
1987 /*  [08]  */	TNSZ("psignb",XMM_66o,16),TNSZ("psignw",XMM_66o,16),TNSZ("psignd",XMM_66o,16),TNSZ("pmulhrsw",XMM_66o,16),
1988 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1989 
1990 /*  [10]  */	TNSZ("pblendvb",XMM_66r,16),INVALID,		INVALID,		INVALID,
1991 /*  [14]  */	TNSZ("blendvps",XMM_66r,16),TNSZ("blendvpd",XMM_66r,16),INVALID,	TNSZ("ptest",XMM_66r,16),
1992 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1993 /*  [1C]  */	TNSZ("pabsb",XMM_66o,16),TNSZ("pabsw",XMM_66o,16),TNSZ("pabsd",XMM_66o,16),INVALID,
1994 
1995 /*  [20]  */	TNSZ("pmovsxbw",XMM_66r,16),TNSZ("pmovsxbd",XMM_66r,16),TNSZ("pmovsxbq",XMM_66r,16),TNSZ("pmovsxwd",XMM_66r,16),
1996 /*  [24]  */	TNSZ("pmovsxwq",XMM_66r,16),TNSZ("pmovsxdq",XMM_66r,16),INVALID,	INVALID,
1997 /*  [28]  */	TNSZ("pmuldq",XMM_66r,16),TNSZ("pcmpeqq",XMM_66r,16),TNSZ("movntdqa",XMMM_66r,16),TNSZ("packusdw",XMM_66r,16),
1998 /*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1999 
2000 /*  [30]  */	TNSZ("pmovzxbw",XMM_66r,16),TNSZ("pmovzxbd",XMM_66r,16),TNSZ("pmovzxbq",XMM_66r,16),TNSZ("pmovzxwd",XMM_66r,16),
2001 /*  [34]  */	TNSZ("pmovzxwq",XMM_66r,16),TNSZ("pmovzxdq",XMM_66r,16),INVALID,	TNSZ("pcmpgtq",XMM_66r,16),
2002 /*  [38]  */	TNSZ("pminsb",XMM_66r,16),TNSZ("pminsd",XMM_66r,16),TNSZ("pminuw",XMM_66r,16),TNSZ("pminud",XMM_66r,16),
2003 /*  [3C]  */	TNSZ("pmaxsb",XMM_66r,16),TNSZ("pmaxsd",XMM_66r,16),TNSZ("pmaxuw",XMM_66r,16),TNSZ("pmaxud",XMM_66r,16),
2004 
2005 /*  [40]  */	TNSZ("pmulld",XMM_66r,16),TNSZ("phminposuw",XMM_66r,16),INVALID,	INVALID,
2006 /*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
2007 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
2008 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2009 
2010 /*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
2011 /*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
2012 /*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
2013 /*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2014 
2015 /*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
2016 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
2017 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
2018 /*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2019 
2020 /*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
2021 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
2022 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
2023 /*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2024 
2025 /*  [80]  */	TNSy("invept", RM_66r),	TNSy("invvpid", RM_66r),TNSy("invpcid", RM_66r),INVALID,
2026 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
2027 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
2028 /*  [8C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2029 
2030 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
2031 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
2032 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
2033 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2034 
2035 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2036 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2037 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2038 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2039 
2040 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2041 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2042 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2043 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2044 
2045 /*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2046 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2047 /*  [C8]  */	TNSZ("sha1nexte",XMM,16),TNSZ("sha1msg1",XMM,16),TNSZ("sha1msg2",XMM,16),TNSZ("sha256rnds2",XMM,16),
2048 /*  [CC]  */	TNSZ("sha256msg1",XMM,16),TNSZ("sha256msg2",XMM,16),INVALID,		TNS("gf2p8mulb",XMM_66r),
2049 
2050 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2051 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2052 /*  [D8]  */	INVALID,		INVALID,		INVALID,		TNSZ("aesimc",XMM_66r,16),
2053 /*  [DC]  */	TNSZ("aesenc",XMM_66r,16),TNSZ("aesenclast",XMM_66r,16),TNSZ("aesdec",XMM_66r,16),TNSZ("aesdeclast",XMM_66r,16),
2054 
2055 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2056 /*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2057 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2058 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2059 /*  [F0]  */	IND(dis_op0F38F0),	IND(dis_op0F38F1),	INVALID,		INVALID,
2060 /*  [F4]  */	INVALID,		INVALID,		IND(dis_op0F38F6),	INVALID,
2061 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2062 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2063 };
2064 
2065 const instable_t dis_opAVX660F38[256] = {
2066 /*  [00]  */	TNSZ("vpshufb",VEX_RMrX,16),TNSZ("vphaddw",VEX_RMrX,16),TNSZ("vphaddd",VEX_RMrX,16),TNSZ("vphaddsw",VEX_RMrX,16),
2067 /*  [04]  */	TNSZ("vpmaddubsw",VEX_RMrX,16),TNSZ("vphsubw",VEX_RMrX,16),	TNSZ("vphsubd",VEX_RMrX,16),TNSZ("vphsubsw",VEX_RMrX,16),
2068 /*  [08]  */	TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16),
2069 /*  [0C]  */	TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8),	TNSZ("vtestpd",VEX_RRI,16),
2070 
2071 /*  [10]  */	INVALID,		INVALID,		INVALID,		TNSZ("vcvtph2ps",VEX_MX,16),
2072 /*  [14]  */	INVALID,		INVALID,		TNSZ("vpermps",VEX_RMrX,16),TNSZ("vptest",VEX_RRI,16),
2073 /*  [18]  */	TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID,
2074 /*  [1C]  */	TNSZ("vpabsb",VEX_MX,16),TNSZ("vpabsw",VEX_MX,16),TNSZ("vpabsd",VEX_MX,16),INVALID,
2075 
2076 /*  [20]  */	TNSZ("vpmovsxbw",VEX_MX,16),TNSZ("vpmovsxbd",VEX_MX,16),TNSZ("vpmovsxbq",VEX_MX,16),TNSZ("vpmovsxwd",VEX_MX,16),
2077 /*  [24]  */	TNSZ("vpmovsxwq",VEX_MX,16),TNSZ("vpmovsxdq",VEX_MX,16),INVALID,	INVALID,
2078 /*  [28]  */	TNSZ("vpmuldq",VEX_RMrX,16),TNSZ("vpcmpeqq",VEX_RMrX,16),TNSZ("vmovntdqa",VEX_MX,16),TNSZ("vpackusdw",VEX_RMrX,16),
2079 /*  [2C]  */	TNSZ("vmaskmovps",VEX_RMrX,8),TNSZ("vmaskmovpd",VEX_RMrX,16),TNSZ("vmaskmovps",VEX_RRM,8),TNSZ("vmaskmovpd",VEX_RRM,16),
2080 
2081 /*  [30]  */	TNSZ("vpmovzxbw",VEX_MX,16),TNSZ("vpmovzxbd",VEX_MX,16),TNSZ("vpmovzxbq",VEX_MX,16),TNSZ("vpmovzxwd",VEX_MX,16),
2082 /*  [34]  */	TNSZ("vpmovzxwq",VEX_MX,16),TNSZ("vpmovzxdq",VEX_MX,16),TNSZ("vpermd",VEX_RMrX,16),TNSZ("vpcmpgtq",VEX_RMrX,16),
2083 /*  [38]  */	TNSZ("vpminsb",VEX_RMrX,16),TNSZ("vpminsd",VEX_RMrX,16),TNSZ("vpminuw",VEX_RMrX,16),TNSZ("vpminud",VEX_RMrX,16),
2084 /*  [3C]  */	TNSZ("vpmaxsb",VEX_RMrX,16),TNSZ("vpmaxsd",VEX_RMrX,16),TNSZ("vpmaxuw",VEX_RMrX,16),TNSZ("vpmaxud",VEX_RMrX,16),
2085 
2086 /*  [40]  */	TNSZ("vpmulld",VEX_RMrX,16),TNSZ("vphminposuw",VEX_MX,16),INVALID,	INVALID,
2087 /*  [44]  */	INVALID,		TSaZ("vpsrlv",VEX_RMrX,16),TNSZ("vpsravd",VEX_RMrX,16),TSaZ("vpsllv",VEX_RMrX,16),
2088 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
2089 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2090 
2091 /*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
2092 /*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
2093 /*  [58]  */	TNSZ("vpbroadcastd",VEX_MX,16),TNSZ("vpbroadcastq",VEX_MX,16),TNSZ("vbroadcasti128",VEX_MX,16),INVALID,
2094 /*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2095 
2096 /*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
2097 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
2098 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
2099 /*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2100 
2101 /*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
2102 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
2103 /*  [78]  */	TNSZ("vpbroadcastb",VEX_MX,16),TNSZ("vpbroadcastw",VEX_MX,16),INVALID,	INVALID,
2104 /*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2105 
2106 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
2107 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
2108 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
2109 /*  [8C]  */	TSaZ("vpmaskmov",VEX_RMrX,16),INVALID,		TSaZ("vpmaskmov",VEX_RRM,16),INVALID,
2110 
2111 /*  [90]  */	TNSZ("vpgatherd",VEX_SbVM,16),TNSZ("vpgatherq",VEX_SbVM,16),TNSZ("vgatherdp",VEX_SbVM,16),TNSZ("vgatherqp",VEX_SbVM,16),
2112 /*  [94]  */	INVALID,		INVALID,		TNSZ("vfmaddsub132p",FMA,16),TNSZ("vfmsubadd132p",FMA,16),
2113 /*  [98]  */	TNSZ("vfmadd132p",FMA,16),TNSZ("vfmadd132s",FMA,16),TNSZ("vfmsub132p",FMA,16),TNSZ("vfmsub132s",FMA,16),
2114 /*  [9C]  */	TNSZ("vfnmadd132p",FMA,16),TNSZ("vfnmadd132s",FMA,16),TNSZ("vfnmsub132p",FMA,16),TNSZ("vfnmsub132s",FMA,16),
2115 
2116 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2117 /*  [A4]  */	INVALID,		INVALID,		TNSZ("vfmaddsub213p",FMA,16),TNSZ("vfmsubadd213p",FMA,16),
2118 /*  [A8]  */	TNSZ("vfmadd213p",FMA,16),TNSZ("vfmadd213s",FMA,16),TNSZ("vfmsub213p",FMA,16),TNSZ("vfmsub213s",FMA,16),
2119 /*  [AC]  */	TNSZ("vfnmadd213p",FMA,16),TNSZ("vfnmadd213s",FMA,16),TNSZ("vfnmsub213p",FMA,16),TNSZ("vfnmsub213s",FMA,16),
2120 
2121 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2122 /*  [B4]  */	INVALID,		INVALID,		TNSZ("vfmaddsub231p",FMA,16),TNSZ("vfmsubadd231p",FMA,16),
2123 /*  [B8]  */	TNSZ("vfmadd231p",FMA,16),TNSZ("vfmadd231s",FMA,16),TNSZ("vfmsub231p",FMA,16),TNSZ("vfmsub231s",FMA,16),
2124 /*  [BC]  */	TNSZ("vfnmadd231p",FMA,16),TNSZ("vfnmadd231s",FMA,16),TNSZ("vfnmsub231p",FMA,16),TNSZ("vfnmsub231s",FMA,16),
2125 
2126 /*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2127 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2128 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2129 /*  [CC]  */	INVALID,		INVALID,		INVALID,		TNS("vgf2p8mulb",VEX_RMrX),
2130 
2131 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2132 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2133 /*  [D8]  */	INVALID,		INVALID,		INVALID,		TNSZ("vaesimc",VEX_MX,16),
2134 /*  [DC]  */	TNSZ("vaesenc",VEX_RMrX,16),TNSZ("vaesenclast",VEX_RMrX,16),TNSZ("vaesdec",VEX_RMrX,16),TNSZ("vaesdeclast",VEX_RMrX,16),
2135 
2136 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2137 /*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2138 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2139 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2140 /*  [F0]  */	IND(dis_op0F38F0),	IND(dis_op0F38F1),	INVALID,		INVALID,
2141 /*  [F4]  */	INVALID,		INVALID,		INVALID,		TNSZvr("shlx",VEX_VRMrX,5),
2142 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2143 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2144 };
2145 
2146 const instable_t dis_op0F3A[256] = {
2147 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
2148 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
2149 /*  [08]  */	TNSZ("roundps",XMMP_66r,16),TNSZ("roundpd",XMMP_66r,16),TNSZ("roundss",XMMP_66r,16),TNSZ("roundsd",XMMP_66r,16),
2150 /*  [0C]  */	TNSZ("blendps",XMMP_66r,16),TNSZ("blendpd",XMMP_66r,16),TNSZ("pblendw",XMMP_66r,16),TNSZ("palignr",XMMP_66o,16),
2151 
2152 /*  [10]  */	INVALID,		INVALID,		INVALID,		INVALID,
2153 /*  [14]  */	TNSZ("pextrb",XMM3PM_66r,8),TNSZ("pextrw",XMM3PM_66r,16),TSZ("pextr",XMM3PM_66r,16),TNSZ("extractps",XMM3PM_66r,16),
2154 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
2155 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2156 
2157 /*  [20]  */	TNSZ("pinsrb",XMMPRM_66r,8),TNSZ("insertps",XMMP_66r,16),TSZ("pinsr",XMMPRM_66r,16),INVALID,
2158 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
2159 /*  [28]  */	INVALID,		INVALID,		INVALID,		INVALID,
2160 /*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2161 
2162 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
2163 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
2164 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
2165 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2166 
2167 /*  [40]  */	TNSZ("dpps",XMMP_66r,16),TNSZ("dppd",XMMP_66r,16),TNSZ("mpsadbw",XMMP_66r,16),INVALID,
2168 /*  [44]  */	TNSZ("pclmulqdq",XMMP_66r,16),INVALID,		INVALID,		INVALID,
2169 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
2170 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2171 
2172 /*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
2173 /*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
2174 /*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
2175 /*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2176 
2177 /*  [60]  */	TNSZ("pcmpestrm",XMMP_66r,16),TNSZ("pcmpestri",XMMP_66r,16),TNSZ("pcmpistrm",XMMP_66r,16),TNSZ("pcmpistri",XMMP_66r,16),
2178 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
2179 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
2180 /*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2181 
2182 /*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
2183 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
2184 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
2185 /*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2186 
2187 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
2188 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
2189 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
2190 /*  [8C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2191 
2192 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
2193 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
2194 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
2195 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2196 
2197 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2198 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2199 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2200 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2201 
2202 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2203 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2204 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2205 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2206 
2207 /*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2208 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2209 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2210 /*  [CC]  */	TNSZ("sha1rnds4",XMMP,16),INVALID,		TNS("gf2p8affineqb",XMMP_66r),TNS("gf2p8affineinvqb",XMMP_66r),
2211 
2212 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2213 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2214 /*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2215 /*  [DC]  */	INVALID,		INVALID,		INVALID,		TNSZ("aeskeygenassist",XMMP_66r,16),
2216 
2217 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2218 /*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2219 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2220 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2221 
2222 /*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2223 /*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2224 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2225 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2226 };
2227 
2228 const instable_t dis_opAVX660F3A[256] = {
2229 /*  [00]  */	TNSZ("vpermq",VEX_MXI,16),TNSZ("vpermpd",VEX_MXI,16),TNSZ("vpblendd",VEX_RMRX,16),INVALID,
2230 /*  [04]  */	TNSZ("vpermilps",VEX_MXI,8),TNSZ("vpermilpd",VEX_MXI,16),TNSZ("vperm2f128",VEX_RMRX,16),INVALID,
2231 /*  [08]  */	TNSZ("vroundps",VEX_MXI,16),TNSZ("vroundpd",VEX_MXI,16),TNSZ("vroundss",VEX_RMRX,16),TNSZ("vroundsd",VEX_RMRX,16),
2232 /*  [0C]  */	TNSZ("vblendps",VEX_RMRX,16),TNSZ("vblendpd",VEX_RMRX,16),TNSZ("vpblendw",VEX_RMRX,16),TNSZ("vpalignr",VEX_RMRX,16),
2233 
2234 /*  [10]  */	INVALID,		INVALID,		INVALID,		INVALID,
2235 /*  [14]  */	TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16),
2236 /*  [18]  */	TNSZ("vinsertf128",VEX_RMRX,16),TNSZ("vextractf128",VEX_RX,16),INVALID,		INVALID,
2237 /*  [1C]  */	INVALID,		TNSZ("vcvtps2ph",VEX_RX,16),		INVALID,		INVALID,
2238 
2239 /*  [20]  */	TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID,
2240 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
2241 /*  [28]  */	INVALID,		INVALID,		INVALID,		INVALID,
2242 /*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2243 
2244 /*  [30]  */	TSvo("kshiftr",VEX_MXI),	TSvo("kshiftr",VEX_MXI),	TSvo("kshiftl",VEX_MXI),	TSvo("kshiftl",VEX_MXI),
2245 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
2246 /*  [38]  */	TNSZ("vinserti128",VEX_RMRX,16),TNSZ("vextracti128",VEX_RIM,16),INVALID,		INVALID,
2247 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2248 
2249 /*  [40]  */	TNSZ("vdpps",VEX_RMRX,16),TNSZ("vdppd",VEX_RMRX,16),TNSZ("vmpsadbw",VEX_RMRX,16),INVALID,
2250 /*  [44]  */	TNSZ("vpclmulqdq",VEX_RMRX,16),INVALID,		TNSZ("vperm2i128",VEX_RMRX,16),INVALID,
2251 /*  [48]  */	INVALID,		INVALID,		TNSZ("vblendvps",VEX_RMRX,8),	TNSZ("vblendvpd",VEX_RMRX,16),
2252 /*  [4C]  */	TNSZ("vpblendvb",VEX_RMRX,16),INVALID,		INVALID,		INVALID,
2253 
2254 /*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
2255 /*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
2256 /*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
2257 /*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2258 
2259 /*  [60]  */	TNSZ("vpcmpestrm",VEX_MXI,16),TNSZ("vpcmpestri",VEX_MXI,16),TNSZ("vpcmpistrm",VEX_MXI,16),TNSZ("vpcmpistri",VEX_MXI,16),
2260 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
2261 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
2262 /*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2263 
2264 /*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
2265 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
2266 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
2267 /*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2268 
2269 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
2270 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
2271 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
2272 /*  [8C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2273 
2274 /*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
2275 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
2276 /*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
2277 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2278 
2279 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2280 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2281 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2282 /*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2283 
2284 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2285 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2286 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2287 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2288 
2289 /*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2290 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2291 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2292 /*  [CC]  */	INVALID,		INVALID,		TNS("vgf2p8affineqb",VEX_RMRX),TNS("vgf2p8affineinvqb",VEX_RMRX),
2293 
2294 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2295 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2296 /*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2297 /*  [DC]  */	INVALID,		INVALID,		INVALID,		TNSZ("vaeskeygenassist",VEX_MXI,16),
2298 
2299 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2300 /*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2301 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2302 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2303 
2304 /*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2305 /*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2306 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2307 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2308 };
2309 
2310 /*
2311  *	Decode table for 0x0F0D which uses the first byte of the mod_rm to
2312  *	indicate a sub-code.
2313  */
2314 const instable_t dis_op0F0D[8] = {
2315 /*  [00]  */	INVALID,		TNS("prefetchw",PREF),	TNS("prefetchwt1",PREF),INVALID,
2316 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
2317 };
2318 
2319 /*
2320  *	Decode table for 0x0F opcodes
2321  */
2322 
2323 const instable_t dis_op0F[16][16] = {
2324 {
2325 /*  [00]  */	IND(dis_op0F00),	IND(dis_op0F01),	TNS("lar",MR),		TNS("lsl",MR),
2326 /*  [04]  */	INVALID,		TNS("syscall",NORM),	TNS("clts",NORM),	TNS("sysret",NORM),
2327 /*  [08]  */	TNS("invd",NORM),	TNS("wbinvd",NORM),	INVALID,		TNS("ud2",NORM),
2328 /*  [0C]  */	INVALID,		IND(dis_op0F0D),	INVALID,		INVALID,
2329 }, {
2330 /*  [10]  */	TNSZ("movups",XMMO,16),	TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8),	TNSZ("movlps",XMMOS,8),
2331 /*  [14]  */	TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8),
2332 /*  [18]  */	IND(dis_op0F18),	INVALID,		INVALID,		INVALID,
2333 /*  [1C]  */	INVALID,		INVALID,		INVALID,		TS("nop",Mw),
2334 }, {
2335 /*  [20]  */	TSy("mov",SREG),	TSy("mov",SREG),	TSy("mov",SREG),	TSy("mov",SREG),
2336 /*  [24]  */	TSx("mov",SREG),	INVALID,		TSx("mov",SREG),	INVALID,
2337 /*  [28]  */	TNSZ("movaps",XMMO,16),	TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16),
2338 /*  [2C]  */	TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4),
2339 }, {
2340 /*  [30]  */	TNS("wrmsr",NORM),	TNS("rdtsc",NORM),	TNS("rdmsr",NORM),	TNS("rdpmc",NORM),
2341 /*  [34]  */	TNS("sysenter",NORM),	TNS("sysexit",NORM),	INVALID,		INVALID,
2342 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
2343 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2344 }, {
2345 /*  [40]  */	TS("cmovx.o",MR),	TS("cmovx.no",MR),	TS("cmovx.b",MR),	TS("cmovx.ae",MR),
2346 /*  [44]  */	TS("cmovx.e",MR),	TS("cmovx.ne",MR),	TS("cmovx.be",MR),	TS("cmovx.a",MR),
2347 /*  [48]  */	TS("cmovx.s",MR),	TS("cmovx.ns",MR),	TS("cmovx.pe",MR),	TS("cmovx.po",MR),
2348 /*  [4C]  */	TS("cmovx.l",MR),	TS("cmovx.ge",MR),	TS("cmovx.le",MR),	TS("cmovx.g",MR),
2349 }, {
2350 /*  [50]  */	TNS("movmskps",XMMOX3),	TNSZ("sqrtps",XMMO,16),	TNSZ("rsqrtps",XMMO,16),TNSZ("rcpps",XMMO,16),
2351 /*  [54]  */	TNSZ("andps",XMMO,16),	TNSZ("andnps",XMMO,16),	TNSZ("orps",XMMO,16),	TNSZ("xorps",XMMO,16),
2352 /*  [58]  */	TNSZ("addps",XMMO,16),	TNSZ("mulps",XMMO,16),	TNSZ("cvtps2pd",XMMO,8),TNSZ("cvtdq2ps",XMMO,16),
2353 /*  [5C]  */	TNSZ("subps",XMMO,16),	TNSZ("minps",XMMO,16),	TNSZ("divps",XMMO,16),	TNSZ("maxps",XMMO,16),
2354 }, {
2355 /*  [60]  */	TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8),
2356 /*  [64]  */	TNSZ("pcmpgtb",MMO,8),	TNSZ("pcmpgtw",MMO,8),	TNSZ("pcmpgtd",MMO,8),	TNSZ("packuswb",MMO,8),
2357 /*  [68]  */	TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8),
2358 /*  [6C]  */	TNSZ("INVALID",MMO,0),	TNSZ("INVALID",MMO,0),	TNSZ("movd",MMO,4),	TNSZ("movq",MMO,8),
2359 }, {
2360 /*  [70]  */	TNSZ("pshufw",MMOPM,8),	TNS("psrXXX",MR),	TNS("psrXXX",MR),	TNS("psrXXX",MR),
2361 /*  [74]  */	TNSZ("pcmpeqb",MMO,8),	TNSZ("pcmpeqw",MMO,8),	TNSZ("pcmpeqd",MMO,8),	TNS("emms",NORM),
2362 /*  [78]  */	TNSy("vmread",RM),	TNSy("vmwrite",MR),	INVALID,		INVALID,
2363 /*  [7C]  */	INVALID,		INVALID,		TNSZ("movd",MMOS,4),	TNSZ("movq",MMOS,8),
2364 }, {
2365 /*  [80]  */	TNS("jo",D),		TNS("jno",D),		TNS("jb",D),		TNS("jae",D),
2366 /*  [84]  */	TNS("je",D),		TNS("jne",D),		TNS("jbe",D),		TNS("ja",D),
2367 /*  [88]  */	TNS("js",D),		TNS("jns",D),		TNS("jp",D),		TNS("jnp",D),
2368 /*  [8C]  */	TNS("jl",D),		TNS("jge",D),		TNS("jle",D),		TNS("jg",D),
2369 }, {
2370 /*  [90]  */	TNS("seto",Mb),		TNS("setno",Mb),	TNS("setb",Mb),		TNS("setae",Mb),
2371 /*  [94]  */	TNS("sete",Mb),		TNS("setne",Mb),	TNS("setbe",Mb),	TNS("seta",Mb),
2372 /*  [98]  */	TNS("sets",Mb),		TNS("setns",Mb),	TNS("setp",Mb),		TNS("setnp",Mb),
2373 /*  [9C]  */	TNS("setl",Mb),		TNS("setge",Mb),	TNS("setle",Mb),	TNS("setg",Mb),
2374 }, {
2375 /*  [A0]  */	TSp("push",LSEG),	TSp("pop",LSEG),	TNS("cpuid",NORM),	TS("bt",RMw),
2376 /*  [A4]  */	TS("shld",DSHIFT),	TS("shld",DSHIFTcl),	INVALID,		INVALID,
2377 /*  [A8]  */	TSp("push",LSEG),	TSp("pop",LSEG),	TNS("rsm",NORM),	TS("bts",RMw),
2378 /*  [AC]  */	TS("shrd",DSHIFT),	TS("shrd",DSHIFTcl),	IND(dis_op0FAE),	TS("imul",MRw),
2379 }, {
2380 /*  [B0]  */	TNS("cmpxchgb",RMw),	TS("cmpxchg",RMw),	TS("lss",MR),		TS("btr",RMw),
2381 /*  [B4]  */	TS("lfs",MR),		TS("lgs",MR),		TS("movzb",MOVZ),	TNS("movzwl",MOVZ),
2382 /*  [B8]  */	TNS("INVALID",MRw),	INVALID,		IND(dis_op0FBA),	TS("btc",RMw),
2383 /*  [BC]  */	TS("bsf",MRw),		TS("bsr",MRw),		TS("movsb",MOVZ),	TNS("movswl",MOVZ),
2384 }, {
2385 /*  [C0]  */	TNS("xaddb",XADDB),	TS("xadd",RMw),		TNSZ("cmpps",XMMOPM,16),TNS("movnti",RM),
2386 /*  [C4]  */	TNSZ("pinsrw",MMOPRM,2),TNS("pextrw",MMO3P),	TNSZ("shufps",XMMOPM,16),IND(dis_op0FC7),
2387 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2388 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2389 }, {
2390 /*  [D0]  */	INVALID,		TNSZ("psrlw",MMO,8),	TNSZ("psrld",MMO,8),	TNSZ("psrlq",MMO,8),
2391 /*  [D4]  */	TNSZ("paddq",MMO,8),	TNSZ("pmullw",MMO,8),	TNSZ("INVALID",MMO,0),	TNS("pmovmskb",MMOM3),
2392 /*  [D8]  */	TNSZ("psubusb",MMO,8),	TNSZ("psubusw",MMO,8),	TNSZ("pminub",MMO,8),	TNSZ("pand",MMO,8),
2393 /*  [DC]  */	TNSZ("paddusb",MMO,8),	TNSZ("paddusw",MMO,8),	TNSZ("pmaxub",MMO,8),	TNSZ("pandn",MMO,8),
2394 }, {
2395 /*  [E0]  */	TNSZ("pavgb",MMO,8),	TNSZ("psraw",MMO,8),	TNSZ("psrad",MMO,8),	TNSZ("pavgw",MMO,8),
2396 /*  [E4]  */	TNSZ("pmulhuw",MMO,8),	TNSZ("pmulhw",MMO,8),	TNS("INVALID",XMMO),	TNSZ("movntq",MMOMS,8),
2397 /*  [E8]  */	TNSZ("psubsb",MMO,8),	TNSZ("psubsw",MMO,8),	TNSZ("pminsw",MMO,8),	TNSZ("por",MMO,8),
2398 /*  [EC]  */	TNSZ("paddsb",MMO,8),	TNSZ("paddsw",MMO,8),	TNSZ("pmaxsw",MMO,8),	TNSZ("pxor",MMO,8),
2399 }, {
2400 /*  [F0]  */	INVALID,		TNSZ("psllw",MMO,8),	TNSZ("pslld",MMO,8),	TNSZ("psllq",MMO,8),
2401 /*  [F4]  */	TNSZ("pmuludq",MMO,8),	TNSZ("pmaddwd",MMO,8),	TNSZ("psadbw",MMO,8),	TNSZ("maskmovq",MMOIMPL,8),
2402 /*  [F8]  */	TNSZ("psubb",MMO,8),	TNSZ("psubw",MMO,8),	TNSZ("psubd",MMO,8),	TNSZ("psubq",MMO,8),
2403 /*  [FC]  */	TNSZ("paddb",MMO,8),	TNSZ("paddw",MMO,8),	TNSZ("paddd",MMO,8),	INVALID,
2404 } };
2405 
2406 const instable_t dis_opAVX0F[16][16] = {
2407 {
2408 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
2409 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
2410 /*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
2411 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2412 }, {
2413 /*  [10]  */	TNSZ("vmovups",VEX_MX,16),	TNSZ("vmovups",VEX_RM,16),TNSZ("vmovlps",VEX_RMrX,8),	TNSZ("vmovlps",VEX_RM,8),
2414 /*  [14]  */	TNSZ("vunpcklps",VEX_RMrX,16),TNSZ("vunpckhps",VEX_RMrX,16),TNSZ("vmovhps",VEX_RMrX,8),TNSZ("vmovhps",VEX_RM,8),
2415 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
2416 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2417 }, {
2418 /*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
2419 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
2420 /*  [28]  */	TNSZ("vmovaps",VEX_MX,16),	TNSZ("vmovaps",VEX_RX,16),INVALID,		TNSZ("vmovntps",VEX_RM,16),
2421 /*  [2C]  */	INVALID,		INVALID,		TNSZ("vucomiss",VEX_MX,4),TNSZ("vcomiss",VEX_MX,4),
2422 }, {
2423 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
2424 /*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
2425 /*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
2426 /*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2427 }, {
2428 /*  [40]  */	INVALID,		TSvo("kand",VEX_RMX),	TSvo("kandn",VEX_RMX),		INVALID,
2429 /*  [44]  */	TSvo("knot",VEX_MX),	TSvo("kor",VEX_RMX),	TSvo("kxnor",VEX_RMX),		TSvo("kxor",VEX_RMX),
2430 /*  [48]  */	INVALID,		INVALID,		TSvo("kadd",VEX_RMX),		TSvo("kunpck",VEX_RMX),
2431 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2432 }, {
2433 /*  [50]  */	TNS("vmovmskps",VEX_MR),	TNSZ("vsqrtps",VEX_MX,16),	TNSZ("vrsqrtps",VEX_MX,16),TNSZ("vrcpps",VEX_MX,16),
2434 /*  [54]  */	TNSZ("vandps",VEX_RMrX,16),	TNSZ("vandnps",VEX_RMrX,16),	TNSZ("vorps",VEX_RMrX,16),	TNSZ("vxorps",VEX_RMrX,16),
2435 /*  [58]  */	TNSZ("vaddps",VEX_RMrX,16),	TNSZ("vmulps",VEX_RMrX,16),	TNSZ("vcvtps2pd",VEX_MX,8),TNSZ("vcvtdq2ps",VEX_MX,16),
2436 /*  [5C]  */	TNSZ("vsubps",VEX_RMrX,16),	TNSZ("vminps",VEX_RMrX,16),	TNSZ("vdivps",VEX_RMrX,16),	TNSZ("vmaxps",VEX_RMrX,16),
2437 }, {
2438 /*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
2439 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
2440 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
2441 /*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2442 }, {
2443 /*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
2444 /*  [74]  */	INVALID,		INVALID,		INVALID,		TNS("vzeroupper", VEX_NONE),
2445 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
2446 /*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2447 }, {
2448 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
2449 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
2450 /*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
2451 /*  [8C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2452 }, {
2453 /*  [90]  */	TSvo("kmov",VEX_KRM),	TSvo("kmov",VEX_KMR),	TSvo("kmov",VEX_KRR),		TSvo("kmov",VEX_MR),
2454 /*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
2455 /*  [98]  */	TSvo("kortest",VEX_MX),	TSvo("ktest",VEX_MX),	INVALID,		INVALID,
2456 /*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2457 }, {
2458 /*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2459 /*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2460 /*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2461 /*  [AC]  */	INVALID,		INVALID,		TNSZ("vldmxcsr",VEX_MO,2),		INVALID,
2462 }, {
2463 /*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2464 /*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2465 /*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2466 /*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2467 }, {
2468 /*  [C0]  */	INVALID,		INVALID,		TNSZ("vcmpps",VEX_RMRX,16),INVALID,
2469 /*  [C4]  */	INVALID,		INVALID,		TNSZ("vshufps",VEX_RMRX,16),INVALID,
2470 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2471 /*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2472 }, {
2473 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2474 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2475 /*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2476 /*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2477 }, {
2478 /*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2479 /*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2480 /*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2481 /*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2482 }, {
2483 /*  [F0]  */	INVALID,		INVALID,		TNSZvr("andn",VEX_RMrX,5),TNSZvr("bls",BLS,5),
2484 /*  [F4]  */	INVALID,		TNSZvr("bzhi",VEX_VRMrX,5),INVALID,		TNSZvr("bextr",VEX_VRMrX,5),
2485 /*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2486 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2487 } };
2488 
2489 /*
2490  *	Decode table for 0x80 opcodes
2491  */
2492 
2493 const instable_t dis_op80[8] = {
2494 
2495 /*  [0]  */	TNS("addb",IMlw),	TNS("orb",IMw),		TNS("adcb",IMlw),	TNS("sbbb",IMlw),
2496 /*  [4]  */	TNS("andb",IMw),	TNS("subb",IMlw),	TNS("xorb",IMw),	TNS("cmpb",IMlw),
2497 };
2498 
2499 
2500 /*
2501  *	Decode table for 0x81 opcodes.
2502  */
2503 
2504 const instable_t dis_op81[8] = {
2505 
2506 /*  [0]  */	TS("add",IMlw),		TS("or",IMw),		TS("adc",IMlw),		TS("sbb",IMlw),
2507 /*  [4]  */	TS("and",IMw),		TS("sub",IMlw),		TS("xor",IMw),		TS("cmp",IMlw),
2508 };
2509 
2510 
2511 /*
2512  *	Decode table for 0x82 opcodes.
2513  */
2514 
2515 const instable_t dis_op82[8] = {
2516 
2517 /*  [0]  */	TNSx("addb",IMlw),	TNSx("orb",IMlw),	TNSx("adcb",IMlw),	TNSx("sbbb",IMlw),
2518 /*  [4]  */	TNSx("andb",IMlw),	TNSx("subb",IMlw),	TNSx("xorb",IMlw),	TNSx("cmpb",IMlw),
2519 };
2520 /*
2521  *	Decode table for 0x83 opcodes.
2522  */
2523 
2524 const instable_t dis_op83[8] = {
2525 
2526 /*  [0]  */	TS("add",IMlw),		TS("or",IMlw),		TS("adc",IMlw),		TS("sbb",IMlw),
2527 /*  [4]  */	TS("and",IMlw),		TS("sub",IMlw),		TS("xor",IMlw),		TS("cmp",IMlw),
2528 };
2529 
2530 /*
2531  *	Decode table for 0xC0 opcodes.
2532  */
2533 
2534 const instable_t dis_opC0[8] = {
2535 
2536 /*  [0]  */	TNS("rolb",MvI),	TNS("rorb",MvI),	TNS("rclb",MvI),	TNS("rcrb",MvI),
2537 /*  [4]  */	TNS("shlb",MvI),	TNS("shrb",MvI),	INVALID,		TNS("sarb",MvI),
2538 };
2539 
2540 /*
2541  *	Decode table for 0xD0 opcodes.
2542  */
2543 
2544 const instable_t dis_opD0[8] = {
2545 
2546 /*  [0]  */	TNS("rolb",Mv),		TNS("rorb",Mv),		TNS("rclb",Mv),		TNS("rcrb",Mv),
2547 /*  [4]  */	TNS("shlb",Mv),		TNS("shrb",Mv),		TNS("salb",Mv),		TNS("sarb",Mv),
2548 };
2549 
2550 /*
2551  *	Decode table for 0xC1 opcodes.
2552  *	186 instruction set
2553  */
2554 
2555 const instable_t dis_opC1[8] = {
2556 
2557 /*  [0]  */	TS("rol",MvI),		TS("ror",MvI),		TS("rcl",MvI),		TS("rcr",MvI),
2558 /*  [4]  */	TS("shl",MvI),		TS("shr",MvI),		TS("sal",MvI),		TS("sar",MvI),
2559 };
2560 
2561 /*
2562  *	Decode table for 0xD1 opcodes.
2563  */
2564 
2565 const instable_t dis_opD1[8] = {
2566 
2567 /*  [0]  */	TS("rol",Mv),		TS("ror",Mv),		TS("rcl",Mv),		TS("rcr",Mv),
2568 /*  [4]  */	TS("shl",Mv),		TS("shr",Mv),		TS("sal",Mv),		TS("sar",Mv),
2569 };
2570 
2571 
2572 /*
2573  *	Decode table for 0xD2 opcodes.
2574  */
2575 
2576 const instable_t dis_opD2[8] = {
2577 
2578 /*  [0]  */	TNS("rolb",Mv),		TNS("rorb",Mv),		TNS("rclb",Mv),		TNS("rcrb",Mv),
2579 /*  [4]  */	TNS("shlb",Mv),		TNS("shrb",Mv),		TNS("salb",Mv),		TNS("sarb",Mv),
2580 };
2581 /*
2582  *	Decode table for 0xD3 opcodes.
2583  */
2584 
2585 const instable_t dis_opD3[8] = {
2586 
2587 /*  [0]  */	TS("rol",Mv),		TS("ror",Mv),		TS("rcl",Mv),		TS("rcr",Mv),
2588 /*  [4]  */	TS("shl",Mv),		TS("shr",Mv),		TS("salb",Mv),		TS("sar",Mv),
2589 };
2590 
2591 
2592 /*
2593  *	Decode table for 0xF6 opcodes.
2594  */
2595 
2596 const instable_t dis_opF6[8] = {
2597 
2598 /*  [0]  */	TNS("testb",IMw),	TNS("testb",IMw),	TNS("notb",Mw),		TNS("negb",Mw),
2599 /*  [4]  */	TNS("mulb",MA),		TNS("imulb",MA),	TNS("divb",MA),		TNS("idivb",MA),
2600 };
2601 
2602 
2603 /*
2604  *	Decode table for 0xF7 opcodes.
2605  */
2606 
2607 const instable_t dis_opF7[8] = {
2608 
2609 /*  [0]  */	TS("test",IMw),		TS("test",IMw),		TS("not",Mw),		TS("neg",Mw),
2610 /*  [4]  */	TS("mul",MA),		TS("imul",MA),		TS("div",MA),		TS("idiv",MA),
2611 };
2612 
2613 
2614 /*
2615  *	Decode table for 0xFE opcodes.
2616  */
2617 
2618 const instable_t dis_opFE[8] = {
2619 
2620 /*  [0]  */	TNS("incb",Mw),		TNS("decb",Mw),		INVALID,		INVALID,
2621 /*  [4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2622 };
2623 /*
2624  *	Decode table for 0xFF opcodes.
2625  */
2626 
2627 const instable_t dis_opFF[8] = {
2628 
2629 /*  [0]  */	TS("inc",Mw),		TS("dec",Mw),		TNSyp("call",INM),	TNS("lcall",INM),
2630 /*  [4]  */	TNSy("jmp",INM),	TNS("ljmp",INM),	TSp("push",M),		INVALID,
2631 };
2632 
2633 /* for 287 instructions, which are a mess to decode */
2634 
2635 const instable_t dis_opFP1n2[8][8] = {
2636 {
2637 /* bit pattern:	1101 1xxx MODxx xR/M */
2638 /*  [0,0] */	TNS("fadds",M),		TNS("fmuls",M),		TNS("fcoms",M),		TNS("fcomps",M),
2639 /*  [0,4] */	TNS("fsubs",M),		TNS("fsubrs",M),	TNS("fdivs",M),		TNS("fdivrs",M),
2640 }, {
2641 /*  [1,0]  */	TNS("flds",M),		INVALID,		TNS("fsts",M),		TNS("fstps",M),
2642 /*  [1,4]  */	TNSZ("fldenv",M,28),	TNSZ("fldcw",M,2),	TNSZ("fnstenv",M,28),	TNSZ("fnstcw",M,2),
2643 }, {
2644 /*  [2,0]  */	TNS("fiaddl",M),	TNS("fimull",M),	TNS("ficoml",M),	TNS("ficompl",M),
2645 /*  [2,4]  */	TNS("fisubl",M),	TNS("fisubrl",M),	TNS("fidivl",M),	TNS("fidivrl",M),
2646 }, {
2647 /*  [3,0]  */	TNS("fildl",M),		TNSZ("tisttpl",M,4),	TNS("fistl",M),		TNS("fistpl",M),
2648 /*  [3,4]  */	INVALID,		TNSZ("fldt",M,10),	INVALID,		TNSZ("fstpt",M,10),
2649 }, {
2650 /*  [4,0]  */	TNSZ("faddl",M,8),	TNSZ("fmull",M,8),	TNSZ("fcoml",M,8),	TNSZ("fcompl",M,8),
2651 /*  [4,1]  */	TNSZ("fsubl",M,8),	TNSZ("fsubrl",M,8),	TNSZ("fdivl",M,8),	TNSZ("fdivrl",M,8),
2652 }, {
2653 /*  [5,0]  */	TNSZ("fldl",M,8),	TNSZ("fisttpll",M,8),	TNSZ("fstl",M,8),	TNSZ("fstpl",M,8),
2654 /*  [5,4]  */	TNSZ("frstor",M,108),	INVALID,		TNSZ("fnsave",M,108),	TNSZ("fnstsw",M,2),
2655 }, {
2656 /*  [6,0]  */	TNSZ("fiadd",M,2),	TNSZ("fimul",M,2),	TNSZ("ficom",M,2),	TNSZ("ficomp",M,2),
2657 /*  [6,4]  */	TNSZ("fisub",M,2),	TNSZ("fisubr",M,2),	TNSZ("fidiv",M,2),	TNSZ("fidivr",M,2),
2658 }, {
2659 /*  [7,0]  */	TNSZ("fild",M,2),	TNSZ("fisttp",M,2),	TNSZ("fist",M,2),	TNSZ("fistp",M,2),
2660 /*  [7,4]  */	TNSZ("fbld",M,10),	TNSZ("fildll",M,8),	TNSZ("fbstp",M,10),	TNSZ("fistpll",M,8),
2661 } };
2662 
2663 const instable_t dis_opFP3[8][8] = {
2664 {
2665 /* bit  pattern:	1101 1xxx 11xx xREG */
2666 /*  [0,0]  */	TNS("fadd",FF),		TNS("fmul",FF),		TNS("fcom",F),		TNS("fcomp",F),
2667 /*  [0,4]  */	TNS("fsub",FF),		TNS("fsubr",FF),	TNS("fdiv",FF),		TNS("fdivr",FF),
2668 }, {
2669 /*  [1,0]  */	TNS("fld",F),		TNS("fxch",F),		TNS("fnop",NORM),	TNS("fstp",F),
2670 /*  [1,4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2671 }, {
2672 /*  [2,0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2673 /*  [2,4]  */	INVALID,		TNS("fucompp",NORM),	INVALID,		INVALID,
2674 }, {
2675 /*  [3,0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2676 /*  [3,4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2677 }, {
2678 /*  [4,0]  */	TNS("fadd",FF),		TNS("fmul",FF),		TNS("fcom",F),		TNS("fcomp",F),
2679 /*  [4,4]  */	TNS("fsub",FF),		TNS("fsubr",FF),	TNS("fdiv",FF),		TNS("fdivr",FF),
2680 }, {
2681 /*  [5,0]  */	TNS("ffree",F),		TNS("fxch",F),		TNS("fst",F),		TNS("fstp",F),
2682 /*  [5,4]  */	TNS("fucom",F),		TNS("fucomp",F),	INVALID,		INVALID,
2683 }, {
2684 /*  [6,0]  */	TNS("faddp",FF),	TNS("fmulp",FF),	TNS("fcomp",F),		TNS("fcompp",NORM),
2685 /*  [6,4]  */	TNS("fsubp",FF),	TNS("fsubrp",FF),	TNS("fdivp",FF),	TNS("fdivrp",FF),
2686 }, {
2687 /*  [7,0]  */	TNS("ffreep",F),		TNS("fxch",F),		TNS("fstp",F),		TNS("fstp",F),
2688 /*  [7,4]  */	TNS("fnstsw",M),	TNS("fucomip",FFC),	TNS("fcomip",FFC),	INVALID,
2689 } };
2690 
2691 const instable_t dis_opFP4[4][8] = {
2692 {
2693 /* bit pattern:	1101 1001 111x xxxx */
2694 /*  [0,0]  */	TNS("fchs",NORM),	TNS("fabs",NORM),	INVALID,		INVALID,
2695 /*  [0,4]  */	TNS("ftst",NORM),	TNS("fxam",NORM),	TNS("ftstp",NORM),	INVALID,
2696 }, {
2697 /*  [1,0]  */	TNS("fld1",NORM),	TNS("fldl2t",NORM),	TNS("fldl2e",NORM),	TNS("fldpi",NORM),
2698 /*  [1,4]  */	TNS("fldlg2",NORM),	TNS("fldln2",NORM),	TNS("fldz",NORM),	INVALID,
2699 }, {
2700 /*  [2,0]  */	TNS("f2xm1",NORM),	TNS("fyl2x",NORM),	TNS("fptan",NORM),	TNS("fpatan",NORM),
2701 /*  [2,4]  */	TNS("fxtract",NORM),	TNS("fprem1",NORM),	TNS("fdecstp",NORM),	TNS("fincstp",NORM),
2702 }, {
2703 /*  [3,0]  */	TNS("fprem",NORM),	TNS("fyl2xp1",NORM),	TNS("fsqrt",NORM),	TNS("fsincos",NORM),
2704 /*  [3,4]  */	TNS("frndint",NORM),	TNS("fscale",NORM),	TNS("fsin",NORM),	TNS("fcos",NORM),
2705 } };
2706 
2707 const instable_t dis_opFP5[8] = {
2708 /* bit pattern:	1101 1011 111x xxxx */
2709 /*  [0]  */	TNS("feni",NORM),	TNS("fdisi",NORM),	TNS("fnclex",NORM),	TNS("fninit",NORM),
2710 /*  [4]  */	TNS("fsetpm",NORM),	TNS("frstpm",NORM),	INVALID,		INVALID,
2711 };
2712 
2713 const instable_t dis_opFP6[8] = {
2714 /* bit pattern:	1101 1011 11yy yxxx */
2715 /*  [00]  */	TNS("fcmov.nb",FF),	TNS("fcmov.ne",FF),	TNS("fcmov.nbe",FF),	TNS("fcmov.nu",FF),
2716 /*  [04]  */	INVALID,		TNS("fucomi",F),	TNS("fcomi",F),		INVALID,
2717 };
2718 
2719 const instable_t dis_opFP7[8] = {
2720 /* bit pattern:	1101 1010 11yy yxxx */
2721 /*  [00]  */	TNS("fcmov.b",FF),	TNS("fcmov.e",FF),	TNS("fcmov.be",FF),	TNS("fcmov.u",FF),
2722 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
2723 };
2724 
2725 /*
2726  *	Main decode table for the op codes.  The first two nibbles
2727  *	will be used as an index into the table.  If there is a
2728  *	a need to further decode an instruction, the array to be
2729  *	referenced is indicated with the other two entries being
2730  *	empty.
2731  */
2732 
2733 const instable_t dis_distable[16][16] = {
2734 {
2735 /* [0,0] */	TNS("addb",RMw),	TS("add",RMw),		TNS("addb",MRw),	TS("add",MRw),
2736 /* [0,4] */	TNS("addb",IA),		TS("add",IA),		TSx("push",SEG),	TSx("pop",SEG),
2737 /* [0,8] */	TNS("orb",RMw),		TS("or",RMw),		TNS("orb",MRw),		TS("or",MRw),
2738 /* [0,C] */	TNS("orb",IA),		TS("or",IA),		TSx("push",SEG),	IND(dis_op0F),
2739 }, {
2740 /* [1,0] */	TNS("adcb",RMw),	TS("adc",RMw),		TNS("adcb",MRw),	TS("adc",MRw),
2741 /* [1,4] */	TNS("adcb",IA),		TS("adc",IA),		TSx("push",SEG),	TSx("pop",SEG),
2742 /* [1,8] */	TNS("sbbb",RMw),	TS("sbb",RMw),		TNS("sbbb",MRw),	TS("sbb",MRw),
2743 /* [1,C] */	TNS("sbbb",IA),		TS("sbb",IA),		TSx("push",SEG),	TSx("pop",SEG),
2744 }, {
2745 /* [2,0] */	TNS("andb",RMw),	TS("and",RMw),		TNS("andb",MRw),	TS("and",MRw),
2746 /* [2,4] */	TNS("andb",IA),		TS("and",IA),		TNSx("%es:",OVERRIDE),	TNSx("daa",NORM),
2747 /* [2,8] */	TNS("subb",RMw),	TS("sub",RMw),		TNS("subb",MRw),	TS("sub",MRw),
2748 /* [2,C] */	TNS("subb",IA),		TS("sub",IA),		TNS("%cs:",OVERRIDE),	TNSx("das",NORM),
2749 }, {
2750 /* [3,0] */	TNS("xorb",RMw),	TS("xor",RMw),		TNS("xorb",MRw),	TS("xor",MRw),
2751 /* [3,4] */	TNS("xorb",IA),		TS("xor",IA),		TNSx("%ss:",OVERRIDE),	TNSx("aaa",NORM),
2752 /* [3,8] */	TNS("cmpb",RMw),	TS("cmp",RMw),		TNS("cmpb",MRw),	TS("cmp",MRw),
2753 /* [3,C] */	TNS("cmpb",IA),		TS("cmp",IA),		TNSx("%ds:",OVERRIDE),	TNSx("aas",NORM),
2754 }, {
2755 /* [4,0] */	TSx("inc",R),		TSx("inc",R),		TSx("inc",R),		TSx("inc",R),
2756 /* [4,4] */	TSx("inc",R),		TSx("inc",R),		TSx("inc",R),		TSx("inc",R),
2757 /* [4,8] */	TSx("dec",R),		TSx("dec",R),		TSx("dec",R),		TSx("dec",R),
2758 /* [4,C] */	TSx("dec",R),		TSx("dec",R),		TSx("dec",R),		TSx("dec",R),
2759 }, {
2760 /* [5,0] */	TSp("push",R),		TSp("push",R),		TSp("push",R),		TSp("push",R),
2761 /* [5,4] */	TSp("push",R),		TSp("push",R),		TSp("push",R),		TSp("push",R),
2762 /* [5,8] */	TSp("pop",R),		TSp("pop",R),		TSp("pop",R),		TSp("pop",R),
2763 /* [5,C] */	TSp("pop",R),		TSp("pop",R),		TSp("pop",R),		TSp("pop",R),
2764 }, {
2765 /* [6,0] */	TSZx("pusha",IMPLMEM,28),TSZx("popa",IMPLMEM,28), TSx("bound",RM),	TNS("arpl",RMw),
2766 /* [6,4] */	TNS("%fs:",OVERRIDE),	TNS("%gs:",OVERRIDE),	TNS("data16",DM),	TNS("addr16",AM),
2767 /* [6,8] */	TSp("push",I),		TS("imul",IMUL),	TSp("push",Ib),	TS("imul",IMUL),
2768 /* [6,C] */	TNSZ("insb",IMPLMEM,1),	TSZ("ins",IMPLMEM,4),	TNSZ("outsb",IMPLMEM,1),TSZ("outs",IMPLMEM,4),
2769 }, {
2770 /* [7,0] */	TNSy("jo",BD),		TNSy("jno",BD),		TNSy("jb",BD),		TNSy("jae",BD),
2771 /* [7,4] */	TNSy("je",BD),		TNSy("jne",BD),		TNSy("jbe",BD),		TNSy("ja",BD),
2772 /* [7,8] */	TNSy("js",BD),		TNSy("jns",BD),		TNSy("jp",BD),		TNSy("jnp",BD),
2773 /* [7,C] */	TNSy("jl",BD),		TNSy("jge",BD),		TNSy("jle",BD),		TNSy("jg",BD),
2774 }, {
2775 /* [8,0] */	IND(dis_op80),		IND(dis_op81),		INDx(dis_op82),		IND(dis_op83),
2776 /* [8,4] */	TNS("testb",RMw),	TS("test",RMw),		TNS("xchgb",RMw),	TS("xchg",RMw),
2777 /* [8,8] */	TNS("movb",RMw),	TS("mov",RMw),		TNS("movb",MRw),	TS("mov",MRw),
2778 /* [8,C] */	TNS("movw",SM),		TS("lea",MR),		TNS("movw",MS),		TSp("pop",M),
2779 }, {
2780 /* [9,0] */	TNS("nop",NORM),	TS("xchg",RA),		TS("xchg",RA),		TS("xchg",RA),
2781 /* [9,4] */	TS("xchg",RA),		TS("xchg",RA),		TS("xchg",RA),		TS("xchg",RA),
2782 /* [9,8] */	TNS("cXtX",CBW),	TNS("cXtX",CWD),	TNSx("lcall",SO),	TNS("fwait",NORM),
2783 /* [9,C] */	TSZy("pushf",IMPLMEM,4),TSZy("popf",IMPLMEM,4),	TNS("sahf",NORM),	TNS("lahf",NORM),
2784 }, {
2785 /* [A,0] */	TNS("movb",OA),		TS("mov",OA),		TNS("movb",AO),		TS("mov",AO),
2786 /* [A,4] */	TNSZ("movsb",SD,1),	TS("movs",SD),		TNSZ("cmpsb",SD,1),	TS("cmps",SD),
2787 /* [A,8] */	TNS("testb",IA),	TS("test",IA),		TNS("stosb",AD),	TS("stos",AD),
2788 /* [A,C] */	TNS("lodsb",SA),	TS("lods",SA),		TNS("scasb",AD),	TS("scas",AD),
2789 }, {
2790 /* [B,0] */	TNS("movb",IR),		TNS("movb",IR),		TNS("movb",IR),		TNS("movb",IR),
2791 /* [B,4] */	TNS("movb",IR),		TNS("movb",IR),		TNS("movb",IR),		TNS("movb",IR),
2792 /* [B,8] */	TS("mov",IR),		TS("mov",IR),		TS("mov",IR),		TS("mov",IR),
2793 /* [B,C] */	TS("mov",IR),		TS("mov",IR),		TS("mov",IR),		TS("mov",IR),
2794 }, {
2795 /* [C,0] */	IND(dis_opC0),		IND(dis_opC1),		TNSyp("ret",RET),	TNSyp("ret",NORM),
2796 /* [C,4] */	TNSx("les",MR),		TNSx("lds",MR),		TNS("movb",IMw),	TS("mov",IMw),
2797 /* [C,8] */	TNSyp("enter",ENTER),	TNSyp("leave",NORM),	TNS("lret",RET),	TNS("lret",NORM),
2798 /* [C,C] */	TNS("int",INT3),	TNS("int",INTx),	TNSx("into",NORM),	TNS("iret",NORM),
2799 }, {
2800 /* [D,0] */	IND(dis_opD0),		IND(dis_opD1),		IND(dis_opD2),		IND(dis_opD3),
2801 /* [D,4] */	TNSx("aam",U),		TNSx("aad",U),		TNSx("falc",NORM),	TNSZ("xlat",IMPLMEM,1),
2802 
2803 /* 287 instructions.  Note that although the indirect field		*/
2804 /* indicates opFP1n2 for further decoding, this is not necessarily	*/
2805 /* the case since the opFP arrays are not partitioned according to key1	*/
2806 /* and key2.  opFP1n2 is given only to indicate that we haven't		*/
2807 /* finished decoding the instruction.					*/
2808 /* [D,8] */	IND(dis_opFP1n2),	IND(dis_opFP1n2),	IND(dis_opFP1n2),	IND(dis_opFP1n2),
2809 /* [D,C] */	IND(dis_opFP1n2),	IND(dis_opFP1n2),	IND(dis_opFP1n2),	IND(dis_opFP1n2),
2810 }, {
2811 /* [E,0] */	TNSy("loopnz",BD),	TNSy("loopz",BD),	TNSy("loop",BD),	TNSy("jcxz",BD),
2812 /* [E,4] */	TNS("inb",P),		TS("in",P),		TNS("outb",P),		TS("out",P),
2813 /* [E,8] */	TNSyp("call",D),	TNSy("jmp",D),		TNSx("ljmp",SO),		TNSy("jmp",BD),
2814 /* [E,C] */	TNS("inb",V),		TS("in",V),		TNS("outb",V),		TS("out",V),
2815 }, {
2816 /* [F,0] */	TNS("lock",LOCK),	TNS("icebp", NORM),	TNS("repnz",PREFIX),	TNS("repz",PREFIX),
2817 /* [F,4] */	TNS("hlt",NORM),	TNS("cmc",NORM),	IND(dis_opF6),		IND(dis_opF7),
2818 /* [F,8] */	TNS("clc",NORM),	TNS("stc",NORM),	TNS("cli",NORM),	TNS("sti",NORM),
2819 /* [F,C] */	TNS("cld",NORM),	TNS("std",NORM),	IND(dis_opFE),		IND(dis_opFF),
2820 } };
2821 
2822 /* END CSTYLED */
2823 
2824 /*
2825  * common functions to decode and disassemble an x86 or amd64 instruction
2826  */
2827 
2828 /*
2829  * These are the individual fields of a REX prefix. Note that a REX
2830  * prefix with none of these set is still needed to:
2831  *	- use the MOVSXD (sign extend 32 to 64 bits) instruction
2832  *	- access the %sil, %dil, %bpl, %spl registers
2833  */
2834 #define	REX_W 0x08	/* 64 bit operand size when set */
2835 #define	REX_R 0x04	/* high order bit extension of ModRM reg field */
2836 #define	REX_X 0x02	/* high order bit extension of SIB index field */
2837 #define	REX_B 0x01	/* extends ModRM r_m, SIB base, or opcode reg */
2838 
2839 /*
2840  * These are the individual fields of a VEX/EVEX prefix.
2841  */
2842 #define	VEX_R 0x08	/* REX.R in 1's complement form */
2843 #define	VEX_X 0x04	/* REX.X in 1's complement form */
2844 #define	VEX_B 0x02	/* REX.B in 1's complement form */
2845 
2846 /* Additional EVEX prefix definitions */
2847 #define	EVEX_R 0x01	/* REX.R' in 1's complement form */
2848 #define	EVEX_OPREG_MASK 0x7 /* bit mask for selecting opmask register number */
2849 #define	EVEX_ZERO_MASK 0x80 /* bit mask for selecting zeroing */
2850 
2851 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector */
2852 #define	VEX_L 0x04
2853 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector, 2: 512-bit */
2854 #define	EVEX_L 0x06	/* bit mask for EVEX.L'L vector length/RC */
2855 #define	VEX_W 0x08	/* opcode specific, use like REX.W */
2856 #define	VEX_m 0x1F	/* VEX m-mmmm field */
2857 #define	EVEX_m 0x3	/* EVEX mm field */
2858 #define	VEX_v 0x78	/* VEX/EVEX register specifier */
2859 #define	VEX_p 0x03	/* VEX pp field, opcode extension */
2860 
2861 /* VEX m-mmmm field, only used by three bytes prefix */
2862 #define	VEX_m_0F 0x01   /* implied 0F leading opcode byte */
2863 #define	VEX_m_0F38 0x02 /* implied 0F 38 leading opcode byte */
2864 #define	VEX_m_0F3A 0x03 /* implied 0F 3A leading opcode byte */
2865 
2866 /* VEX pp field, providing equivalent functionality of a SIMD prefix */
2867 #define	VEX_p_66 0x01
2868 #define	VEX_p_F3 0x02
2869 #define	VEX_p_F2 0x03
2870 
2871 /*
2872  * Even in 64 bit mode, usually only 4 byte immediate operands are supported.
2873  */
2874 static int isize[] = {1, 2, 4, 4};
2875 static int isize64[] = {1, 2, 4, 8};
2876 
2877 /*
2878  * Just a bunch of useful macros.
2879  */
2880 #define	WBIT(x)	(x & 0x1)		/* to get w bit	*/
2881 #define	REGNO(x) (x & 0x7)		/* to get 3 bit register */
2882 #define	VBIT(x)	((x)>>1 & 0x1)		/* to get 'v' bit */
2883 #define	OPSIZE(osize, wbit) ((wbit) ? isize[osize] : 1)
2884 #define	OPSIZE64(osize, wbit) ((wbit) ? isize64[osize] : 1)
2885 
2886 #define	REG_ONLY 3	/* mode to indicate a register operand (not memory) */
2887 
2888 #define	BYTE_OPND	0	/* w-bit value indicating byte register */
2889 #define	LONG_OPND	1	/* w-bit value indicating opnd_size register */
2890 #define	MM_OPND		2	/* "value" used to indicate a mmx reg */
2891 #define	XMM_OPND	3	/* "value" used to indicate a xmm reg */
2892 #define	SEG_OPND	4	/* "value" used to indicate a segment reg */
2893 #define	CONTROL_OPND	5	/* "value" used to indicate a control reg */
2894 #define	DEBUG_OPND	6	/* "value" used to indicate a debug reg */
2895 #define	TEST_OPND	7	/* "value" used to indicate a test reg */
2896 #define	WORD_OPND	8	/* w-bit value indicating word size reg */
2897 #define	YMM_OPND	9	/* "value" used to indicate a ymm reg */
2898 #define	KOPMASK_OPND	10	/* "value" used to indicate an opmask reg */
2899 #define	ZMM_OPND	11	/* "value" used to indicate a zmm reg */
2900 
2901 /*
2902  * The AVX2 gather instructions are a bit of a mess. While there's a pattern,
2903  * there's not really a consistent scheme that we can use to know what the mode
2904  * is supposed to be for a given type. Various instructions, like VPGATHERDD,
2905  * always match the value of VEX_L. Other instructions like VPGATHERDQ, have
2906  * some registers match VEX_L, but the VSIB is always XMM.
2907  *
2908  * The simplest way to deal with this is to just define a table based on the
2909  * instruction opcodes, which are 0x90-0x93, so we subtract 0x90 to index into
2910  * them.
2911  *
2912  * We further have to subdivide this based on the value of VEX_W and the value
2913  * of VEX_L. The array is constructed to be indexed as:
2914  *	[opcode - 0x90][VEX_W][VEX_L].
2915  */
2916 /* w = 0, 0x90 */
2917 typedef struct dis_gather_regs {
2918 	uint_t dgr_arg0;	/* src reg */
2919 	uint_t dgr_arg1;	/* vsib reg */
2920 	uint_t dgr_arg2;	/* dst reg */
2921 	char   *dgr_suffix;	/* suffix to append */
2922 } dis_gather_regs_t;
2923 
2924 static dis_gather_regs_t dis_vgather[4][2][2] = {
2925 	{
2926 		/* op 0x90, W.0 */
2927 		{
2928 			{ XMM_OPND, XMM_OPND, XMM_OPND, "d" },
2929 			{ YMM_OPND, YMM_OPND, YMM_OPND, "d" }
2930 		},
2931 		/* op 0x90, W.1 */
2932 		{
2933 			{ XMM_OPND, XMM_OPND, XMM_OPND, "q" },
2934 			{ YMM_OPND, XMM_OPND, YMM_OPND, "q" }
2935 		}
2936 	},
2937 	{
2938 		/* op 0x91, W.0 */
2939 		{
2940 			{ XMM_OPND, XMM_OPND, XMM_OPND, "d" },
2941 			{ XMM_OPND, YMM_OPND, XMM_OPND, "d" },
2942 		},
2943 		/* op 0x91, W.1 */
2944 		{
2945 			{ XMM_OPND, XMM_OPND, XMM_OPND, "q" },
2946 			{ YMM_OPND, YMM_OPND, YMM_OPND, "q" },
2947 		}
2948 	},
2949 	{
2950 		/* op 0x92, W.0 */
2951 		{
2952 			{ XMM_OPND, XMM_OPND, XMM_OPND, "s" },
2953 			{ YMM_OPND, YMM_OPND, YMM_OPND, "s" }
2954 		},
2955 		/* op 0x92, W.1 */
2956 		{
2957 			{ XMM_OPND, XMM_OPND, XMM_OPND, "d" },
2958 			{ YMM_OPND, XMM_OPND, YMM_OPND, "d" }
2959 		}
2960 	},
2961 	{
2962 		/* op 0x93, W.0 */
2963 		{
2964 			{ XMM_OPND, XMM_OPND, XMM_OPND, "s" },
2965 			{ XMM_OPND, YMM_OPND, XMM_OPND, "s" }
2966 		},
2967 		/* op 0x93, W.1 */
2968 		{
2969 			{ XMM_OPND, XMM_OPND, XMM_OPND, "d" },
2970 			{ YMM_OPND, YMM_OPND, YMM_OPND, "d" }
2971 		}
2972 	}
2973 };
2974 
2975 /*
2976  * Get the next byte and separate the op code into the high and low nibbles.
2977  */
2978 static int
2979 dtrace_get_opcode(dis86_t *x, uint_t *high, uint_t *low)
2980 {
2981 	int byte;
2982 
2983 	/*
2984 	 * x86 instructions have a maximum length of 15 bytes.  Bail out if
2985 	 * we try to read more.
2986 	 */
2987 	if (x->d86_len >= 15)
2988 		return (x->d86_error = 1);
2989 
2990 	if (x->d86_error)
2991 		return (1);
2992 	byte = x->d86_get_byte(x->d86_data);
2993 	if (byte < 0)
2994 		return (x->d86_error = 1);
2995 	x->d86_bytes[x->d86_len++] = byte;
2996 	*low = byte & 0xf;		/* ----xxxx low 4 bits */
2997 	*high = byte >> 4 & 0xf;	/* xxxx---- bits 7 to 4 */
2998 	return (0);
2999 }
3000 
3001 /*
3002  * Get and decode an SIB (scaled index base) byte
3003  */
3004 static void
3005 dtrace_get_SIB(dis86_t *x, uint_t *ss, uint_t *index, uint_t *base)
3006 {
3007 	int byte;
3008 
3009 	if (x->d86_error)
3010 		return;
3011 
3012 	byte = x->d86_get_byte(x->d86_data);
3013 	if (byte < 0) {
3014 		x->d86_error = 1;
3015 		return;
3016 	}
3017 	x->d86_bytes[x->d86_len++] = byte;
3018 
3019 	*base = byte & 0x7;
3020 	*index = (byte >> 3) & 0x7;
3021 	*ss = (byte >> 6) & 0x3;
3022 }
3023 
3024 /*
3025  * Get the byte following the op code and separate it into the
3026  * mode, register, and r/m fields.
3027  */
3028 static void
3029 dtrace_get_modrm(dis86_t *x, uint_t *mode, uint_t *reg, uint_t *r_m)
3030 {
3031 	if (x->d86_got_modrm == 0) {
3032 		if (x->d86_rmindex == -1)
3033 			x->d86_rmindex = x->d86_len;
3034 		dtrace_get_SIB(x, mode, reg, r_m);
3035 		x->d86_got_modrm = 1;
3036 	}
3037 }
3038 
3039 /*
3040  * Adjust register selection based on any REX prefix bits present.
3041  */
3042 /*ARGSUSED*/
3043 static void
3044 dtrace_rex_adjust(uint_t rex_prefix, uint_t mode, uint_t *reg, uint_t *r_m)
3045 {
3046 	if (reg != NULL && r_m == NULL) {
3047 		if (rex_prefix & REX_B)
3048 			*reg += 8;
3049 	} else {
3050 		if (reg != NULL && (REX_R & rex_prefix) != 0)
3051 			*reg += 8;
3052 		if (r_m != NULL && (REX_B & rex_prefix) != 0)
3053 			*r_m += 8;
3054 	}
3055 }
3056 
3057 /*
3058  * Adjust register selection based on any VEX prefix bits present.
3059  * Notes: VEX.R, VEX.X and VEX.B use the inverted form compared with REX prefix
3060  */
3061 /*ARGSUSED*/
3062 static void
3063 dtrace_vex_adjust(uint_t vex_byte1, uint_t mode, uint_t *reg, uint_t *r_m)
3064 {
3065 	if (reg != NULL && r_m == NULL) {
3066 		if (!(vex_byte1 & VEX_B))
3067 			*reg += 8;
3068 	} else {
3069 		if (reg != NULL && ((VEX_R & vex_byte1) == 0))
3070 			*reg += 8;
3071 		if (r_m != NULL && ((VEX_B & vex_byte1) == 0))
3072 			*r_m += 8;
3073 	}
3074 }
3075 
3076 /*
3077  * Adjust the instruction mnemonic with the appropriate suffix.
3078  */
3079 /* ARGSUSED */
3080 static void
3081 dtrace_evex_mnem_adjust(dis86_t *x, const instable_t *dp, uint_t vex_W,
3082     uint_t evex_byte2)
3083 {
3084 #ifdef DIS_TEXT
3085 	if (dp == &dis_opEVEX660F[0x7f] ||		/* vmovdqa */
3086 	    dp == &dis_opEVEX660F[0x6f]) {
3087 		(void) strlcat(x->d86_mnem, vex_W != 0 ? "64" : "32",
3088 		    OPLEN);
3089 	}
3090 
3091 	if (dp == &dis_opEVEXF20F[0x7f] ||		/* vmovdqu */
3092 	    dp == &dis_opEVEXF20F[0x6f] ||
3093 	    dp == &dis_opEVEXF30F[0x7f] ||
3094 	    dp == &dis_opEVEXF30F[0x6f]) {
3095 		switch (evex_byte2 & 0x81) {
3096 		case 0x0:
3097 			(void) strlcat(x->d86_mnem, "32", OPLEN);
3098 			break;
3099 		case 0x1:
3100 			(void) strlcat(x->d86_mnem, "8", OPLEN);
3101 			break;
3102 		case 0x80:
3103 			(void) strlcat(x->d86_mnem, "64", OPLEN);
3104 			break;
3105 		case 0x81:
3106 			(void) strlcat(x->d86_mnem, "16", OPLEN);
3107 			break;
3108 		}
3109 	}
3110 
3111 	if (dp->it_avxsuf == AVS5Q) {
3112 		(void) strlcat(x->d86_mnem, vex_W != 0 ?  "q" : "d",
3113 		    OPLEN);
3114 	}
3115 #endif
3116 }
3117 
3118 /*
3119  * The following three functions adjust the register selection based on any
3120  * EVEX prefix bits present. See Intel 64 and IA-32 Architectures Software
3121  * Developer’s Manual Volume 2 (IASDv2), section 2.6.1 Table 2-30 and
3122  * section 2.6.2 Table 2-31.
3123  */
3124 static void
3125 dtrace_evex_adjust_reg(uint_t evex_byte1, uint_t *reg)
3126 {
3127 	if (reg != NULL) {
3128 		if ((VEX_R & evex_byte1) == 0) {
3129 			*reg += 8;
3130 		}
3131 		if ((EVEX_R & evex_byte1) == 0) {
3132 			*reg += 16;
3133 		}
3134 	}
3135 }
3136 
3137 static void
3138 dtrace_evex_adjust_rm(uint_t evex_byte1, uint_t *r_m)
3139 {
3140 	if (r_m != NULL) {
3141 		if ((VEX_B & evex_byte1) == 0) {
3142 			*r_m += 8;
3143 		}
3144 		if ((VEX_X & evex_byte1) == 0) {
3145 			*r_m += 16;
3146 		}
3147 	}
3148 }
3149 
3150 /*
3151  * Use evex_L to set wbit. See IASDv2 Section 2.6.10 and Table 2-36.
3152  */
3153 static void
3154 dtrace_evex_adjust_reg_name(uint_t evex_L, uint_t *wbitp)
3155 {
3156 	switch (evex_L) {
3157 	case 0x0:
3158 		*wbitp = XMM_OPND;
3159 		break;
3160 	case 0x1:
3161 		*wbitp = YMM_OPND;
3162 		break;
3163 	case 0x2:
3164 		*wbitp = ZMM_OPND;
3165 		break;
3166 	}
3167 }
3168 
3169 /*
3170  * Adjust operand value for disp8*N immediate. See IASDv2 Section 2.6.5.
3171  * This currently only handles a subset of the possibilities.
3172  */
3173 static void
3174 dtrace_evex_adjust_disp8_n(dis86_t *x, int opindex, uint_t L, uint_t modrm)
3175 {
3176 	d86opnd_t *opnd = &x->d86_opnd[opindex];
3177 
3178 	if (x->d86_error)
3179 		return;
3180 
3181 	/* Check disp8 bit in the ModR/M byte */
3182 	if ((modrm & 0x80) == 0x80)
3183 		return;
3184 
3185 	/* use evex_L to adjust the value */
3186 	switch (L) {
3187 	case 0x0:
3188 		opnd->d86_value *= 16;
3189 		break;
3190 	case 0x1:
3191 		opnd->d86_value *= 32;
3192 		break;
3193 	case 0x2:
3194 		opnd->d86_value *= 64;
3195 		break;
3196 	}
3197 }
3198 
3199 /*
3200  * Adjust target for opmask and zeroing. See IASDv2 Section 2.6.1 Table 2-30.
3201  */
3202 /* ARGSUSED */
3203 static void
3204 dtrace_evex_adjust_z_opmask(dis86_t *x, uint_t tgtop, uint_t evex_byte3)
3205 {
3206 #ifdef DIS_TEXT
3207 	char *opnd = x->d86_opnd[tgtop].d86_opnd;
3208 	int opmask_reg = evex_byte3 & EVEX_OPREG_MASK;
3209 #endif
3210 	if (x->d86_error)
3211 		return;
3212 
3213 #ifdef DIS_TEXT
3214 	if (opmask_reg != 0) {
3215 		/* Append the opmask register to operand 1 */
3216 		(void) strlcat(opnd, "{", OPLEN);
3217 		(void) strlcat(opnd, dis_KOPMASKREG[opmask_reg], OPLEN);
3218 		(void) strlcat(opnd, "}", OPLEN);
3219 	}
3220 	if ((evex_byte3 & EVEX_ZERO_MASK) != 0) {
3221 		/* Append the 'zeroing' modifier to operand 1 */
3222 		(void) strlcat(opnd, "{z}", OPLEN);
3223 	}
3224 #endif /* DIS_TEXT */
3225 }
3226 
3227 /*
3228  * Get an immediate operand of the given size, with sign extension.
3229  */
3230 static void
3231 dtrace_imm_opnd(dis86_t *x, int wbit, int size, int opindex)
3232 {
3233 	int i;
3234 	int byte;
3235 	int valsize;
3236 
3237 	if (x->d86_numopnds < opindex + 1)
3238 		x->d86_numopnds = opindex + 1;
3239 
3240 	switch (wbit) {
3241 	case BYTE_OPND:
3242 		valsize = 1;
3243 		break;
3244 	case LONG_OPND:
3245 		if (x->d86_opnd_size == SIZE16)
3246 			valsize = 2;
3247 		else if (x->d86_opnd_size == SIZE32)
3248 			valsize = 4;
3249 		else
3250 			valsize = 8;
3251 		break;
3252 	case MM_OPND:
3253 	case XMM_OPND:
3254 	case YMM_OPND:
3255 	case ZMM_OPND:
3256 	case SEG_OPND:
3257 	case CONTROL_OPND:
3258 	case DEBUG_OPND:
3259 	case TEST_OPND:
3260 		valsize = size;
3261 		break;
3262 	case WORD_OPND:
3263 		valsize = 2;
3264 		break;
3265 	}
3266 	if (valsize < size)
3267 		valsize = size;
3268 
3269 	if (x->d86_error)
3270 		return;
3271 	x->d86_opnd[opindex].d86_value = 0;
3272 	for (i = 0; i < size; ++i) {
3273 		byte = x->d86_get_byte(x->d86_data);
3274 		if (byte < 0) {
3275 			x->d86_error = 1;
3276 			return;
3277 		}
3278 		x->d86_bytes[x->d86_len++] = byte;
3279 		x->d86_opnd[opindex].d86_value |= (uint64_t)byte << (i * 8);
3280 	}
3281 	/* Do sign extension */
3282 	if (x->d86_bytes[x->d86_len - 1] & 0x80) {
3283 		for (; i < sizeof (uint64_t); i++)
3284 			x->d86_opnd[opindex].d86_value |=
3285 			    (uint64_t)0xff << (i * 8);
3286 	}
3287 #ifdef DIS_TEXT
3288 	x->d86_opnd[opindex].d86_mode = MODE_SIGNED;
3289 	x->d86_opnd[opindex].d86_value_size = valsize;
3290 	x->d86_imm_bytes += size;
3291 #endif
3292 }
3293 
3294 /*
3295  * Get an ip relative operand of the given size, with sign extension.
3296  */
3297 static void
3298 dtrace_disp_opnd(dis86_t *x, int wbit, int size, int opindex)
3299 {
3300 	dtrace_imm_opnd(x, wbit, size, opindex);
3301 #ifdef DIS_TEXT
3302 	x->d86_opnd[opindex].d86_mode = MODE_IPREL;
3303 #endif
3304 }
3305 
3306 /*
3307  * Check to see if there is a segment override prefix pending.
3308  * If so, print it in the current 'operand' location and set
3309  * the override flag back to false.
3310  */
3311 /*ARGSUSED*/
3312 static void
3313 dtrace_check_override(dis86_t *x, int opindex)
3314 {
3315 #ifdef DIS_TEXT
3316 	if (x->d86_seg_prefix) {
3317 		(void) strlcat(x->d86_opnd[opindex].d86_prefix,
3318 		    x->d86_seg_prefix, PFIXLEN);
3319 	}
3320 #endif
3321 	x->d86_seg_prefix = NULL;
3322 }
3323 
3324 
3325 /*
3326  * Process a single instruction Register or Memory operand.
3327  *
3328  * mode = addressing mode from ModRM byte
3329  * r_m = r_m (or reg if mode == 3) field from ModRM byte
3330  * wbit = indicates which register (8bit, 16bit, ... MMX, etc.) set to use.
3331  * o = index of operand that we are processing (0, 1 or 2)
3332  *
3333  * the value of reg or r_m must have already been adjusted for any REX prefix.
3334  */
3335 /*ARGSUSED*/
3336 static void
3337 dtrace_get_operand(dis86_t *x, uint_t mode, uint_t r_m, int wbit, int opindex)
3338 {
3339 	int have_SIB = 0;	/* flag presence of scale-index-byte */
3340 	uint_t ss;		/* scale-factor from opcode */
3341 	uint_t index;		/* index register number */
3342 	uint_t base;		/* base register number */
3343 	int dispsize;		/* size of displacement in bytes */
3344 #ifdef DIS_TEXT
3345 	char *opnd = x->d86_opnd[opindex].d86_opnd;
3346 #endif
3347 
3348 	if (x->d86_numopnds < opindex + 1)
3349 		x->d86_numopnds = opindex + 1;
3350 
3351 	if (x->d86_error)
3352 		return;
3353 
3354 	/*
3355 	 * first handle a simple register
3356 	 */
3357 	if (mode == REG_ONLY) {
3358 #ifdef DIS_TEXT
3359 		switch (wbit) {
3360 		case MM_OPND:
3361 			(void) strlcat(opnd, dis_MMREG[r_m], OPLEN);
3362 			break;
3363 		case XMM_OPND:
3364 			(void) strlcat(opnd, dis_XMMREG[r_m], OPLEN);
3365 			break;
3366 		case YMM_OPND:
3367 			(void) strlcat(opnd, dis_YMMREG[r_m], OPLEN);
3368 			break;
3369 		case ZMM_OPND:
3370 			(void) strlcat(opnd, dis_ZMMREG[r_m], OPLEN);
3371 			break;
3372 		case KOPMASK_OPND:
3373 			(void) strlcat(opnd, dis_KOPMASKREG[r_m], OPLEN);
3374 			break;
3375 		case SEG_OPND:
3376 			(void) strlcat(opnd, dis_SEGREG[r_m], OPLEN);
3377 			break;
3378 		case CONTROL_OPND:
3379 			(void) strlcat(opnd, dis_CONTROLREG[r_m], OPLEN);
3380 			break;
3381 		case DEBUG_OPND:
3382 			(void) strlcat(opnd, dis_DEBUGREG[r_m], OPLEN);
3383 			break;
3384 		case TEST_OPND:
3385 			(void) strlcat(opnd, dis_TESTREG[r_m], OPLEN);
3386 			break;
3387 		case BYTE_OPND:
3388 			if (x->d86_rex_prefix == 0)
3389 				(void) strlcat(opnd, dis_REG8[r_m], OPLEN);
3390 			else
3391 				(void) strlcat(opnd, dis_REG8_REX[r_m], OPLEN);
3392 			break;
3393 		case WORD_OPND:
3394 			(void) strlcat(opnd, dis_REG16[r_m], OPLEN);
3395 			break;
3396 		case LONG_OPND:
3397 			if (x->d86_opnd_size == SIZE16)
3398 				(void) strlcat(opnd, dis_REG16[r_m], OPLEN);
3399 			else if (x->d86_opnd_size == SIZE32)
3400 				(void) strlcat(opnd, dis_REG32[r_m], OPLEN);
3401 			else
3402 				(void) strlcat(opnd, dis_REG64[r_m], OPLEN);
3403 			break;
3404 		}
3405 #endif /* DIS_TEXT */
3406 		return;
3407 	}
3408 
3409 	/*
3410 	 * if symbolic representation, skip override prefix, if any
3411 	 */
3412 	dtrace_check_override(x, opindex);
3413 
3414 	/*
3415 	 * Handle 16 bit memory references first, since they decode
3416 	 * the mode values more simply.
3417 	 * mode 1 is r_m + 8 bit displacement
3418 	 * mode 2 is r_m + 16 bit displacement
3419 	 * mode 0 is just r_m, unless r_m is 6 which is 16 bit disp
3420 	 */
3421 	if (x->d86_addr_size == SIZE16) {
3422 		if ((mode == 0 && r_m == 6) || mode == 2)
3423 			dtrace_imm_opnd(x, WORD_OPND, 2, opindex);
3424 		else if (mode == 1)
3425 			dtrace_imm_opnd(x, BYTE_OPND, 1, opindex);
3426 #ifdef DIS_TEXT
3427 		if (mode == 0 && r_m == 6)
3428 			x->d86_opnd[opindex].d86_mode = MODE_SIGNED;
3429 		else if (mode == 0)
3430 			x->d86_opnd[opindex].d86_mode = MODE_NONE;
3431 		else
3432 			x->d86_opnd[opindex].d86_mode = MODE_OFFSET;
3433 		(void) strlcat(opnd, dis_addr16[mode][r_m], OPLEN);
3434 #endif
3435 		return;
3436 	}
3437 
3438 	/*
3439 	 * 32 and 64 bit addressing modes are more complex since they can
3440 	 * involve an SIB (scaled index and base) byte to decode. When using VEX
3441 	 * and EVEX encodings, the r_m indicator for a SIB may be offset by 8
3442 	 * and 24 (8 + 16) respectively.
3443 	 */
3444 	if (r_m == ESP_REGNO || r_m == ESP_REGNO + 8 || r_m == ESP_REGNO + 24) {
3445 		have_SIB = 1;
3446 		dtrace_get_SIB(x, &ss, &index, &base);
3447 		if (x->d86_error)
3448 			return;
3449 		if (base != 5 || mode != 0)
3450 			if (x->d86_rex_prefix & REX_B)
3451 				base += 8;
3452 		if (x->d86_rex_prefix & REX_X)
3453 			index += 8;
3454 	} else {
3455 		base = r_m;
3456 	}
3457 
3458 	/*
3459 	 * Compute the displacement size and get its bytes
3460 	 */
3461 	dispsize = 0;
3462 
3463 	if (mode == 1)
3464 		dispsize = 1;
3465 	else if (mode == 2)
3466 		dispsize = 4;
3467 	else if ((r_m & 7) == EBP_REGNO ||
3468 	    (have_SIB && (base & 7) == EBP_REGNO))
3469 		dispsize = 4;
3470 
3471 	if (dispsize > 0) {
3472 		dtrace_imm_opnd(x, dispsize == 4 ? LONG_OPND : BYTE_OPND,
3473 		    dispsize, opindex);
3474 		if (x->d86_error)
3475 			return;
3476 	}
3477 
3478 #ifdef DIS_TEXT
3479 	if (dispsize > 0)
3480 		x->d86_opnd[opindex].d86_mode = MODE_OFFSET;
3481 
3482 	if (have_SIB == 0) {
3483 		if (x->d86_mode == SIZE32) {
3484 			if (mode == 0)
3485 				(void) strlcat(opnd, dis_addr32_mode0[r_m],
3486 				    OPLEN);
3487 			else
3488 				(void) strlcat(opnd, dis_addr32_mode12[r_m],
3489 				    OPLEN);
3490 		} else {
3491 			if (mode == 0) {
3492 				(void) strlcat(opnd, dis_addr64_mode0[r_m],
3493 				    OPLEN);
3494 				if (r_m == 5) {
3495 					x->d86_opnd[opindex].d86_mode =
3496 					    MODE_RIPREL;
3497 				}
3498 			} else {
3499 				(void) strlcat(opnd, dis_addr64_mode12[r_m],
3500 				    OPLEN);
3501 			}
3502 		}
3503 	} else {
3504 		uint_t need_paren = 0;
3505 		char **regs;
3506 		char **bregs;
3507 		const char *const *sf;
3508 		if (x->d86_mode == SIZE32) /* NOTE this is not addr_size! */
3509 			regs = (char **)dis_REG32;
3510 		else
3511 			regs = (char **)dis_REG64;
3512 
3513 		if (x->d86_vsib != 0) {
3514 			if (wbit == YMM_OPND) { /* NOTE this is not addr_size */
3515 				bregs = (char **)dis_YMMREG;
3516 			} else if (wbit == XMM_OPND) {
3517 				bregs = (char **)dis_XMMREG;
3518 			} else {
3519 				bregs = (char **)dis_ZMMREG;
3520 			}
3521 			sf = dis_vscale_factor;
3522 		} else {
3523 			bregs = regs;
3524 			sf = dis_scale_factor;
3525 		}
3526 
3527 		/*
3528 		 * print the base (if any)
3529 		 */
3530 		if (base == EBP_REGNO && mode == 0) {
3531 			if (index != ESP_REGNO || x->d86_vsib != 0) {
3532 				(void) strlcat(opnd, "(", OPLEN);
3533 				need_paren = 1;
3534 			}
3535 		} else {
3536 			(void) strlcat(opnd, "(", OPLEN);
3537 			(void) strlcat(opnd, regs[base], OPLEN);
3538 			need_paren = 1;
3539 		}
3540 
3541 		/*
3542 		 * print the index (if any)
3543 		 */
3544 		if (index != ESP_REGNO || x->d86_vsib) {
3545 			(void) strlcat(opnd, ",", OPLEN);
3546 			(void) strlcat(opnd, bregs[index], OPLEN);
3547 			(void) strlcat(opnd, sf[ss], OPLEN);
3548 		} else
3549 			if (need_paren)
3550 				(void) strlcat(opnd, ")", OPLEN);
3551 	}
3552 #endif
3553 }
3554 
3555 /*
3556  * Operand sequence for standard instruction involving one register
3557  * and one register/memory operand.
3558  * wbit indicates a byte(0) or opnd_size(1) operation
3559  * vbit indicates direction (0 for "opcode r,r_m") or (1 for "opcode r_m, r")
3560  */
3561 #define	STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, vbit)  {	\
3562 		dtrace_get_modrm(x, &mode, &reg, &r_m);			\
3563 		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);	\
3564 		dtrace_get_operand(x, mode, r_m, wbit, vbit);		\
3565 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 1 - vbit);	\
3566 }
3567 
3568 /*
3569  * Similar to above, but allows for the two operands to be of different
3570  * classes (ie. wbit).
3571  *	wbit is for the r_m operand
3572  *	w2 is for the reg operand
3573  */
3574 #define	MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, w2, vbit)	{	\
3575 		dtrace_get_modrm(x, &mode, &reg, &r_m);			\
3576 		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);	\
3577 		dtrace_get_operand(x, mode, r_m, wbit, vbit);		\
3578 		dtrace_get_operand(x, REG_ONLY, reg, w2, 1 - vbit);	\
3579 }
3580 
3581 /*
3582  * Similar, but for 2 operands plus an immediate.
3583  * vbit indicates direction
3584  *	0 for "opcode imm, r, r_m" or
3585  *	1 for "opcode imm, r_m, r"
3586  */
3587 #define	THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize, vbit) { \
3588 		dtrace_get_modrm(x, &mode, &reg, &r_m);			\
3589 		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);	\
3590 		dtrace_get_operand(x, mode, r_m, wbit, 2-vbit);		\
3591 		dtrace_get_operand(x, REG_ONLY, reg, w2, 1+vbit);	\
3592 		dtrace_imm_opnd(x, wbit, immsize, 0);			\
3593 }
3594 
3595 /*
3596  * Similar, but for 2 operands plus two immediates.
3597  */
3598 #define	FOUROPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize) { \
3599 		dtrace_get_modrm(x, &mode, &reg, &r_m);			\
3600 		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);	\
3601 		dtrace_get_operand(x, mode, r_m, wbit, 2);		\
3602 		dtrace_get_operand(x, REG_ONLY, reg, w2, 3);		\
3603 		dtrace_imm_opnd(x, wbit, immsize, 1);			\
3604 		dtrace_imm_opnd(x, wbit, immsize, 0);			\
3605 }
3606 
3607 /*
3608  * 1 operands plus two immediates.
3609  */
3610 #define	ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, wbit, immsize) { \
3611 		dtrace_get_modrm(x, &mode, &reg, &r_m);			\
3612 		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);	\
3613 		dtrace_get_operand(x, mode, r_m, wbit, 2);		\
3614 		dtrace_imm_opnd(x, wbit, immsize, 1);			\
3615 		dtrace_imm_opnd(x, wbit, immsize, 0);			\
3616 }
3617 
3618 /*
3619  * Dissassemble a single x86 or amd64 instruction.
3620  *
3621  * Mode determines the default operating mode (SIZE16, SIZE32 or SIZE64)
3622  * for interpreting instructions.
3623  *
3624  * returns non-zero for bad opcode
3625  */
3626 int
3627 dtrace_disx86(dis86_t *x, uint_t cpu_mode)
3628 {
3629 	const instable_t *dp;	/* decode table being used */
3630 #ifdef DIS_TEXT
3631 	uint_t i;
3632 #endif
3633 #ifdef DIS_MEM
3634 	uint_t nomem = 0;
3635 #define	NOMEM	(nomem = 1)
3636 #else
3637 #define	NOMEM	/* nothing */
3638 #endif
3639 	uint_t opnd_size;	/* SIZE16, SIZE32 or SIZE64 */
3640 	uint_t addr_size;	/* SIZE16, SIZE32 or SIZE64 */
3641 	uint_t wbit;		/* opcode wbit, 0 is 8 bit, !0 for opnd_size */
3642 	uint_t w2;		/* wbit value for second operand */
3643 	uint_t vbit;
3644 	uint_t mode = 0;	/* mode value from ModRM byte */
3645 	uint_t reg;		/* reg value from ModRM byte */
3646 	uint_t r_m;		/* r_m value from ModRM byte */
3647 
3648 	uint_t opcode1;		/* high nibble of 1st byte */
3649 	uint_t opcode2;		/* low nibble of 1st byte */
3650 	uint_t opcode3;		/* extra opcode bits usually from ModRM byte */
3651 	uint_t opcode4;		/* high nibble of 2nd byte */
3652 	uint_t opcode5;		/* low nibble of 2nd byte */
3653 	uint_t opcode6;		/* high nibble of 3rd byte */
3654 	uint_t opcode7;		/* low nibble of 3rd byte */
3655 	uint_t opcode8;		/* high nibble of 4th byte */
3656 	uint_t opcode9;		/* low nibble of 4th byte */
3657 	uint_t opcode_bytes = 1;
3658 
3659 	/*
3660 	 * legacy prefixes come in 5 flavors, you should have only one of each
3661 	 */
3662 	uint_t	opnd_size_prefix = 0;
3663 	uint_t	addr_size_prefix = 0;
3664 	uint_t	segment_prefix = 0;
3665 	uint_t	lock_prefix = 0;
3666 	uint_t	rep_prefix = 0;
3667 	uint_t	rex_prefix = 0;	/* amd64 register extension prefix */
3668 
3669 	/*
3670 	 * Intel VEX instruction encoding prefix and fields
3671 	 */
3672 
3673 	/* 0xC4 means 3 bytes prefix, 0xC5 means 2 bytes prefix */
3674 	uint_t vex_prefix = 0;
3675 
3676 	/*
3677 	 * VEX prefix byte 1, includes vex.r, vex.x and vex.b
3678 	 * (for 3 bytes prefix)
3679 	 */
3680 	uint_t vex_byte1 = 0;
3681 
3682 	/*
3683 	 * EVEX prefix byte 1 includes vex.r, vex.x, vex.b and evex.r.
3684 	 */
3685 	uint_t evex_byte1 = 0;
3686 	uint_t evex_byte2 = 0;
3687 	uint_t evex_byte3 = 0;
3688 
3689 	/*
3690 	 * For 32-bit mode, it should prefetch the next byte to
3691 	 * distinguish between AVX and les/lds
3692 	 */
3693 	uint_t vex_prefetch = 0;
3694 
3695 	uint_t vex_m = 0;
3696 	uint_t vex_v = 0;
3697 	uint_t vex_p = 0;
3698 	uint_t vex_R = 1;
3699 	uint_t vex_X = 1;
3700 	uint_t vex_B = 1;
3701 	uint_t vex_W = 0;
3702 	uint_t vex_L = 0;
3703 	uint_t evex_L = 0;
3704 	uint_t evex_modrm = 0;
3705 	uint_t evex_prefix = 0;
3706 	dis_gather_regs_t *vreg;
3707 
3708 #ifdef	DIS_TEXT
3709 	/* Instruction name for BLS* family of instructions */
3710 	char *blsinstr;
3711 #endif
3712 
3713 	size_t	off;
3714 
3715 	instable_t dp_mmx;
3716 
3717 	x->d86_len = 0;
3718 	x->d86_rmindex = -1;
3719 	x->d86_error = 0;
3720 #ifdef DIS_TEXT
3721 	x->d86_numopnds = 0;
3722 	x->d86_seg_prefix = NULL;
3723 	x->d86_mnem[0] = 0;
3724 	for (i = 0; i < 4; ++i) {
3725 		x->d86_opnd[i].d86_opnd[0] = 0;
3726 		x->d86_opnd[i].d86_prefix[0] = 0;
3727 		x->d86_opnd[i].d86_value_size = 0;
3728 		x->d86_opnd[i].d86_value = 0;
3729 		x->d86_opnd[i].d86_mode = MODE_NONE;
3730 	}
3731 #endif
3732 	x->d86_rex_prefix = 0;
3733 	x->d86_got_modrm = 0;
3734 	x->d86_memsize = 0;
3735 	x->d86_vsib = 0;
3736 
3737 	if (cpu_mode == SIZE16) {
3738 		opnd_size = SIZE16;
3739 		addr_size = SIZE16;
3740 	} else if (cpu_mode == SIZE32) {
3741 		opnd_size = SIZE32;
3742 		addr_size = SIZE32;
3743 	} else {
3744 		opnd_size = SIZE32;
3745 		addr_size = SIZE64;
3746 	}
3747 
3748 	/*
3749 	 * Get one opcode byte and check for zero padding that follows
3750 	 * jump tables.
3751 	 */
3752 	if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3753 		goto error;
3754 
3755 	if (opcode1 == 0 && opcode2 == 0 &&
3756 	    x->d86_check_func != NULL && x->d86_check_func(x->d86_data)) {
3757 #ifdef DIS_TEXT
3758 		(void) strncpy(x->d86_mnem, ".byte\t0", OPLEN);
3759 #endif
3760 		goto done;
3761 	}
3762 
3763 	/*
3764 	 * Gather up legacy x86 prefix bytes.
3765 	 */
3766 	for (;;) {
3767 		uint_t *which_prefix = NULL;
3768 
3769 		dp = (instable_t *)&dis_distable[opcode1][opcode2];
3770 
3771 		switch (dp->it_adrmode) {
3772 		case PREFIX:
3773 			which_prefix = &rep_prefix;
3774 			break;
3775 		case LOCK:
3776 			which_prefix = &lock_prefix;
3777 			break;
3778 		case OVERRIDE:
3779 			which_prefix = &segment_prefix;
3780 #ifdef DIS_TEXT
3781 			x->d86_seg_prefix = (char *)dp->it_name;
3782 #endif
3783 			if (dp->it_invalid64 && cpu_mode == SIZE64)
3784 				goto error;
3785 			break;
3786 		case AM:
3787 			which_prefix = &addr_size_prefix;
3788 			break;
3789 		case DM:
3790 			which_prefix = &opnd_size_prefix;
3791 			break;
3792 		}
3793 		if (which_prefix == NULL)
3794 			break;
3795 		*which_prefix = (opcode1 << 4) | opcode2;
3796 		if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3797 			goto error;
3798 	}
3799 
3800 	/*
3801 	 * Handle amd64 mode PREFIX values.
3802 	 * Some of the segment prefixes are no-ops. (only FS/GS actually work)
3803 	 * We might have a REX prefix (opcodes 0x40-0x4f)
3804 	 */
3805 	if (cpu_mode == SIZE64) {
3806 		if (segment_prefix != 0x64 && segment_prefix != 0x65)
3807 			segment_prefix = 0;
3808 
3809 		if (opcode1 == 0x4) {
3810 			rex_prefix = (opcode1 << 4) | opcode2;
3811 			if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3812 				goto error;
3813 			dp = (instable_t *)&dis_distable[opcode1][opcode2];
3814 		} else if (opcode1 == 0xC &&
3815 		    (opcode2 == 0x4 || opcode2 == 0x5)) {
3816 			/* AVX instructions */
3817 			vex_prefix = (opcode1 << 4) | opcode2;
3818 			x->d86_rex_prefix = 0x40;
3819 		}
3820 	} else if (opcode1 == 0xC && (opcode2 == 0x4 || opcode2 == 0x5)) {
3821 		/* LDS, LES or AVX */
3822 		dtrace_get_modrm(x, &mode, &reg, &r_m);
3823 		vex_prefetch = 1;
3824 
3825 		if (mode == REG_ONLY) {
3826 			/* AVX */
3827 			vex_prefix = (opcode1 << 4) | opcode2;
3828 			x->d86_rex_prefix = 0x40;
3829 			opcode3 = (((mode << 3) | reg)>>1) & 0x0F;
3830 			opcode4 = ((reg << 3) | r_m) & 0x0F;
3831 		}
3832 	}
3833 
3834 	/*
3835 	 * The EVEX prefix and "bound" instruction share the same first byte.
3836 	 * "bound" is only valid for 32-bit. For 64-bit this byte begins the
3837 	 * EVEX prefix and the 2nd byte must have bits 2 & 3 set to 0.
3838 	 */
3839 	if (opcode1 == 0x6 && opcode2 == 0x2) {
3840 		evex_prefix = 0x62;
3841 
3842 		/*
3843 		 * An EVEX prefix is 4 bytes long, get the next 3 bytes.
3844 		 */
3845 		if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0)
3846 			goto error;
3847 
3848 		if (addr_size == SIZE32 && (opcode4 & 0xf) == 0) {
3849 			/*
3850 			 * Upper bits in 2nd byte == 0 is 'bound' instn.
3851 			 *
3852 			 * We've already read the byte so perform the
3853 			 * equivalent of dtrace_get_modrm on the byte and set
3854 			 * the flag to indicate we've already read it.
3855 			 */
3856 			char b = (opcode4 << 4) | opcode5;
3857 
3858 			r_m = b & 0x7;
3859 			reg = (b >> 3) & 0x7;
3860 			mode = (b >> 6) & 0x3;
3861 			vex_prefetch = 1;
3862 			goto not_avx512;
3863 		}
3864 
3865 		/* check for correct bits being 0 in 2nd byte */
3866 		if ((opcode5 & 0xc) != 0)
3867 			goto error;
3868 
3869 		if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
3870 			goto error;
3871 		/* check for correct bit being 1 in 3rd byte */
3872 		if ((opcode7 & 0x4) == 0)
3873 			goto error;
3874 
3875 		if (dtrace_get_opcode(x, &opcode8, &opcode9) != 0)
3876 			goto error;
3877 
3878 		/* Reuse opcode1 & opcode2 to get the real opcode now */
3879 		if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3880 			goto error;
3881 
3882 		/*
3883 		 * We only use the high nibble from the 2nd byte of the prefix
3884 		 * and save it in the low bits of evex_byte1. This is because
3885 		 * two of the bits in opcode5 are constant 0 (checked above),
3886 		 * and the other two bits are captured in vex_m. Also, the VEX
3887 		 * constants we check in evex_byte1 are against the low bits.
3888 		 */
3889 		evex_byte1 = opcode4;
3890 		evex_byte2 = (opcode6 << 4) | opcode7;
3891 		evex_byte3 = (opcode8 << 4) | opcode9;
3892 
3893 		vex_m = opcode5 & EVEX_m;
3894 		vex_v = (((opcode6 << 4) | opcode7) & VEX_v) >> 3;
3895 		vex_W = (opcode6 & VEX_W) >> 3;
3896 		vex_p = opcode7 & VEX_p;
3897 
3898 		/*
3899 		 * Store the corresponding prefix information for later use when
3900 		 * calculating the SIB.
3901 		 */
3902 		if ((evex_byte1 & VEX_R) == 0)
3903 			x->d86_rex_prefix |= REX_R;
3904 		if ((evex_byte1 & VEX_X) == 0)
3905 			x->d86_rex_prefix |= REX_X;
3906 		if ((evex_byte1 & VEX_B) == 0)
3907 			x->d86_rex_prefix |= REX_B;
3908 
3909 		/* Currently only 3 valid values for evex L'L: 00, 01, 10 */
3910 		evex_L = (opcode8 & EVEX_L) >> 1;
3911 
3912 		switch (vex_p) {
3913 		case VEX_p_66:
3914 			switch (vex_m) {
3915 			case VEX_m_0F:
3916 				dp = &dis_opEVEX660F[(opcode1 << 4) | opcode2];
3917 				break;
3918 			case VEX_m_0F38:
3919 				dp = &dis_opEVEX660F38[(opcode1 << 4) |
3920 				    opcode2];
3921 				break;
3922 			case VEX_m_0F3A:
3923 				dp = &dis_opEVEX660F3A[(opcode1 << 4) |
3924 				    opcode2];
3925 				break;
3926 			default:
3927 				goto error;
3928 			}
3929 			break;
3930 		case VEX_p_F3:
3931 			switch (vex_m) {
3932 			case VEX_m_0F:
3933 				dp = &dis_opEVEXF30F[(opcode1 << 4) | opcode2];
3934 				break;
3935 			default:
3936 				goto error;
3937 			}
3938 			break;
3939 		case VEX_p_F2:
3940 			switch (vex_m) {
3941 			case VEX_m_0F:
3942 				dp = &dis_opEVEXF20F[(opcode1 << 4) | opcode2];
3943 				break;
3944 			default:
3945 				goto error;
3946 			}
3947 			break;
3948 		default:
3949 			dp = &dis_opEVEX0F[(opcode1 << 4) | opcode2];
3950 			break;
3951 		}
3952 	}
3953 not_avx512:
3954 
3955 	if (vex_prefix == VEX_2bytes) {
3956 		if (!vex_prefetch) {
3957 			if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0)
3958 				goto error;
3959 		}
3960 		vex_R = ((opcode3 & VEX_R) & 0x0F) >> 3;
3961 		vex_L = ((opcode4 & VEX_L) & 0x0F) >> 2;
3962 		vex_v = (((opcode3 << 4) | opcode4) & VEX_v) >> 3;
3963 		vex_p = opcode4 & VEX_p;
3964 		/*
3965 		 * The vex.x and vex.b bits are not defined in two bytes
3966 		 * mode vex prefix, their default values are 1
3967 		 */
3968 		vex_byte1 = (opcode3 & VEX_R) | VEX_X | VEX_B;
3969 
3970 		if (vex_R == 0)
3971 			x->d86_rex_prefix |= REX_R;
3972 
3973 		if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3974 			goto error;
3975 
3976 		switch (vex_p) {
3977 			case VEX_p_66:
3978 				dp = (instable_t *)
3979 				    &dis_opAVX660F[(opcode1 << 4) | opcode2];
3980 				break;
3981 			case VEX_p_F3:
3982 				dp = (instable_t *)
3983 				    &dis_opAVXF30F[(opcode1 << 4) | opcode2];
3984 				break;
3985 			case VEX_p_F2:
3986 				dp = (instable_t *)
3987 				    &dis_opAVXF20F [(opcode1 << 4) | opcode2];
3988 				break;
3989 			default:
3990 				dp = (instable_t *)
3991 				    &dis_opAVX0F[opcode1][opcode2];
3992 
3993 		}
3994 
3995 	} else if (vex_prefix == VEX_3bytes) {
3996 		if (!vex_prefetch) {
3997 			if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0)
3998 				goto error;
3999 		}
4000 		vex_R = (opcode3 & VEX_R) >> 3;
4001 		vex_X = (opcode3 & VEX_X) >> 2;
4002 		vex_B = (opcode3 & VEX_B) >> 1;
4003 		vex_m = (((opcode3 << 4) | opcode4) & VEX_m);
4004 		vex_byte1 = opcode3 & (VEX_R | VEX_X | VEX_B);
4005 
4006 		if (vex_R == 0)
4007 			x->d86_rex_prefix |= REX_R;
4008 		if (vex_X == 0)
4009 			x->d86_rex_prefix |= REX_X;
4010 		if (vex_B == 0)
4011 			x->d86_rex_prefix |= REX_B;
4012 
4013 		if (dtrace_get_opcode(x, &opcode5, &opcode6) != 0)
4014 			goto error;
4015 		vex_W = (opcode5 & VEX_W) >> 3;
4016 		vex_L = (opcode6 & VEX_L) >> 2;
4017 		vex_v = (((opcode5 << 4) | opcode6) & VEX_v) >> 3;
4018 		vex_p = opcode6 & VEX_p;
4019 
4020 		if (vex_W)
4021 			x->d86_rex_prefix |= REX_W;
4022 
4023 		/* Only these three vex_m values valid; others are reserved */
4024 		if ((vex_m != VEX_m_0F) && (vex_m != VEX_m_0F38) &&
4025 		    (vex_m != VEX_m_0F3A))
4026 			goto error;
4027 
4028 		if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
4029 			goto error;
4030 
4031 		switch (vex_p) {
4032 			case VEX_p_66:
4033 				if (vex_m == VEX_m_0F) {
4034 					dp = (instable_t *)
4035 					    &dis_opAVX660F
4036 					    [(opcode1 << 4) | opcode2];
4037 				} else if (vex_m == VEX_m_0F38) {
4038 					dp = (instable_t *)
4039 					    &dis_opAVX660F38
4040 					    [(opcode1 << 4) | opcode2];
4041 				} else if (vex_m == VEX_m_0F3A) {
4042 					dp = (instable_t *)
4043 					    &dis_opAVX660F3A
4044 					    [(opcode1 << 4) | opcode2];
4045 				} else {
4046 					goto error;
4047 				}
4048 				break;
4049 			case VEX_p_F3:
4050 				if (vex_m == VEX_m_0F) {
4051 					dp = (instable_t *)
4052 					    &dis_opAVXF30F
4053 					    [(opcode1 << 4) | opcode2];
4054 				} else if (vex_m == VEX_m_0F38) {
4055 					dp = (instable_t *)
4056 					    &dis_opAVXF30F38
4057 					    [(opcode1 << 4) | opcode2];
4058 				} else {
4059 					goto error;
4060 				}
4061 				break;
4062 			case VEX_p_F2:
4063 				if (vex_m == VEX_m_0F) {
4064 					dp = (instable_t *)
4065 					    &dis_opAVXF20F
4066 					    [(opcode1 << 4) | opcode2];
4067 				} else if (vex_m == VEX_m_0F3A) {
4068 					dp = (instable_t *)
4069 					    &dis_opAVXF20F3A
4070 					    [(opcode1 << 4) | opcode2];
4071 				} else if (vex_m == VEX_m_0F38) {
4072 					dp = (instable_t *)
4073 					    &dis_opAVXF20F38
4074 					    [(opcode1 << 4) | opcode2];
4075 				} else {
4076 					goto error;
4077 				}
4078 				break;
4079 			default:
4080 				dp = (instable_t *)
4081 				    &dis_opAVX0F[opcode1][opcode2];
4082 
4083 		}
4084 	}
4085 	if (vex_prefix) {
4086 		if (dp->it_vexwoxmm) {
4087 			wbit = LONG_OPND;
4088 		} else if (dp->it_vexopmask) {
4089 			wbit = KOPMASK_OPND;
4090 		} else {
4091 			if (vex_L) {
4092 				wbit = YMM_OPND;
4093 			} else {
4094 				wbit = XMM_OPND;
4095 			}
4096 		}
4097 	}
4098 
4099 	/*
4100 	 * Deal with selection of operand and address size now.
4101 	 * Note that the REX.W bit being set causes opnd_size_prefix to be
4102 	 * ignored.
4103 	 */
4104 	if (cpu_mode == SIZE64) {
4105 		if ((rex_prefix & REX_W) || vex_W)
4106 			opnd_size = SIZE64;
4107 		else if (opnd_size_prefix)
4108 			opnd_size = SIZE16;
4109 
4110 		if (addr_size_prefix)
4111 			addr_size = SIZE32;
4112 	} else if (cpu_mode == SIZE32) {
4113 		if (opnd_size_prefix)
4114 			opnd_size = SIZE16;
4115 		if (addr_size_prefix)
4116 			addr_size = SIZE16;
4117 	} else {
4118 		if (opnd_size_prefix)
4119 			opnd_size = SIZE32;
4120 		if (addr_size_prefix)
4121 			addr_size = SIZE32;
4122 	}
4123 	/*
4124 	 * The pause instruction - a repz'd nop.  This doesn't fit
4125 	 * with any of the other prefix goop added for SSE, so we'll
4126 	 * special-case it here.
4127 	 */
4128 	if (rep_prefix == 0xf3 && opcode1 == 0x9 && opcode2 == 0x0) {
4129 		rep_prefix = 0;
4130 		dp = (instable_t *)&dis_opPause;
4131 	}
4132 
4133 	/*
4134 	 * Some 386 instructions have 2 bytes of opcode before the mod_r/m
4135 	 * byte so we may need to perform a table indirection.
4136 	 */
4137 	if (dp->it_indirect == (instable_t *)dis_op0F) {
4138 		if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0)
4139 			goto error;
4140 		opcode_bytes = 2;
4141 		if (opcode4 == 0x7 && opcode5 >= 0x1 && opcode5 <= 0x3) {
4142 			uint_t	subcode;
4143 
4144 			if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
4145 				goto error;
4146 			opcode_bytes = 3;
4147 			subcode = ((opcode6 & 0x3) << 1) |
4148 			    ((opcode7 & 0x8) >> 3);
4149 			dp = (instable_t *)&dis_op0F7123[opcode5][subcode];
4150 		} else if ((opcode4 == 0xc) && (opcode5 >= 0x8)) {
4151 			dp = (instable_t *)&dis_op0FC8[0];
4152 		} else if ((opcode4 == 0x3) && (opcode5 == 0xA)) {
4153 			opcode_bytes = 3;
4154 			if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
4155 				goto error;
4156 			if (opnd_size == SIZE16)
4157 				opnd_size = SIZE32;
4158 
4159 			dp = (instable_t *)&dis_op0F3A[(opcode6<<4)|opcode7];
4160 #ifdef DIS_TEXT
4161 			if (strcmp(dp->it_name, "INVALID") == 0)
4162 				goto error;
4163 #endif
4164 			switch (dp->it_adrmode) {
4165 				case XMMP:
4166 					break;
4167 				case XMMP_66r:
4168 				case XMMPRM_66r:
4169 				case XMM3PM_66r:
4170 					if (opnd_size_prefix == 0) {
4171 						goto error;
4172 					}
4173 
4174 					break;
4175 				case XMMP_66o:
4176 					if (opnd_size_prefix == 0) {
4177 						/* SSSE3 MMX instructions */
4178 						dp_mmx = *dp;
4179 						dp_mmx.it_adrmode = MMOPM_66o;
4180 #ifdef	DIS_MEM
4181 						dp_mmx.it_size = 8;
4182 #endif
4183 						dp = &dp_mmx;
4184 					}
4185 					break;
4186 				default:
4187 					goto error;
4188 			}
4189 		} else if ((opcode4 == 0x3) && (opcode5 == 0x8)) {
4190 			opcode_bytes = 3;
4191 			if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
4192 				goto error;
4193 			dp = (instable_t *)&dis_op0F38[(opcode6<<4)|opcode7];
4194 
4195 			/*
4196 			 * Both crc32 and movbe have the same 3rd opcode
4197 			 * byte of either 0xF0 or 0xF1, so we use another
4198 			 * indirection to distinguish between the two.
4199 			 */
4200 			if (dp->it_indirect == (instable_t *)dis_op0F38F0 ||
4201 			    dp->it_indirect == (instable_t *)dis_op0F38F1) {
4202 
4203 				dp = dp->it_indirect;
4204 				if (rep_prefix != 0xF2) {
4205 					/* It is movbe */
4206 					dp++;
4207 				}
4208 			}
4209 
4210 			/*
4211 			 * The adx family of instructions (adcx and adox)
4212 			 * continue the classic Intel tradition of abusing
4213 			 * arbitrary prefixes without actually meaning the
4214 			 * prefix bit. Therefore, if we find either the
4215 			 * opnd_size_prefix or rep_prefix we end up zeroing it
4216 			 * out after making our determination so as to ensure
4217 			 * that we don't get confused and accidentally print
4218 			 * repz prefixes and the like on these instructions.
4219 			 *
4220 			 * In addition, these instructions are actually much
4221 			 * closer to AVX instructions in semantics. Importantly,
4222 			 * they always default to having 32-bit operands.
4223 			 * However, if the CPU is in 64-bit mode, then and only
4224 			 * then, does it use REX.w promotes things to 64-bits
4225 			 * and REX.r allows 64-bit mode to use register r8-r15.
4226 			 */
4227 			if (dp->it_indirect == (instable_t *)dis_op0F38F6) {
4228 				dp = dp->it_indirect;
4229 				if (opnd_size_prefix == 0 &&
4230 				    rep_prefix == 0xf3) {
4231 					/* It is adox */
4232 					dp++;
4233 				} else if (opnd_size_prefix != 0x66 &&
4234 				    rep_prefix != 0) {
4235 					/* It isn't adcx */
4236 					goto error;
4237 				}
4238 				opnd_size_prefix = 0;
4239 				rep_prefix = 0;
4240 				opnd_size = SIZE32;
4241 				if (rex_prefix & REX_W)
4242 					opnd_size = SIZE64;
4243 			}
4244 
4245 #ifdef DIS_TEXT
4246 			if (strcmp(dp->it_name, "INVALID") == 0)
4247 				goto error;
4248 #endif
4249 			switch (dp->it_adrmode) {
4250 				case ADX:
4251 				case XMM:
4252 					break;
4253 				case RM_66r:
4254 				case XMM_66r:
4255 				case XMMM_66r:
4256 					if (opnd_size_prefix == 0) {
4257 						goto error;
4258 					}
4259 					break;
4260 				case XMM_66o:
4261 					if (opnd_size_prefix == 0) {
4262 						/* SSSE3 MMX instructions */
4263 						dp_mmx = *dp;
4264 						dp_mmx.it_adrmode = MM;
4265 #ifdef	DIS_MEM
4266 						dp_mmx.it_size = 8;
4267 #endif
4268 						dp = &dp_mmx;
4269 					}
4270 					break;
4271 				case CRC32:
4272 					if (rep_prefix != 0xF2) {
4273 						goto error;
4274 					}
4275 					rep_prefix = 0;
4276 					break;
4277 				case MOVBE:
4278 					if (rep_prefix != 0x0) {
4279 						goto error;
4280 					}
4281 					break;
4282 				default:
4283 					goto error;
4284 			}
4285 		} else if (rep_prefix == 0xf3 && opcode4 == 0 && opcode5 == 9) {
4286 			rep_prefix = 0;
4287 			dp = (instable_t *)&dis_opWbnoinvd;
4288 		} else {
4289 			dp = (instable_t *)&dis_op0F[opcode4][opcode5];
4290 		}
4291 	}
4292 
4293 	/*
4294 	 * If still not at a TERM decode entry, then a ModRM byte
4295 	 * exists and its fields further decode the instruction.
4296 	 */
4297 	x->d86_got_modrm = 0;
4298 	if (dp->it_indirect != TERM) {
4299 		dtrace_get_modrm(x, &mode, &opcode3, &r_m);
4300 		if (x->d86_error)
4301 			goto error;
4302 		reg = opcode3;
4303 
4304 		/*
4305 		 * decode 287 instructions (D8-DF) from opcodeN
4306 		 */
4307 		if (opcode1 == 0xD && opcode2 >= 0x8) {
4308 			if (opcode2 == 0xB && mode == 0x3 && opcode3 == 4)
4309 				dp = (instable_t *)&dis_opFP5[r_m];
4310 			else if (opcode2 == 0xA && mode == 0x3 && opcode3 < 4)
4311 				dp = (instable_t *)&dis_opFP7[opcode3];
4312 			else if (opcode2 == 0xB && mode == 0x3)
4313 				dp = (instable_t *)&dis_opFP6[opcode3];
4314 			else if (opcode2 == 0x9 && mode == 0x3 && opcode3 >= 4)
4315 				dp = (instable_t *)&dis_opFP4[opcode3 - 4][r_m];
4316 			else if (mode == 0x3)
4317 				dp = (instable_t *)
4318 				    &dis_opFP3[opcode2 - 8][opcode3];
4319 			else
4320 				dp = (instable_t *)
4321 				    &dis_opFP1n2[opcode2 - 8][opcode3];
4322 		} else {
4323 			dp = (instable_t *)dp->it_indirect + opcode3;
4324 		}
4325 	}
4326 
4327 	/*
4328 	 * In amd64 bit mode, ARPL opcode is changed to MOVSXD
4329 	 * (sign extend 32bit to 64 bit)
4330 	 */
4331 	if ((vex_prefix == 0) && cpu_mode == SIZE64 &&
4332 	    opcode1 == 0x6 && opcode2 == 0x3)
4333 		dp = (instable_t *)&dis_opMOVSLD;
4334 
4335 	/*
4336 	 * at this point we should have a correct (or invalid) opcode
4337 	 */
4338 	if (cpu_mode == SIZE64 && dp->it_invalid64 ||
4339 	    cpu_mode != SIZE64 && dp->it_invalid32)
4340 		goto error;
4341 	if (dp->it_indirect != TERM)
4342 		goto error;
4343 
4344 	/*
4345 	 * Deal with MMX/SSE opcodes which are changed by prefixes. Note, we do
4346 	 * need to include UNKNOWN below, as we may have instructions that
4347 	 * actually have a prefix, but don't exist in any other form.
4348 	 */
4349 	switch (dp->it_adrmode) {
4350 	case UNKNOWN:
4351 	case MMO:
4352 	case MMOIMPL:
4353 	case MMO3P:
4354 	case MMOM3:
4355 	case MMOMS:
4356 	case MMOPM:
4357 	case MMOPRM:
4358 	case MMOS:
4359 	case XMMO:
4360 	case XMMOM:
4361 	case XMMOMS:
4362 	case XMMOPM:
4363 	case XMMOS:
4364 	case XMMOMX:
4365 	case XMMOX3:
4366 	case XMMOXMM:
4367 		/*
4368 		 * This is horrible.  Some SIMD instructions take the
4369 		 * form 0x0F 0x?? ..., which is easily decoded using the
4370 		 * existing tables.  Other SIMD instructions use various
4371 		 * prefix bytes to overload existing instructions.  For
4372 		 * Example, addps is F0, 58, whereas addss is F3 (repz),
4373 		 * F0, 58.  Presumably someone got a raise for this.
4374 		 *
4375 		 * If we see one of the instructions which can be
4376 		 * modified in this way (if we've got one of the SIMDO*
4377 		 * address modes), we'll check to see if the last prefix
4378 		 * was a repz.  If it was, we strip the prefix from the
4379 		 * mnemonic, and we indirect using the dis_opSIMDrepz
4380 		 * table.
4381 		 */
4382 
4383 		/*
4384 		 * Calculate our offset in dis_op0F
4385 		 */
4386 		if ((uintptr_t)dp - (uintptr_t)dis_op0F > sizeof (dis_op0F))
4387 			goto error;
4388 
4389 		off = ((uintptr_t)dp - (uintptr_t)dis_op0F) /
4390 		    sizeof (instable_t);
4391 
4392 		/*
4393 		 * Rewrite if this instruction used one of the magic prefixes.
4394 		 */
4395 		if (rep_prefix) {
4396 			if (rep_prefix == 0xf2)
4397 				dp = (instable_t *)&dis_opSIMDrepnz[off];
4398 			else
4399 				dp = (instable_t *)&dis_opSIMDrepz[off];
4400 			rep_prefix = 0;
4401 		} else if (opnd_size_prefix) {
4402 			dp = (instable_t *)&dis_opSIMDdata16[off];
4403 			opnd_size_prefix = 0;
4404 			if (opnd_size == SIZE16)
4405 				opnd_size = SIZE32;
4406 		}
4407 		break;
4408 
4409 	case MG9:
4410 		/*
4411 		 * More horribleness: the group 9 (0xF0 0xC7) instructions are
4412 		 * allowed an optional prefix of 0x66 or 0xF3.  This is similar
4413 		 * to the SIMD business described above, but with a different
4414 		 * addressing mode (and an indirect table), so we deal with it
4415 		 * separately (if similarly).
4416 		 *
4417 		 * Intel further complicated this with the release of Ivy Bridge
4418 		 * where they overloaded these instructions based on the ModR/M
4419 		 * bytes. The VMX instructions have a mode of 0 since they are
4420 		 * memory instructions but rdrand instructions have a mode of
4421 		 * 0b11 (REG_ONLY) because they only operate on registers. While
4422 		 * there are different prefix formats, for now it is sufficient
4423 		 * to use a single different table.
4424 		 */
4425 
4426 		/*
4427 		 * Calculate our offset in dis_op0FC7 (the group 9 table)
4428 		 */
4429 		if ((uintptr_t)dp - (uintptr_t)dis_op0FC7 > sizeof (dis_op0FC7))
4430 			goto error;
4431 
4432 		off = ((uintptr_t)dp - (uintptr_t)dis_op0FC7) /
4433 		    sizeof (instable_t);
4434 
4435 		/*
4436 		 * If we have a mode of 0b11 then we have to rewrite this.
4437 		 */
4438 		dtrace_get_modrm(x, &mode, &reg, &r_m);
4439 		if (mode == REG_ONLY) {
4440 			dp = (instable_t *)&dis_op0FC7m3[off];
4441 			break;
4442 		}
4443 
4444 		/*
4445 		 * Rewrite if this instruction used one of the magic prefixes.
4446 		 */
4447 		if (rep_prefix) {
4448 			if (rep_prefix == 0xf3)
4449 				dp = (instable_t *)&dis_opF30FC7[off];
4450 			else
4451 				goto error;
4452 			rep_prefix = 0;
4453 		} else if (opnd_size_prefix) {
4454 			dp = (instable_t *)&dis_op660FC7[off];
4455 			opnd_size_prefix = 0;
4456 			if (opnd_size == SIZE16)
4457 				opnd_size = SIZE32;
4458 		} else if (reg == 4 || reg == 5) {
4459 			/*
4460 			 * We have xsavec (4) or xsaves (5), so rewrite.
4461 			 */
4462 			dp = (instable_t *)&dis_op0FC7[reg];
4463 			break;
4464 		}
4465 		break;
4466 
4467 
4468 	case MMOSH:
4469 		/*
4470 		 * As with the "normal" SIMD instructions, the MMX
4471 		 * shuffle instructions are overloaded.  These
4472 		 * instructions, however, are special in that they use
4473 		 * an extra byte, and thus an extra table.  As of this
4474 		 * writing, they only use the opnd_size prefix.
4475 		 */
4476 
4477 		/*
4478 		 * Calculate our offset in dis_op0F7123
4479 		 */
4480 		if ((uintptr_t)dp - (uintptr_t)dis_op0F7123 >
4481 		    sizeof (dis_op0F7123))
4482 			goto error;
4483 
4484 		if (opnd_size_prefix) {
4485 			off = ((uintptr_t)dp - (uintptr_t)dis_op0F7123) /
4486 			    sizeof (instable_t);
4487 			dp = (instable_t *)&dis_opSIMD7123[off];
4488 			opnd_size_prefix = 0;
4489 			if (opnd_size == SIZE16)
4490 				opnd_size = SIZE32;
4491 		}
4492 		break;
4493 	case MRw:
4494 		if (rep_prefix) {
4495 			if (rep_prefix == 0xf3) {
4496 
4497 				/*
4498 				 * Calculate our offset in dis_op0F
4499 				 */
4500 				if ((uintptr_t)dp - (uintptr_t)dis_op0F >
4501 				    sizeof (dis_op0F))
4502 					goto error;
4503 
4504 				off = ((uintptr_t)dp - (uintptr_t)dis_op0F) /
4505 				    sizeof (instable_t);
4506 
4507 				dp = (instable_t *)&dis_opSIMDrepz[off];
4508 				rep_prefix = 0;
4509 			} else {
4510 				goto error;
4511 			}
4512 		}
4513 		break;
4514 	case FSGS:
4515 		if (rep_prefix == 0xf3) {
4516 			if ((uintptr_t)dp - (uintptr_t)dis_op0FAE >
4517 			    sizeof (dis_op0FAE))
4518 				goto error;
4519 
4520 			off = ((uintptr_t)dp - (uintptr_t)dis_op0FAE) /
4521 			    sizeof (instable_t);
4522 			dp = (instable_t *)&dis_opF30FAE[off];
4523 			rep_prefix = 0;
4524 		} else if (rep_prefix != 0x00) {
4525 			goto error;
4526 		}
4527 	}
4528 
4529 	/*
4530 	 * In 64 bit mode, some opcodes automatically use opnd_size == SIZE64.
4531 	 */
4532 	if (cpu_mode == SIZE64)
4533 		if (dp->it_always64 || (opnd_size == SIZE32 && dp->it_stackop))
4534 			opnd_size = SIZE64;
4535 
4536 #ifdef DIS_TEXT
4537 	/*
4538 	 * At this point most instructions can format the opcode mnemonic
4539 	 * including the prefixes.
4540 	 */
4541 	if (lock_prefix)
4542 		(void) strlcat(x->d86_mnem, "lock ", OPLEN);
4543 
4544 	if (rep_prefix == 0xf2)
4545 		(void) strlcat(x->d86_mnem, "repnz ", OPLEN);
4546 	else if (rep_prefix == 0xf3)
4547 		(void) strlcat(x->d86_mnem, "repz ", OPLEN);
4548 
4549 	if (cpu_mode == SIZE64 && addr_size_prefix)
4550 		(void) strlcat(x->d86_mnem, "addr32 ", OPLEN);
4551 
4552 	if (dp->it_adrmode != CBW &&
4553 	    dp->it_adrmode != CWD &&
4554 	    dp->it_adrmode != XMMSFNC) {
4555 		if (strcmp(dp->it_name, "INVALID") == 0)
4556 			goto error;
4557 		(void) strlcat(x->d86_mnem, dp->it_name, OPLEN);
4558 		if (dp->it_avxsuf == AVS2 && dp->it_suffix) {
4559 			(void) strlcat(x->d86_mnem, vex_W != 0 ? "q" : "d",
4560 			    OPLEN);
4561 		} else if (dp->it_vexopmask && dp->it_suffix) {
4562 			/* opmask instructions */
4563 
4564 			if (opcode1 == 4 && opcode2 == 0xb) {
4565 				/* It's a kunpck. */
4566 				if (vex_prefix == VEX_2bytes) {
4567 					(void) strlcat(x->d86_mnem,
4568 					    vex_p == 0 ? "wd" : "bw", OPLEN);
4569 				} else {
4570 					/* vex_prefix == VEX_3bytes */
4571 					(void) strlcat(x->d86_mnem,
4572 					    "dq", OPLEN);
4573 				}
4574 			} else if (opcode1 == 3) {
4575 				/* It's a kshift[l|r]. */
4576 				if (vex_W == 0) {
4577 					(void) strlcat(x->d86_mnem,
4578 					    opcode2 == 2 ||
4579 					    opcode2 == 0 ?
4580 					    "b" : "d", OPLEN);
4581 				} else {
4582 					/* W == 1 */
4583 					(void) strlcat(x->d86_mnem,
4584 					    opcode2 == 3 || opcode2 == 1 ?
4585 					    "q" : "w", OPLEN);
4586 				}
4587 			} else {
4588 				/* if (vex_prefix == VEX_2bytes) { */
4589 				if ((cpu_mode == SIZE64 && opnd_size == 2) ||
4590 				    vex_prefix == VEX_2bytes) {
4591 					(void) strlcat(x->d86_mnem,
4592 					    vex_p == 0 ? "w" :
4593 					    vex_p == 1 ? "b" : "d",
4594 					    OPLEN);
4595 				} else {
4596 					/* vex_prefix == VEX_3bytes */
4597 					(void) strlcat(x->d86_mnem,
4598 					    vex_p == 1 ? "d" : "q", OPLEN);
4599 				}
4600 			}
4601 		} else if (dp->it_suffix) {
4602 			char *types[] = {"", "w", "l", "q"};
4603 			if (opcode_bytes == 2 && opcode4 == 4) {
4604 				/* It's a cmovx.yy. Replace the suffix x */
4605 				for (i = 5; i < OPLEN; i++) {
4606 					if (x->d86_mnem[i] == '.')
4607 						break;
4608 				}
4609 				x->d86_mnem[i - 1] = *types[opnd_size];
4610 			} else if ((opnd_size == 2) && (opcode_bytes == 3) &&
4611 			    ((opcode6 == 1 && opcode7 == 6) ||
4612 			    (opcode6 == 2 && opcode7 == 2))) {
4613 				/*
4614 				 * To handle PINSRD and PEXTRD
4615 				 */
4616 				(void) strlcat(x->d86_mnem, "d", OPLEN);
4617 			} else if (dp != &dis_distable[0x6][0x2]) {
4618 				/* bound instructions (0x62) have no suffix */
4619 				(void) strlcat(x->d86_mnem, types[opnd_size],
4620 				    OPLEN);
4621 			}
4622 		}
4623 	}
4624 #endif
4625 
4626 	/*
4627 	 * Process operands based on the addressing modes.
4628 	 */
4629 	x->d86_mode = cpu_mode;
4630 	/*
4631 	 * In vex mode the rex_prefix has no meaning
4632 	 */
4633 	if (!vex_prefix && evex_prefix == 0)
4634 		x->d86_rex_prefix = rex_prefix;
4635 	x->d86_opnd_size = opnd_size;
4636 	x->d86_addr_size = addr_size;
4637 	vbit = 0;		/* initialize for mem/reg -> reg */
4638 	switch (dp->it_adrmode) {
4639 		/*
4640 		 * amd64 instruction to sign extend 32 bit reg/mem operands
4641 		 * into 64 bit register values
4642 		 */
4643 	case MOVSXZ:
4644 #ifdef DIS_TEXT
4645 		if (rex_prefix == 0)
4646 			(void) strncpy(x->d86_mnem, "movzld", OPLEN);
4647 #endif
4648 		dtrace_get_modrm(x, &mode, &reg, &r_m);
4649 		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
4650 		x->d86_opnd_size = SIZE64;
4651 		dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
4652 		x->d86_opnd_size = opnd_size = SIZE32;
4653 		wbit = LONG_OPND;
4654 		dtrace_get_operand(x, mode, r_m, wbit, 0);
4655 		break;
4656 
4657 		/*
4658 		 * movsbl movsbw movsbq (0x0FBE) or movswl movswq (0x0FBF)
4659 		 * movzbl movzbw movzbq (0x0FB6) or movzwl movzwq (0x0FB7)
4660 		 * wbit lives in 2nd byte, note that operands
4661 		 * are different sized
4662 		 */
4663 	case MOVZ:
4664 		if (rex_prefix & REX_W) {
4665 			/* target register size = 64 bit */
4666 			x->d86_mnem[5] = 'q';
4667 		}
4668 		dtrace_get_modrm(x, &mode, &reg, &r_m);
4669 		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
4670 		dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
4671 		x->d86_opnd_size = opnd_size = SIZE16;
4672 		wbit = WBIT(opcode5);
4673 		dtrace_get_operand(x, mode, r_m, wbit, 0);
4674 		break;
4675 	case CRC32:
4676 		opnd_size = SIZE32;
4677 		if (rex_prefix & REX_W)
4678 			opnd_size = SIZE64;
4679 		x->d86_opnd_size = opnd_size;
4680 
4681 		dtrace_get_modrm(x, &mode, &reg, &r_m);
4682 		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
4683 		dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
4684 		wbit = WBIT(opcode7);
4685 		if (opnd_size_prefix)
4686 			x->d86_opnd_size = opnd_size = SIZE16;
4687 		dtrace_get_operand(x, mode, r_m, wbit, 0);
4688 		break;
4689 	case MOVBE:
4690 		opnd_size = SIZE32;
4691 		if (rex_prefix & REX_W)
4692 			opnd_size = SIZE64;
4693 		x->d86_opnd_size = opnd_size;
4694 
4695 		dtrace_get_modrm(x, &mode, &reg, &r_m);
4696 		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
4697 		wbit = WBIT(opcode7);
4698 		if (opnd_size_prefix)
4699 			x->d86_opnd_size = opnd_size = SIZE16;
4700 		if (wbit) {
4701 			/* reg -> mem */
4702 			dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);
4703 			dtrace_get_operand(x, mode, r_m, wbit, 1);
4704 		} else {
4705 			/* mem -> reg */
4706 			dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
4707 			dtrace_get_operand(x, mode, r_m, wbit, 0);
4708 		}
4709 		break;
4710 
4711 	/*
4712 	 * imul instruction, with either 8-bit or longer immediate
4713 	 * opcode 0x6B for byte, sign-extended displacement, 0x69 for word(s)
4714 	 */
4715 	case IMUL:
4716 		wbit = LONG_OPND;
4717 		THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND,
4718 		    OPSIZE(opnd_size, opcode2 == 0x9), 1);
4719 		break;
4720 
4721 	/* memory or register operand to register, with 'w' bit	*/
4722 	case MRw:
4723 	case ADX:
4724 		wbit = WBIT(opcode2);
4725 		STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
4726 		break;
4727 
4728 	/* register to memory or register operand, with 'w' bit	*/
4729 	/* arpl happens to fit here also because it is odd */
4730 	case RMw:
4731 		if (opcode_bytes == 2)
4732 			wbit = WBIT(opcode5);
4733 		else
4734 			wbit = WBIT(opcode2);
4735 		STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
4736 		break;
4737 
4738 	/* xaddb instruction */
4739 	case XADDB:
4740 		wbit = 0;
4741 		STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
4742 		break;
4743 
4744 	/* MMX register to memory or register operand		*/
4745 	case MMS:
4746 	case MMOS:
4747 #ifdef DIS_TEXT
4748 		wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND;
4749 #else
4750 		wbit = LONG_OPND;
4751 #endif
4752 		MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1);
4753 		break;
4754 
4755 	/* MMX register to memory */
4756 	case MMOMS:
4757 		dtrace_get_modrm(x, &mode, &reg, &r_m);
4758 		if (mode == REG_ONLY)
4759 			goto error;
4760 		wbit = MM_OPND;
4761 		MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1);
4762 		break;
4763 
4764 	/* Double shift. Has immediate operand specifying the shift. */
4765 	case DSHIFT:
4766 		wbit = LONG_OPND;
4767 		dtrace_get_modrm(x, &mode, &reg, &r_m);
4768 		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
4769 		dtrace_get_operand(x, mode, r_m, wbit, 2);
4770 		dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
4771 		dtrace_imm_opnd(x, wbit, 1, 0);
4772 		break;
4773 
4774 	/*
4775 	 * Double shift. With no immediate operand, specifies using %cl.
4776 	 */
4777 	case DSHIFTcl:
4778 		wbit = LONG_OPND;
4779 		STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
4780 		break;
4781 
4782 	/* immediate to memory or register operand */
4783 	case IMlw:
4784 		wbit = WBIT(opcode2);
4785 		dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
4786 		dtrace_get_operand(x, mode, r_m, wbit, 1);
4787 		/*
4788 		 * Have long immediate for opcode 0x81, but not 0x80 nor 0x83
4789 		 */
4790 		dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, opcode2 == 1), 0);
4791 		break;
4792 
4793 	/* immediate to memory or register operand with the	*/
4794 	/* 'w' bit present					*/
4795 	case IMw:
4796 		wbit = WBIT(opcode2);
4797 		dtrace_get_modrm(x, &mode, &reg, &r_m);
4798 		dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
4799 		dtrace_get_operand(x, mode, r_m, wbit, 1);
4800 		dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0);
4801 		break;
4802 
4803 	/* immediate to register with register in low 3 bits	*/
4804 	/* of op code						*/
4805 	case IR:
4806 		/* w-bit here (with regs) is bit 3 */
4807 		wbit = opcode2 >>3 & 0x1;
4808 		reg = REGNO(opcode2);
4809 		dtrace_rex_adjust(rex_prefix, mode, &reg, NULL);
4810 		mode = REG_ONLY;
4811 		r_m = reg;
4812 		dtrace_get_operand(x, mode, r_m, wbit, 1);
4813 		dtrace_imm_opnd(x, wbit, OPSIZE64(opnd_size, wbit), 0);
4814 		break;
4815 
4816 	/* MMX immediate shift of register */
4817 	case MMSH:
4818 	case MMOSH:
4819 		wbit = MM_OPND;
4820 		goto mm_shift;	/* in next case */
4821 
4822 	/* SIMD immediate shift of register */
4823 	case XMMSH:
4824 		wbit = XMM_OPND;
4825 mm_shift:
4826 		reg = REGNO(opcode7);
4827 		dtrace_rex_adjust(rex_prefix, mode, &reg, NULL);
4828 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
4829 		dtrace_imm_opnd(x, wbit, 1, 0);
4830 		NOMEM;
4831 		break;
4832 
4833 	/* accumulator to memory operand */
4834 	case AO:
4835 		vbit = 1;
4836 		/*FALLTHROUGH*/
4837 
4838 	/* memory operand to accumulator */
4839 	case OA:
4840 		wbit = WBIT(opcode2);
4841 		dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1 - vbit);
4842 		dtrace_imm_opnd(x, wbit, OPSIZE64(addr_size, LONG_OPND), vbit);
4843 #ifdef DIS_TEXT
4844 		x->d86_opnd[vbit].d86_mode = MODE_OFFSET;
4845 #endif
4846 		break;
4847 
4848 
4849 	/* segment register to memory or register operand */
4850 	case SM:
4851 		vbit = 1;
4852 		/*FALLTHROUGH*/
4853 
4854 	/* memory or register operand to segment register */
4855 	case MS:
4856 		dtrace_get_modrm(x, &mode, &reg, &r_m);
4857 		dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
4858 		dtrace_get_operand(x, mode, r_m, LONG_OPND, vbit);
4859 		dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 1 - vbit);
4860 		break;
4861 
4862 	/*
4863 	 * rotate or shift instructions, which may shift by 1 or
4864 	 * consult the cl register, depending on the 'v' bit
4865 	 */
4866 	case Mv:
4867 		vbit = VBIT(opcode2);
4868 		wbit = WBIT(opcode2);
4869 		dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
4870 		dtrace_get_operand(x, mode, r_m, wbit, 1);
4871 #ifdef DIS_TEXT
4872 		if (vbit) {
4873 			(void) strlcat(x->d86_opnd[0].d86_opnd, "%cl", OPLEN);
4874 		} else {
4875 			x->d86_opnd[0].d86_mode = MODE_SIGNED;
4876 			x->d86_opnd[0].d86_value_size = 1;
4877 			x->d86_opnd[0].d86_value = 1;
4878 		}
4879 #endif
4880 		break;
4881 	/*
4882 	 * immediate rotate or shift instructions
4883 	 */
4884 	case MvI:
4885 		wbit = WBIT(opcode2);
4886 normal_imm_mem:
4887 		dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
4888 		dtrace_get_operand(x, mode, r_m, wbit, 1);
4889 		dtrace_imm_opnd(x, wbit, 1, 0);
4890 		break;
4891 
4892 	/* bit test instructions */
4893 	case MIb:
4894 		wbit = LONG_OPND;
4895 		goto normal_imm_mem;
4896 
4897 	/* single memory or register operand with 'w' bit present */
4898 	case Mw:
4899 		wbit = WBIT(opcode2);
4900 just_mem:
4901 		dtrace_get_modrm(x, &mode, &reg, &r_m);
4902 		dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
4903 		dtrace_get_operand(x, mode, r_m, wbit, 0);
4904 		break;
4905 
4906 	case SWAPGS_RDTSCP:
4907 		if (cpu_mode == SIZE64 && mode == 3 && r_m == 0) {
4908 #ifdef DIS_TEXT
4909 			(void) strncpy(x->d86_mnem, "swapgs", OPLEN);
4910 #endif
4911 			NOMEM;
4912 			break;
4913 		} else if (mode == 3 && r_m == 1) {
4914 #ifdef DIS_TEXT
4915 			(void) strncpy(x->d86_mnem, "rdtscp", OPLEN);
4916 #endif
4917 			NOMEM;
4918 			break;
4919 		} else if (mode == 3 && r_m == 2) {
4920 #ifdef DIS_TEXT
4921 			(void) strncpy(x->d86_mnem, "monitorx", OPLEN);
4922 #endif
4923 			NOMEM;
4924 			break;
4925 		} else if (mode == 3 && r_m == 3) {
4926 #ifdef DIS_TEXT
4927 			(void) strncpy(x->d86_mnem, "mwaitx", OPLEN);
4928 #endif
4929 			NOMEM;
4930 			break;
4931 		} else if (mode == 3 && r_m == 4) {
4932 #ifdef DIS_TEXT
4933 			(void) strncpy(x->d86_mnem, "clzero", OPLEN);
4934 #endif
4935 			NOMEM;
4936 			break;
4937 		}
4938 
4939 		/*FALLTHROUGH*/
4940 
4941 	/* prefetch instruction - memory operand, but no memory acess */
4942 	case PREF:
4943 		NOMEM;
4944 		/*FALLTHROUGH*/
4945 
4946 	/* single memory or register operand */
4947 	case M:
4948 	case MG9:
4949 		wbit = LONG_OPND;
4950 		goto just_mem;
4951 
4952 	/* single memory or register byte operand */
4953 	case Mb:
4954 		wbit = BYTE_OPND;
4955 		goto just_mem;
4956 
4957 	case VMx:
4958 		if (mode == 3) {
4959 #ifdef DIS_TEXT
4960 			char *vminstr;
4961 
4962 			switch (r_m) {
4963 			case 1:
4964 				vminstr = "vmcall";
4965 				break;
4966 			case 2:
4967 				vminstr = "vmlaunch";
4968 				break;
4969 			case 3:
4970 				vminstr = "vmresume";
4971 				break;
4972 			case 4:
4973 				vminstr = "vmxoff";
4974 				break;
4975 			default:
4976 				goto error;
4977 			}
4978 
4979 			(void) strncpy(x->d86_mnem, vminstr, OPLEN);
4980 #else
4981 			if (r_m < 1 || r_m > 4)
4982 				goto error;
4983 #endif
4984 
4985 			NOMEM;
4986 			break;
4987 		}
4988 		/*FALLTHROUGH*/
4989 	case SVM:
4990 		if (mode == 3) {
4991 #if DIS_TEXT
4992 			char *vinstr;
4993 
4994 			switch (r_m) {
4995 			case 0:
4996 				vinstr = "vmrun";
4997 				break;
4998 			case 1:
4999 				vinstr = "vmmcall";
5000 				break;
5001 			case 2:
5002 				vinstr = "vmload";
5003 				break;
5004 			case 3:
5005 				vinstr = "vmsave";
5006 				break;
5007 			case 4:
5008 				vinstr = "stgi";
5009 				break;
5010 			case 5:
5011 				vinstr = "clgi";
5012 				break;
5013 			case 6:
5014 				vinstr = "skinit";
5015 				break;
5016 			case 7:
5017 				vinstr = "invlpga";
5018 				break;
5019 			}
5020 
5021 			(void) strncpy(x->d86_mnem, vinstr, OPLEN);
5022 #endif
5023 			NOMEM;
5024 			break;
5025 		}
5026 		/*FALLTHROUGH*/
5027 	case MONITOR_MWAIT:
5028 		if (mode == 3) {
5029 			if (r_m == 0) {
5030 #ifdef DIS_TEXT
5031 				(void) strncpy(x->d86_mnem, "monitor", OPLEN);
5032 #endif
5033 				NOMEM;
5034 				break;
5035 			} else if (r_m == 1) {
5036 #ifdef DIS_TEXT
5037 				(void) strncpy(x->d86_mnem, "mwait", OPLEN);
5038 #endif
5039 				NOMEM;
5040 				break;
5041 			} else if (r_m == 2) {
5042 #ifdef DIS_TEXT
5043 				(void) strncpy(x->d86_mnem, "clac", OPLEN);
5044 #endif
5045 				NOMEM;
5046 				break;
5047 			} else if (r_m == 3) {
5048 #ifdef DIS_TEXT
5049 				(void) strncpy(x->d86_mnem, "stac", OPLEN);
5050 #endif
5051 				NOMEM;
5052 				break;
5053 			} else {
5054 				goto error;
5055 			}
5056 		}
5057 		/*FALLTHROUGH*/
5058 	case XGETBV_XSETBV:
5059 		if (mode == 3) {
5060 			if (r_m == 0) {
5061 #ifdef DIS_TEXT
5062 				(void) strncpy(x->d86_mnem, "xgetbv", OPLEN);
5063 #endif
5064 				NOMEM;
5065 				break;
5066 			} else if (r_m == 1) {
5067 #ifdef DIS_TEXT
5068 				(void) strncpy(x->d86_mnem, "xsetbv", OPLEN);
5069 #endif
5070 				NOMEM;
5071 				break;
5072 			} else {
5073 				goto error;
5074 			}
5075 
5076 		}
5077 		/*FALLTHROUGH*/
5078 	case MO:
5079 		/* Similar to M, but only memory (no direct registers) */
5080 		wbit = LONG_OPND;
5081 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5082 		if (mode == 3)
5083 			goto error;
5084 		dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
5085 		dtrace_get_operand(x, mode, r_m, wbit, 0);
5086 		break;
5087 
5088 	/* move special register to register or reverse if vbit */
5089 	case SREG:
5090 		switch (opcode5) {
5091 
5092 		case 2:
5093 			vbit = 1;
5094 			/*FALLTHROUGH*/
5095 		case 0:
5096 			wbit = CONTROL_OPND;
5097 			break;
5098 
5099 		case 3:
5100 			vbit = 1;
5101 			/*FALLTHROUGH*/
5102 		case 1:
5103 			wbit = DEBUG_OPND;
5104 			break;
5105 
5106 		case 6:
5107 			vbit = 1;
5108 			/*FALLTHROUGH*/
5109 		case 4:
5110 			wbit = TEST_OPND;
5111 			break;
5112 
5113 		}
5114 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5115 		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
5116 		dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit);
5117 		dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 1 - vbit);
5118 		NOMEM;
5119 		break;
5120 
5121 	/*
5122 	 * single register operand with register in the low 3
5123 	 * bits of op code
5124 	 */
5125 	case R:
5126 		if (opcode_bytes == 2)
5127 			reg = REGNO(opcode5);
5128 		else
5129 			reg = REGNO(opcode2);
5130 		dtrace_rex_adjust(rex_prefix, mode, &reg, NULL);
5131 		dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);
5132 		NOMEM;
5133 		break;
5134 
5135 	/*
5136 	 * register to accumulator with register in the low 3
5137 	 * bits of op code, xchg instructions
5138 	 */
5139 	case RA:
5140 		NOMEM;
5141 		reg = REGNO(opcode2);
5142 		dtrace_rex_adjust(rex_prefix, mode, &reg, NULL);
5143 		dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);
5144 		dtrace_get_operand(x, REG_ONLY, EAX_REGNO, LONG_OPND, 1);
5145 		break;
5146 
5147 	/*
5148 	 * single segment register operand, with register in
5149 	 * bits 3-4 of op code byte
5150 	 */
5151 	case SEG:
5152 		NOMEM;
5153 		reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x3;
5154 		dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0);
5155 		break;
5156 
5157 	/*
5158 	 * single segment register operand, with register in
5159 	 * bits 3-5 of op code
5160 	 */
5161 	case LSEG:
5162 		NOMEM;
5163 		/* long seg reg from opcode */
5164 		reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x7;
5165 		dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0);
5166 		break;
5167 
5168 	/* memory or register operand to register */
5169 	case MR:
5170 		if (vex_prefetch)
5171 			x->d86_got_modrm = 1;
5172 		wbit = LONG_OPND;
5173 		STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
5174 		break;
5175 
5176 	case RM:
5177 	case RM_66r:
5178 		if (vex_prefetch)
5179 			x->d86_got_modrm = 1;
5180 		wbit = LONG_OPND;
5181 		STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
5182 		break;
5183 
5184 	/* MMX/SIMD-Int memory or mm reg to mm reg		*/
5185 	case MM:
5186 	case MMO:
5187 #ifdef DIS_TEXT
5188 		wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND;
5189 #else
5190 		wbit = LONG_OPND;
5191 #endif
5192 		MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0);
5193 		break;
5194 
5195 	case MMOIMPL:
5196 #ifdef DIS_TEXT
5197 		wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND;
5198 #else
5199 		wbit = LONG_OPND;
5200 #endif
5201 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5202 		if (mode != REG_ONLY)
5203 			goto error;
5204 
5205 		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
5206 		dtrace_get_operand(x, mode, r_m, wbit, 0);
5207 		dtrace_get_operand(x, REG_ONLY, reg, MM_OPND, 1);
5208 		mode = 0;	/* change for memory access size... */
5209 		break;
5210 
5211 	/* MMX/SIMD-Int and SIMD-FP predicated mm reg to r32 */
5212 	case MMO3P:
5213 		wbit = MM_OPND;
5214 		goto xmm3p;
5215 	case XMM3P:
5216 		wbit = XMM_OPND;
5217 xmm3p:
5218 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5219 		if (mode != REG_ONLY)
5220 			goto error;
5221 
5222 		THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 1,
5223 		    1);
5224 		NOMEM;
5225 		break;
5226 
5227 	case XMM3PM_66r:
5228 		THREEOPERAND(x, mode, reg, r_m, rex_prefix, LONG_OPND, XMM_OPND,
5229 		    1, 0);
5230 		break;
5231 
5232 	/* MMX/SIMD-Int predicated r32/mem to mm reg */
5233 	case MMOPRM:
5234 		wbit = LONG_OPND;
5235 		w2 = MM_OPND;
5236 		goto xmmprm;
5237 	case XMMPRM:
5238 	case XMMPRM_66r:
5239 		wbit = LONG_OPND;
5240 		w2 = XMM_OPND;
5241 xmmprm:
5242 		THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, 1, 1);
5243 		break;
5244 
5245 	/* MMX/SIMD-Int predicated mm/mem to mm reg */
5246 	case MMOPM:
5247 	case MMOPM_66o:
5248 		wbit = w2 = MM_OPND;
5249 		goto xmmprm;
5250 
5251 	/* MMX/SIMD-Int mm reg to r32 */
5252 	case MMOM3:
5253 		NOMEM;
5254 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5255 		if (mode != REG_ONLY)
5256 			goto error;
5257 		wbit = MM_OPND;
5258 		MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0);
5259 		break;
5260 
5261 	/* SIMD memory or xmm reg operand to xmm reg		*/
5262 	case XMM:
5263 	case XMM_66o:
5264 	case XMM_66r:
5265 	case XMMO:
5266 	case XMMXIMPL:
5267 		wbit = XMM_OPND;
5268 		STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
5269 
5270 		if (dp->it_adrmode == XMMXIMPL && mode != REG_ONLY)
5271 			goto error;
5272 
5273 #ifdef DIS_TEXT
5274 		/*
5275 		 * movlps and movhlps share opcodes.  They differ in the
5276 		 * addressing modes allowed for their operands.
5277 		 * movhps and movlhps behave similarly.
5278 		 */
5279 		if (mode == REG_ONLY) {
5280 			if (strcmp(dp->it_name, "movlps") == 0)
5281 				(void) strncpy(x->d86_mnem, "movhlps", OPLEN);
5282 			else if (strcmp(dp->it_name, "movhps") == 0)
5283 				(void) strncpy(x->d86_mnem, "movlhps", OPLEN);
5284 		}
5285 #endif
5286 		if (dp->it_adrmode == XMMXIMPL)
5287 			mode = 0;	/* change for memory access size... */
5288 		break;
5289 
5290 	/* SIMD xmm reg to memory or xmm reg */
5291 	case XMMS:
5292 	case XMMOS:
5293 	case XMMMS:
5294 	case XMMOMS:
5295 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5296 #ifdef DIS_TEXT
5297 		if ((strcmp(dp->it_name, "movlps") == 0 ||
5298 		    strcmp(dp->it_name, "movhps") == 0 ||
5299 		    strcmp(dp->it_name, "movntps") == 0) &&
5300 		    mode == REG_ONLY)
5301 			goto error;
5302 #endif
5303 		wbit = XMM_OPND;
5304 		MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1);
5305 		break;
5306 
5307 	/* SIMD memory to xmm reg */
5308 	case XMMM:
5309 	case XMMM_66r:
5310 	case XMMOM:
5311 		wbit = XMM_OPND;
5312 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5313 #ifdef DIS_TEXT
5314 		if (mode == REG_ONLY) {
5315 			if (strcmp(dp->it_name, "movhps") == 0)
5316 				(void) strncpy(x->d86_mnem, "movlhps", OPLEN);
5317 			else
5318 				goto error;
5319 		}
5320 #endif
5321 		MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0);
5322 		break;
5323 
5324 	/* SIMD memory or r32 to xmm reg			*/
5325 	case XMM3MX:
5326 		wbit = LONG_OPND;
5327 		MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0);
5328 		break;
5329 
5330 	case XMM3MXS:
5331 		wbit = LONG_OPND;
5332 		MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1);
5333 		break;
5334 
5335 	/* SIMD memory or mm reg to xmm reg			*/
5336 	case XMMOMX:
5337 	/* SIMD mm to xmm */
5338 	case XMMMX:
5339 		wbit = MM_OPND;
5340 		MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0);
5341 		break;
5342 
5343 	/* SIMD memory or xmm reg to mm reg			*/
5344 	case XMMXMM:
5345 	case XMMOXMM:
5346 	case XMMXM:
5347 		wbit = XMM_OPND;
5348 		MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0);
5349 		break;
5350 
5351 
5352 	/* SIMD memory or xmm reg to r32			*/
5353 	case XMMXM3:
5354 		wbit = XMM_OPND;
5355 		MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0);
5356 		break;
5357 
5358 	/* SIMD xmm to r32					*/
5359 	case XMMX3:
5360 	case XMMOX3:
5361 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5362 		if (mode != REG_ONLY)
5363 			goto error;
5364 		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
5365 		dtrace_get_operand(x, mode, r_m, XMM_OPND, 0);
5366 		dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
5367 		NOMEM;
5368 		break;
5369 
5370 	/* SIMD predicated memory or xmm reg with/to xmm reg */
5371 	case XMMP:
5372 	case XMMP_66r:
5373 	case XMMP_66o:
5374 	case XMMOPM:
5375 		wbit = XMM_OPND;
5376 		THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1,
5377 		    1);
5378 
5379 #ifdef DIS_TEXT
5380 		/*
5381 		 * cmpps and cmpss vary their instruction name based
5382 		 * on the value of imm8.  Other XMMP instructions,
5383 		 * such as shufps, require explicit specification of
5384 		 * the predicate.
5385 		 */
5386 		if (dp->it_name[0] == 'c' &&
5387 		    dp->it_name[1] == 'm' &&
5388 		    dp->it_name[2] == 'p' &&
5389 		    strlen(dp->it_name) == 5) {
5390 			uchar_t pred = x->d86_opnd[0].d86_value & 0xff;
5391 
5392 			if (pred >= (sizeof (dis_PREDSUFFIX) / sizeof (char *)))
5393 				goto error;
5394 
5395 			(void) strncpy(x->d86_mnem, "cmp", OPLEN);
5396 			(void) strlcat(x->d86_mnem, dis_PREDSUFFIX[pred],
5397 			    OPLEN);
5398 			(void) strlcat(x->d86_mnem,
5399 			    dp->it_name + strlen(dp->it_name) - 2,
5400 			    OPLEN);
5401 			x->d86_opnd[0] = x->d86_opnd[1];
5402 			x->d86_opnd[1] = x->d86_opnd[2];
5403 			x->d86_numopnds = 2;
5404 		}
5405 
5406 		/*
5407 		 * The pclmulqdq instruction has a series of alternate names for
5408 		 * various encodings of the immediate byte. As such, if we
5409 		 * happen to find it and the immediate value matches, we'll
5410 		 * rewrite the mnemonic.
5411 		 */
5412 		if (strcmp(dp->it_name, "pclmulqdq") == 0) {
5413 			boolean_t changed = B_TRUE;
5414 			switch (x->d86_opnd[0].d86_value) {
5415 			case 0x00:
5416 				(void) strncpy(x->d86_mnem, "pclmullqlqdq",
5417 				    OPLEN);
5418 				break;
5419 			case 0x01:
5420 				(void) strncpy(x->d86_mnem, "pclmulhqlqdq",
5421 				    OPLEN);
5422 				break;
5423 			case 0x10:
5424 				(void) strncpy(x->d86_mnem, "pclmullqhqdq",
5425 				    OPLEN);
5426 				break;
5427 			case 0x11:
5428 				(void) strncpy(x->d86_mnem, "pclmulhqhqdq",
5429 				    OPLEN);
5430 				break;
5431 			default:
5432 				changed = B_FALSE;
5433 				break;
5434 			}
5435 
5436 			if (changed == B_TRUE) {
5437 				x->d86_opnd[0].d86_value_size = 0;
5438 				x->d86_opnd[0] = x->d86_opnd[1];
5439 				x->d86_opnd[1] = x->d86_opnd[2];
5440 				x->d86_numopnds = 2;
5441 			}
5442 		}
5443 #endif
5444 		break;
5445 
5446 	case XMMX2I:
5447 		FOUROPERAND(x, mode, reg, r_m, rex_prefix, XMM_OPND, XMM_OPND,
5448 		    1);
5449 		NOMEM;
5450 		break;
5451 
5452 	case XMM2I:
5453 		ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, XMM_OPND, 1);
5454 		NOMEM;
5455 		break;
5456 
5457 	/* immediate operand to accumulator */
5458 	case IA:
5459 		wbit = WBIT(opcode2);
5460 		dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1);
5461 		dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0);
5462 		NOMEM;
5463 		break;
5464 
5465 	/* memory or register operand to accumulator */
5466 	case MA:
5467 		wbit = WBIT(opcode2);
5468 		dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
5469 		dtrace_get_operand(x, mode, r_m, wbit, 0);
5470 		break;
5471 
5472 	/* si register to di register used to reference memory		*/
5473 	case SD:
5474 #ifdef DIS_TEXT
5475 		dtrace_check_override(x, 0);
5476 		x->d86_numopnds = 2;
5477 		if (addr_size == SIZE64) {
5478 			(void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)",
5479 			    OPLEN);
5480 			(void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)",
5481 			    OPLEN);
5482 		} else if (addr_size == SIZE32) {
5483 			(void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)",
5484 			    OPLEN);
5485 			(void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)",
5486 			    OPLEN);
5487 		} else {
5488 			(void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)",
5489 			    OPLEN);
5490 			(void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)",
5491 			    OPLEN);
5492 		}
5493 #endif
5494 		wbit = LONG_OPND;
5495 		break;
5496 
5497 	/* accumulator to di register				*/
5498 	case AD:
5499 		wbit = WBIT(opcode2);
5500 #ifdef DIS_TEXT
5501 		dtrace_check_override(x, 1);
5502 		x->d86_numopnds = 2;
5503 		dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 0);
5504 		if (addr_size == SIZE64)
5505 			(void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)",
5506 			    OPLEN);
5507 		else if (addr_size == SIZE32)
5508 			(void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)",
5509 			    OPLEN);
5510 		else
5511 			(void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)",
5512 			    OPLEN);
5513 #endif
5514 		break;
5515 
5516 	/* si register to accumulator				*/
5517 	case SA:
5518 		wbit = WBIT(opcode2);
5519 #ifdef DIS_TEXT
5520 		dtrace_check_override(x, 0);
5521 		x->d86_numopnds = 2;
5522 		if (addr_size == SIZE64)
5523 			(void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)",
5524 			    OPLEN);
5525 		else if (addr_size == SIZE32)
5526 			(void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)",
5527 			    OPLEN);
5528 		else
5529 			(void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)",
5530 			    OPLEN);
5531 		dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1);
5532 #endif
5533 		break;
5534 
5535 	/*
5536 	 * single operand, a 16/32 bit displacement
5537 	 */
5538 	case D:
5539 		wbit = LONG_OPND;
5540 		dtrace_disp_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0);
5541 		NOMEM;
5542 		break;
5543 
5544 	/* jmp/call indirect to memory or register operand		*/
5545 	case INM:
5546 #ifdef DIS_TEXT
5547 		(void) strlcat(x->d86_opnd[0].d86_prefix, "*", OPLEN);
5548 #endif
5549 		dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
5550 		dtrace_get_operand(x, mode, r_m, LONG_OPND, 0);
5551 		wbit = LONG_OPND;
5552 		break;
5553 
5554 	/*
5555 	 * for long jumps and long calls -- a new code segment
5556 	 * register and an offset in IP -- stored in object
5557 	 * code in reverse order. Note - not valid in amd64
5558 	 */
5559 	case SO:
5560 		dtrace_check_override(x, 1);
5561 		wbit = LONG_OPND;
5562 		dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 1);
5563 #ifdef DIS_TEXT
5564 		x->d86_opnd[1].d86_mode = MODE_SIGNED;
5565 #endif
5566 		/* will now get segment operand */
5567 		dtrace_imm_opnd(x, wbit, 2, 0);
5568 		break;
5569 
5570 	/*
5571 	 * jmp/call. single operand, 8 bit displacement.
5572 	 * added to current EIP in 'compofff'
5573 	 */
5574 	case BD:
5575 		dtrace_disp_opnd(x, BYTE_OPND, 1, 0);
5576 		NOMEM;
5577 		break;
5578 
5579 	/* single 32/16 bit immediate operand			*/
5580 	case I:
5581 		wbit = LONG_OPND;
5582 		dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0);
5583 		break;
5584 
5585 	/* single 8 bit immediate operand			*/
5586 	case Ib:
5587 		wbit = LONG_OPND;
5588 		dtrace_imm_opnd(x, wbit, 1, 0);
5589 		break;
5590 
5591 	case ENTER:
5592 		wbit = LONG_OPND;
5593 		dtrace_imm_opnd(x, wbit, 2, 0);
5594 		dtrace_imm_opnd(x, wbit, 1, 1);
5595 		switch (opnd_size) {
5596 		case SIZE64:
5597 			x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 8;
5598 			break;
5599 		case SIZE32:
5600 			x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 4;
5601 			break;
5602 		case SIZE16:
5603 			x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 2;
5604 			break;
5605 		}
5606 
5607 		break;
5608 
5609 	/* 16-bit immediate operand */
5610 	case RET:
5611 		wbit = LONG_OPND;
5612 		dtrace_imm_opnd(x, wbit, 2, 0);
5613 		break;
5614 
5615 	/* single 8 bit port operand				*/
5616 	case P:
5617 		dtrace_check_override(x, 0);
5618 		dtrace_imm_opnd(x, BYTE_OPND, 1, 0);
5619 		NOMEM;
5620 		break;
5621 
5622 	/* single operand, dx register (variable port instruction) */
5623 	case V:
5624 		x->d86_numopnds = 1;
5625 		dtrace_check_override(x, 0);
5626 #ifdef DIS_TEXT
5627 		(void) strlcat(x->d86_opnd[0].d86_opnd, "(%dx)", OPLEN);
5628 #endif
5629 		NOMEM;
5630 		break;
5631 
5632 	/*
5633 	 * The int instruction, which has two forms:
5634 	 * int 3 (breakpoint) or
5635 	 * int n, where n is indicated in the subsequent
5636 	 * byte (format Ib).  The int 3 instruction (opcode 0xCC),
5637 	 * where, although the 3 looks  like an operand,
5638 	 * it is implied by the opcode. It must be converted
5639 	 * to the correct base and output.
5640 	 */
5641 	case INT3:
5642 #ifdef DIS_TEXT
5643 		x->d86_numopnds = 1;
5644 		x->d86_opnd[0].d86_mode = MODE_SIGNED;
5645 		x->d86_opnd[0].d86_value_size = 1;
5646 		x->d86_opnd[0].d86_value = 3;
5647 #endif
5648 		NOMEM;
5649 		break;
5650 
5651 	/* single 8 bit immediate operand			*/
5652 	case INTx:
5653 		dtrace_imm_opnd(x, BYTE_OPND, 1, 0);
5654 		NOMEM;
5655 		break;
5656 
5657 	/* an unused byte must be discarded */
5658 	case U:
5659 		if (x->d86_get_byte(x->d86_data) < 0)
5660 			goto error;
5661 		x->d86_len++;
5662 		NOMEM;
5663 		break;
5664 
5665 	case CBW:
5666 #ifdef DIS_TEXT
5667 		if (opnd_size == SIZE16)
5668 			(void) strlcat(x->d86_mnem, "cbtw", OPLEN);
5669 		else if (opnd_size == SIZE32)
5670 			(void) strlcat(x->d86_mnem, "cwtl", OPLEN);
5671 		else
5672 			(void) strlcat(x->d86_mnem, "cltq", OPLEN);
5673 #endif
5674 		wbit = LONG_OPND;
5675 		NOMEM;
5676 		break;
5677 
5678 	case CWD:
5679 #ifdef DIS_TEXT
5680 		if (opnd_size == SIZE16)
5681 			(void) strlcat(x->d86_mnem, "cwtd", OPLEN);
5682 		else if (opnd_size == SIZE32)
5683 			(void) strlcat(x->d86_mnem, "cltd", OPLEN);
5684 		else
5685 			(void) strlcat(x->d86_mnem, "cqtd", OPLEN);
5686 #endif
5687 		wbit = LONG_OPND;
5688 		NOMEM;
5689 		break;
5690 
5691 	case XMMSFNC:
5692 		/*
5693 		 * sfence is sfence if mode is REG_ONLY.  If mode isn't
5694 		 * REG_ONLY, mnemonic should be 'clflush'.
5695 		 */
5696 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5697 
5698 		/* sfence doesn't take operands */
5699 		if (mode != REG_ONLY) {
5700 			if (opnd_size_prefix == 0x66) {
5701 #ifdef DIS_TEXT
5702 				(void) strlcat(x->d86_mnem, "clflushopt",
5703 				    OPLEN);
5704 #endif
5705 			} else if (opnd_size_prefix == 0) {
5706 #ifdef DIS_TEXT
5707 				(void) strlcat(x->d86_mnem, "clflush", OPLEN);
5708 #endif
5709 			} else {
5710 				/* Unknown instruction */
5711 				goto error;
5712 			}
5713 
5714 			dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
5715 			dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0);
5716 			NOMEM;
5717 #ifdef DIS_TEXT
5718 		} else {
5719 			(void) strlcat(x->d86_mnem, "sfence", OPLEN);
5720 #endif
5721 		}
5722 		break;
5723 
5724 	case FSGS:
5725 		/*
5726 		 * The FSGSBASE instructions are taken only when the mode is set
5727 		 * to registers. They share opcodes with instructions like
5728 		 * fxrstor, stmxcsr, etc. We handle the repz prefix earlier.
5729 		 */
5730 		wbit = WBIT(opcode2);
5731 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5732 		dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
5733 		dtrace_get_operand(x, mode, r_m, wbit, 0);
5734 		if (mode == REG_ONLY) {
5735 			NOMEM;
5736 		}
5737 		break;
5738 
5739 	/*
5740 	 * no disassembly, the mnemonic was all there was so go on
5741 	 */
5742 	case NORM:
5743 		if (dp->it_invalid32 && cpu_mode != SIZE64)
5744 			goto error;
5745 		NOMEM;
5746 		/*FALLTHROUGH*/
5747 	case IMPLMEM:
5748 		break;
5749 
5750 	case XMMFENCE:
5751 		/*
5752 		 * XRSTOR, XSAVEOPT and LFENCE share the same opcode but
5753 		 * differ in mode and reg.
5754 		 */
5755 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5756 
5757 		if (mode == REG_ONLY) {
5758 			/*
5759 			 * Only the following exact byte sequences are allowed:
5760 			 *
5761 			 *	0f ae e8	lfence
5762 			 *	0f ae f0	mfence
5763 			 */
5764 			if ((uint8_t)x->d86_bytes[x->d86_len - 1] != 0xe8 &&
5765 			    (uint8_t)x->d86_bytes[x->d86_len - 1] != 0xf0)
5766 				goto error;
5767 		} else {
5768 #ifdef DIS_TEXT
5769 			if (reg == 5) {
5770 				(void) strncpy(x->d86_mnem, "xrstor", OPLEN);
5771 			} else if (reg == 6) {
5772 				if (opnd_size_prefix == 0x66) {
5773 					(void) strncpy(x->d86_mnem, "clwb",
5774 					    OPLEN);
5775 				} else if (opnd_size_prefix == 0x00) {
5776 					(void) strncpy(x->d86_mnem, "xsaveopt",
5777 					    OPLEN);
5778 				} else {
5779 					goto error;
5780 				}
5781 			} else {
5782 				goto error;
5783 			}
5784 #endif
5785 			dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
5786 			dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0);
5787 		}
5788 		break;
5789 
5790 	/* float reg */
5791 	case F:
5792 #ifdef DIS_TEXT
5793 		x->d86_numopnds = 1;
5794 		(void) strlcat(x->d86_opnd[0].d86_opnd, "%st(X)", OPLEN);
5795 		x->d86_opnd[0].d86_opnd[4] = r_m + '0';
5796 #endif
5797 		NOMEM;
5798 		break;
5799 
5800 	/* float reg to float reg, with ret bit present */
5801 	case FF:
5802 		vbit = opcode2 >> 2 & 0x1;	/* vbit = 1: st -> st(i) */
5803 		/*FALLTHROUGH*/
5804 	case FFC:				/* case for vbit always = 0 */
5805 #ifdef DIS_TEXT
5806 		x->d86_numopnds = 2;
5807 		(void) strlcat(x->d86_opnd[1 - vbit].d86_opnd, "%st", OPLEN);
5808 		(void) strlcat(x->d86_opnd[vbit].d86_opnd, "%st(X)", OPLEN);
5809 		x->d86_opnd[vbit].d86_opnd[4] = r_m + '0';
5810 #endif
5811 		NOMEM;
5812 		break;
5813 
5814 	/* AVX instructions */
5815 	case VEX_MO:
5816 		/* op(ModR/M.r/m) */
5817 		x->d86_numopnds = 1;
5818 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5819 #ifdef DIS_TEXT
5820 		if ((dp == &dis_opAVX0F[0xA][0xE]) && (reg == 3))
5821 			(void) strncpy(x->d86_mnem, "vstmxcsr", OPLEN);
5822 #endif
5823 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5824 		dtrace_get_operand(x, mode, r_m, wbit, 0);
5825 		break;
5826 	case VEX_RMrX:
5827 	case FMA:
5828 		/* ModR/M.reg := op(VEX.vvvv, ModR/M.r/m) */
5829 		x->d86_numopnds = 3;
5830 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5831 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5832 
5833 		/*
5834 		 * In classic Intel fashion, the opcodes for all of the FMA
5835 		 * instructions all have two possible mnemonics which vary by
5836 		 * one letter, which is selected based on the value of the wbit.
5837 		 * When wbit is one, they have the 'd' suffix and when 'wbit' is
5838 		 * 0, they have the 's' suffix. Otherwise, the FMA instructions
5839 		 * are all a standard VEX_RMrX.
5840 		 */
5841 #ifdef DIS_TEXT
5842 		if (dp->it_adrmode == FMA) {
5843 			size_t len = strlen(dp->it_name);
5844 			(void) strncpy(x->d86_mnem, dp->it_name, OPLEN);
5845 			if (len + 1 < OPLEN) {
5846 				(void) strncpy(x->d86_mnem + len,
5847 				    vex_W != 0 ? "d" : "s", OPLEN - len);
5848 			}
5849 		}
5850 #endif
5851 
5852 		if (mode != REG_ONLY) {
5853 			if ((dp == &dis_opAVXF20F[0x10]) ||
5854 			    (dp == &dis_opAVXF30F[0x10])) {
5855 				/* vmovsd <m64>, <xmm> */
5856 				/* or vmovss <m64>, <xmm> */
5857 				x->d86_numopnds = 2;
5858 				goto L_VEX_MX;
5859 			}
5860 		}
5861 
5862 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
5863 		/*
5864 		 * VEX prefix uses the 1's complement form to encode the
5865 		 * XMM/YMM regs
5866 		 */
5867 		dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
5868 
5869 		if ((dp == &dis_opAVXF20F[0x2A]) ||
5870 		    (dp == &dis_opAVXF30F[0x2A])) {
5871 			/*
5872 			 * vcvtsi2si </r,m>, <xmm>, <xmm> or vcvtsi2ss </r,m>,
5873 			 * <xmm>, <xmm>
5874 			 */
5875 			wbit = LONG_OPND;
5876 		}
5877 #ifdef DIS_TEXT
5878 		else if ((mode == REG_ONLY) &&
5879 		    (dp == &dis_opAVX0F[0x1][0x6])) {	/* vmovlhps */
5880 			(void) strncpy(x->d86_mnem, "vmovlhps", OPLEN);
5881 		} else if ((mode == REG_ONLY) &&
5882 		    (dp == &dis_opAVX0F[0x1][0x2])) {	/* vmovhlps */
5883 			(void) strncpy(x->d86_mnem, "vmovhlps", OPLEN);
5884 		}
5885 #endif
5886 		dtrace_get_operand(x, mode, r_m, wbit, 0);
5887 
5888 		break;
5889 
5890 	case VEX_VRMrX:
5891 		/* ModR/M.reg := op(MODR/M.r/m, VEX.vvvv) */
5892 		x->d86_numopnds = 3;
5893 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5894 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5895 
5896 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
5897 		/*
5898 		 * VEX prefix uses the 1's complement form to encode the
5899 		 * XMM/YMM regs
5900 		 */
5901 		dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 0);
5902 
5903 		dtrace_get_operand(x, mode, r_m, wbit, 1);
5904 		break;
5905 
5906 	case VEX_SbVM:
5907 		/* ModR/M.reg := op(MODR/M.r/m, VSIB, VEX.vvvv) */
5908 		x->d86_numopnds = 3;
5909 		x->d86_vsib = 1;
5910 
5911 		/*
5912 		 * All instructions that use VSIB are currently a mess. See the
5913 		 * comment around the dis_gather_regs_t structure definition.
5914 		 */
5915 
5916 		vreg = &dis_vgather[opcode2][vex_W][vex_L];
5917 
5918 #ifdef DIS_TEXT
5919 		(void) strncpy(x->d86_mnem, dp->it_name, OPLEN);
5920 		(void) strlcat(x->d86_mnem + strlen(dp->it_name),
5921 		    vreg->dgr_suffix, OPLEN - strlen(dp->it_name));
5922 #endif
5923 
5924 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5925 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5926 
5927 		dtrace_get_operand(x, REG_ONLY, reg, vreg->dgr_arg2, 2);
5928 		/*
5929 		 * VEX prefix uses the 1's complement form to encode the
5930 		 * XMM/YMM regs
5931 		 */
5932 		dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), vreg->dgr_arg0,
5933 		    0);
5934 		dtrace_get_operand(x, mode, r_m, vreg->dgr_arg1, 1);
5935 		break;
5936 
5937 	case VEX_RRX:
5938 		/* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */
5939 		x->d86_numopnds = 3;
5940 
5941 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5942 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5943 
5944 		if (mode != REG_ONLY) {
5945 			if ((dp == &dis_opAVXF20F[0x11]) ||
5946 			    (dp == &dis_opAVXF30F[0x11])) {
5947 				/* vmovsd <xmm>, <m64> */
5948 				/* or vmovss <xmm>, <m64> */
5949 				x->d86_numopnds = 2;
5950 				goto L_VEX_RM;
5951 			}
5952 		}
5953 
5954 		dtrace_get_operand(x, mode, r_m, wbit, 2);
5955 		dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
5956 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
5957 		break;
5958 
5959 	case VEX_RMRX:
5960 		/* ModR/M.reg := op(VEX.vvvv, ModR/M.r_m, imm8[7:4]) */
5961 		x->d86_numopnds = 4;
5962 
5963 		dtrace_get_modrm(x, &mode, &reg, &r_m);
5964 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5965 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 3);
5966 		dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2);
5967 		if (dp == &dis_opAVX660F3A[0x18]) {
5968 			/* vinsertf128 <imm8>, <xmm>, <ymm>, <ymm> */
5969 			dtrace_get_operand(x, mode, r_m, XMM_OPND, 1);
5970 		} else if ((dp == &dis_opAVX660F3A[0x20]) ||
5971 		    (dp == & dis_opAVX660F[0xC4])) {
5972 			/* vpinsrb <imm8>, <reg/mm>, <xmm>, <xmm> */
5973 			/* or vpinsrw <imm8>, <reg/mm>, <xmm>, <xmm> */
5974 			dtrace_get_operand(x, mode, r_m, LONG_OPND, 1);
5975 		} else if (dp == &dis_opAVX660F3A[0x22]) {
5976 			/* vpinsrd/q <imm8>, <reg/mm>, <xmm>, <xmm> */
5977 #ifdef DIS_TEXT
5978 			if (vex_W)
5979 				x->d86_mnem[6] = 'q';
5980 #endif
5981 			dtrace_get_operand(x, mode, r_m, LONG_OPND, 1);
5982 		} else {
5983 			dtrace_get_operand(x, mode, r_m, wbit, 1);
5984 		}
5985 
5986 		/* one byte immediate number */
5987 		dtrace_imm_opnd(x, wbit, 1, 0);
5988 
5989 		/* vblendvpd, vblendvps, vblendvb use the imm encode the regs */
5990 		if ((dp == &dis_opAVX660F3A[0x4A]) ||
5991 		    (dp == &dis_opAVX660F3A[0x4B]) ||
5992 		    (dp == &dis_opAVX660F3A[0x4C])) {
5993 #ifdef DIS_TEXT
5994 			int regnum = (x->d86_opnd[0].d86_value & 0xF0) >> 4;
5995 #endif
5996 			x->d86_opnd[0].d86_mode = MODE_NONE;
5997 #ifdef DIS_TEXT
5998 			if (vex_L)
5999 				(void) strncpy(x->d86_opnd[0].d86_opnd,
6000 				    dis_YMMREG[regnum], OPLEN);
6001 			else
6002 				(void) strncpy(x->d86_opnd[0].d86_opnd,
6003 				    dis_XMMREG[regnum], OPLEN);
6004 #endif
6005 		}
6006 		break;
6007 
6008 	case VEX_MX:
6009 		/* ModR/M.reg := op(ModR/M.rm) */
6010 		x->d86_numopnds = 2;
6011 
6012 		dtrace_get_modrm(x, &mode, &reg, &r_m);
6013 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
6014 L_VEX_MX:
6015 
6016 		if ((dp == &dis_opAVXF20F[0xE6]) ||
6017 		    (dp == &dis_opAVX660F[0x5A]) ||
6018 		    (dp == &dis_opAVX660F[0xE6])) {
6019 			/* vcvtpd2dq <ymm>, <xmm> */
6020 			/* or vcvtpd2ps <ymm>, <xmm> */
6021 			/* or vcvttpd2dq <ymm>, <xmm> */
6022 			dtrace_get_operand(x, REG_ONLY, reg, XMM_OPND, 1);
6023 			dtrace_get_operand(x, mode, r_m, wbit, 0);
6024 		} else if ((dp == &dis_opAVXF30F[0xE6]) ||
6025 		    (dp == &dis_opAVX0F[0x5][0xA]) ||
6026 		    (dp == &dis_opAVX660F38[0x13]) ||
6027 		    (dp == &dis_opAVX660F38[0x18]) ||
6028 		    (dp == &dis_opAVX660F38[0x19]) ||
6029 		    (dp == &dis_opAVX660F38[0x58]) ||
6030 		    (dp == &dis_opAVX660F38[0x78]) ||
6031 		    (dp == &dis_opAVX660F38[0x79]) ||
6032 		    (dp == &dis_opAVX660F38[0x59])) {
6033 			/* vcvtdq2pd <xmm>, <ymm> */
6034 			/* or vcvtps2pd <xmm>, <ymm> */
6035 			/* or vcvtph2ps <xmm>, <ymm> */
6036 			/* or vbroadcasts* <xmm>, <ymm> */
6037 			dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
6038 			dtrace_get_operand(x, mode, r_m, XMM_OPND, 0);
6039 		} else if (dp == &dis_opAVX660F[0x6E]) {
6040 			/* vmovd/q <reg/mem 32/64>, <xmm> */
6041 #ifdef DIS_TEXT
6042 			if (vex_W)
6043 				x->d86_mnem[4] = 'q';
6044 #endif
6045 			dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
6046 			dtrace_get_operand(x, mode, r_m, LONG_OPND, 0);
6047 		} else {
6048 			dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
6049 			dtrace_get_operand(x, mode, r_m, wbit, 0);
6050 		}
6051 
6052 		break;
6053 
6054 	case VEX_MXI:
6055 		/* ModR/M.reg := op(ModR/M.rm, imm8) */
6056 		x->d86_numopnds = 3;
6057 
6058 		dtrace_get_modrm(x, &mode, &reg, &r_m);
6059 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
6060 
6061 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
6062 		dtrace_get_operand(x, mode, r_m, wbit, 1);
6063 
6064 		/* one byte immediate number */
6065 		dtrace_imm_opnd(x, wbit, 1, 0);
6066 		break;
6067 
6068 	case VEX_XXI:
6069 		/* VEX.vvvv := op(ModR/M.rm, imm8) */
6070 		x->d86_numopnds = 3;
6071 
6072 		dtrace_get_modrm(x, &mode, &reg, &r_m);
6073 #ifdef DIS_TEXT
6074 		(void) strncpy(x->d86_mnem, dis_AVXvgrp7[opcode2 - 1][reg],
6075 		    OPLEN);
6076 #endif
6077 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
6078 
6079 		dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2);
6080 		dtrace_get_operand(x, REG_ONLY, r_m, wbit, 1);
6081 
6082 		/* one byte immediate number */
6083 		dtrace_imm_opnd(x, wbit, 1, 0);
6084 		break;
6085 
6086 	case VEX_MR:
6087 		/* ModR/M.reg (reg32/64) := op(ModR/M.rm) */
6088 		if (dp == &dis_opAVX660F[0xC5]) {
6089 			/* vpextrw <imm8>, <xmm>, <reg> */
6090 			x->d86_numopnds = 2;
6091 			vbit = 2;
6092 		} else {
6093 			x->d86_numopnds = 2;
6094 			vbit = 1;
6095 		}
6096 
6097 		dtrace_get_modrm(x, &mode, &reg, &r_m);
6098 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
6099 		dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, vbit);
6100 		dtrace_get_operand(x, mode, r_m, wbit, vbit - 1);
6101 
6102 		if (vbit == 2)
6103 			dtrace_imm_opnd(x, wbit, 1, 0);
6104 
6105 		break;
6106 
6107 	case VEX_KMR:
6108 		/* opmask: mod_rm := %k */
6109 		x->d86_numopnds = 2;
6110 		dtrace_get_modrm(x, &mode, &reg, &r_m);
6111 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
6112 		dtrace_get_operand(x, mode, r_m, LONG_OPND, 1);
6113 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
6114 		break;
6115 
6116 	case VEX_KRM:
6117 		/* opmask: mod_reg := mod_rm */
6118 		x->d86_numopnds = 2;
6119 		dtrace_get_modrm(x, &mode, &reg, &r_m);
6120 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
6121 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
6122 		if (mode == REG_ONLY) {
6123 			dtrace_get_operand(x, mode, r_m, KOPMASK_OPND, 0);
6124 		} else {
6125 			dtrace_get_operand(x, mode, r_m, LONG_OPND, 0);
6126 		}
6127 		break;
6128 
6129 	case VEX_KRR:
6130 		/* opmask: mod_reg := mod_rm */
6131 		x->d86_numopnds = 2;
6132 		dtrace_get_modrm(x, &mode, &reg, &r_m);
6133 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
6134 		dtrace_get_operand(x, mode, reg, wbit, 1);
6135 		dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 0);
6136 		break;
6137 
6138 	case VEX_RRI:
6139 		/* implicit(eflags/r32) := op(ModR/M.reg, ModR/M.rm) */
6140 		x->d86_numopnds = 2;
6141 
6142 		dtrace_get_modrm(x, &mode, &reg, &r_m);
6143 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
6144 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
6145 		dtrace_get_operand(x, mode, r_m, wbit, 0);
6146 		break;
6147 
6148 	case VEX_RX:
6149 		/* ModR/M.rm := op(ModR/M.reg) */
6150 		/* vextractf128 || vcvtps2ph */
6151 		if (dp == &dis_opAVX660F3A[0x19] ||
6152 		    dp == &dis_opAVX660F3A[0x1d]) {
6153 			x->d86_numopnds = 3;
6154 
6155 			dtrace_get_modrm(x, &mode, &reg, &r_m);
6156 			dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
6157 
6158 			dtrace_get_operand(x, mode, r_m, XMM_OPND, 2);
6159 			dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
6160 
6161 			/* one byte immediate number */
6162 			dtrace_imm_opnd(x, wbit, 1, 0);
6163 			break;
6164 		}
6165 
6166 		x->d86_numopnds = 2;
6167 
6168 		dtrace_get_modrm(x, &mode, &reg, &r_m);
6169 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
6170 		dtrace_get_operand(x, mode, r_m, wbit, 1);
6171 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
6172 		break;
6173 
6174 	case VEX_RR:
6175 		/* ModR/M.rm := op(ModR/M.reg) */
6176 		x->d86_numopnds = 2;
6177 
6178 		dtrace_get_modrm(x, &mode, &reg, &r_m);
6179 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
6180 
6181 		if (dp == &dis_opAVX660F[0x7E]) {
6182 			/* vmovd/q <reg/mem 32/64>, <xmm> */
6183 #ifdef DIS_TEXT
6184 			if (vex_W)
6185 				x->d86_mnem[4] = 'q';
6186 #endif
6187 			dtrace_get_operand(x, mode, r_m, LONG_OPND, 1);
6188 		} else
6189 			dtrace_get_operand(x, mode, r_m, wbit, 1);
6190 
6191 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
6192 		break;
6193 
6194 	case VEX_RRi:
6195 		/* ModR/M.rm := op(ModR/M.reg, imm) */
6196 		x->d86_numopnds = 3;
6197 
6198 		dtrace_get_modrm(x, &mode, &reg, &r_m);
6199 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
6200 
6201 #ifdef DIS_TEXT
6202 		if (dp == &dis_opAVX660F3A[0x16]) {
6203 			/* vpextrd/q <imm>, <xmm>, <reg/mem 32/64> */
6204 			if (vex_W)
6205 				x->d86_mnem[6] = 'q';
6206 		}
6207 #endif
6208 		dtrace_get_operand(x, mode, r_m, LONG_OPND, 2);
6209 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
6210 
6211 		/* one byte immediate number */
6212 		dtrace_imm_opnd(x, wbit, 1, 0);
6213 		break;
6214 	case VEX_RIM:
6215 		/* ModR/M.rm := op(ModR/M.reg, imm) */
6216 		x->d86_numopnds = 3;
6217 
6218 		dtrace_get_modrm(x, &mode, &reg, &r_m);
6219 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
6220 
6221 		dtrace_get_operand(x, mode, r_m, XMM_OPND, 2);
6222 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
6223 		/* one byte immediate number */
6224 		dtrace_imm_opnd(x, wbit, 1, 0);
6225 		break;
6226 
6227 	case VEX_RM:
6228 		/* ModR/M.rm := op(ModR/M.reg) */
6229 		if (dp == &dis_opAVX660F3A[0x17]) {	/* vextractps */
6230 			x->d86_numopnds = 3;
6231 
6232 			dtrace_get_modrm(x, &mode, &reg, &r_m);
6233 			dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
6234 
6235 			dtrace_get_operand(x, mode, r_m, LONG_OPND, 2);
6236 			dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
6237 			/* one byte immediate number */
6238 			dtrace_imm_opnd(x, wbit, 1, 0);
6239 			break;
6240 		}
6241 		x->d86_numopnds = 2;
6242 
6243 		dtrace_get_modrm(x, &mode, &reg, &r_m);
6244 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
6245 L_VEX_RM:
6246 		vbit = 1;
6247 		dtrace_get_operand(x, mode, r_m, wbit, vbit);
6248 		dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit - 1);
6249 
6250 		break;
6251 
6252 	case VEX_RRM:
6253 		/* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */
6254 		x->d86_numopnds = 3;
6255 
6256 		dtrace_get_modrm(x, &mode, &reg, &r_m);
6257 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
6258 		dtrace_get_operand(x, mode, r_m, wbit, 2);
6259 		/* VEX use the 1's complement form encode the XMM/YMM regs */
6260 		dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
6261 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
6262 		break;
6263 
6264 	case VEX_RMX:
6265 		/* ModR/M.reg := op(VEX.vvvv, ModR/M.rm) */
6266 		x->d86_numopnds = 3;
6267 
6268 		dtrace_get_modrm(x, &mode, &reg, &r_m);
6269 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
6270 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
6271 		dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
6272 		dtrace_get_operand(x, REG_ONLY, r_m, wbit, 0);
6273 		break;
6274 
6275 	case VEX_NONE:
6276 #ifdef DIS_TEXT
6277 		if (vex_L)
6278 			(void) strncpy(x->d86_mnem, "vzeroall", OPLEN);
6279 #endif
6280 		break;
6281 	case BLS: {
6282 
6283 		/*
6284 		 * The BLS instructions are VEX instructions that are based on
6285 		 * VEX.0F38.F3; however, they are considered special group 17
6286 		 * and like everything else, they use the bits in 3-5 of the
6287 		 * MOD R/M to determine the sub instruction. Unlike many others
6288 		 * like the VMX instructions, these are valid both for memory
6289 		 * and register forms.
6290 		 */
6291 
6292 		dtrace_get_modrm(x, &mode, &reg, &r_m);
6293 		dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
6294 
6295 		switch (reg) {
6296 		case 1:
6297 #ifdef	DIS_TEXT
6298 			blsinstr = "blsr";
6299 #endif
6300 			break;
6301 		case 2:
6302 #ifdef	DIS_TEXT
6303 			blsinstr = "blsmsk";
6304 #endif
6305 			break;
6306 		case 3:
6307 #ifdef	DIS_TEXT
6308 			blsinstr = "blsi";
6309 #endif
6310 			break;
6311 		default:
6312 			goto error;
6313 		}
6314 
6315 		x->d86_numopnds = 2;
6316 #ifdef DIS_TEXT
6317 		(void) strncpy(x->d86_mnem, blsinstr, OPLEN);
6318 #endif
6319 		dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
6320 		dtrace_get_operand(x, mode, r_m, wbit, 0);
6321 		break;
6322 	}
6323 	case EVEX_MX:
6324 		/* ModR/M.reg := op(ModR/M.rm) */
6325 		x->d86_numopnds = 2;
6326 		dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2);
6327 		dtrace_get_modrm(x, &mode, &reg, &r_m);
6328 		evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff;
6329 		dtrace_evex_adjust_reg(evex_byte1, &reg);
6330 		dtrace_evex_adjust_rm(evex_byte1, &r_m);
6331 		dtrace_evex_adjust_reg_name(evex_L, &wbit);
6332 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
6333 		dtrace_evex_adjust_z_opmask(x, 1, evex_byte3);
6334 		dtrace_get_operand(x, mode, r_m, wbit, 0);
6335 		dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm);
6336 		break;
6337 	case EVEX_RX:
6338 		/* ModR/M.rm := op(ModR/M.reg) */
6339 		x->d86_numopnds = 2;
6340 		dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2);
6341 		dtrace_get_modrm(x, &mode, &reg, &r_m);
6342 		evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff;
6343 		dtrace_evex_adjust_reg(evex_byte1, &reg);
6344 		dtrace_evex_adjust_rm(evex_byte1, &r_m);
6345 		dtrace_evex_adjust_reg_name(evex_L, &wbit);
6346 		dtrace_get_operand(x, mode, r_m, wbit, 1);
6347 		dtrace_evex_adjust_disp8_n(x, 1, evex_L, evex_modrm);
6348 		dtrace_evex_adjust_z_opmask(x, 1, evex_byte3);
6349 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
6350 		break;
6351 	case EVEX_RMrX:
6352 		/* ModR/M.reg := op(EVEX.vvvv, ModR/M.r/m) */
6353 		x->d86_numopnds = 3;
6354 		dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2);
6355 		dtrace_get_modrm(x, &mode, &reg, &r_m);
6356 		evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff;
6357 		dtrace_evex_adjust_reg(evex_byte1, &reg);
6358 		dtrace_evex_adjust_rm(evex_byte1, &r_m);
6359 		dtrace_evex_adjust_reg_name(evex_L, &wbit);
6360 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
6361 		/*
6362 		 * EVEX.vvvv is the same as VEX.vvvv (ones complement of the
6363 		 * register specifier). The EVEX prefix handling uses the vex_v
6364 		 * variable for these bits.
6365 		 */
6366 		dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
6367 		dtrace_get_operand(x, mode, r_m, wbit, 0);
6368 		dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm);
6369 		dtrace_evex_adjust_z_opmask(x, 2, evex_byte3);
6370 		break;
6371 	case EVEX_RMRX:
6372 		/* ModR/M.reg := op(EVEX.vvvv, ModR/M.r_m, imm8) */
6373 		x->d86_numopnds = 4;
6374 
6375 		dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2);
6376 		dtrace_get_modrm(x, &mode, &reg, &r_m);
6377 		evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff;
6378 		dtrace_evex_adjust_reg(evex_byte1, &reg);
6379 		dtrace_evex_adjust_rm(evex_byte1, &r_m);
6380 		dtrace_evex_adjust_reg_name(evex_L, &wbit);
6381 		dtrace_get_operand(x, REG_ONLY, reg, wbit, 3);
6382 		/*
6383 		 * EVEX.vvvv is the same as VEX.vvvv (ones complement of the
6384 		 * register specifier). The EVEX prefix handling uses the vex_v
6385 		 * variable for these bits.
6386 		 */
6387 		dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2);
6388 		dtrace_get_operand(x, mode, r_m, wbit, 1);
6389 		dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm);
6390 		dtrace_evex_adjust_z_opmask(x, 3, evex_byte3);
6391 
6392 		dtrace_imm_opnd(x, wbit, 1, 0);
6393 		break;
6394 	/* an invalid op code */
6395 	case AM:
6396 	case DM:
6397 	case OVERRIDE:
6398 	case PREFIX:
6399 	case UNKNOWN:
6400 		NOMEM;
6401 	default:
6402 		goto error;
6403 	} /* end switch */
6404 	if (x->d86_error)
6405 		goto error;
6406 
6407 done:
6408 #ifdef DIS_MEM
6409 	/*
6410 	 * compute the size of any memory accessed by the instruction
6411 	 */
6412 	if (x->d86_memsize != 0) {
6413 		return (0);
6414 	} else if (dp->it_stackop) {
6415 		switch (opnd_size) {
6416 		case SIZE16:
6417 			x->d86_memsize = 2;
6418 			break;
6419 		case SIZE32:
6420 			x->d86_memsize = 4;
6421 			break;
6422 		case SIZE64:
6423 			x->d86_memsize = 8;
6424 			break;
6425 		}
6426 	} else if (nomem || mode == REG_ONLY) {
6427 		x->d86_memsize = 0;
6428 
6429 	} else if (dp->it_size != 0) {
6430 		/*
6431 		 * In 64 bit mode descriptor table entries
6432 		 * go up to 10 bytes and popf/pushf are always 8 bytes
6433 		 */
6434 		if (x->d86_mode == SIZE64 && dp->it_size == 6)
6435 			x->d86_memsize = 10;
6436 		else if (x->d86_mode == SIZE64 && opcode1 == 0x9 &&
6437 		    (opcode2 == 0xc || opcode2 == 0xd))
6438 			x->d86_memsize = 8;
6439 		else
6440 			x->d86_memsize = dp->it_size;
6441 
6442 	} else if (wbit == 0) {
6443 		x->d86_memsize = 1;
6444 
6445 	} else if (wbit == LONG_OPND) {
6446 		if (opnd_size == SIZE64)
6447 			x->d86_memsize = 8;
6448 		else if (opnd_size == SIZE32)
6449 			x->d86_memsize = 4;
6450 		else
6451 			x->d86_memsize = 2;
6452 
6453 	} else if (wbit == SEG_OPND) {
6454 		x->d86_memsize = 4;
6455 
6456 	} else {
6457 		x->d86_memsize = 8;
6458 	}
6459 #endif
6460 	return (0);
6461 
6462 error:
6463 #ifdef DIS_TEXT
6464 	(void) strlcat(x->d86_mnem, "undef", OPLEN);
6465 #endif
6466 	return (1);
6467 }
6468 
6469 #ifdef DIS_TEXT
6470 
6471 /*
6472  * Some instructions should have immediate operands printed
6473  * as unsigned integers. We compare against this table.
6474  */
6475 static char *unsigned_ops[] = {
6476 	"or", "and", "xor", "test", "in", "out", "lcall", "ljmp",
6477 	"rcr", "rcl", "ror", "rol", "shl", "shr", "sal", "psr", "psl",
6478 	0
6479 };
6480 
6481 
6482 static int
6483 isunsigned_op(char *opcode)
6484 {
6485 	char *where;
6486 	int i;
6487 	int is_unsigned = 0;
6488 
6489 	/*
6490 	 * Work back to start of last mnemonic, since we may have
6491 	 * prefixes on some opcodes.
6492 	 */
6493 	where = opcode + strlen(opcode) - 1;
6494 	while (where > opcode && *where != ' ')
6495 		--where;
6496 	if (*where == ' ')
6497 		++where;
6498 
6499 	for (i = 0; unsigned_ops[i]; ++i) {
6500 		if (strncmp(where, unsigned_ops[i],
6501 		    strlen(unsigned_ops[i])))
6502 			continue;
6503 		is_unsigned = 1;
6504 		break;
6505 	}
6506 	return (is_unsigned);
6507 }
6508 
6509 /*
6510  * Print a numeric immediate into end of buf, maximum length buflen.
6511  * The immediate may be an address or a displacement.  Mask is set
6512  * for address size.  If the immediate is a "small negative", or
6513  * if it's a negative displacement of any magnitude, print as -<absval>.
6514  * Respect the "octal" flag.  "Small negative" is defined as "in the
6515  * interval [NEG_LIMIT, 0)".
6516  *
6517  * Also, "isunsigned_op()" instructions never print negatives.
6518  *
6519  * Return whether we decided to print a negative value or not.
6520  */
6521 
6522 #define	NEG_LIMIT	-255
6523 enum {IMM, DISP};
6524 enum {POS, TRY_NEG};
6525 
6526 static int
6527 print_imm(dis86_t *dis, uint64_t usv, uint64_t mask, char *buf,
6528     size_t buflen, int disp, int try_neg)
6529 {
6530 	int curlen;
6531 	int64_t sv = (int64_t)usv;
6532 	int octal = dis->d86_flags & DIS_F_OCTAL;
6533 
6534 	curlen = strlen(buf);
6535 
6536 	if (try_neg == TRY_NEG && sv < 0 &&
6537 	    (disp || sv >= NEG_LIMIT) &&
6538 	    !isunsigned_op(dis->d86_mnem)) {
6539 		dis->d86_sprintf_func(buf + curlen, buflen - curlen,
6540 		    octal ? "-0%llo" : "-0x%llx", (-sv) & mask);
6541 		return (1);
6542 	} else {
6543 		if (disp == DISP)
6544 			dis->d86_sprintf_func(buf + curlen, buflen - curlen,
6545 			    octal ? "+0%llo" : "+0x%llx", usv & mask);
6546 		else
6547 			dis->d86_sprintf_func(buf + curlen, buflen - curlen,
6548 			    octal ? "0%llo" : "0x%llx", usv & mask);
6549 		return (0);
6550 
6551 	}
6552 }
6553 
6554 
6555 static int
6556 log2(int size)
6557 {
6558 	switch (size) {
6559 	case 1: return (0);
6560 	case 2: return (1);
6561 	case 4: return (2);
6562 	case 8: return (3);
6563 	}
6564 	return (0);
6565 }
6566 
6567 /* ARGSUSED */
6568 void
6569 dtrace_disx86_str(dis86_t *dis, uint_t mode, uint64_t pc, char *buf,
6570     size_t buflen)
6571 {
6572 	uint64_t reltgt = 0;
6573 	uint64_t tgt = 0;
6574 	int curlen;
6575 	int (*lookup)(void *, uint64_t, char *, size_t);
6576 	int i;
6577 	int64_t sv;
6578 	uint64_t usv, mask, save_mask, save_usv;
6579 	static uint64_t masks[] =
6580 	    {0xffU, 0xffffU, 0xffffffffU, 0xffffffffffffffffULL};
6581 	save_usv = 0;
6582 
6583 	dis->d86_sprintf_func(buf, buflen, "%-6s ", dis->d86_mnem);
6584 
6585 	/*
6586 	 * For PC-relative jumps, the pc is really the next pc after executing
6587 	 * this instruction, so increment it appropriately.
6588 	 */
6589 	pc += dis->d86_len;
6590 
6591 	for (i = 0; i < dis->d86_numopnds; i++) {
6592 		d86opnd_t *op = &dis->d86_opnd[i];
6593 
6594 		if (i != 0)
6595 			(void) strlcat(buf, ",", buflen);
6596 
6597 		(void) strlcat(buf, op->d86_prefix, buflen);
6598 
6599 		/*
6600 		 * sv is for the signed, possibly-truncated immediate or
6601 		 * displacement; usv retains the original size and
6602 		 * unsignedness for symbol lookup.
6603 		 */
6604 
6605 		sv = usv = op->d86_value;
6606 
6607 		/*
6608 		 * About masks: for immediates that represent
6609 		 * addresses, the appropriate display size is
6610 		 * the effective address size of the instruction.
6611 		 * This includes MODE_OFFSET, MODE_IPREL, and
6612 		 * MODE_RIPREL.  Immediates that are simply
6613 		 * immediate values should display in the operand's
6614 		 * size, however, since they don't represent addresses.
6615 		 */
6616 
6617 		/* d86_addr_size is SIZEnn, which is log2(real size) */
6618 		mask = masks[dis->d86_addr_size];
6619 
6620 		/* d86_value_size and d86_imm_bytes are in bytes */
6621 		if (op->d86_mode == MODE_SIGNED ||
6622 		    op->d86_mode == MODE_IMPLIED)
6623 			mask = masks[log2(op->d86_value_size)];
6624 
6625 		switch (op->d86_mode) {
6626 
6627 		case MODE_NONE:
6628 
6629 			(void) strlcat(buf, op->d86_opnd, buflen);
6630 			break;
6631 
6632 		case MODE_SIGNED:
6633 		case MODE_IMPLIED:
6634 		case MODE_OFFSET:
6635 
6636 			tgt = usv;
6637 
6638 			if (dis->d86_seg_prefix)
6639 				(void) strlcat(buf, dis->d86_seg_prefix,
6640 				    buflen);
6641 
6642 			if (op->d86_mode == MODE_SIGNED ||
6643 			    op->d86_mode == MODE_IMPLIED) {
6644 				(void) strlcat(buf, "$", buflen);
6645 			}
6646 
6647 			if (print_imm(dis, usv, mask, buf, buflen,
6648 			    IMM, TRY_NEG) &&
6649 			    (op->d86_mode == MODE_SIGNED ||
6650 			    op->d86_mode == MODE_IMPLIED)) {
6651 
6652 				/*
6653 				 * We printed a negative value for an
6654 				 * immediate that wasn't a
6655 				 * displacement.  Note that fact so we can
6656 				 * print the positive value as an
6657 				 * annotation.
6658 				 */
6659 
6660 				save_usv = usv;
6661 				save_mask = mask;
6662 			}
6663 			(void) strlcat(buf, op->d86_opnd, buflen);
6664 			break;
6665 
6666 		case MODE_IPREL:
6667 		case MODE_RIPREL:
6668 
6669 			reltgt = pc + sv;
6670 
6671 			switch (mode) {
6672 			case SIZE16:
6673 				reltgt = (uint16_t)reltgt;
6674 				break;
6675 			case SIZE32:
6676 				reltgt = (uint32_t)reltgt;
6677 				break;
6678 			}
6679 
6680 			(void) print_imm(dis, usv, mask, buf, buflen,
6681 			    DISP, TRY_NEG);
6682 
6683 			if (op->d86_mode == MODE_RIPREL)
6684 				(void) strlcat(buf, "(%rip)", buflen);
6685 			break;
6686 		}
6687 	}
6688 
6689 	/*
6690 	 * The symbol lookups may result in false positives,
6691 	 * particularly on object files, where small numbers may match
6692 	 * the 0-relative non-relocated addresses of symbols.
6693 	 */
6694 
6695 	lookup = dis->d86_sym_lookup;
6696 	if (tgt != 0) {
6697 		if ((dis->d86_flags & DIS_F_NOIMMSYM) == 0 &&
6698 		    lookup(dis->d86_data, tgt, NULL, 0) == 0) {
6699 			(void) strlcat(buf, "\t<", buflen);
6700 			curlen = strlen(buf);
6701 			lookup(dis->d86_data, tgt, buf + curlen,
6702 			    buflen - curlen);
6703 			(void) strlcat(buf, ">", buflen);
6704 		}
6705 
6706 		/*
6707 		 * If we printed a negative immediate above, print the
6708 		 * positive in case our heuristic was unhelpful
6709 		 */
6710 		if (save_usv) {
6711 			(void) strlcat(buf, "\t<", buflen);
6712 			(void) print_imm(dis, save_usv, save_mask, buf, buflen,
6713 			    IMM, POS);
6714 			(void) strlcat(buf, ">", buflen);
6715 		}
6716 	}
6717 
6718 	if (reltgt != 0) {
6719 		/* Print symbol or effective address for reltgt */
6720 
6721 		(void) strlcat(buf, "\t<", buflen);
6722 		curlen = strlen(buf);
6723 		lookup(dis->d86_data, reltgt, buf + curlen,
6724 		    buflen - curlen);
6725 		(void) strlcat(buf, ">", buflen);
6726 	}
6727 }
6728 
6729 #endif /* DIS_TEXT */
6730