1 /* 2 * 3 * CDDL HEADER START 4 * 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright 2017 Joyent, Inc. 25 */ 26 27 /* 28 * Copyright (c) 2010, Intel Corporation. 29 * All rights reserved. 30 */ 31 32 /* Copyright (c) 1988 AT&T */ 33 /* All Rights Reserved */ 34 35 #include "dis_tables.h" 36 37 /* BEGIN CSTYLED */ 38 39 /* 40 * Disassembly begins in dis_distable, which is equivalent to the One-byte 41 * Opcode Map in the Intel IA32 ISA Reference (page A-6 in my copy). The 42 * decoding loops then traverse out through the other tables as necessary to 43 * decode a given instruction. 44 * 45 * The behavior of this file can be controlled by one of the following flags: 46 * 47 * DIS_TEXT Include text for disassembly 48 * DIS_MEM Include memory-size calculations 49 * 50 * Either or both of these can be defined. 51 * 52 * This file is not, and will never be, cstyled. If anything, the tables should 53 * be taken out another tab stop or two so nothing overlaps. 54 */ 55 56 /* 57 * These functions must be provided for the consumer to do disassembly. 58 */ 59 #ifdef DIS_TEXT 60 extern char *strncpy(char *, const char *, size_t); 61 extern size_t strlen(const char *); 62 extern int strcmp(const char *, const char *); 63 extern int strncmp(const char *, const char *, size_t); 64 extern size_t strlcat(char *, const char *, size_t); 65 #endif 66 67 68 #define TERM 0 /* used to indicate that the 'indirect' */ 69 /* field terminates - no pointer. */ 70 71 /* Used to decode instructions. */ 72 typedef struct instable { 73 struct instable *it_indirect; /* for decode op codes */ 74 uchar_t it_adrmode; 75 #ifdef DIS_TEXT 76 char it_name[NCPS]; 77 uint_t it_suffix:1; /* mnem + "w", "l", or "d" */ 78 #endif 79 #ifdef DIS_MEM 80 uint_t it_size:16; 81 #endif 82 uint_t it_invalid64:1; /* opcode invalid in amd64 */ 83 uint_t it_always64:1; /* 64 bit when in 64 bit mode */ 84 uint_t it_invalid32:1; /* invalid in IA32 */ 85 uint_t it_stackop:1; /* push/pop stack operation */ 86 uint_t it_vexwoxmm:1; /* VEX instructions that don't use XMM/YMM */ 87 uint_t it_avxsuf:1; /* AVX suffix required */ 88 uint_t it_vexopmask:1; /* VEX inst. that use opmask */ 89 } instable_t; 90 91 /* 92 * Instruction formats. 93 */ 94 enum { 95 UNKNOWN, 96 MRw, 97 IMlw, 98 IMw, 99 IR, 100 OA, 101 AO, 102 MS, 103 SM, 104 Mv, 105 Mw, 106 M, /* register or memory */ 107 MG9, /* register or memory in group 9 (prefix optional) */ 108 Mb, /* register or memory, always byte sized */ 109 MO, /* memory only (no registers) */ 110 PREF, 111 SWAPGS_RDTSCP, 112 MONITOR_MWAIT, 113 R, 114 RA, 115 SEG, 116 MR, 117 RM, 118 RM_66r, /* RM, but with a required 0x66 prefix */ 119 IA, 120 MA, 121 SD, 122 AD, 123 SA, 124 D, 125 INM, 126 SO, 127 BD, 128 I, 129 P, 130 V, 131 DSHIFT, /* for double shift that has an 8-bit immediate */ 132 U, 133 OVERRIDE, 134 NORM, /* instructions w/o ModR/M byte, no memory access */ 135 IMPLMEM, /* instructions w/o ModR/M byte, implicit mem access */ 136 O, /* for call */ 137 JTAB, /* jump table */ 138 IMUL, /* for 186 iimul instr */ 139 CBW, /* so data16 can be evaluated for cbw and variants */ 140 MvI, /* for 186 logicals */ 141 ENTER, /* for 186 enter instr */ 142 RMw, /* for 286 arpl instr */ 143 Ib, /* for push immediate byte */ 144 F, /* for 287 instructions */ 145 FF, /* for 287 instructions */ 146 FFC, /* for 287 instructions */ 147 DM, /* 16-bit data */ 148 AM, /* 16-bit addr */ 149 LSEG, /* for 3-bit seg reg encoding */ 150 MIb, /* for 386 logicals */ 151 SREG, /* for 386 special registers */ 152 PREFIX, /* a REP instruction prefix */ 153 LOCK, /* a LOCK instruction prefix */ 154 INT3, /* The int 3 instruction, which has a fake operand */ 155 INTx, /* The normal int instruction, with explicit int num */ 156 DSHIFTcl, /* for double shift that implicitly uses %cl */ 157 CWD, /* so data16 can be evaluated for cwd and variants */ 158 RET, /* single immediate 16-bit operand */ 159 MOVZ, /* for movs and movz, with different size operands */ 160 CRC32, /* for crc32, with different size operands */ 161 XADDB, /* for xaddb */ 162 MOVSXZ, /* AMD64 mov sign extend 32 to 64 bit instruction */ 163 MOVBE, /* movbe instruction */ 164 165 /* 166 * MMX/SIMD addressing modes. 167 */ 168 169 MMO, /* Prefixable MMX/SIMD-Int mm/mem -> mm */ 170 MMOIMPL, /* Prefixable MMX/SIMD-Int mm -> mm (mem) */ 171 MMO3P, /* Prefixable MMX/SIMD-Int mm -> r32,imm8 */ 172 MMOM3, /* Prefixable MMX/SIMD-Int mm -> r32 */ 173 MMOS, /* Prefixable MMX/SIMD-Int mm -> mm/mem */ 174 MMOMS, /* Prefixable MMX/SIMD-Int mm -> mem */ 175 MMOPM, /* MMX/SIMD-Int mm/mem -> mm,imm8 */ 176 MMOPM_66o, /* MMX/SIMD-Int 0x66 optional mm/mem -> mm,imm8 */ 177 MMOPRM, /* Prefixable MMX/SIMD-Int r32/mem -> mm,imm8 */ 178 MMOSH, /* Prefixable MMX mm,imm8 */ 179 MM, /* MMX/SIMD-Int mm/mem -> mm */ 180 MMS, /* MMX/SIMD-Int mm -> mm/mem */ 181 MMSH, /* MMX mm,imm8 */ 182 XMMO, /* Prefixable SIMD xmm/mem -> xmm */ 183 XMMOS, /* Prefixable SIMD xmm -> xmm/mem */ 184 XMMOPM, /* Prefixable SIMD xmm/mem w/to xmm,imm8 */ 185 XMMOMX, /* Prefixable SIMD mm/mem -> xmm */ 186 XMMOX3, /* Prefixable SIMD xmm -> r32 */ 187 XMMOXMM, /* Prefixable SIMD xmm/mem -> mm */ 188 XMMOM, /* Prefixable SIMD xmm -> mem */ 189 XMMOMS, /* Prefixable SIMD mem -> xmm */ 190 XMM, /* SIMD xmm/mem -> xmm */ 191 XMM_66r, /* SIMD 0x66 prefix required xmm/mem -> xmm */ 192 XMM_66o, /* SIMD 0x66 prefix optional xmm/mem -> xmm */ 193 XMMXIMPL, /* SIMD xmm -> xmm (mem) */ 194 XMM3P, /* SIMD xmm -> r32,imm8 */ 195 XMM3PM_66r, /* SIMD 0x66 prefix required xmm -> r32/mem,imm8 */ 196 XMMP, /* SIMD xmm/mem w/to xmm,imm8 */ 197 XMMP_66o, /* SIMD 0x66 prefix optional xmm/mem w/to xmm,imm8 */ 198 XMMP_66r, /* SIMD 0x66 prefix required xmm/mem w/to xmm,imm8 */ 199 XMMPRM, /* SIMD r32/mem -> xmm,imm8 */ 200 XMMPRM_66r, /* SIMD 0x66 prefix required r32/mem -> xmm,imm8 */ 201 XMMS, /* SIMD xmm -> xmm/mem */ 202 XMMM, /* SIMD mem -> xmm */ 203 XMMM_66r, /* SIMD 0x66 prefix required mem -> xmm */ 204 XMMMS, /* SIMD xmm -> mem */ 205 XMM3MX, /* SIMD r32/mem -> xmm */ 206 XMM3MXS, /* SIMD xmm -> r32/mem */ 207 XMMSH, /* SIMD xmm,imm8 */ 208 XMMXM3, /* SIMD xmm/mem -> r32 */ 209 XMMX3, /* SIMD xmm -> r32 */ 210 XMMXMM, /* SIMD xmm/mem -> mm */ 211 XMMMX, /* SIMD mm -> xmm */ 212 XMMXM, /* SIMD xmm -> mm */ 213 XMMX2I, /* SIMD xmm -> xmm, imm, imm */ 214 XMM2I, /* SIMD xmm, imm, imm */ 215 XMMFENCE, /* SIMD lfence or mfence */ 216 XMMSFNC, /* SIMD sfence (none or mem) */ 217 XGETBV_XSETBV, 218 VEX_NONE, /* VEX no operand */ 219 VEX_MO, /* VEX mod_rm -> implicit reg */ 220 VEX_RMrX, /* VEX VEX.vvvv, mod_rm -> mod_reg */ 221 VEX_VRMrX, /* VEX mod_rm, VEX.vvvv -> mod_rm */ 222 VEX_RRX, /* VEX VEX.vvvv, mod_reg -> mod_rm */ 223 VEX_RMRX, /* VEX VEX.vvvv, mod_rm, imm8[7:4] -> mod_reg */ 224 VEX_MX, /* VEX mod_rm -> mod_reg */ 225 VEX_MXI, /* VEX mod_rm, imm8 -> mod_reg */ 226 VEX_XXI, /* VEX mod_rm, imm8 -> VEX.vvvv */ 227 VEX_MR, /* VEX mod_rm -> mod_reg */ 228 VEX_RRI, /* VEX mod_reg, mod_rm -> implicit(eflags/r32) */ 229 VEX_RX, /* VEX mod_reg -> mod_rm */ 230 VEX_KRR, /* VEX mod_rm -> mod_reg */ 231 VEX_KMR, /* VEX mod_reg -> mod_rm */ 232 VEX_KRM, /* VEX mod_rm -> mod_reg */ 233 VEX_RR, /* VEX mod_rm -> mod_reg */ 234 VEX_RRi, /* VEX mod_rm, imm8 -> mod_reg */ 235 VEX_RM, /* VEX mod_reg -> mod_rm */ 236 VEX_RIM, /* VEX mod_reg, imm8 -> mod_rm */ 237 VEX_RRM, /* VEX VEX.vvvv, mod_reg -> mod_rm */ 238 VEX_RMX, /* VEX VEX.vvvv, mod_rm -> mod_reg */ 239 VEX_SbVM, /* VEX SIB, VEX.vvvv -> mod_rm */ 240 VMx, /* vmcall/vmlaunch/vmresume/vmxoff */ 241 VMxo, /* VMx instruction with optional prefix */ 242 SVM, /* AMD SVM instructions */ 243 BLS, /* BLSR, BLSMSK, BLSI */ 244 FMA, /* FMA instructions, all VEX_RMrX */ 245 ADX /* ADX instructions, support REX.w, mod_rm->mod_reg */ 246 }; 247 248 /* 249 * VEX prefixes 250 */ 251 #define VEX_2bytes 0xC5 /* the first byte of two-byte form */ 252 #define VEX_3bytes 0xC4 /* the first byte of three-byte form */ 253 254 #define FILL 0x90 /* Fill byte used for alignment (nop) */ 255 256 /* 257 ** Register numbers for the i386 258 */ 259 #define EAX_REGNO 0 260 #define ECX_REGNO 1 261 #define EDX_REGNO 2 262 #define EBX_REGNO 3 263 #define ESP_REGNO 4 264 #define EBP_REGNO 5 265 #define ESI_REGNO 6 266 #define EDI_REGNO 7 267 268 /* 269 * modes for immediate values 270 */ 271 #define MODE_NONE 0 272 #define MODE_IPREL 1 /* signed IP relative value */ 273 #define MODE_SIGNED 2 /* sign extended immediate */ 274 #define MODE_IMPLIED 3 /* constant value implied from opcode */ 275 #define MODE_OFFSET 4 /* offset part of an address */ 276 #define MODE_RIPREL 5 /* like IPREL, but from %rip (amd64) */ 277 278 /* 279 * The letters used in these macros are: 280 * IND - indirect to another to another table 281 * "T" - means to Terminate indirections (this is the final opcode) 282 * "S" - means "operand length suffix required" 283 * "Sa" - means AVX2 suffix (d/q) required 284 * "NS" - means "no suffix" which is the operand length suffix of the opcode 285 * "Z" - means instruction size arg required 286 * "u" - means the opcode is invalid in IA32 but valid in amd64 287 * "x" - means the opcode is invalid in amd64, but not IA32 288 * "y" - means the operand size is always 64 bits in 64 bit mode 289 * "p" - means push/pop stack operation 290 * "vr" - means VEX instruction that operates on normal registers, not fpu 291 * "vo" - means VEX instruction that operates on opmask registers, not fpu 292 */ 293 294 #if defined(DIS_TEXT) && defined(DIS_MEM) 295 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0, 0} 296 #define INDx(table) {(instable_t *)table, 0, "", 0, 0, 1, 0, 0, 0} 297 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0} 298 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 0, 1, 0} 299 #define TNSx(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0, 0} 300 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 0} 301 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 1} 302 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0} 303 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, sz, 0, 1, 0, 0} 304 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0, 1} 305 #define TSavo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 1, 1} 306 #define TSvo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 0, 1} 307 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0} 308 #define TSx(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0, 0} 309 #define TSy(name, amode) {TERM, amode, name, 1, 0, 0, 1, 0, 0} 310 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 1} 311 #define TSZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0} 312 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0, 0, 1} 313 #define TSZx(name, amode, sz) {TERM, amode, name, 1, sz, 1, 0, 0, 0} 314 #define TSZy(name, amode, sz) {TERM, amode, name, 1, sz, 0, 1, 0, 0} 315 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0} 316 #elif defined(DIS_TEXT) 317 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0} 318 #define INDx(table) {(instable_t *)table, 0, "", 0, 1, 0, 0, 0} 319 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0} 320 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0} 321 #define TNSx(name, amode) {TERM, amode, name, 0, 1, 0, 0, 0} 322 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0} 323 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 1, 0, 1} 324 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0} 325 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, 0, 1, 0, 0} 326 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0, 1} 327 #define TSvo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 1} 328 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0} 329 #define TSx(name, amode) {TERM, amode, name, 1, 1, 0, 0, 0} 330 #define TSy(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0} 331 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 1} 332 #define TSZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0} 333 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 1} 334 #define TSZx(name, amode, sz) {TERM, amode, name, 1, 1, 0, 0, 0} 335 #define TSZy(name, amode, sz) {TERM, amode, name, 1, 0, 1, 0, 0} 336 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0} 337 #elif defined(DIS_MEM) 338 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0, 0} 339 #define INDx(table) {(instable_t *)table, 0, 0, 1, 0, 0, 0} 340 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0, 0} 341 #define TNSu(name, amode) {TERM, amode, 0, 0, 0, 1, 0} 342 #define TNSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0} 343 #define TNSyp(name, amode) {TERM, amode, 0, 0, 1, 0, 1} 344 #define TNSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0} 345 #define TNSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0} 346 #define TNSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0} 347 #define TNSZvr(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 1} 348 #define TSvo(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 0, 1} 349 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0, 0} 350 #define TSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0} 351 #define TSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0} 352 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 0, 1} 353 #define TSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0} 354 #define TSaZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 0, 1} 355 #define TSZx(name, amode, sz) {TERM, amode, sz, 1, 0, 0, 0} 356 #define TSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0} 357 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0, 0} 358 #else 359 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0} 360 #define INDx(table) {(instable_t *)table, 0, 1, 0, 0, 0} 361 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0} 362 #define TNSu(name, amode) {TERM, amode, 0, 0, 1, 0} 363 #define TNSy(name, amode) {TERM, amode, 0, 1, 0, 0} 364 #define TNSyp(name, amode) {TERM, amode, 0, 1, 0, 1} 365 #define TNSx(name, amode) {TERM, amode, 1, 0, 0, 0} 366 #define TNSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0} 367 #define TNSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0} 368 #define TNSZvr(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 1} 369 #define TSvo(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 1} 370 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0} 371 #define TSx(name, amode) {TERM, amode, 1, 0, 0, 0} 372 #define TSy(name, amode) {TERM, amode, 0, 1, 0, 0} 373 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 1} 374 #define TSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0} 375 #define TSaZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 0, 1} 376 #define TSZx(name, amode, sz) {TERM, amode, 1, 0, 0, 0} 377 #define TSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0} 378 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0} 379 #endif 380 381 #ifdef DIS_TEXT 382 /* 383 * this decodes the r_m field for mode's 0, 1, 2 in 16 bit mode 384 */ 385 const char *const dis_addr16[3][8] = { 386 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "", 387 "(%bx)", 388 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di", "(%bp)", 389 "(%bx)", 390 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "(%bp)", 391 "(%bx)", 392 }; 393 394 395 /* 396 * This decodes 32 bit addressing mode r_m field for modes 0, 1, 2 397 */ 398 const char *const dis_addr32_mode0[16] = { 399 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "", "(%esi)", "(%edi)", 400 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "", "(%r14d)", "(%r15d)" 401 }; 402 403 const char *const dis_addr32_mode12[16] = { 404 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "(%ebp)", "(%esi)", "(%edi)", 405 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "(%r13d)", "(%r14d)", "(%r15d)" 406 }; 407 408 /* 409 * This decodes 64 bit addressing mode r_m field for modes 0, 1, 2 410 */ 411 const char *const dis_addr64_mode0[16] = { 412 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rip)", "(%rsi)", "(%rdi)", 413 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%rip)", "(%r14)", "(%r15)" 414 }; 415 const char *const dis_addr64_mode12[16] = { 416 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rbp)", "(%rsi)", "(%rdi)", 417 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%r13)", "(%r14)", "(%r15)" 418 }; 419 420 /* 421 * decode for scale from SIB byte 422 */ 423 const char *const dis_scale_factor[4] = { ")", ",2)", ",4)", ",8)" }; 424 425 /* 426 * decode for scale from VSIB byte, note that we always include the scale factor 427 * to match gas. 428 */ 429 const char *const dis_vscale_factor[4] = { ",1)", ",2)", ",4)", ",8)" }; 430 431 /* 432 * register decoding for normal references to registers (ie. not addressing) 433 */ 434 const char *const dis_REG8[16] = { 435 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", 436 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 437 }; 438 439 const char *const dis_REG8_REX[16] = { 440 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", 441 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 442 }; 443 444 const char *const dis_REG16[16] = { 445 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", 446 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" 447 }; 448 449 const char *const dis_REG32[16] = { 450 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", 451 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" 452 }; 453 454 const char *const dis_REG64[16] = { 455 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", 456 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" 457 }; 458 459 const char *const dis_DEBUGREG[16] = { 460 "%db0", "%db1", "%db2", "%db3", "%db4", "%db5", "%db6", "%db7", 461 "%db8", "%db9", "%db10", "%db11", "%db12", "%db13", "%db14", "%db15" 462 }; 463 464 const char *const dis_CONTROLREG[16] = { 465 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5?", "%cr6?", "%cr7?", 466 "%cr8", "%cr9?", "%cr10?", "%cr11?", "%cr12?", "%cr13?", "%cr14?", "%cr15?" 467 }; 468 469 const char *const dis_TESTREG[16] = { 470 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7", 471 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7" 472 }; 473 474 const char *const dis_MMREG[16] = { 475 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7", 476 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7" 477 }; 478 479 const char *const dis_XMMREG[16] = { 480 "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7", 481 "%xmm8", "%xmm9", "%xmm10", "%xmm11", "%xmm12", "%xmm13", "%xmm14", "%xmm15" 482 }; 483 484 const char *const dis_YMMREG[16] = { 485 "%ymm0", "%ymm1", "%ymm2", "%ymm3", "%ymm4", "%ymm5", "%ymm6", "%ymm7", 486 "%ymm8", "%ymm9", "%ymm10", "%ymm11", "%ymm12", "%ymm13", "%ymm14", "%ymm15" 487 }; 488 489 const char *const dis_KOPMASKREG[8] = { 490 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" 491 }; 492 493 const char *const dis_SEGREG[16] = { 494 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>", 495 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>" 496 }; 497 498 /* 499 * SIMD predicate suffixes 500 */ 501 const char *const dis_PREDSUFFIX[8] = { 502 "eq", "lt", "le", "unord", "neq", "nlt", "nle", "ord" 503 }; 504 505 const char *const dis_AVXvgrp7[3][8] = { 506 /*0 1 2 3 4 5 6 7*/ 507 /*71*/ {"", "", "vpsrlw", "", "vpsraw", "", "vpsllw", ""}, 508 /*72*/ {"", "", "vpsrld", "", "vpsrad", "", "vpslld", ""}, 509 /*73*/ {"", "", "vpsrlq", "vpsrldq", "", "", "vpsllq", "vpslldq"} 510 }; 511 512 #endif /* DIS_TEXT */ 513 514 /* 515 * "decode table" for 64 bit mode MOVSXD instruction (opcode 0x63) 516 */ 517 const instable_t dis_opMOVSLD = TNS("movslq",MOVSXZ); 518 519 /* 520 * "decode table" for pause and clflush instructions 521 */ 522 const instable_t dis_opPause = TNS("pause", NORM); 523 524 /* 525 * Decode table for 0x0F00 opcodes 526 */ 527 const instable_t dis_op0F00[8] = { 528 529 /* [0] */ TNS("sldt",M), TNS("str",M), TNSy("lldt",M), TNSy("ltr",M), 530 /* [4] */ TNSZ("verr",M,2), TNSZ("verw",M,2), INVALID, INVALID, 531 }; 532 533 534 /* 535 * Decode table for 0x0F01 opcodes 536 */ 537 const instable_t dis_op0F01[8] = { 538 539 /* [0] */ TNSZ("sgdt",VMx,6), TNSZ("sidt",MONITOR_MWAIT,6), TNSZ("lgdt",XGETBV_XSETBV,6), TNSZ("lidt",SVM,6), 540 /* [4] */ TNSZ("smsw",M,2), INVALID, TNSZ("lmsw",M,2), TNS("invlpg",SWAPGS_RDTSCP), 541 }; 542 543 /* 544 * Decode table for 0x0F18 opcodes -- SIMD prefetch 545 */ 546 const instable_t dis_op0F18[8] = { 547 548 /* [0] */ TNS("prefetchnta",PREF),TNS("prefetcht0",PREF), TNS("prefetcht1",PREF), TNS("prefetcht2",PREF), 549 /* [4] */ INVALID, INVALID, INVALID, INVALID, 550 }; 551 552 /* 553 * Decode table for 0x0FAE opcodes -- SIMD state save/restore 554 */ 555 const instable_t dis_op0FAE[8] = { 556 /* [0] */ TNSZ("fxsave",M,512), TNSZ("fxrstor",M,512), TNS("ldmxcsr",M), TNS("stmxcsr",M), 557 /* [4] */ TNSZ("xsave",M,512), TNS("lfence",XMMFENCE), TNS("mfence",XMMFENCE), TNS("sfence",XMMSFNC), 558 }; 559 560 /* 561 * Decode table for 0x0FBA opcodes 562 */ 563 564 const instable_t dis_op0FBA[8] = { 565 566 /* [0] */ INVALID, INVALID, INVALID, INVALID, 567 /* [4] */ TS("bt",MIb), TS("bts",MIb), TS("btr",MIb), TS("btc",MIb), 568 }; 569 570 /* 571 * Decode table for 0x0FC7 opcode (group 9) 572 */ 573 574 const instable_t dis_op0FC7[8] = { 575 576 /* [0] */ INVALID, TNS("cmpxchg8b",M), INVALID, TNS("xrstors",MG9), 577 /* [4] */ TNS("xsavec",MG9), TNS("xsaves",MG9), TNS("vmptrld",MG9), TNS("vmptrst",MG9), 578 }; 579 580 /* 581 * Decode table for 0x0FC7 opcode (group 9) mode 3 582 */ 583 584 const instable_t dis_op0FC7m3[8] = { 585 586 /* [0] */ INVALID, INVALID, INVALID, INVALID, 587 /* [4] */ INVALID, INVALID, TNS("rdrand",MG9), TNS("rdseed", MG9), 588 }; 589 590 /* 591 * Decode table for 0x0FC7 opcode with 0x66 prefix 592 */ 593 594 const instable_t dis_op660FC7[8] = { 595 596 /* [0] */ INVALID, INVALID, INVALID, INVALID, 597 /* [4] */ INVALID, INVALID, TNS("vmclear",M), INVALID, 598 }; 599 600 /* 601 * Decode table for 0x0FC7 opcode with 0xF3 prefix 602 */ 603 604 const instable_t dis_opF30FC7[8] = { 605 606 /* [0] */ INVALID, INVALID, INVALID, INVALID, 607 /* [4] */ INVALID, INVALID, TNS("vmxon",M), INVALID, 608 }; 609 610 /* 611 * Decode table for 0x0FC8 opcode -- 486 bswap instruction 612 * 613 *bit pattern: 0000 1111 1100 1reg 614 */ 615 const instable_t dis_op0FC8[4] = { 616 /* [0] */ TNS("bswap",R), INVALID, INVALID, INVALID, 617 }; 618 619 /* 620 * Decode table for 0x0F71, 0x0F72, and 0x0F73 opcodes -- MMX instructions 621 */ 622 const instable_t dis_op0F7123[4][8] = { 623 { 624 /* [70].0 */ INVALID, INVALID, INVALID, INVALID, 625 /* .4 */ INVALID, INVALID, INVALID, INVALID, 626 }, { 627 /* [71].0 */ INVALID, INVALID, TNS("psrlw",MMOSH), INVALID, 628 /* .4 */ TNS("psraw",MMOSH), INVALID, TNS("psllw",MMOSH), INVALID, 629 }, { 630 /* [72].0 */ INVALID, INVALID, TNS("psrld",MMOSH), INVALID, 631 /* .4 */ TNS("psrad",MMOSH), INVALID, TNS("pslld",MMOSH), INVALID, 632 }, { 633 /* [73].0 */ INVALID, INVALID, TNS("psrlq",MMOSH), TNS("INVALID",MMOSH), 634 /* .4 */ INVALID, INVALID, TNS("psllq",MMOSH), TNS("INVALID",MMOSH), 635 } }; 636 637 /* 638 * Decode table for SIMD extensions to above 0x0F71-0x0F73 opcodes. 639 */ 640 const instable_t dis_opSIMD7123[32] = { 641 /* [70].0 */ INVALID, INVALID, INVALID, INVALID, 642 /* .4 */ INVALID, INVALID, INVALID, INVALID, 643 644 /* [71].0 */ INVALID, INVALID, TNS("psrlw",XMMSH), INVALID, 645 /* .4 */ TNS("psraw",XMMSH), INVALID, TNS("psllw",XMMSH), INVALID, 646 647 /* [72].0 */ INVALID, INVALID, TNS("psrld",XMMSH), INVALID, 648 /* .4 */ TNS("psrad",XMMSH), INVALID, TNS("pslld",XMMSH), INVALID, 649 650 /* [73].0 */ INVALID, INVALID, TNS("psrlq",XMMSH), TNS("psrldq",XMMSH), 651 /* .4 */ INVALID, INVALID, TNS("psllq",XMMSH), TNS("pslldq",XMMSH), 652 }; 653 654 /* 655 * SIMD instructions have been wedged into the existing IA32 instruction 656 * set through the use of prefixes. That is, while 0xf0 0x58 may be 657 * addps, 0xf3 0xf0 0x58 (literally, repz addps) is a completely different 658 * instruction - addss. At present, three prefixes have been coopted in 659 * this manner - address size (0x66), repnz (0xf2) and repz (0xf3). The 660 * following tables are used to provide the prefixed instruction names. 661 * The arrays are sparse, but they're fast. 662 */ 663 664 /* 665 * Decode table for SIMD instructions with the address size (0x66) prefix. 666 */ 667 const instable_t dis_opSIMDdata16[256] = { 668 /* [00] */ INVALID, INVALID, INVALID, INVALID, 669 /* [04] */ INVALID, INVALID, INVALID, INVALID, 670 /* [08] */ INVALID, INVALID, INVALID, INVALID, 671 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 672 673 /* [10] */ TNSZ("movupd",XMM,16), TNSZ("movupd",XMMS,16), TNSZ("movlpd",XMMM,8), TNSZ("movlpd",XMMMS,8), 674 /* [14] */ TNSZ("unpcklpd",XMM,16),TNSZ("unpckhpd",XMM,16),TNSZ("movhpd",XMMM,8), TNSZ("movhpd",XMMMS,8), 675 /* [18] */ INVALID, INVALID, INVALID, INVALID, 676 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 677 678 /* [20] */ INVALID, INVALID, INVALID, INVALID, 679 /* [24] */ INVALID, INVALID, INVALID, INVALID, 680 /* [28] */ TNSZ("movapd",XMM,16), TNSZ("movapd",XMMS,16), TNSZ("cvtpi2pd",XMMOMX,8),TNSZ("movntpd",XMMOMS,16), 681 /* [2C] */ TNSZ("cvttpd2pi",XMMXMM,16),TNSZ("cvtpd2pi",XMMXMM,16),TNSZ("ucomisd",XMM,8),TNSZ("comisd",XMM,8), 682 683 /* [30] */ INVALID, INVALID, INVALID, INVALID, 684 /* [34] */ INVALID, INVALID, INVALID, INVALID, 685 /* [38] */ INVALID, INVALID, INVALID, INVALID, 686 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 687 688 /* [40] */ INVALID, INVALID, INVALID, INVALID, 689 /* [44] */ INVALID, INVALID, INVALID, INVALID, 690 /* [48] */ INVALID, INVALID, INVALID, INVALID, 691 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 692 693 /* [50] */ TNS("movmskpd",XMMOX3), TNSZ("sqrtpd",XMM,16), INVALID, INVALID, 694 /* [54] */ TNSZ("andpd",XMM,16), TNSZ("andnpd",XMM,16), TNSZ("orpd",XMM,16), TNSZ("xorpd",XMM,16), 695 /* [58] */ TNSZ("addpd",XMM,16), TNSZ("mulpd",XMM,16), TNSZ("cvtpd2ps",XMM,16),TNSZ("cvtps2dq",XMM,16), 696 /* [5C] */ TNSZ("subpd",XMM,16), TNSZ("minpd",XMM,16), TNSZ("divpd",XMM,16), TNSZ("maxpd",XMM,16), 697 698 /* [60] */ TNSZ("punpcklbw",XMM,16),TNSZ("punpcklwd",XMM,16),TNSZ("punpckldq",XMM,16),TNSZ("packsswb",XMM,16), 699 /* [64] */ TNSZ("pcmpgtb",XMM,16), TNSZ("pcmpgtw",XMM,16), TNSZ("pcmpgtd",XMM,16), TNSZ("packuswb",XMM,16), 700 /* [68] */ TNSZ("punpckhbw",XMM,16),TNSZ("punpckhwd",XMM,16),TNSZ("punpckhdq",XMM,16),TNSZ("packssdw",XMM,16), 701 /* [6C] */ TNSZ("punpcklqdq",XMM,16),TNSZ("punpckhqdq",XMM,16),TNSZ("movd",XMM3MX,4),TNSZ("movdqa",XMM,16), 702 703 /* [70] */ TNSZ("pshufd",XMMP,16), INVALID, INVALID, INVALID, 704 /* [74] */ TNSZ("pcmpeqb",XMM,16), TNSZ("pcmpeqw",XMM,16), TNSZ("pcmpeqd",XMM,16), INVALID, 705 /* [78] */ TNSZ("extrq",XMM2I,16), TNSZ("extrq",XMM,16), INVALID, INVALID, 706 /* [7C] */ TNSZ("haddpd",XMM,16), TNSZ("hsubpd",XMM,16), TNSZ("movd",XMM3MXS,4), TNSZ("movdqa",XMMS,16), 707 708 /* [80] */ INVALID, INVALID, INVALID, INVALID, 709 /* [84] */ INVALID, INVALID, INVALID, INVALID, 710 /* [88] */ INVALID, INVALID, INVALID, INVALID, 711 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 712 713 /* [90] */ INVALID, INVALID, INVALID, INVALID, 714 /* [94] */ INVALID, INVALID, INVALID, INVALID, 715 /* [98] */ INVALID, INVALID, INVALID, INVALID, 716 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 717 718 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 719 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 720 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 721 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 722 723 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 724 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 725 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 726 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 727 728 /* [C0] */ INVALID, INVALID, TNSZ("cmppd",XMMP,16), INVALID, 729 /* [C4] */ TNSZ("pinsrw",XMMPRM,2),TNS("pextrw",XMM3P), TNSZ("shufpd",XMMP,16), INVALID, 730 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 731 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 732 733 /* [D0] */ TNSZ("addsubpd",XMM,16),TNSZ("psrlw",XMM,16), TNSZ("psrld",XMM,16), TNSZ("psrlq",XMM,16), 734 /* [D4] */ TNSZ("paddq",XMM,16), TNSZ("pmullw",XMM,16), TNSZ("movq",XMMS,8), TNS("pmovmskb",XMMX3), 735 /* [D8] */ TNSZ("psubusb",XMM,16), TNSZ("psubusw",XMM,16), TNSZ("pminub",XMM,16), TNSZ("pand",XMM,16), 736 /* [DC] */ TNSZ("paddusb",XMM,16), TNSZ("paddusw",XMM,16), TNSZ("pmaxub",XMM,16), TNSZ("pandn",XMM,16), 737 738 /* [E0] */ TNSZ("pavgb",XMM,16), TNSZ("psraw",XMM,16), TNSZ("psrad",XMM,16), TNSZ("pavgw",XMM,16), 739 /* [E4] */ TNSZ("pmulhuw",XMM,16), TNSZ("pmulhw",XMM,16), TNSZ("cvttpd2dq",XMM,16),TNSZ("movntdq",XMMS,16), 740 /* [E8] */ TNSZ("psubsb",XMM,16), TNSZ("psubsw",XMM,16), TNSZ("pminsw",XMM,16), TNSZ("por",XMM,16), 741 /* [EC] */ TNSZ("paddsb",XMM,16), TNSZ("paddsw",XMM,16), TNSZ("pmaxsw",XMM,16), TNSZ("pxor",XMM,16), 742 743 /* [F0] */ INVALID, TNSZ("psllw",XMM,16), TNSZ("pslld",XMM,16), TNSZ("psllq",XMM,16), 744 /* [F4] */ TNSZ("pmuludq",XMM,16), TNSZ("pmaddwd",XMM,16), TNSZ("psadbw",XMM,16), TNSZ("maskmovdqu", XMMXIMPL,16), 745 /* [F8] */ TNSZ("psubb",XMM,16), TNSZ("psubw",XMM,16), TNSZ("psubd",XMM,16), TNSZ("psubq",XMM,16), 746 /* [FC] */ TNSZ("paddb",XMM,16), TNSZ("paddw",XMM,16), TNSZ("paddd",XMM,16), INVALID, 747 }; 748 749 const instable_t dis_opAVX660F[256] = { 750 /* [00] */ INVALID, INVALID, INVALID, INVALID, 751 /* [04] */ INVALID, INVALID, INVALID, INVALID, 752 /* [08] */ INVALID, INVALID, INVALID, INVALID, 753 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 754 755 /* [10] */ TNSZ("vmovupd",VEX_MX,16), TNSZ("vmovupd",VEX_RX,16), TNSZ("vmovlpd",VEX_RMrX,8), TNSZ("vmovlpd",VEX_RM,8), 756 /* [14] */ TNSZ("vunpcklpd",VEX_RMrX,16),TNSZ("vunpckhpd",VEX_RMrX,16),TNSZ("vmovhpd",VEX_RMrX,8), TNSZ("vmovhpd",VEX_RM,8), 757 /* [18] */ INVALID, INVALID, INVALID, INVALID, 758 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 759 760 /* [20] */ INVALID, INVALID, INVALID, INVALID, 761 /* [24] */ INVALID, INVALID, INVALID, INVALID, 762 /* [28] */ TNSZ("vmovapd",VEX_MX,16), TNSZ("vmovapd",VEX_RX,16), INVALID, TNSZ("vmovntpd",VEX_RM,16), 763 /* [2C] */ INVALID, INVALID, TNSZ("vucomisd",VEX_MX,8),TNSZ("vcomisd",VEX_MX,8), 764 765 /* [30] */ INVALID, INVALID, INVALID, INVALID, 766 /* [34] */ INVALID, INVALID, INVALID, INVALID, 767 /* [38] */ INVALID, INVALID, INVALID, INVALID, 768 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 769 770 /* [40] */ INVALID, TSvo("kand",VEX_RMX), TSvo("kandn",VEX_RMX), INVALID, 771 /* [44] */ TSvo("knot",VEX_MX), TSvo("kor",VEX_RMX), TSvo("kxnor",VEX_RMX), TSvo("kxor",VEX_RMX), 772 /* [48] */ INVALID, INVALID, TSvo("kadd",VEX_RMX), TSvo("kunpck",VEX_RMX), 773 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 774 775 /* [50] */ TNS("vmovmskpd",VEX_MR), TNSZ("vsqrtpd",VEX_MX,16), INVALID, INVALID, 776 /* [54] */ TNSZ("vandpd",VEX_RMrX,16), TNSZ("vandnpd",VEX_RMrX,16), TNSZ("vorpd",VEX_RMrX,16), TNSZ("vxorpd",VEX_RMrX,16), 777 /* [58] */ TNSZ("vaddpd",VEX_RMrX,16), TNSZ("vmulpd",VEX_RMrX,16), TNSZ("vcvtpd2ps",VEX_MX,16),TNSZ("vcvtps2dq",VEX_MX,16), 778 /* [5C] */ TNSZ("vsubpd",VEX_RMrX,16), TNSZ("vminpd",VEX_RMrX,16), TNSZ("vdivpd",VEX_RMrX,16), TNSZ("vmaxpd",VEX_RMrX,16), 779 780 /* [60] */ TNSZ("vpunpcklbw",VEX_RMrX,16),TNSZ("vpunpcklwd",VEX_RMrX,16),TNSZ("vpunpckldq",VEX_RMrX,16),TNSZ("vpacksswb",VEX_RMrX,16), 781 /* [64] */ TNSZ("vpcmpgtb",VEX_RMrX,16), TNSZ("vpcmpgtw",VEX_RMrX,16), TNSZ("vpcmpgtd",VEX_RMrX,16), TNSZ("vpackuswb",VEX_RMrX,16), 782 /* [68] */ TNSZ("vpunpckhbw",VEX_RMrX,16),TNSZ("vpunpckhwd",VEX_RMrX,16),TNSZ("vpunpckhdq",VEX_RMrX,16),TNSZ("vpackssdw",VEX_RMrX,16), 783 /* [6C] */ TNSZ("vpunpcklqdq",VEX_RMrX,16),TNSZ("vpunpckhqdq",VEX_RMrX,16),TNSZ("vmovd",VEX_MX,4),TNSZ("vmovdqa",VEX_MX,16), 784 785 /* [70] */ TNSZ("vpshufd",VEX_MXI,16), TNSZ("vgrp71",VEX_XXI,16), TNSZ("vgrp72",VEX_XXI,16), TNSZ("vgrp73",VEX_XXI,16), 786 /* [74] */ TNSZ("vpcmpeqb",VEX_RMrX,16), TNSZ("vpcmpeqw",VEX_RMrX,16), TNSZ("vpcmpeqd",VEX_RMrX,16), INVALID, 787 /* [78] */ INVALID, INVALID, INVALID, INVALID, 788 /* [7C] */ TNSZ("vhaddpd",VEX_RMrX,16), TNSZ("vhsubpd",VEX_RMrX,16), TNSZ("vmovd",VEX_RR,4), TNSZ("vmovdqa",VEX_RX,16), 789 790 /* [80] */ INVALID, INVALID, INVALID, INVALID, 791 /* [84] */ INVALID, INVALID, INVALID, INVALID, 792 /* [88] */ INVALID, INVALID, INVALID, INVALID, 793 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 794 795 /* [90] */ TSvo("kmov",VEX_KRM), TSvo("kmov",VEX_KMR), TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR), 796 /* [94] */ INVALID, INVALID, INVALID, INVALID, 797 /* [98] */ TSvo("kortest",VEX_MX), TSvo("ktest",VEX_MX), INVALID, INVALID, 798 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 799 800 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 801 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 802 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 803 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 804 805 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 806 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 807 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 808 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 809 810 /* [C0] */ INVALID, INVALID, TNSZ("vcmppd",VEX_RMRX,16), INVALID, 811 /* [C4] */ TNSZ("vpinsrw",VEX_RMRX,2),TNS("vpextrw",VEX_MR), TNSZ("vshufpd",VEX_RMRX,16), INVALID, 812 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 813 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 814 815 /* [D0] */ TNSZ("vaddsubpd",VEX_RMrX,16),TNSZ("vpsrlw",VEX_RMrX,16), TNSZ("vpsrld",VEX_RMrX,16), TNSZ("vpsrlq",VEX_RMrX,16), 816 /* [D4] */ TNSZ("vpaddq",VEX_RMrX,16), TNSZ("vpmullw",VEX_RMrX,16), TNSZ("vmovq",VEX_RX,8), TNS("vpmovmskb",VEX_MR), 817 /* [D8] */ TNSZ("vpsubusb",VEX_RMrX,16), TNSZ("vpsubusw",VEX_RMrX,16), TNSZ("vpminub",VEX_RMrX,16), TNSZ("vpand",VEX_RMrX,16), 818 /* [DC] */ TNSZ("vpaddusb",VEX_RMrX,16), TNSZ("vpaddusw",VEX_RMrX,16), TNSZ("vpmaxub",VEX_RMrX,16), TNSZ("vpandn",VEX_RMrX,16), 819 820 /* [E0] */ TNSZ("vpavgb",VEX_RMrX,16), TNSZ("vpsraw",VEX_RMrX,16), TNSZ("vpsrad",VEX_RMrX,16), TNSZ("vpavgw",VEX_RMrX,16), 821 /* [E4] */ TNSZ("vpmulhuw",VEX_RMrX,16), TNSZ("vpmulhw",VEX_RMrX,16), TNSZ("vcvttpd2dq",VEX_MX,16),TNSZ("vmovntdq",VEX_RM,16), 822 /* [E8] */ TNSZ("vpsubsb",VEX_RMrX,16), TNSZ("vpsubsw",VEX_RMrX,16), TNSZ("vpminsw",VEX_RMrX,16), TNSZ("vpor",VEX_RMrX,16), 823 /* [EC] */ TNSZ("vpaddsb",VEX_RMrX,16), TNSZ("vpaddsw",VEX_RMrX,16), TNSZ("vpmaxsw",VEX_RMrX,16), TNSZ("vpxor",VEX_RMrX,16), 824 825 /* [F0] */ INVALID, TNSZ("vpsllw",VEX_RMrX,16), TNSZ("vpslld",VEX_RMrX,16), TNSZ("vpsllq",VEX_RMrX,16), 826 /* [F4] */ TNSZ("vpmuludq",VEX_RMrX,16), TNSZ("vpmaddwd",VEX_RMrX,16), TNSZ("vpsadbw",VEX_RMrX,16), TNS("vmaskmovdqu",VEX_MX), 827 /* [F8] */ TNSZ("vpsubb",VEX_RMrX,16), TNSZ("vpsubw",VEX_RMrX,16), TNSZ("vpsubd",VEX_RMrX,16), TNSZ("vpsubq",VEX_RMrX,16), 828 /* [FC] */ TNSZ("vpaddb",VEX_RMrX,16), TNSZ("vpaddw",VEX_RMrX,16), TNSZ("vpaddd",VEX_RMrX,16), INVALID, 829 }; 830 831 /* 832 * Decode table for SIMD instructions with the repnz (0xf2) prefix. 833 */ 834 const instable_t dis_opSIMDrepnz[256] = { 835 /* [00] */ INVALID, INVALID, INVALID, INVALID, 836 /* [04] */ INVALID, INVALID, INVALID, INVALID, 837 /* [08] */ INVALID, INVALID, INVALID, INVALID, 838 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 839 840 /* [10] */ TNSZ("movsd",XMM,8), TNSZ("movsd",XMMS,8), TNSZ("movddup",XMM,8), INVALID, 841 /* [14] */ INVALID, INVALID, INVALID, INVALID, 842 /* [18] */ INVALID, INVALID, INVALID, INVALID, 843 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 844 845 /* [20] */ INVALID, INVALID, INVALID, INVALID, 846 /* [24] */ INVALID, INVALID, INVALID, INVALID, 847 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2sd",XMM3MX,4),TNSZ("movntsd",XMMMS,8), 848 /* [2C] */ TNSZ("cvttsd2si",XMMXM3,8),TNSZ("cvtsd2si",XMMXM3,8),INVALID, INVALID, 849 850 /* [30] */ INVALID, INVALID, INVALID, INVALID, 851 /* [34] */ INVALID, INVALID, INVALID, INVALID, 852 /* [38] */ INVALID, INVALID, INVALID, INVALID, 853 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 854 855 /* [40] */ INVALID, INVALID, INVALID, INVALID, 856 /* [44] */ INVALID, INVALID, INVALID, INVALID, 857 /* [48] */ INVALID, INVALID, INVALID, INVALID, 858 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 859 860 /* [50] */ INVALID, TNSZ("sqrtsd",XMM,8), INVALID, INVALID, 861 /* [54] */ INVALID, INVALID, INVALID, INVALID, 862 /* [58] */ TNSZ("addsd",XMM,8), TNSZ("mulsd",XMM,8), TNSZ("cvtsd2ss",XMM,8), INVALID, 863 /* [5C] */ TNSZ("subsd",XMM,8), TNSZ("minsd",XMM,8), TNSZ("divsd",XMM,8), TNSZ("maxsd",XMM,8), 864 865 /* [60] */ INVALID, INVALID, INVALID, INVALID, 866 /* [64] */ INVALID, INVALID, INVALID, INVALID, 867 /* [68] */ INVALID, INVALID, INVALID, INVALID, 868 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 869 870 /* [70] */ TNSZ("pshuflw",XMMP,16),INVALID, INVALID, INVALID, 871 /* [74] */ INVALID, INVALID, INVALID, INVALID, 872 /* [78] */ TNSZ("insertq",XMMX2I,16),TNSZ("insertq",XMM,8),INVALID, INVALID, 873 /* [7C] */ TNSZ("haddps",XMM,16), TNSZ("hsubps",XMM,16), INVALID, INVALID, 874 875 /* [80] */ INVALID, INVALID, INVALID, INVALID, 876 /* [84] */ INVALID, INVALID, INVALID, INVALID, 877 /* [88] */ INVALID, INVALID, INVALID, INVALID, 878 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 879 880 /* [90] */ INVALID, INVALID, INVALID, INVALID, 881 /* [94] */ INVALID, INVALID, INVALID, INVALID, 882 /* [98] */ INVALID, INVALID, INVALID, INVALID, 883 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 884 885 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 886 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 887 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 888 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 889 890 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 891 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 892 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 893 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 894 895 /* [C0] */ INVALID, INVALID, TNSZ("cmpsd",XMMP,8), INVALID, 896 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 897 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 898 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 899 900 /* [D0] */ TNSZ("addsubps",XMM,16),INVALID, INVALID, INVALID, 901 /* [D4] */ INVALID, INVALID, TNS("movdq2q",XMMXM), INVALID, 902 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 903 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 904 905 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 906 /* [E4] */ INVALID, INVALID, TNSZ("cvtpd2dq",XMM,16),INVALID, 907 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 908 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 909 910 /* [F0] */ TNS("lddqu",XMMM), INVALID, INVALID, INVALID, 911 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 912 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 913 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 914 }; 915 916 const instable_t dis_opAVXF20F[256] = { 917 /* [00] */ INVALID, INVALID, INVALID, INVALID, 918 /* [04] */ INVALID, INVALID, INVALID, INVALID, 919 /* [08] */ INVALID, INVALID, INVALID, INVALID, 920 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 921 922 /* [10] */ TNSZ("vmovsd",VEX_RMrX,8), TNSZ("vmovsd",VEX_RRX,8), TNSZ("vmovddup",VEX_MX,8), INVALID, 923 /* [14] */ INVALID, INVALID, INVALID, INVALID, 924 /* [18] */ INVALID, INVALID, INVALID, INVALID, 925 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 926 927 /* [20] */ INVALID, INVALID, INVALID, INVALID, 928 /* [24] */ INVALID, INVALID, INVALID, INVALID, 929 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2sd",VEX_RMrX,4),INVALID, 930 /* [2C] */ TNSZ("vcvttsd2si",VEX_MR,8),TNSZ("vcvtsd2si",VEX_MR,8),INVALID, INVALID, 931 932 /* [30] */ INVALID, INVALID, INVALID, INVALID, 933 /* [34] */ INVALID, INVALID, INVALID, INVALID, 934 /* [38] */ INVALID, INVALID, INVALID, INVALID, 935 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 936 937 /* [40] */ INVALID, INVALID, INVALID, INVALID, 938 /* [44] */ INVALID, INVALID, INVALID, INVALID, 939 /* [48] */ INVALID, INVALID, INVALID, INVALID, 940 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 941 942 /* [50] */ INVALID, TNSZ("vsqrtsd",VEX_RMrX,8), INVALID, INVALID, 943 /* [54] */ INVALID, INVALID, INVALID, INVALID, 944 /* [58] */ TNSZ("vaddsd",VEX_RMrX,8), TNSZ("vmulsd",VEX_RMrX,8), TNSZ("vcvtsd2ss",VEX_RMrX,8), INVALID, 945 /* [5C] */ TNSZ("vsubsd",VEX_RMrX,8), TNSZ("vminsd",VEX_RMrX,8), TNSZ("vdivsd",VEX_RMrX,8), TNSZ("vmaxsd",VEX_RMrX,8), 946 947 /* [60] */ INVALID, INVALID, INVALID, INVALID, 948 /* [64] */ INVALID, INVALID, INVALID, INVALID, 949 /* [68] */ INVALID, INVALID, INVALID, INVALID, 950 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 951 952 /* [70] */ TNSZ("vpshuflw",VEX_MXI,16),INVALID, INVALID, INVALID, 953 /* [74] */ INVALID, INVALID, INVALID, INVALID, 954 /* [78] */ INVALID, INVALID, INVALID, INVALID, 955 /* [7C] */ TNSZ("vhaddps",VEX_RMrX,8), TNSZ("vhsubps",VEX_RMrX,8), INVALID, INVALID, 956 957 /* [80] */ INVALID, INVALID, INVALID, INVALID, 958 /* [84] */ INVALID, INVALID, INVALID, INVALID, 959 /* [88] */ INVALID, INVALID, INVALID, INVALID, 960 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 961 962 /* [90] */ INVALID, INVALID, TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR), 963 /* [94] */ INVALID, INVALID, INVALID, INVALID, 964 /* [98] */ INVALID, INVALID, INVALID, INVALID, 965 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 966 967 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 968 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 969 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 970 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 971 972 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 973 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 974 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 975 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 976 977 /* [C0] */ INVALID, INVALID, TNSZ("vcmpsd",VEX_RMRX,8), INVALID, 978 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 979 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 980 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 981 982 /* [D0] */ TNSZ("vaddsubps",VEX_RMrX,8), INVALID, INVALID, INVALID, 983 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 984 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 985 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 986 987 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 988 /* [E4] */ INVALID, INVALID, TNSZ("vcvtpd2dq",VEX_MX,16),INVALID, 989 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 990 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 991 992 /* [F0] */ TNSZ("vlddqu",VEX_MX,16), INVALID, INVALID, INVALID, 993 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 994 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 995 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 996 }; 997 998 const instable_t dis_opAVXF20F3A[256] = { 999 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1000 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1001 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1002 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1003 1004 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1005 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1006 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1007 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1008 1009 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1010 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1011 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1012 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1013 1014 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1015 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1016 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1017 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1018 1019 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1020 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1021 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1022 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1023 1024 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1025 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1026 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1027 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1028 1029 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1030 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1031 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1032 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1033 1034 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1035 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1036 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1037 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1038 1039 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1040 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1041 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1042 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1043 1044 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1045 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1046 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1047 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1048 1049 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1050 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1051 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1052 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1053 1054 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1055 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1056 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1057 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1058 1059 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1060 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1061 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1062 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1063 1064 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1065 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1066 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1067 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1068 1069 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1070 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1071 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1072 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1073 1074 /* [F0] */ TNSZvr("rorx",VEX_MXI,6),INVALID, INVALID, INVALID, 1075 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1076 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1077 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1078 }; 1079 1080 const instable_t dis_opAVXF20F38[256] = { 1081 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1082 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1083 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1084 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1085 1086 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1087 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1088 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1089 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1090 1091 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1092 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1093 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1094 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1095 1096 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1097 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1098 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1099 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1100 1101 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1102 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1103 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1104 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1105 1106 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1107 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1108 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1109 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1110 1111 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1112 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1113 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1114 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1115 1116 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1117 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1118 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1119 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1120 1121 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1122 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1123 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1124 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1125 1126 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1127 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1128 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1129 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1130 1131 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1132 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1133 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1134 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1135 1136 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1137 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1138 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1139 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1140 1141 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1142 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1143 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1144 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1145 1146 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1147 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1148 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1149 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1150 1151 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1152 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1153 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1154 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1155 1156 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1157 /* [F4] */ INVALID, TNSZvr("pdep",VEX_RMrX,5),TNSZvr("mulx",VEX_RMrX,5),TNSZvr("shrx",VEX_VRMrX,5), 1158 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1159 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1160 }; 1161 1162 const instable_t dis_opAVXF30F38[256] = { 1163 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1164 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1165 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1166 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1167 1168 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1169 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1170 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1171 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1172 1173 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1174 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1175 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1176 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1177 1178 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1179 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1180 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1181 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1182 1183 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1184 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1185 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1186 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1187 1188 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1189 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1190 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1191 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1192 1193 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1194 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1195 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1196 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1197 1198 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1199 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1200 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1201 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1202 1203 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1204 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1205 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1206 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1207 1208 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1209 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1210 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1211 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1212 1213 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1214 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1215 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1216 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1217 1218 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1219 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1220 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1221 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1222 1223 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1224 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1225 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1226 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1227 1228 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1229 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1230 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1231 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1232 1233 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1234 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1235 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1236 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1237 1238 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1239 /* [F4] */ INVALID, TNSZvr("pext",VEX_RMrX,5),INVALID, TNSZvr("sarx",VEX_VRMrX,5), 1240 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1241 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1242 }; 1243 /* 1244 * Decode table for SIMD instructions with the repz (0xf3) prefix. 1245 */ 1246 const instable_t dis_opSIMDrepz[256] = { 1247 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1248 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1249 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1250 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1251 1252 /* [10] */ TNSZ("movss",XMM,4), TNSZ("movss",XMMS,4), TNSZ("movsldup",XMM,16),INVALID, 1253 /* [14] */ INVALID, INVALID, TNSZ("movshdup",XMM,16),INVALID, 1254 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1255 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1256 1257 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1258 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1259 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2ss",XMM3MX,4),TNSZ("movntss",XMMMS,4), 1260 /* [2C] */ TNSZ("cvttss2si",XMMXM3,4),TNSZ("cvtss2si",XMMXM3,4),INVALID, INVALID, 1261 1262 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1263 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1264 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1265 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1266 1267 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1268 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1269 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1270 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1271 1272 /* [50] */ INVALID, TNSZ("sqrtss",XMM,4), TNSZ("rsqrtss",XMM,4), TNSZ("rcpss",XMM,4), 1273 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1274 /* [58] */ TNSZ("addss",XMM,4), TNSZ("mulss",XMM,4), TNSZ("cvtss2sd",XMM,4), TNSZ("cvttps2dq",XMM,16), 1275 /* [5C] */ TNSZ("subss",XMM,4), TNSZ("minss",XMM,4), TNSZ("divss",XMM,4), TNSZ("maxss",XMM,4), 1276 1277 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1278 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1279 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1280 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("movdqu",XMM,16), 1281 1282 /* [70] */ TNSZ("pshufhw",XMMP,16),INVALID, INVALID, INVALID, 1283 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1284 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1285 /* [7C] */ INVALID, INVALID, TNSZ("movq",XMM,8), TNSZ("movdqu",XMMS,16), 1286 1287 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1288 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1289 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1290 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1291 1292 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1293 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1294 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1295 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1296 1297 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1298 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1299 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1300 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1301 1302 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1303 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1304 /* [B8] */ TS("popcnt",MRw), INVALID, INVALID, INVALID, 1305 /* [BC] */ TNSZ("tzcnt",MRw,5), TS("lzcnt",MRw), INVALID, INVALID, 1306 1307 /* [C0] */ INVALID, INVALID, TNSZ("cmpss",XMMP,4), INVALID, 1308 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1309 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1310 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1311 1312 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1313 /* [D4] */ INVALID, INVALID, TNS("movq2dq",XMMMX), INVALID, 1314 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1315 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1316 1317 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1318 /* [E4] */ INVALID, INVALID, TNSZ("cvtdq2pd",XMM,8), INVALID, 1319 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1320 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1321 1322 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1323 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1324 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1325 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1326 }; 1327 1328 const instable_t dis_opAVXF30F[256] = { 1329 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1330 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1331 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1332 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1333 1334 /* [10] */ TNSZ("vmovss",VEX_RMrX,4), TNSZ("vmovss",VEX_RRX,4), TNSZ("vmovsldup",VEX_MX,4), INVALID, 1335 /* [14] */ INVALID, INVALID, TNSZ("vmovshdup",VEX_MX,4), INVALID, 1336 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1337 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1338 1339 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1340 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1341 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2ss",VEX_RMrX,4),INVALID, 1342 /* [2C] */ TNSZ("vcvttss2si",VEX_MR,4),TNSZ("vcvtss2si",VEX_MR,4),INVALID, INVALID, 1343 1344 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1345 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1346 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1347 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1348 1349 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1350 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1351 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1352 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1353 1354 /* [50] */ INVALID, TNSZ("vsqrtss",VEX_RMrX,4), TNSZ("vrsqrtss",VEX_RMrX,4), TNSZ("vrcpss",VEX_RMrX,4), 1355 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1356 /* [58] */ TNSZ("vaddss",VEX_RMrX,4), TNSZ("vmulss",VEX_RMrX,4), TNSZ("vcvtss2sd",VEX_RMrX,4), TNSZ("vcvttps2dq",VEX_MX,16), 1357 /* [5C] */ TNSZ("vsubss",VEX_RMrX,4), TNSZ("vminss",VEX_RMrX,4), TNSZ("vdivss",VEX_RMrX,4), TNSZ("vmaxss",VEX_RMrX,4), 1358 1359 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1360 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1361 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1362 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("vmovdqu",VEX_MX,16), 1363 1364 /* [70] */ TNSZ("vpshufhw",VEX_MXI,16),INVALID, INVALID, INVALID, 1365 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1366 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1367 /* [7C] */ INVALID, INVALID, TNSZ("vmovq",VEX_MX,8), TNSZ("vmovdqu",VEX_RX,16), 1368 1369 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1370 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1371 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1372 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1373 1374 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1375 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1376 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1377 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1378 1379 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1380 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1381 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1382 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1383 1384 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1385 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1386 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1387 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1388 1389 /* [C0] */ INVALID, INVALID, TNSZ("vcmpss",VEX_RMRX,4), INVALID, 1390 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1391 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1392 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1393 1394 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1395 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1396 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1397 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1398 1399 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1400 /* [E4] */ INVALID, INVALID, TNSZ("vcvtdq2pd",VEX_MX,8), INVALID, 1401 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1402 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1403 1404 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1405 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1406 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1407 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1408 }; 1409 /* 1410 * The following two tables are used to encode crc32 and movbe 1411 * since they share the same opcodes. 1412 */ 1413 const instable_t dis_op0F38F0[2] = { 1414 /* [00] */ TNS("crc32b",CRC32), 1415 TS("movbe",MOVBE), 1416 }; 1417 1418 const instable_t dis_op0F38F1[2] = { 1419 /* [00] */ TS("crc32",CRC32), 1420 TS("movbe",MOVBE), 1421 }; 1422 1423 /* 1424 * The following table is used to distinguish between adox and adcx which share 1425 * the same opcodes. 1426 */ 1427 const instable_t dis_op0F38F6[2] = { 1428 /* [00] */ TNS("adcx",ADX), 1429 TNS("adox",ADX), 1430 }; 1431 1432 const instable_t dis_op0F38[256] = { 1433 /* [00] */ TNSZ("pshufb",XMM_66o,16),TNSZ("phaddw",XMM_66o,16),TNSZ("phaddd",XMM_66o,16),TNSZ("phaddsw",XMM_66o,16), 1434 /* [04] */ TNSZ("pmaddubsw",XMM_66o,16),TNSZ("phsubw",XMM_66o,16), TNSZ("phsubd",XMM_66o,16),TNSZ("phsubsw",XMM_66o,16), 1435 /* [08] */ TNSZ("psignb",XMM_66o,16),TNSZ("psignw",XMM_66o,16),TNSZ("psignd",XMM_66o,16),TNSZ("pmulhrsw",XMM_66o,16), 1436 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1437 1438 /* [10] */ TNSZ("pblendvb",XMM_66r,16),INVALID, INVALID, INVALID, 1439 /* [14] */ TNSZ("blendvps",XMM_66r,16),TNSZ("blendvpd",XMM_66r,16),INVALID, TNSZ("ptest",XMM_66r,16), 1440 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1441 /* [1C] */ TNSZ("pabsb",XMM_66o,16),TNSZ("pabsw",XMM_66o,16),TNSZ("pabsd",XMM_66o,16),INVALID, 1442 1443 /* [20] */ TNSZ("pmovsxbw",XMM_66r,16),TNSZ("pmovsxbd",XMM_66r,16),TNSZ("pmovsxbq",XMM_66r,16),TNSZ("pmovsxwd",XMM_66r,16), 1444 /* [24] */ TNSZ("pmovsxwq",XMM_66r,16),TNSZ("pmovsxdq",XMM_66r,16),INVALID, INVALID, 1445 /* [28] */ TNSZ("pmuldq",XMM_66r,16),TNSZ("pcmpeqq",XMM_66r,16),TNSZ("movntdqa",XMMM_66r,16),TNSZ("packusdw",XMM_66r,16), 1446 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1447 1448 /* [30] */ TNSZ("pmovzxbw",XMM_66r,16),TNSZ("pmovzxbd",XMM_66r,16),TNSZ("pmovzxbq",XMM_66r,16),TNSZ("pmovzxwd",XMM_66r,16), 1449 /* [34] */ TNSZ("pmovzxwq",XMM_66r,16),TNSZ("pmovzxdq",XMM_66r,16),INVALID, TNSZ("pcmpgtq",XMM_66r,16), 1450 /* [38] */ TNSZ("pminsb",XMM_66r,16),TNSZ("pminsd",XMM_66r,16),TNSZ("pminuw",XMM_66r,16),TNSZ("pminud",XMM_66r,16), 1451 /* [3C] */ TNSZ("pmaxsb",XMM_66r,16),TNSZ("pmaxsd",XMM_66r,16),TNSZ("pmaxuw",XMM_66r,16),TNSZ("pmaxud",XMM_66r,16), 1452 1453 /* [40] */ TNSZ("pmulld",XMM_66r,16),TNSZ("phminposuw",XMM_66r,16),INVALID, INVALID, 1454 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1455 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1456 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1457 1458 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1459 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1460 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1461 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1462 1463 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1464 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1465 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1466 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1467 1468 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1469 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1470 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1471 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1472 1473 /* [80] */ TNSy("invept", RM_66r), TNSy("invvpid", RM_66r),TNSy("invpcid", RM_66r),INVALID, 1474 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1475 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1476 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1477 1478 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1479 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1480 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1481 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1482 1483 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1484 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1485 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1486 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1487 1488 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1489 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1490 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1491 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1492 1493 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1494 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1495 /* [C8] */ TNSZ("sha1nexte",XMM,16),TNSZ("sha1msg1",XMM,16),TNSZ("sha1msg2",XMM,16),TNSZ("sha256rnds2",XMM,16), 1496 /* [CC] */ TNSZ("sha256msg1",XMM,16),TNSZ("sha256msg2",XMM,16),INVALID, INVALID, 1497 1498 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1499 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1500 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("aesimc",XMM_66r,16), 1501 /* [DC] */ TNSZ("aesenc",XMM_66r,16),TNSZ("aesenclast",XMM_66r,16),TNSZ("aesdec",XMM_66r,16),TNSZ("aesdeclast",XMM_66r,16), 1502 1503 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1504 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1505 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1506 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1507 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID, 1508 /* [F4] */ INVALID, INVALID, IND(dis_op0F38F6), INVALID, 1509 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1510 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1511 }; 1512 1513 const instable_t dis_opAVX660F38[256] = { 1514 /* [00] */ TNSZ("vpshufb",VEX_RMrX,16),TNSZ("vphaddw",VEX_RMrX,16),TNSZ("vphaddd",VEX_RMrX,16),TNSZ("vphaddsw",VEX_RMrX,16), 1515 /* [04] */ TNSZ("vpmaddubsw",VEX_RMrX,16),TNSZ("vphsubw",VEX_RMrX,16), TNSZ("vphsubd",VEX_RMrX,16),TNSZ("vphsubsw",VEX_RMrX,16), 1516 /* [08] */ TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16), 1517 /* [0C] */ TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8), TNSZ("vtestpd",VEX_RRI,16), 1518 1519 /* [10] */ INVALID, INVALID, INVALID, TNSZ("vcvtph2ps",VEX_MX,16), 1520 /* [14] */ INVALID, INVALID, TNSZ("vpermps",VEX_RMrX,16),TNSZ("vptest",VEX_RRI,16), 1521 /* [18] */ TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID, 1522 /* [1C] */ TNSZ("vpabsb",VEX_MX,16),TNSZ("vpabsw",VEX_MX,16),TNSZ("vpabsd",VEX_MX,16),INVALID, 1523 1524 /* [20] */ TNSZ("vpmovsxbw",VEX_MX,16),TNSZ("vpmovsxbd",VEX_MX,16),TNSZ("vpmovsxbq",VEX_MX,16),TNSZ("vpmovsxwd",VEX_MX,16), 1525 /* [24] */ TNSZ("vpmovsxwq",VEX_MX,16),TNSZ("vpmovsxdq",VEX_MX,16),INVALID, INVALID, 1526 /* [28] */ TNSZ("vpmuldq",VEX_RMrX,16),TNSZ("vpcmpeqq",VEX_RMrX,16),TNSZ("vmovntdqa",VEX_MX,16),TNSZ("vpackusdw",VEX_RMrX,16), 1527 /* [2C] */ TNSZ("vmaskmovps",VEX_RMrX,8),TNSZ("vmaskmovpd",VEX_RMrX,16),TNSZ("vmaskmovps",VEX_RRM,8),TNSZ("vmaskmovpd",VEX_RRM,16), 1528 1529 /* [30] */ TNSZ("vpmovzxbw",VEX_MX,16),TNSZ("vpmovzxbd",VEX_MX,16),TNSZ("vpmovzxbq",VEX_MX,16),TNSZ("vpmovzxwd",VEX_MX,16), 1530 /* [34] */ TNSZ("vpmovzxwq",VEX_MX,16),TNSZ("vpmovzxdq",VEX_MX,16),TNSZ("vpermd",VEX_RMrX,16),TNSZ("vpcmpgtq",VEX_RMrX,16), 1531 /* [38] */ TNSZ("vpminsb",VEX_RMrX,16),TNSZ("vpminsd",VEX_RMrX,16),TNSZ("vpminuw",VEX_RMrX,16),TNSZ("vpminud",VEX_RMrX,16), 1532 /* [3C] */ TNSZ("vpmaxsb",VEX_RMrX,16),TNSZ("vpmaxsd",VEX_RMrX,16),TNSZ("vpmaxuw",VEX_RMrX,16),TNSZ("vpmaxud",VEX_RMrX,16), 1533 1534 /* [40] */ TNSZ("vpmulld",VEX_RMrX,16),TNSZ("vphminposuw",VEX_MX,16),INVALID, INVALID, 1535 /* [44] */ INVALID, TSaZ("vpsrlv",VEX_RMrX,16),TNSZ("vpsravd",VEX_RMrX,16),TSaZ("vpsllv",VEX_RMrX,16), 1536 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1537 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1538 1539 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1540 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1541 /* [58] */ TNSZ("vpbroadcastd",VEX_MX,16),TNSZ("vpbroadcastq",VEX_MX,16),TNSZ("vbroadcasti128",VEX_MX,16),INVALID, 1542 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1543 1544 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1545 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1546 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1547 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1548 1549 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1550 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1551 /* [78] */ TNSZ("vpbroadcastb",VEX_MX,16),TNSZ("vpbroadcastw",VEX_MX,16),INVALID, INVALID, 1552 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1553 1554 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1555 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1556 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1557 /* [8C] */ TSaZ("vpmaskmov",VEX_RMrX,16),INVALID, TSaZ("vpmaskmov",VEX_RRM,16),INVALID, 1558 1559 /* [90] */ TNSZ("vpgatherd",VEX_SbVM,16),TNSZ("vpgatherq",VEX_SbVM,16),TNSZ("vgatherdp",VEX_SbVM,16),TNSZ("vgatherqp",VEX_SbVM,16), 1560 /* [94] */ INVALID, INVALID, TNSZ("vfmaddsub132p",FMA,16),TNSZ("vfmsubadd132p",FMA,16), 1561 /* [98] */ TNSZ("vfmadd132p",FMA,16),TNSZ("vfmadd132s",FMA,16),TNSZ("vfmsub132p",FMA,16),TNSZ("vfmsub132s",FMA,16), 1562 /* [9C] */ TNSZ("vfnmadd132p",FMA,16),TNSZ("vfnmadd132s",FMA,16),TNSZ("vfnmsub132p",FMA,16),TNSZ("vfnmsub132s",FMA,16), 1563 1564 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1565 /* [A4] */ INVALID, INVALID, TNSZ("vfmaddsub213p",FMA,16),TNSZ("vfmsubadd213p",FMA,16), 1566 /* [A8] */ TNSZ("vfmadd213p",FMA,16),TNSZ("vfmadd213s",FMA,16),TNSZ("vfmsub213p",FMA,16),TNSZ("vfmsub213s",FMA,16), 1567 /* [AC] */ TNSZ("vfnmadd213p",FMA,16),TNSZ("vfnmadd213s",FMA,16),TNSZ("vfnmsub213p",FMA,16),TNSZ("vfnmsub213s",FMA,16), 1568 1569 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1570 /* [B4] */ INVALID, INVALID, TNSZ("vfmaddsub231p",FMA,16),TNSZ("vfmsubadd231p",FMA,16), 1571 /* [B8] */ TNSZ("vfmadd231p",FMA,16),TNSZ("vfmadd231s",FMA,16),TNSZ("vfmsub231p",FMA,16),TNSZ("vfmsub231s",FMA,16), 1572 /* [BC] */ TNSZ("vfnmadd231p",FMA,16),TNSZ("vfnmadd231s",FMA,16),TNSZ("vfnmsub231p",FMA,16),TNSZ("vfnmsub231s",FMA,16), 1573 1574 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1575 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1576 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1577 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1578 1579 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1580 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1581 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("vaesimc",VEX_MX,16), 1582 /* [DC] */ TNSZ("vaesenc",VEX_RMrX,16),TNSZ("vaesenclast",VEX_RMrX,16),TNSZ("vaesdec",VEX_RMrX,16),TNSZ("vaesdeclast",VEX_RMrX,16), 1583 1584 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1585 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1586 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1587 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1588 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID, 1589 /* [F4] */ INVALID, INVALID, INVALID, TNSZvr("shlx",VEX_VRMrX,5), 1590 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1591 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1592 }; 1593 1594 const instable_t dis_op0F3A[256] = { 1595 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1596 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1597 /* [08] */ TNSZ("roundps",XMMP_66r,16),TNSZ("roundpd",XMMP_66r,16),TNSZ("roundss",XMMP_66r,16),TNSZ("roundsd",XMMP_66r,16), 1598 /* [0C] */ TNSZ("blendps",XMMP_66r,16),TNSZ("blendpd",XMMP_66r,16),TNSZ("pblendw",XMMP_66r,16),TNSZ("palignr",XMMP_66o,16), 1599 1600 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1601 /* [14] */ TNSZ("pextrb",XMM3PM_66r,8),TNSZ("pextrw",XMM3PM_66r,16),TSZ("pextr",XMM3PM_66r,16),TNSZ("extractps",XMM3PM_66r,16), 1602 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1603 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1604 1605 /* [20] */ TNSZ("pinsrb",XMMPRM_66r,8),TNSZ("insertps",XMMP_66r,16),TSZ("pinsr",XMMPRM_66r,16),INVALID, 1606 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1607 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1608 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1609 1610 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1611 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1612 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1613 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1614 1615 /* [40] */ TNSZ("dpps",XMMP_66r,16),TNSZ("dppd",XMMP_66r,16),TNSZ("mpsadbw",XMMP_66r,16),INVALID, 1616 /* [44] */ TNSZ("pclmulqdq",XMMP_66r,16),INVALID, INVALID, INVALID, 1617 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1618 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1619 1620 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1621 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1622 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1623 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1624 1625 /* [60] */ TNSZ("pcmpestrm",XMMP_66r,16),TNSZ("pcmpestri",XMMP_66r,16),TNSZ("pcmpistrm",XMMP_66r,16),TNSZ("pcmpistri",XMMP_66r,16), 1626 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1627 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1628 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1629 1630 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1631 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1632 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1633 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1634 1635 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1636 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1637 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1638 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1639 1640 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1641 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1642 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1643 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1644 1645 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1646 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1647 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1648 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1649 1650 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1651 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1652 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1653 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1654 1655 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1656 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1657 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1658 /* [CC] */ TNSZ("sha1rnds4",XMMP,16),INVALID, INVALID, INVALID, 1659 1660 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1661 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1662 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1663 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("aeskeygenassist",XMMP_66r,16), 1664 1665 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1666 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1667 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1668 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1669 1670 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1671 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1672 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1673 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1674 }; 1675 1676 const instable_t dis_opAVX660F3A[256] = { 1677 /* [00] */ TNSZ("vpermq",VEX_MXI,16),TNSZ("vpermpd",VEX_MXI,16),TNSZ("vpblendd",VEX_RMRX,16),INVALID, 1678 /* [04] */ TNSZ("vpermilps",VEX_MXI,8),TNSZ("vpermilpd",VEX_MXI,16),TNSZ("vperm2f128",VEX_RMRX,16),INVALID, 1679 /* [08] */ TNSZ("vroundps",VEX_MXI,16),TNSZ("vroundpd",VEX_MXI,16),TNSZ("vroundss",VEX_RMRX,16),TNSZ("vroundsd",VEX_RMRX,16), 1680 /* [0C] */ TNSZ("vblendps",VEX_RMRX,16),TNSZ("vblendpd",VEX_RMRX,16),TNSZ("vpblendw",VEX_RMRX,16),TNSZ("vpalignr",VEX_RMRX,16), 1681 1682 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1683 /* [14] */ TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16), 1684 /* [18] */ TNSZ("vinsertf128",VEX_RMRX,16),TNSZ("vextractf128",VEX_RX,16),INVALID, INVALID, 1685 /* [1C] */ INVALID, TNSZ("vcvtps2ph",VEX_RX,16), INVALID, INVALID, 1686 1687 /* [20] */ TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID, 1688 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1689 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1690 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1691 1692 /* [30] */ TSvo("kshiftr",VEX_MXI), TSvo("kshiftr",VEX_MXI), TSvo("kshiftl",VEX_MXI), TSvo("kshiftl",VEX_MXI), 1693 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1694 /* [38] */ TNSZ("vinserti128",VEX_RMRX,16),TNSZ("vextracti128",VEX_RIM,16),INVALID, INVALID, 1695 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1696 1697 /* [40] */ TNSZ("vdpps",VEX_RMRX,16),TNSZ("vdppd",VEX_RMRX,16),TNSZ("vmpsadbw",VEX_RMRX,16),INVALID, 1698 /* [44] */ TNSZ("vpclmulqdq",VEX_RMRX,16),INVALID, TNSZ("vperm2i128",VEX_RMRX,16),INVALID, 1699 /* [48] */ INVALID, INVALID, TNSZ("vblendvps",VEX_RMRX,8), TNSZ("vblendvpd",VEX_RMRX,16), 1700 /* [4C] */ TNSZ("vpblendvb",VEX_RMRX,16),INVALID, INVALID, INVALID, 1701 1702 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1703 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1704 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1705 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1706 1707 /* [60] */ TNSZ("vpcmpestrm",VEX_MXI,16),TNSZ("vpcmpestri",VEX_MXI,16),TNSZ("vpcmpistrm",VEX_MXI,16),TNSZ("vpcmpistri",VEX_MXI,16), 1708 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1709 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1710 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1711 1712 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1713 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1714 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1715 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1716 1717 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1718 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1719 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1720 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1721 1722 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1723 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1724 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1725 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1726 1727 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1728 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1729 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1730 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1731 1732 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1733 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1734 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1735 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1736 1737 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1738 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1739 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1740 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1741 1742 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1743 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1744 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1745 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("vaeskeygenassist",VEX_MXI,16), 1746 1747 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1748 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1749 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1750 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1751 1752 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1753 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1754 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1755 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1756 }; 1757 1758 /* 1759 * Decode table for 0x0F0D which uses the first byte of the mod_rm to 1760 * indicate a sub-code. 1761 */ 1762 const instable_t dis_op0F0D[8] = { 1763 /* [00] */ INVALID, TNS("prefetchw",PREF), TNS("prefetchwt1",PREF),INVALID, 1764 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1765 }; 1766 1767 /* 1768 * Decode table for 0x0F opcodes 1769 */ 1770 1771 const instable_t dis_op0F[16][16] = { 1772 { 1773 /* [00] */ IND(dis_op0F00), IND(dis_op0F01), TNS("lar",MR), TNS("lsl",MR), 1774 /* [04] */ INVALID, TNS("syscall",NORM), TNS("clts",NORM), TNS("sysret",NORM), 1775 /* [08] */ TNS("invd",NORM), TNS("wbinvd",NORM), INVALID, TNS("ud2",NORM), 1776 /* [0C] */ INVALID, IND(dis_op0F0D), INVALID, INVALID, 1777 }, { 1778 /* [10] */ TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8), TNSZ("movlps",XMMOS,8), 1779 /* [14] */ TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8), 1780 /* [18] */ IND(dis_op0F18), INVALID, INVALID, INVALID, 1781 /* [1C] */ INVALID, INVALID, INVALID, TS("nop",Mw), 1782 }, { 1783 /* [20] */ TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), 1784 /* [24] */ TSx("mov",SREG), INVALID, TSx("mov",SREG), INVALID, 1785 /* [28] */ TNSZ("movaps",XMMO,16), TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16), 1786 /* [2C] */ TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4), 1787 }, { 1788 /* [30] */ TNS("wrmsr",NORM), TNS("rdtsc",NORM), TNS("rdmsr",NORM), TNS("rdpmc",NORM), 1789 /* [34] */ TNS("sysenter",NORM), TNS("sysexit",NORM), INVALID, INVALID, 1790 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1791 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1792 }, { 1793 /* [40] */ TS("cmovx.o",MR), TS("cmovx.no",MR), TS("cmovx.b",MR), TS("cmovx.ae",MR), 1794 /* [44] */ TS("cmovx.e",MR), TS("cmovx.ne",MR), TS("cmovx.be",MR), TS("cmovx.a",MR), 1795 /* [48] */ TS("cmovx.s",MR), TS("cmovx.ns",MR), TS("cmovx.pe",MR), TS("cmovx.po",MR), 1796 /* [4C] */ TS("cmovx.l",MR), TS("cmovx.ge",MR), TS("cmovx.le",MR), TS("cmovx.g",MR), 1797 }, { 1798 /* [50] */ TNS("movmskps",XMMOX3), TNSZ("sqrtps",XMMO,16), TNSZ("rsqrtps",XMMO,16),TNSZ("rcpps",XMMO,16), 1799 /* [54] */ TNSZ("andps",XMMO,16), TNSZ("andnps",XMMO,16), TNSZ("orps",XMMO,16), TNSZ("xorps",XMMO,16), 1800 /* [58] */ TNSZ("addps",XMMO,16), TNSZ("mulps",XMMO,16), TNSZ("cvtps2pd",XMMO,8),TNSZ("cvtdq2ps",XMMO,16), 1801 /* [5C] */ TNSZ("subps",XMMO,16), TNSZ("minps",XMMO,16), TNSZ("divps",XMMO,16), TNSZ("maxps",XMMO,16), 1802 }, { 1803 /* [60] */ TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8), 1804 /* [64] */ TNSZ("pcmpgtb",MMO,8), TNSZ("pcmpgtw",MMO,8), TNSZ("pcmpgtd",MMO,8), TNSZ("packuswb",MMO,8), 1805 /* [68] */ TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8), 1806 /* [6C] */ TNSZ("INVALID",MMO,0), TNSZ("INVALID",MMO,0), TNSZ("movd",MMO,4), TNSZ("movq",MMO,8), 1807 }, { 1808 /* [70] */ TNSZ("pshufw",MMOPM,8), TNS("psrXXX",MR), TNS("psrXXX",MR), TNS("psrXXX",MR), 1809 /* [74] */ TNSZ("pcmpeqb",MMO,8), TNSZ("pcmpeqw",MMO,8), TNSZ("pcmpeqd",MMO,8), TNS("emms",NORM), 1810 /* [78] */ TNSy("vmread",RM), TNSy("vmwrite",MR), INVALID, INVALID, 1811 /* [7C] */ INVALID, INVALID, TNSZ("movd",MMOS,4), TNSZ("movq",MMOS,8), 1812 }, { 1813 /* [80] */ TNS("jo",D), TNS("jno",D), TNS("jb",D), TNS("jae",D), 1814 /* [84] */ TNS("je",D), TNS("jne",D), TNS("jbe",D), TNS("ja",D), 1815 /* [88] */ TNS("js",D), TNS("jns",D), TNS("jp",D), TNS("jnp",D), 1816 /* [8C] */ TNS("jl",D), TNS("jge",D), TNS("jle",D), TNS("jg",D), 1817 }, { 1818 /* [90] */ TNS("seto",Mb), TNS("setno",Mb), TNS("setb",Mb), TNS("setae",Mb), 1819 /* [94] */ TNS("sete",Mb), TNS("setne",Mb), TNS("setbe",Mb), TNS("seta",Mb), 1820 /* [98] */ TNS("sets",Mb), TNS("setns",Mb), TNS("setp",Mb), TNS("setnp",Mb), 1821 /* [9C] */ TNS("setl",Mb), TNS("setge",Mb), TNS("setle",Mb), TNS("setg",Mb), 1822 }, { 1823 /* [A0] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("cpuid",NORM), TS("bt",RMw), 1824 /* [A4] */ TS("shld",DSHIFT), TS("shld",DSHIFTcl), INVALID, INVALID, 1825 /* [A8] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("rsm",NORM), TS("bts",RMw), 1826 /* [AC] */ TS("shrd",DSHIFT), TS("shrd",DSHIFTcl), IND(dis_op0FAE), TS("imul",MRw), 1827 }, { 1828 /* [B0] */ TNS("cmpxchgb",RMw), TS("cmpxchg",RMw), TS("lss",MR), TS("btr",RMw), 1829 /* [B4] */ TS("lfs",MR), TS("lgs",MR), TS("movzb",MOVZ), TNS("movzwl",MOVZ), 1830 /* [B8] */ TNS("INVALID",MRw), INVALID, IND(dis_op0FBA), TS("btc",RMw), 1831 /* [BC] */ TS("bsf",MRw), TS("bsr",MRw), TS("movsb",MOVZ), TNS("movswl",MOVZ), 1832 }, { 1833 /* [C0] */ TNS("xaddb",XADDB), TS("xadd",RMw), TNSZ("cmpps",XMMOPM,16),TNS("movnti",RM), 1834 /* [C4] */ TNSZ("pinsrw",MMOPRM,2),TNS("pextrw",MMO3P), TNSZ("shufps",XMMOPM,16),IND(dis_op0FC7), 1835 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1836 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1837 }, { 1838 /* [D0] */ INVALID, TNSZ("psrlw",MMO,8), TNSZ("psrld",MMO,8), TNSZ("psrlq",MMO,8), 1839 /* [D4] */ TNSZ("paddq",MMO,8), TNSZ("pmullw",MMO,8), TNSZ("INVALID",MMO,0), TNS("pmovmskb",MMOM3), 1840 /* [D8] */ TNSZ("psubusb",MMO,8), TNSZ("psubusw",MMO,8), TNSZ("pminub",MMO,8), TNSZ("pand",MMO,8), 1841 /* [DC] */ TNSZ("paddusb",MMO,8), TNSZ("paddusw",MMO,8), TNSZ("pmaxub",MMO,8), TNSZ("pandn",MMO,8), 1842 }, { 1843 /* [E0] */ TNSZ("pavgb",MMO,8), TNSZ("psraw",MMO,8), TNSZ("psrad",MMO,8), TNSZ("pavgw",MMO,8), 1844 /* [E4] */ TNSZ("pmulhuw",MMO,8), TNSZ("pmulhw",MMO,8), TNS("INVALID",XMMO), TNSZ("movntq",MMOMS,8), 1845 /* [E8] */ TNSZ("psubsb",MMO,8), TNSZ("psubsw",MMO,8), TNSZ("pminsw",MMO,8), TNSZ("por",MMO,8), 1846 /* [EC] */ TNSZ("paddsb",MMO,8), TNSZ("paddsw",MMO,8), TNSZ("pmaxsw",MMO,8), TNSZ("pxor",MMO,8), 1847 }, { 1848 /* [F0] */ INVALID, TNSZ("psllw",MMO,8), TNSZ("pslld",MMO,8), TNSZ("psllq",MMO,8), 1849 /* [F4] */ TNSZ("pmuludq",MMO,8), TNSZ("pmaddwd",MMO,8), TNSZ("psadbw",MMO,8), TNSZ("maskmovq",MMOIMPL,8), 1850 /* [F8] */ TNSZ("psubb",MMO,8), TNSZ("psubw",MMO,8), TNSZ("psubd",MMO,8), TNSZ("psubq",MMO,8), 1851 /* [FC] */ TNSZ("paddb",MMO,8), TNSZ("paddw",MMO,8), TNSZ("paddd",MMO,8), INVALID, 1852 } }; 1853 1854 const instable_t dis_opAVX0F[16][16] = { 1855 { 1856 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1857 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1858 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1859 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1860 }, { 1861 /* [10] */ TNSZ("vmovups",VEX_MX,16), TNSZ("vmovups",VEX_RM,16),TNSZ("vmovlps",VEX_RMrX,8), TNSZ("vmovlps",VEX_RM,8), 1862 /* [14] */ TNSZ("vunpcklps",VEX_RMrX,16),TNSZ("vunpckhps",VEX_RMrX,16),TNSZ("vmovhps",VEX_RMrX,8),TNSZ("vmovhps",VEX_RM,8), 1863 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1864 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1865 }, { 1866 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1867 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1868 /* [28] */ TNSZ("vmovaps",VEX_MX,16), TNSZ("vmovaps",VEX_RX,16),INVALID, TNSZ("vmovntps",VEX_RM,16), 1869 /* [2C] */ INVALID, INVALID, TNSZ("vucomiss",VEX_MX,4),TNSZ("vcomiss",VEX_MX,4), 1870 }, { 1871 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1872 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1873 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1874 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1875 }, { 1876 /* [40] */ INVALID, TSvo("kand",VEX_RMX), TSvo("kandn",VEX_RMX), INVALID, 1877 /* [44] */ TSvo("knot",VEX_MX), TSvo("kor",VEX_RMX), TSvo("kxnor",VEX_RMX), TSvo("kxor",VEX_RMX), 1878 /* [48] */ INVALID, INVALID, TSvo("kadd",VEX_RMX), TSvo("kunpck",VEX_RMX), 1879 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1880 }, { 1881 /* [50] */ TNS("vmovmskps",VEX_MR), TNSZ("vsqrtps",VEX_MX,16), TNSZ("vrsqrtps",VEX_MX,16),TNSZ("vrcpps",VEX_MX,16), 1882 /* [54] */ TNSZ("vandps",VEX_RMrX,16), TNSZ("vandnps",VEX_RMrX,16), TNSZ("vorps",VEX_RMrX,16), TNSZ("vxorps",VEX_RMrX,16), 1883 /* [58] */ TNSZ("vaddps",VEX_RMrX,16), TNSZ("vmulps",VEX_RMrX,16), TNSZ("vcvtps2pd",VEX_MX,8),TNSZ("vcvtdq2ps",VEX_MX,16), 1884 /* [5C] */ TNSZ("vsubps",VEX_RMrX,16), TNSZ("vminps",VEX_RMrX,16), TNSZ("vdivps",VEX_RMrX,16), TNSZ("vmaxps",VEX_RMrX,16), 1885 }, { 1886 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1887 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1888 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1889 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1890 }, { 1891 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1892 /* [74] */ INVALID, INVALID, INVALID, TNS("vzeroupper", VEX_NONE), 1893 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1894 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1895 }, { 1896 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1897 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1898 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1899 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1900 }, { 1901 /* [90] */ TSvo("kmov",VEX_KRM), TSvo("kmov",VEX_KMR), TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR), 1902 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1903 /* [98] */ TSvo("kortest",VEX_MX), TSvo("ktest",VEX_MX), INVALID, INVALID, 1904 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1905 }, { 1906 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1907 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1908 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1909 /* [AC] */ INVALID, INVALID, TNSZ("vldmxcsr",VEX_MO,2), INVALID, 1910 }, { 1911 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1912 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1913 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1914 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1915 }, { 1916 /* [C0] */ INVALID, INVALID, TNSZ("vcmpps",VEX_RMRX,16),INVALID, 1917 /* [C4] */ INVALID, INVALID, TNSZ("vshufps",VEX_RMRX,16),INVALID, 1918 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1919 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1920 }, { 1921 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1922 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1923 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1924 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1925 }, { 1926 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1927 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1928 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1929 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1930 }, { 1931 /* [F0] */ INVALID, INVALID, TNSZvr("andn",VEX_RMrX,5),TNSZvr("bls",BLS,5), 1932 /* [F4] */ INVALID, TNSZvr("bzhi",VEX_VRMrX,5),INVALID, TNSZvr("bextr",VEX_VRMrX,5), 1933 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1934 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1935 } }; 1936 1937 /* 1938 * Decode table for 0x80 opcodes 1939 */ 1940 1941 const instable_t dis_op80[8] = { 1942 1943 /* [0] */ TNS("addb",IMlw), TNS("orb",IMw), TNS("adcb",IMlw), TNS("sbbb",IMlw), 1944 /* [4] */ TNS("andb",IMw), TNS("subb",IMlw), TNS("xorb",IMw), TNS("cmpb",IMlw), 1945 }; 1946 1947 1948 /* 1949 * Decode table for 0x81 opcodes. 1950 */ 1951 1952 const instable_t dis_op81[8] = { 1953 1954 /* [0] */ TS("add",IMlw), TS("or",IMw), TS("adc",IMlw), TS("sbb",IMlw), 1955 /* [4] */ TS("and",IMw), TS("sub",IMlw), TS("xor",IMw), TS("cmp",IMlw), 1956 }; 1957 1958 1959 /* 1960 * Decode table for 0x82 opcodes. 1961 */ 1962 1963 const instable_t dis_op82[8] = { 1964 1965 /* [0] */ TNSx("addb",IMlw), TNSx("orb",IMlw), TNSx("adcb",IMlw), TNSx("sbbb",IMlw), 1966 /* [4] */ TNSx("andb",IMlw), TNSx("subb",IMlw), TNSx("xorb",IMlw), TNSx("cmpb",IMlw), 1967 }; 1968 /* 1969 * Decode table for 0x83 opcodes. 1970 */ 1971 1972 const instable_t dis_op83[8] = { 1973 1974 /* [0] */ TS("add",IMlw), TS("or",IMlw), TS("adc",IMlw), TS("sbb",IMlw), 1975 /* [4] */ TS("and",IMlw), TS("sub",IMlw), TS("xor",IMlw), TS("cmp",IMlw), 1976 }; 1977 1978 /* 1979 * Decode table for 0xC0 opcodes. 1980 */ 1981 1982 const instable_t dis_opC0[8] = { 1983 1984 /* [0] */ TNS("rolb",MvI), TNS("rorb",MvI), TNS("rclb",MvI), TNS("rcrb",MvI), 1985 /* [4] */ TNS("shlb",MvI), TNS("shrb",MvI), INVALID, TNS("sarb",MvI), 1986 }; 1987 1988 /* 1989 * Decode table for 0xD0 opcodes. 1990 */ 1991 1992 const instable_t dis_opD0[8] = { 1993 1994 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv), 1995 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv), 1996 }; 1997 1998 /* 1999 * Decode table for 0xC1 opcodes. 2000 * 186 instruction set 2001 */ 2002 2003 const instable_t dis_opC1[8] = { 2004 2005 /* [0] */ TS("rol",MvI), TS("ror",MvI), TS("rcl",MvI), TS("rcr",MvI), 2006 /* [4] */ TS("shl",MvI), TS("shr",MvI), TS("sal",MvI), TS("sar",MvI), 2007 }; 2008 2009 /* 2010 * Decode table for 0xD1 opcodes. 2011 */ 2012 2013 const instable_t dis_opD1[8] = { 2014 2015 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv), 2016 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("sal",Mv), TS("sar",Mv), 2017 }; 2018 2019 2020 /* 2021 * Decode table for 0xD2 opcodes. 2022 */ 2023 2024 const instable_t dis_opD2[8] = { 2025 2026 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv), 2027 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv), 2028 }; 2029 /* 2030 * Decode table for 0xD3 opcodes. 2031 */ 2032 2033 const instable_t dis_opD3[8] = { 2034 2035 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv), 2036 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("salb",Mv), TS("sar",Mv), 2037 }; 2038 2039 2040 /* 2041 * Decode table for 0xF6 opcodes. 2042 */ 2043 2044 const instable_t dis_opF6[8] = { 2045 2046 /* [0] */ TNS("testb",IMw), TNS("testb",IMw), TNS("notb",Mw), TNS("negb",Mw), 2047 /* [4] */ TNS("mulb",MA), TNS("imulb",MA), TNS("divb",MA), TNS("idivb",MA), 2048 }; 2049 2050 2051 /* 2052 * Decode table for 0xF7 opcodes. 2053 */ 2054 2055 const instable_t dis_opF7[8] = { 2056 2057 /* [0] */ TS("test",IMw), TS("test",IMw), TS("not",Mw), TS("neg",Mw), 2058 /* [4] */ TS("mul",MA), TS("imul",MA), TS("div",MA), TS("idiv",MA), 2059 }; 2060 2061 2062 /* 2063 * Decode table for 0xFE opcodes. 2064 */ 2065 2066 const instable_t dis_opFE[8] = { 2067 2068 /* [0] */ TNS("incb",Mw), TNS("decb",Mw), INVALID, INVALID, 2069 /* [4] */ INVALID, INVALID, INVALID, INVALID, 2070 }; 2071 /* 2072 * Decode table for 0xFF opcodes. 2073 */ 2074 2075 const instable_t dis_opFF[8] = { 2076 2077 /* [0] */ TS("inc",Mw), TS("dec",Mw), TNSyp("call",INM), TNS("lcall",INM), 2078 /* [4] */ TNSy("jmp",INM), TNS("ljmp",INM), TSp("push",M), INVALID, 2079 }; 2080 2081 /* for 287 instructions, which are a mess to decode */ 2082 2083 const instable_t dis_opFP1n2[8][8] = { 2084 { 2085 /* bit pattern: 1101 1xxx MODxx xR/M */ 2086 /* [0,0] */ TNS("fadds",M), TNS("fmuls",M), TNS("fcoms",M), TNS("fcomps",M), 2087 /* [0,4] */ TNS("fsubs",M), TNS("fsubrs",M), TNS("fdivs",M), TNS("fdivrs",M), 2088 }, { 2089 /* [1,0] */ TNS("flds",M), INVALID, TNS("fsts",M), TNS("fstps",M), 2090 /* [1,4] */ TNSZ("fldenv",M,28), TNSZ("fldcw",M,2), TNSZ("fnstenv",M,28), TNSZ("fnstcw",M,2), 2091 }, { 2092 /* [2,0] */ TNS("fiaddl",M), TNS("fimull",M), TNS("ficoml",M), TNS("ficompl",M), 2093 /* [2,4] */ TNS("fisubl",M), TNS("fisubrl",M), TNS("fidivl",M), TNS("fidivrl",M), 2094 }, { 2095 /* [3,0] */ TNS("fildl",M), TNSZ("tisttpl",M,4), TNS("fistl",M), TNS("fistpl",M), 2096 /* [3,4] */ INVALID, TNSZ("fldt",M,10), INVALID, TNSZ("fstpt",M,10), 2097 }, { 2098 /* [4,0] */ TNSZ("faddl",M,8), TNSZ("fmull",M,8), TNSZ("fcoml",M,8), TNSZ("fcompl",M,8), 2099 /* [4,1] */ TNSZ("fsubl",M,8), TNSZ("fsubrl",M,8), TNSZ("fdivl",M,8), TNSZ("fdivrl",M,8), 2100 }, { 2101 /* [5,0] */ TNSZ("fldl",M,8), TNSZ("fisttpll",M,8), TNSZ("fstl",M,8), TNSZ("fstpl",M,8), 2102 /* [5,4] */ TNSZ("frstor",M,108), INVALID, TNSZ("fnsave",M,108), TNSZ("fnstsw",M,2), 2103 }, { 2104 /* [6,0] */ TNSZ("fiadd",M,2), TNSZ("fimul",M,2), TNSZ("ficom",M,2), TNSZ("ficomp",M,2), 2105 /* [6,4] */ TNSZ("fisub",M,2), TNSZ("fisubr",M,2), TNSZ("fidiv",M,2), TNSZ("fidivr",M,2), 2106 }, { 2107 /* [7,0] */ TNSZ("fild",M,2), TNSZ("fisttp",M,2), TNSZ("fist",M,2), TNSZ("fistp",M,2), 2108 /* [7,4] */ TNSZ("fbld",M,10), TNSZ("fildll",M,8), TNSZ("fbstp",M,10), TNSZ("fistpll",M,8), 2109 } }; 2110 2111 const instable_t dis_opFP3[8][8] = { 2112 { 2113 /* bit pattern: 1101 1xxx 11xx xREG */ 2114 /* [0,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F), 2115 /* [0,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF), 2116 }, { 2117 /* [1,0] */ TNS("fld",F), TNS("fxch",F), TNS("fnop",NORM), TNS("fstp",F), 2118 /* [1,4] */ INVALID, INVALID, INVALID, INVALID, 2119 }, { 2120 /* [2,0] */ INVALID, INVALID, INVALID, INVALID, 2121 /* [2,4] */ INVALID, TNS("fucompp",NORM), INVALID, INVALID, 2122 }, { 2123 /* [3,0] */ INVALID, INVALID, INVALID, INVALID, 2124 /* [3,4] */ INVALID, INVALID, INVALID, INVALID, 2125 }, { 2126 /* [4,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F), 2127 /* [4,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF), 2128 }, { 2129 /* [5,0] */ TNS("ffree",F), TNS("fxch",F), TNS("fst",F), TNS("fstp",F), 2130 /* [5,4] */ TNS("fucom",F), TNS("fucomp",F), INVALID, INVALID, 2131 }, { 2132 /* [6,0] */ TNS("faddp",FF), TNS("fmulp",FF), TNS("fcomp",F), TNS("fcompp",NORM), 2133 /* [6,4] */ TNS("fsubp",FF), TNS("fsubrp",FF), TNS("fdivp",FF), TNS("fdivrp",FF), 2134 }, { 2135 /* [7,0] */ TNS("ffreep",F), TNS("fxch",F), TNS("fstp",F), TNS("fstp",F), 2136 /* [7,4] */ TNS("fnstsw",M), TNS("fucomip",FFC), TNS("fcomip",FFC), INVALID, 2137 } }; 2138 2139 const instable_t dis_opFP4[4][8] = { 2140 { 2141 /* bit pattern: 1101 1001 111x xxxx */ 2142 /* [0,0] */ TNS("fchs",NORM), TNS("fabs",NORM), INVALID, INVALID, 2143 /* [0,4] */ TNS("ftst",NORM), TNS("fxam",NORM), TNS("ftstp",NORM), INVALID, 2144 }, { 2145 /* [1,0] */ TNS("fld1",NORM), TNS("fldl2t",NORM), TNS("fldl2e",NORM), TNS("fldpi",NORM), 2146 /* [1,4] */ TNS("fldlg2",NORM), TNS("fldln2",NORM), TNS("fldz",NORM), INVALID, 2147 }, { 2148 /* [2,0] */ TNS("f2xm1",NORM), TNS("fyl2x",NORM), TNS("fptan",NORM), TNS("fpatan",NORM), 2149 /* [2,4] */ TNS("fxtract",NORM), TNS("fprem1",NORM), TNS("fdecstp",NORM), TNS("fincstp",NORM), 2150 }, { 2151 /* [3,0] */ TNS("fprem",NORM), TNS("fyl2xp1",NORM), TNS("fsqrt",NORM), TNS("fsincos",NORM), 2152 /* [3,4] */ TNS("frndint",NORM), TNS("fscale",NORM), TNS("fsin",NORM), TNS("fcos",NORM), 2153 } }; 2154 2155 const instable_t dis_opFP5[8] = { 2156 /* bit pattern: 1101 1011 111x xxxx */ 2157 /* [0] */ TNS("feni",NORM), TNS("fdisi",NORM), TNS("fnclex",NORM), TNS("fninit",NORM), 2158 /* [4] */ TNS("fsetpm",NORM), TNS("frstpm",NORM), INVALID, INVALID, 2159 }; 2160 2161 const instable_t dis_opFP6[8] = { 2162 /* bit pattern: 1101 1011 11yy yxxx */ 2163 /* [00] */ TNS("fcmov.nb",FF), TNS("fcmov.ne",FF), TNS("fcmov.nbe",FF), TNS("fcmov.nu",FF), 2164 /* [04] */ INVALID, TNS("fucomi",F), TNS("fcomi",F), INVALID, 2165 }; 2166 2167 const instable_t dis_opFP7[8] = { 2168 /* bit pattern: 1101 1010 11yy yxxx */ 2169 /* [00] */ TNS("fcmov.b",FF), TNS("fcmov.e",FF), TNS("fcmov.be",FF), TNS("fcmov.u",FF), 2170 /* [04] */ INVALID, INVALID, INVALID, INVALID, 2171 }; 2172 2173 /* 2174 * Main decode table for the op codes. The first two nibbles 2175 * will be used as an index into the table. If there is a 2176 * a need to further decode an instruction, the array to be 2177 * referenced is indicated with the other two entries being 2178 * empty. 2179 */ 2180 2181 const instable_t dis_distable[16][16] = { 2182 { 2183 /* [0,0] */ TNS("addb",RMw), TS("add",RMw), TNS("addb",MRw), TS("add",MRw), 2184 /* [0,4] */ TNS("addb",IA), TS("add",IA), TSx("push",SEG), TSx("pop",SEG), 2185 /* [0,8] */ TNS("orb",RMw), TS("or",RMw), TNS("orb",MRw), TS("or",MRw), 2186 /* [0,C] */ TNS("orb",IA), TS("or",IA), TSx("push",SEG), IND(dis_op0F), 2187 }, { 2188 /* [1,0] */ TNS("adcb",RMw), TS("adc",RMw), TNS("adcb",MRw), TS("adc",MRw), 2189 /* [1,4] */ TNS("adcb",IA), TS("adc",IA), TSx("push",SEG), TSx("pop",SEG), 2190 /* [1,8] */ TNS("sbbb",RMw), TS("sbb",RMw), TNS("sbbb",MRw), TS("sbb",MRw), 2191 /* [1,C] */ TNS("sbbb",IA), TS("sbb",IA), TSx("push",SEG), TSx("pop",SEG), 2192 }, { 2193 /* [2,0] */ TNS("andb",RMw), TS("and",RMw), TNS("andb",MRw), TS("and",MRw), 2194 /* [2,4] */ TNS("andb",IA), TS("and",IA), TNSx("%es:",OVERRIDE), TNSx("daa",NORM), 2195 /* [2,8] */ TNS("subb",RMw), TS("sub",RMw), TNS("subb",MRw), TS("sub",MRw), 2196 /* [2,C] */ TNS("subb",IA), TS("sub",IA), TNS("%cs:",OVERRIDE), TNSx("das",NORM), 2197 }, { 2198 /* [3,0] */ TNS("xorb",RMw), TS("xor",RMw), TNS("xorb",MRw), TS("xor",MRw), 2199 /* [3,4] */ TNS("xorb",IA), TS("xor",IA), TNSx("%ss:",OVERRIDE), TNSx("aaa",NORM), 2200 /* [3,8] */ TNS("cmpb",RMw), TS("cmp",RMw), TNS("cmpb",MRw), TS("cmp",MRw), 2201 /* [3,C] */ TNS("cmpb",IA), TS("cmp",IA), TNSx("%ds:",OVERRIDE), TNSx("aas",NORM), 2202 }, { 2203 /* [4,0] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R), 2204 /* [4,4] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R), 2205 /* [4,8] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R), 2206 /* [4,C] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R), 2207 }, { 2208 /* [5,0] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R), 2209 /* [5,4] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R), 2210 /* [5,8] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R), 2211 /* [5,C] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R), 2212 }, { 2213 /* [6,0] */ TSZx("pusha",IMPLMEM,28),TSZx("popa",IMPLMEM,28), TSx("bound",MR), TNS("arpl",RMw), 2214 /* [6,4] */ TNS("%fs:",OVERRIDE), TNS("%gs:",OVERRIDE), TNS("data16",DM), TNS("addr16",AM), 2215 /* [6,8] */ TSp("push",I), TS("imul",IMUL), TSp("push",Ib), TS("imul",IMUL), 2216 /* [6,C] */ TNSZ("insb",IMPLMEM,1), TSZ("ins",IMPLMEM,4), TNSZ("outsb",IMPLMEM,1),TSZ("outs",IMPLMEM,4), 2217 }, { 2218 /* [7,0] */ TNSy("jo",BD), TNSy("jno",BD), TNSy("jb",BD), TNSy("jae",BD), 2219 /* [7,4] */ TNSy("je",BD), TNSy("jne",BD), TNSy("jbe",BD), TNSy("ja",BD), 2220 /* [7,8] */ TNSy("js",BD), TNSy("jns",BD), TNSy("jp",BD), TNSy("jnp",BD), 2221 /* [7,C] */ TNSy("jl",BD), TNSy("jge",BD), TNSy("jle",BD), TNSy("jg",BD), 2222 }, { 2223 /* [8,0] */ IND(dis_op80), IND(dis_op81), INDx(dis_op82), IND(dis_op83), 2224 /* [8,4] */ TNS("testb",RMw), TS("test",RMw), TNS("xchgb",RMw), TS("xchg",RMw), 2225 /* [8,8] */ TNS("movb",RMw), TS("mov",RMw), TNS("movb",MRw), TS("mov",MRw), 2226 /* [8,C] */ TNS("movw",SM), TS("lea",MR), TNS("movw",MS), TSp("pop",M), 2227 }, { 2228 /* [9,0] */ TNS("nop",NORM), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), 2229 /* [9,4] */ TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), 2230 /* [9,8] */ TNS("cXtX",CBW), TNS("cXtX",CWD), TNSx("lcall",SO), TNS("fwait",NORM), 2231 /* [9,C] */ TSZy("pushf",IMPLMEM,4),TSZy("popf",IMPLMEM,4), TNS("sahf",NORM), TNS("lahf",NORM), 2232 }, { 2233 /* [A,0] */ TNS("movb",OA), TS("mov",OA), TNS("movb",AO), TS("mov",AO), 2234 /* [A,4] */ TNSZ("movsb",SD,1), TS("movs",SD), TNSZ("cmpsb",SD,1), TS("cmps",SD), 2235 /* [A,8] */ TNS("testb",IA), TS("test",IA), TNS("stosb",AD), TS("stos",AD), 2236 /* [A,C] */ TNS("lodsb",SA), TS("lods",SA), TNS("scasb",AD), TS("scas",AD), 2237 }, { 2238 /* [B,0] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), 2239 /* [B,4] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), 2240 /* [B,8] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR), 2241 /* [B,C] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR), 2242 }, { 2243 /* [C,0] */ IND(dis_opC0), IND(dis_opC1), TNSyp("ret",RET), TNSyp("ret",NORM), 2244 /* [C,4] */ TNSx("les",MR), TNSx("lds",MR), TNS("movb",IMw), TS("mov",IMw), 2245 /* [C,8] */ TNSyp("enter",ENTER), TNSyp("leave",NORM), TNS("lret",RET), TNS("lret",NORM), 2246 /* [C,C] */ TNS("int",INT3), TNS("int",INTx), TNSx("into",NORM), TNS("iret",NORM), 2247 }, { 2248 /* [D,0] */ IND(dis_opD0), IND(dis_opD1), IND(dis_opD2), IND(dis_opD3), 2249 /* [D,4] */ TNSx("aam",U), TNSx("aad",U), TNSx("falc",NORM), TNSZ("xlat",IMPLMEM,1), 2250 2251 /* 287 instructions. Note that although the indirect field */ 2252 /* indicates opFP1n2 for further decoding, this is not necessarily */ 2253 /* the case since the opFP arrays are not partitioned according to key1 */ 2254 /* and key2. opFP1n2 is given only to indicate that we haven't */ 2255 /* finished decoding the instruction. */ 2256 /* [D,8] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), 2257 /* [D,C] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), 2258 }, { 2259 /* [E,0] */ TNSy("loopnz",BD), TNSy("loopz",BD), TNSy("loop",BD), TNSy("jcxz",BD), 2260 /* [E,4] */ TNS("inb",P), TS("in",P), TNS("outb",P), TS("out",P), 2261 /* [E,8] */ TNSyp("call",D), TNSy("jmp",D), TNSx("ljmp",SO), TNSy("jmp",BD), 2262 /* [E,C] */ TNS("inb",V), TS("in",V), TNS("outb",V), TS("out",V), 2263 }, { 2264 /* [F,0] */ TNS("lock",LOCK), TNS("icebp", NORM), TNS("repnz",PREFIX), TNS("repz",PREFIX), 2265 /* [F,4] */ TNS("hlt",NORM), TNS("cmc",NORM), IND(dis_opF6), IND(dis_opF7), 2266 /* [F,8] */ TNS("clc",NORM), TNS("stc",NORM), TNS("cli",NORM), TNS("sti",NORM), 2267 /* [F,C] */ TNS("cld",NORM), TNS("std",NORM), IND(dis_opFE), IND(dis_opFF), 2268 } }; 2269 2270 /* END CSTYLED */ 2271 2272 /* 2273 * common functions to decode and disassemble an x86 or amd64 instruction 2274 */ 2275 2276 /* 2277 * These are the individual fields of a REX prefix. Note that a REX 2278 * prefix with none of these set is still needed to: 2279 * - use the MOVSXD (sign extend 32 to 64 bits) instruction 2280 * - access the %sil, %dil, %bpl, %spl registers 2281 */ 2282 #define REX_W 0x08 /* 64 bit operand size when set */ 2283 #define REX_R 0x04 /* high order bit extension of ModRM reg field */ 2284 #define REX_X 0x02 /* high order bit extension of SIB index field */ 2285 #define REX_B 0x01 /* extends ModRM r_m, SIB base, or opcode reg */ 2286 2287 /* 2288 * These are the individual fields of a VEX prefix. 2289 */ 2290 #define VEX_R 0x08 /* REX.R in 1's complement form */ 2291 #define VEX_X 0x04 /* REX.X in 1's complement form */ 2292 #define VEX_B 0x02 /* REX.B in 1's complement form */ 2293 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector */ 2294 #define VEX_L 0x04 2295 #define VEX_W 0x08 /* opcode specific, use like REX.W */ 2296 #define VEX_m 0x1F /* VEX m-mmmm field */ 2297 #define VEX_v 0x78 /* VEX register specifier */ 2298 #define VEX_p 0x03 /* VEX pp field, opcode extension */ 2299 2300 /* VEX m-mmmm field, only used by three bytes prefix */ 2301 #define VEX_m_0F 0x01 /* implied 0F leading opcode byte */ 2302 #define VEX_m_0F38 0x02 /* implied 0F 38 leading opcode byte */ 2303 #define VEX_m_0F3A 0x03 /* implied 0F 3A leading opcode byte */ 2304 2305 /* VEX pp field, providing equivalent functionality of a SIMD prefix */ 2306 #define VEX_p_66 0x01 2307 #define VEX_p_F3 0x02 2308 #define VEX_p_F2 0x03 2309 2310 /* 2311 * Even in 64 bit mode, usually only 4 byte immediate operands are supported. 2312 */ 2313 static int isize[] = {1, 2, 4, 4}; 2314 static int isize64[] = {1, 2, 4, 8}; 2315 2316 /* 2317 * Just a bunch of useful macros. 2318 */ 2319 #define WBIT(x) (x & 0x1) /* to get w bit */ 2320 #define REGNO(x) (x & 0x7) /* to get 3 bit register */ 2321 #define VBIT(x) ((x)>>1 & 0x1) /* to get 'v' bit */ 2322 #define OPSIZE(osize, wbit) ((wbit) ? isize[osize] : 1) 2323 #define OPSIZE64(osize, wbit) ((wbit) ? isize64[osize] : 1) 2324 2325 #define REG_ONLY 3 /* mode to indicate a register operand (not memory) */ 2326 2327 #define BYTE_OPND 0 /* w-bit value indicating byte register */ 2328 #define LONG_OPND 1 /* w-bit value indicating opnd_size register */ 2329 #define MM_OPND 2 /* "value" used to indicate a mmx reg */ 2330 #define XMM_OPND 3 /* "value" used to indicate a xmm reg */ 2331 #define SEG_OPND 4 /* "value" used to indicate a segment reg */ 2332 #define CONTROL_OPND 5 /* "value" used to indicate a control reg */ 2333 #define DEBUG_OPND 6 /* "value" used to indicate a debug reg */ 2334 #define TEST_OPND 7 /* "value" used to indicate a test reg */ 2335 #define WORD_OPND 8 /* w-bit value indicating word size reg */ 2336 #define YMM_OPND 9 /* "value" used to indicate a ymm reg */ 2337 #define KOPMASK_OPND 10 /* "value" used to indicate an opmask reg */ 2338 2339 /* 2340 * The AVX2 gather instructions are a bit of a mess. While there's a pattern, 2341 * there's not really a consistent scheme that we can use to know what the mode 2342 * is supposed to be for a given type. Various instructions, like VPGATHERDD, 2343 * always match the value of VEX_L. Other instructions like VPGATHERDQ, have 2344 * some registers match VEX_L, but the VSIB is always XMM. 2345 * 2346 * The simplest way to deal with this is to just define a table based on the 2347 * instruction opcodes, which are 0x90-0x93, so we subtract 0x90 to index into 2348 * them. 2349 * 2350 * We further have to subdivide this based on the value of VEX_W and the value 2351 * of VEX_L. The array is constructed to be indexed as: 2352 * [opcode - 0x90][VEX_W][VEX_L]. 2353 */ 2354 /* w = 0, 0x90 */ 2355 typedef struct dis_gather_regs { 2356 uint_t dgr_arg0; /* src reg */ 2357 uint_t dgr_arg1; /* vsib reg */ 2358 uint_t dgr_arg2; /* dst reg */ 2359 char *dgr_suffix; /* suffix to append */ 2360 } dis_gather_regs_t; 2361 2362 static dis_gather_regs_t dis_vgather[4][2][2] = { 2363 { 2364 /* op 0x90, W.0 */ 2365 { 2366 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2367 { YMM_OPND, YMM_OPND, YMM_OPND, "d" } 2368 }, 2369 /* op 0x90, W.1 */ 2370 { 2371 { XMM_OPND, XMM_OPND, XMM_OPND, "q" }, 2372 { YMM_OPND, XMM_OPND, YMM_OPND, "q" } 2373 } 2374 }, 2375 { 2376 /* op 0x91, W.0 */ 2377 { 2378 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2379 { XMM_OPND, YMM_OPND, XMM_OPND, "d" }, 2380 }, 2381 /* op 0x91, W.1 */ 2382 { 2383 { XMM_OPND, XMM_OPND, XMM_OPND, "q" }, 2384 { YMM_OPND, YMM_OPND, YMM_OPND, "q" }, 2385 } 2386 }, 2387 { 2388 /* op 0x92, W.0 */ 2389 { 2390 { XMM_OPND, XMM_OPND, XMM_OPND, "s" }, 2391 { YMM_OPND, YMM_OPND, YMM_OPND, "s" } 2392 }, 2393 /* op 0x92, W.1 */ 2394 { 2395 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2396 { YMM_OPND, XMM_OPND, YMM_OPND, "d" } 2397 } 2398 }, 2399 { 2400 /* op 0x93, W.0 */ 2401 { 2402 { XMM_OPND, XMM_OPND, XMM_OPND, "s" }, 2403 { XMM_OPND, YMM_OPND, XMM_OPND, "s" } 2404 }, 2405 /* op 0x93, W.1 */ 2406 { 2407 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2408 { YMM_OPND, YMM_OPND, YMM_OPND, "d" } 2409 } 2410 } 2411 }; 2412 2413 /* 2414 * Get the next byte and separate the op code into the high and low nibbles. 2415 */ 2416 static int 2417 dtrace_get_opcode(dis86_t *x, uint_t *high, uint_t *low) 2418 { 2419 int byte; 2420 2421 /* 2422 * x86 instructions have a maximum length of 15 bytes. Bail out if 2423 * we try to read more. 2424 */ 2425 if (x->d86_len >= 15) 2426 return (x->d86_error = 1); 2427 2428 if (x->d86_error) 2429 return (1); 2430 byte = x->d86_get_byte(x->d86_data); 2431 if (byte < 0) 2432 return (x->d86_error = 1); 2433 x->d86_bytes[x->d86_len++] = byte; 2434 *low = byte & 0xf; /* ----xxxx low 4 bits */ 2435 *high = byte >> 4 & 0xf; /* xxxx---- bits 7 to 4 */ 2436 return (0); 2437 } 2438 2439 /* 2440 * Get and decode an SIB (scaled index base) byte 2441 */ 2442 static void 2443 dtrace_get_SIB(dis86_t *x, uint_t *ss, uint_t *index, uint_t *base) 2444 { 2445 int byte; 2446 2447 if (x->d86_error) 2448 return; 2449 2450 byte = x->d86_get_byte(x->d86_data); 2451 if (byte < 0) { 2452 x->d86_error = 1; 2453 return; 2454 } 2455 x->d86_bytes[x->d86_len++] = byte; 2456 2457 *base = byte & 0x7; 2458 *index = (byte >> 3) & 0x7; 2459 *ss = (byte >> 6) & 0x3; 2460 } 2461 2462 /* 2463 * Get the byte following the op code and separate it into the 2464 * mode, register, and r/m fields. 2465 */ 2466 static void 2467 dtrace_get_modrm(dis86_t *x, uint_t *mode, uint_t *reg, uint_t *r_m) 2468 { 2469 if (x->d86_got_modrm == 0) { 2470 if (x->d86_rmindex == -1) 2471 x->d86_rmindex = x->d86_len; 2472 dtrace_get_SIB(x, mode, reg, r_m); 2473 x->d86_got_modrm = 1; 2474 } 2475 } 2476 2477 /* 2478 * Adjust register selection based on any REX prefix bits present. 2479 */ 2480 /*ARGSUSED*/ 2481 static void 2482 dtrace_rex_adjust(uint_t rex_prefix, uint_t mode, uint_t *reg, uint_t *r_m) 2483 { 2484 if (reg != NULL && r_m == NULL) { 2485 if (rex_prefix & REX_B) 2486 *reg += 8; 2487 } else { 2488 if (reg != NULL && (REX_R & rex_prefix) != 0) 2489 *reg += 8; 2490 if (r_m != NULL && (REX_B & rex_prefix) != 0) 2491 *r_m += 8; 2492 } 2493 } 2494 2495 /* 2496 * Adjust register selection based on any VEX prefix bits present. 2497 * Notes: VEX.R, VEX.X and VEX.B use the inverted form compared with REX prefix 2498 */ 2499 /*ARGSUSED*/ 2500 static void 2501 dtrace_vex_adjust(uint_t vex_byte1, uint_t mode, uint_t *reg, uint_t *r_m) 2502 { 2503 if (reg != NULL && r_m == NULL) { 2504 if (!(vex_byte1 & VEX_B)) 2505 *reg += 8; 2506 } else { 2507 if (reg != NULL && ((VEX_R & vex_byte1) == 0)) 2508 *reg += 8; 2509 if (r_m != NULL && ((VEX_B & vex_byte1) == 0)) 2510 *r_m += 8; 2511 } 2512 } 2513 2514 /* 2515 * Get an immediate operand of the given size, with sign extension. 2516 */ 2517 static void 2518 dtrace_imm_opnd(dis86_t *x, int wbit, int size, int opindex) 2519 { 2520 int i; 2521 int byte; 2522 int valsize; 2523 2524 if (x->d86_numopnds < opindex + 1) 2525 x->d86_numopnds = opindex + 1; 2526 2527 switch (wbit) { 2528 case BYTE_OPND: 2529 valsize = 1; 2530 break; 2531 case LONG_OPND: 2532 if (x->d86_opnd_size == SIZE16) 2533 valsize = 2; 2534 else if (x->d86_opnd_size == SIZE32) 2535 valsize = 4; 2536 else 2537 valsize = 8; 2538 break; 2539 case MM_OPND: 2540 case XMM_OPND: 2541 case YMM_OPND: 2542 case SEG_OPND: 2543 case CONTROL_OPND: 2544 case DEBUG_OPND: 2545 case TEST_OPND: 2546 valsize = size; 2547 break; 2548 case WORD_OPND: 2549 valsize = 2; 2550 break; 2551 } 2552 if (valsize < size) 2553 valsize = size; 2554 2555 if (x->d86_error) 2556 return; 2557 x->d86_opnd[opindex].d86_value = 0; 2558 for (i = 0; i < size; ++i) { 2559 byte = x->d86_get_byte(x->d86_data); 2560 if (byte < 0) { 2561 x->d86_error = 1; 2562 return; 2563 } 2564 x->d86_bytes[x->d86_len++] = byte; 2565 x->d86_opnd[opindex].d86_value |= (uint64_t)byte << (i * 8); 2566 } 2567 /* Do sign extension */ 2568 if (x->d86_bytes[x->d86_len - 1] & 0x80) { 2569 for (; i < sizeof (uint64_t); i++) 2570 x->d86_opnd[opindex].d86_value |= 2571 (uint64_t)0xff << (i * 8); 2572 } 2573 #ifdef DIS_TEXT 2574 x->d86_opnd[opindex].d86_mode = MODE_SIGNED; 2575 x->d86_opnd[opindex].d86_value_size = valsize; 2576 x->d86_imm_bytes += size; 2577 #endif 2578 } 2579 2580 /* 2581 * Get an ip relative operand of the given size, with sign extension. 2582 */ 2583 static void 2584 dtrace_disp_opnd(dis86_t *x, int wbit, int size, int opindex) 2585 { 2586 dtrace_imm_opnd(x, wbit, size, opindex); 2587 #ifdef DIS_TEXT 2588 x->d86_opnd[opindex].d86_mode = MODE_IPREL; 2589 #endif 2590 } 2591 2592 /* 2593 * Check to see if there is a segment override prefix pending. 2594 * If so, print it in the current 'operand' location and set 2595 * the override flag back to false. 2596 */ 2597 /*ARGSUSED*/ 2598 static void 2599 dtrace_check_override(dis86_t *x, int opindex) 2600 { 2601 #ifdef DIS_TEXT 2602 if (x->d86_seg_prefix) { 2603 (void) strlcat(x->d86_opnd[opindex].d86_prefix, 2604 x->d86_seg_prefix, PFIXLEN); 2605 } 2606 #endif 2607 x->d86_seg_prefix = NULL; 2608 } 2609 2610 2611 /* 2612 * Process a single instruction Register or Memory operand. 2613 * 2614 * mode = addressing mode from ModRM byte 2615 * r_m = r_m (or reg if mode == 3) field from ModRM byte 2616 * wbit = indicates which register (8bit, 16bit, ... MMX, etc.) set to use. 2617 * o = index of operand that we are processing (0, 1 or 2) 2618 * 2619 * the value of reg or r_m must have already been adjusted for any REX prefix. 2620 */ 2621 /*ARGSUSED*/ 2622 static void 2623 dtrace_get_operand(dis86_t *x, uint_t mode, uint_t r_m, int wbit, int opindex) 2624 { 2625 int have_SIB = 0; /* flag presence of scale-index-byte */ 2626 uint_t ss; /* scale-factor from opcode */ 2627 uint_t index; /* index register number */ 2628 uint_t base; /* base register number */ 2629 int dispsize; /* size of displacement in bytes */ 2630 #ifdef DIS_TEXT 2631 char *opnd = x->d86_opnd[opindex].d86_opnd; 2632 #endif 2633 2634 if (x->d86_numopnds < opindex + 1) 2635 x->d86_numopnds = opindex + 1; 2636 2637 if (x->d86_error) 2638 return; 2639 2640 /* 2641 * first handle a simple register 2642 */ 2643 if (mode == REG_ONLY) { 2644 #ifdef DIS_TEXT 2645 switch (wbit) { 2646 case MM_OPND: 2647 (void) strlcat(opnd, dis_MMREG[r_m], OPLEN); 2648 break; 2649 case XMM_OPND: 2650 (void) strlcat(opnd, dis_XMMREG[r_m], OPLEN); 2651 break; 2652 case YMM_OPND: 2653 (void) strlcat(opnd, dis_YMMREG[r_m], OPLEN); 2654 break; 2655 case KOPMASK_OPND: 2656 (void) strlcat(opnd, dis_KOPMASKREG[r_m], OPLEN); 2657 break; 2658 case SEG_OPND: 2659 (void) strlcat(opnd, dis_SEGREG[r_m], OPLEN); 2660 break; 2661 case CONTROL_OPND: 2662 (void) strlcat(opnd, dis_CONTROLREG[r_m], OPLEN); 2663 break; 2664 case DEBUG_OPND: 2665 (void) strlcat(opnd, dis_DEBUGREG[r_m], OPLEN); 2666 break; 2667 case TEST_OPND: 2668 (void) strlcat(opnd, dis_TESTREG[r_m], OPLEN); 2669 break; 2670 case BYTE_OPND: 2671 if (x->d86_rex_prefix == 0) 2672 (void) strlcat(opnd, dis_REG8[r_m], OPLEN); 2673 else 2674 (void) strlcat(opnd, dis_REG8_REX[r_m], OPLEN); 2675 break; 2676 case WORD_OPND: 2677 (void) strlcat(opnd, dis_REG16[r_m], OPLEN); 2678 break; 2679 case LONG_OPND: 2680 if (x->d86_opnd_size == SIZE16) 2681 (void) strlcat(opnd, dis_REG16[r_m], OPLEN); 2682 else if (x->d86_opnd_size == SIZE32) 2683 (void) strlcat(opnd, dis_REG32[r_m], OPLEN); 2684 else 2685 (void) strlcat(opnd, dis_REG64[r_m], OPLEN); 2686 break; 2687 } 2688 #endif /* DIS_TEXT */ 2689 return; 2690 } 2691 2692 /* 2693 * if symbolic representation, skip override prefix, if any 2694 */ 2695 dtrace_check_override(x, opindex); 2696 2697 /* 2698 * Handle 16 bit memory references first, since they decode 2699 * the mode values more simply. 2700 * mode 1 is r_m + 8 bit displacement 2701 * mode 2 is r_m + 16 bit displacement 2702 * mode 0 is just r_m, unless r_m is 6 which is 16 bit disp 2703 */ 2704 if (x->d86_addr_size == SIZE16) { 2705 if ((mode == 0 && r_m == 6) || mode == 2) 2706 dtrace_imm_opnd(x, WORD_OPND, 2, opindex); 2707 else if (mode == 1) 2708 dtrace_imm_opnd(x, BYTE_OPND, 1, opindex); 2709 #ifdef DIS_TEXT 2710 if (mode == 0 && r_m == 6) 2711 x->d86_opnd[opindex].d86_mode = MODE_SIGNED; 2712 else if (mode == 0) 2713 x->d86_opnd[opindex].d86_mode = MODE_NONE; 2714 else 2715 x->d86_opnd[opindex].d86_mode = MODE_OFFSET; 2716 (void) strlcat(opnd, dis_addr16[mode][r_m], OPLEN); 2717 #endif 2718 return; 2719 } 2720 2721 /* 2722 * 32 and 64 bit addressing modes are more complex since they 2723 * can involve an SIB (scaled index and base) byte to decode. 2724 */ 2725 if (r_m == ESP_REGNO || r_m == ESP_REGNO + 8) { 2726 have_SIB = 1; 2727 dtrace_get_SIB(x, &ss, &index, &base); 2728 if (x->d86_error) 2729 return; 2730 if (base != 5 || mode != 0) 2731 if (x->d86_rex_prefix & REX_B) 2732 base += 8; 2733 if (x->d86_rex_prefix & REX_X) 2734 index += 8; 2735 } else { 2736 base = r_m; 2737 } 2738 2739 /* 2740 * Compute the displacement size and get its bytes 2741 */ 2742 dispsize = 0; 2743 2744 if (mode == 1) 2745 dispsize = 1; 2746 else if (mode == 2) 2747 dispsize = 4; 2748 else if ((r_m & 7) == EBP_REGNO || 2749 (have_SIB && (base & 7) == EBP_REGNO)) 2750 dispsize = 4; 2751 2752 if (dispsize > 0) { 2753 dtrace_imm_opnd(x, dispsize == 4 ? LONG_OPND : BYTE_OPND, 2754 dispsize, opindex); 2755 if (x->d86_error) 2756 return; 2757 } 2758 2759 #ifdef DIS_TEXT 2760 if (dispsize > 0) 2761 x->d86_opnd[opindex].d86_mode = MODE_OFFSET; 2762 2763 if (have_SIB == 0) { 2764 if (x->d86_mode == SIZE32) { 2765 if (mode == 0) 2766 (void) strlcat(opnd, dis_addr32_mode0[r_m], 2767 OPLEN); 2768 else 2769 (void) strlcat(opnd, dis_addr32_mode12[r_m], 2770 OPLEN); 2771 } else { 2772 if (mode == 0) { 2773 (void) strlcat(opnd, dis_addr64_mode0[r_m], 2774 OPLEN); 2775 if (r_m == 5) { 2776 x->d86_opnd[opindex].d86_mode = 2777 MODE_RIPREL; 2778 } 2779 } else { 2780 (void) strlcat(opnd, dis_addr64_mode12[r_m], 2781 OPLEN); 2782 } 2783 } 2784 } else { 2785 uint_t need_paren = 0; 2786 char **regs; 2787 char **bregs; 2788 const char *const *sf; 2789 if (x->d86_mode == SIZE32) /* NOTE this is not addr_size! */ 2790 regs = (char **)dis_REG32; 2791 else 2792 regs = (char **)dis_REG64; 2793 2794 if (x->d86_vsib != 0) { 2795 if (wbit == YMM_OPND) /* NOTE this is not addr_size! */ 2796 bregs = (char **)dis_YMMREG; 2797 else 2798 bregs = (char **)dis_XMMREG; 2799 sf = dis_vscale_factor; 2800 } else { 2801 bregs = regs; 2802 sf = dis_scale_factor; 2803 } 2804 2805 /* 2806 * print the base (if any) 2807 */ 2808 if (base == EBP_REGNO && mode == 0) { 2809 if (index != ESP_REGNO || x->d86_vsib != 0) { 2810 (void) strlcat(opnd, "(", OPLEN); 2811 need_paren = 1; 2812 } 2813 } else { 2814 (void) strlcat(opnd, "(", OPLEN); 2815 (void) strlcat(opnd, regs[base], OPLEN); 2816 need_paren = 1; 2817 } 2818 2819 /* 2820 * print the index (if any) 2821 */ 2822 if (index != ESP_REGNO || x->d86_vsib) { 2823 (void) strlcat(opnd, ",", OPLEN); 2824 (void) strlcat(opnd, bregs[index], OPLEN); 2825 (void) strlcat(opnd, sf[ss], OPLEN); 2826 } else 2827 if (need_paren) 2828 (void) strlcat(opnd, ")", OPLEN); 2829 } 2830 #endif 2831 } 2832 2833 /* 2834 * Operand sequence for standard instruction involving one register 2835 * and one register/memory operand. 2836 * wbit indicates a byte(0) or opnd_size(1) operation 2837 * vbit indicates direction (0 for "opcode r,r_m") or (1 for "opcode r_m, r") 2838 */ 2839 #define STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, vbit) { \ 2840 dtrace_get_modrm(x, &mode, ®, &r_m); \ 2841 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 2842 dtrace_get_operand(x, mode, r_m, wbit, vbit); \ 2843 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1 - vbit); \ 2844 } 2845 2846 /* 2847 * Similar to above, but allows for the two operands to be of different 2848 * classes (ie. wbit). 2849 * wbit is for the r_m operand 2850 * w2 is for the reg operand 2851 */ 2852 #define MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, w2, vbit) { \ 2853 dtrace_get_modrm(x, &mode, ®, &r_m); \ 2854 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 2855 dtrace_get_operand(x, mode, r_m, wbit, vbit); \ 2856 dtrace_get_operand(x, REG_ONLY, reg, w2, 1 - vbit); \ 2857 } 2858 2859 /* 2860 * Similar, but for 2 operands plus an immediate. 2861 * vbit indicates direction 2862 * 0 for "opcode imm, r, r_m" or 2863 * 1 for "opcode imm, r_m, r" 2864 */ 2865 #define THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize, vbit) { \ 2866 dtrace_get_modrm(x, &mode, ®, &r_m); \ 2867 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 2868 dtrace_get_operand(x, mode, r_m, wbit, 2-vbit); \ 2869 dtrace_get_operand(x, REG_ONLY, reg, w2, 1+vbit); \ 2870 dtrace_imm_opnd(x, wbit, immsize, 0); \ 2871 } 2872 2873 /* 2874 * Similar, but for 2 operands plus two immediates. 2875 */ 2876 #define FOUROPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize) { \ 2877 dtrace_get_modrm(x, &mode, ®, &r_m); \ 2878 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 2879 dtrace_get_operand(x, mode, r_m, wbit, 2); \ 2880 dtrace_get_operand(x, REG_ONLY, reg, w2, 3); \ 2881 dtrace_imm_opnd(x, wbit, immsize, 1); \ 2882 dtrace_imm_opnd(x, wbit, immsize, 0); \ 2883 } 2884 2885 /* 2886 * 1 operands plus two immediates. 2887 */ 2888 #define ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, wbit, immsize) { \ 2889 dtrace_get_modrm(x, &mode, ®, &r_m); \ 2890 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 2891 dtrace_get_operand(x, mode, r_m, wbit, 2); \ 2892 dtrace_imm_opnd(x, wbit, immsize, 1); \ 2893 dtrace_imm_opnd(x, wbit, immsize, 0); \ 2894 } 2895 2896 /* 2897 * Dissassemble a single x86 or amd64 instruction. 2898 * 2899 * Mode determines the default operating mode (SIZE16, SIZE32 or SIZE64) 2900 * for interpreting instructions. 2901 * 2902 * returns non-zero for bad opcode 2903 */ 2904 int 2905 dtrace_disx86(dis86_t *x, uint_t cpu_mode) 2906 { 2907 instable_t *dp; /* decode table being used */ 2908 #ifdef DIS_TEXT 2909 uint_t i; 2910 #endif 2911 #ifdef DIS_MEM 2912 uint_t nomem = 0; 2913 #define NOMEM (nomem = 1) 2914 #else 2915 #define NOMEM /* nothing */ 2916 #endif 2917 uint_t opnd_size; /* SIZE16, SIZE32 or SIZE64 */ 2918 uint_t addr_size; /* SIZE16, SIZE32 or SIZE64 */ 2919 uint_t wbit; /* opcode wbit, 0 is 8 bit, !0 for opnd_size */ 2920 uint_t w2; /* wbit value for second operand */ 2921 uint_t vbit; 2922 uint_t mode = 0; /* mode value from ModRM byte */ 2923 uint_t reg; /* reg value from ModRM byte */ 2924 uint_t r_m; /* r_m value from ModRM byte */ 2925 2926 uint_t opcode1; /* high nibble of 1st byte */ 2927 uint_t opcode2; /* low nibble of 1st byte */ 2928 uint_t opcode3; /* extra opcode bits usually from ModRM byte */ 2929 uint_t opcode4; /* high nibble of 2nd byte */ 2930 uint_t opcode5; /* low nibble of 2nd byte */ 2931 uint_t opcode6; /* high nibble of 3rd byte */ 2932 uint_t opcode7; /* low nibble of 3rd byte */ 2933 uint_t opcode_bytes = 1; 2934 2935 /* 2936 * legacy prefixes come in 5 flavors, you should have only one of each 2937 */ 2938 uint_t opnd_size_prefix = 0; 2939 uint_t addr_size_prefix = 0; 2940 uint_t segment_prefix = 0; 2941 uint_t lock_prefix = 0; 2942 uint_t rep_prefix = 0; 2943 uint_t rex_prefix = 0; /* amd64 register extension prefix */ 2944 2945 /* 2946 * Intel VEX instruction encoding prefix and fields 2947 */ 2948 2949 /* 0xC4 means 3 bytes prefix, 0xC5 means 2 bytes prefix */ 2950 uint_t vex_prefix = 0; 2951 2952 /* 2953 * VEX prefix byte 1, includes vex.r, vex.x and vex.b 2954 * (for 3 bytes prefix) 2955 */ 2956 uint_t vex_byte1 = 0; 2957 2958 /* 2959 * For 32-bit mode, it should prefetch the next byte to 2960 * distinguish between AVX and les/lds 2961 */ 2962 uint_t vex_prefetch = 0; 2963 2964 uint_t vex_m = 0; 2965 uint_t vex_v = 0; 2966 uint_t vex_p = 0; 2967 uint_t vex_R = 1; 2968 uint_t vex_X = 1; 2969 uint_t vex_B = 1; 2970 uint_t vex_W = 0; 2971 uint_t vex_L; 2972 dis_gather_regs_t *vreg; 2973 2974 #ifdef DIS_TEXT 2975 /* Instruction name for BLS* family of instructions */ 2976 char *blsinstr; 2977 #endif 2978 2979 size_t off; 2980 2981 instable_t dp_mmx; 2982 2983 x->d86_len = 0; 2984 x->d86_rmindex = -1; 2985 x->d86_error = 0; 2986 #ifdef DIS_TEXT 2987 x->d86_numopnds = 0; 2988 x->d86_seg_prefix = NULL; 2989 x->d86_mnem[0] = 0; 2990 for (i = 0; i < 4; ++i) { 2991 x->d86_opnd[i].d86_opnd[0] = 0; 2992 x->d86_opnd[i].d86_prefix[0] = 0; 2993 x->d86_opnd[i].d86_value_size = 0; 2994 x->d86_opnd[i].d86_value = 0; 2995 x->d86_opnd[i].d86_mode = MODE_NONE; 2996 } 2997 #endif 2998 x->d86_rex_prefix = 0; 2999 x->d86_got_modrm = 0; 3000 x->d86_memsize = 0; 3001 x->d86_vsib = 0; 3002 3003 if (cpu_mode == SIZE16) { 3004 opnd_size = SIZE16; 3005 addr_size = SIZE16; 3006 } else if (cpu_mode == SIZE32) { 3007 opnd_size = SIZE32; 3008 addr_size = SIZE32; 3009 } else { 3010 opnd_size = SIZE32; 3011 addr_size = SIZE64; 3012 } 3013 3014 /* 3015 * Get one opcode byte and check for zero padding that follows 3016 * jump tables. 3017 */ 3018 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3019 goto error; 3020 3021 if (opcode1 == 0 && opcode2 == 0 && 3022 x->d86_check_func != NULL && x->d86_check_func(x->d86_data)) { 3023 #ifdef DIS_TEXT 3024 (void) strncpy(x->d86_mnem, ".byte\t0", OPLEN); 3025 #endif 3026 goto done; 3027 } 3028 3029 /* 3030 * Gather up legacy x86 prefix bytes. 3031 */ 3032 for (;;) { 3033 uint_t *which_prefix = NULL; 3034 3035 dp = (instable_t *)&dis_distable[opcode1][opcode2]; 3036 3037 switch (dp->it_adrmode) { 3038 case PREFIX: 3039 which_prefix = &rep_prefix; 3040 break; 3041 case LOCK: 3042 which_prefix = &lock_prefix; 3043 break; 3044 case OVERRIDE: 3045 which_prefix = &segment_prefix; 3046 #ifdef DIS_TEXT 3047 x->d86_seg_prefix = (char *)dp->it_name; 3048 #endif 3049 if (dp->it_invalid64 && cpu_mode == SIZE64) 3050 goto error; 3051 break; 3052 case AM: 3053 which_prefix = &addr_size_prefix; 3054 break; 3055 case DM: 3056 which_prefix = &opnd_size_prefix; 3057 break; 3058 } 3059 if (which_prefix == NULL) 3060 break; 3061 *which_prefix = (opcode1 << 4) | opcode2; 3062 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3063 goto error; 3064 } 3065 3066 /* 3067 * Handle amd64 mode PREFIX values. 3068 * Some of the segment prefixes are no-ops. (only FS/GS actually work) 3069 * We might have a REX prefix (opcodes 0x40-0x4f) 3070 */ 3071 if (cpu_mode == SIZE64) { 3072 if (segment_prefix != 0x64 && segment_prefix != 0x65) 3073 segment_prefix = 0; 3074 3075 if (opcode1 == 0x4) { 3076 rex_prefix = (opcode1 << 4) | opcode2; 3077 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3078 goto error; 3079 dp = (instable_t *)&dis_distable[opcode1][opcode2]; 3080 } else if (opcode1 == 0xC && 3081 (opcode2 == 0x4 || opcode2 == 0x5)) { 3082 /* AVX instructions */ 3083 vex_prefix = (opcode1 << 4) | opcode2; 3084 x->d86_rex_prefix = 0x40; 3085 } 3086 } else if (opcode1 == 0xC && (opcode2 == 0x4 || opcode2 == 0x5)) { 3087 /* LDS, LES or AVX */ 3088 dtrace_get_modrm(x, &mode, ®, &r_m); 3089 vex_prefetch = 1; 3090 3091 if (mode == REG_ONLY) { 3092 /* AVX */ 3093 vex_prefix = (opcode1 << 4) | opcode2; 3094 x->d86_rex_prefix = 0x40; 3095 opcode3 = (((mode << 3) | reg)>>1) & 0x0F; 3096 opcode4 = ((reg << 3) | r_m) & 0x0F; 3097 } 3098 } 3099 3100 if (vex_prefix == VEX_2bytes) { 3101 if (!vex_prefetch) { 3102 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0) 3103 goto error; 3104 } 3105 vex_R = ((opcode3 & VEX_R) & 0x0F) >> 3; 3106 vex_L = ((opcode4 & VEX_L) & 0x0F) >> 2; 3107 vex_v = (((opcode3 << 4) | opcode4) & VEX_v) >> 3; 3108 vex_p = opcode4 & VEX_p; 3109 /* 3110 * The vex.x and vex.b bits are not defined in two bytes 3111 * mode vex prefix, their default values are 1 3112 */ 3113 vex_byte1 = (opcode3 & VEX_R) | VEX_X | VEX_B; 3114 3115 if (vex_R == 0) 3116 x->d86_rex_prefix |= REX_R; 3117 3118 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3119 goto error; 3120 3121 switch (vex_p) { 3122 case VEX_p_66: 3123 dp = (instable_t *) 3124 &dis_opAVX660F[(opcode1 << 4) | opcode2]; 3125 break; 3126 case VEX_p_F3: 3127 dp = (instable_t *) 3128 &dis_opAVXF30F[(opcode1 << 4) | opcode2]; 3129 break; 3130 case VEX_p_F2: 3131 dp = (instable_t *) 3132 &dis_opAVXF20F [(opcode1 << 4) | opcode2]; 3133 break; 3134 default: 3135 dp = (instable_t *) 3136 &dis_opAVX0F[opcode1][opcode2]; 3137 3138 } 3139 3140 } else if (vex_prefix == VEX_3bytes) { 3141 if (!vex_prefetch) { 3142 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0) 3143 goto error; 3144 } 3145 vex_R = (opcode3 & VEX_R) >> 3; 3146 vex_X = (opcode3 & VEX_X) >> 2; 3147 vex_B = (opcode3 & VEX_B) >> 1; 3148 vex_m = (((opcode3 << 4) | opcode4) & VEX_m); 3149 vex_byte1 = opcode3 & (VEX_R | VEX_X | VEX_B); 3150 3151 if (vex_R == 0) 3152 x->d86_rex_prefix |= REX_R; 3153 if (vex_X == 0) 3154 x->d86_rex_prefix |= REX_X; 3155 if (vex_B == 0) 3156 x->d86_rex_prefix |= REX_B; 3157 3158 if (dtrace_get_opcode(x, &opcode5, &opcode6) != 0) 3159 goto error; 3160 vex_W = (opcode5 & VEX_W) >> 3; 3161 vex_L = (opcode6 & VEX_L) >> 2; 3162 vex_v = (((opcode5 << 4) | opcode6) & VEX_v) >> 3; 3163 vex_p = opcode6 & VEX_p; 3164 3165 if (vex_W) 3166 x->d86_rex_prefix |= REX_W; 3167 3168 /* Only these three vex_m values valid; others are reserved */ 3169 if ((vex_m != VEX_m_0F) && (vex_m != VEX_m_0F38) && 3170 (vex_m != VEX_m_0F3A)) 3171 goto error; 3172 3173 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3174 goto error; 3175 3176 switch (vex_p) { 3177 case VEX_p_66: 3178 if (vex_m == VEX_m_0F) { 3179 dp = (instable_t *) 3180 &dis_opAVX660F 3181 [(opcode1 << 4) | opcode2]; 3182 } else if (vex_m == VEX_m_0F38) { 3183 dp = (instable_t *) 3184 &dis_opAVX660F38 3185 [(opcode1 << 4) | opcode2]; 3186 } else if (vex_m == VEX_m_0F3A) { 3187 dp = (instable_t *) 3188 &dis_opAVX660F3A 3189 [(opcode1 << 4) | opcode2]; 3190 } else { 3191 goto error; 3192 } 3193 break; 3194 case VEX_p_F3: 3195 if (vex_m == VEX_m_0F) { 3196 dp = (instable_t *) 3197 &dis_opAVXF30F 3198 [(opcode1 << 4) | opcode2]; 3199 } else if (vex_m == VEX_m_0F38) { 3200 dp = (instable_t *) 3201 &dis_opAVXF30F38 3202 [(opcode1 << 4) | opcode2]; 3203 } else { 3204 goto error; 3205 } 3206 break; 3207 case VEX_p_F2: 3208 if (vex_m == VEX_m_0F) { 3209 dp = (instable_t *) 3210 &dis_opAVXF20F 3211 [(opcode1 << 4) | opcode2]; 3212 } else if (vex_m == VEX_m_0F3A) { 3213 dp = (instable_t *) 3214 &dis_opAVXF20F3A 3215 [(opcode1 << 4) | opcode2]; 3216 } else if (vex_m == VEX_m_0F38) { 3217 dp = (instable_t *) 3218 &dis_opAVXF20F38 3219 [(opcode1 << 4) | opcode2]; 3220 } else { 3221 goto error; 3222 } 3223 break; 3224 default: 3225 dp = (instable_t *) 3226 &dis_opAVX0F[opcode1][opcode2]; 3227 3228 } 3229 } 3230 if (vex_prefix) { 3231 if (dp->it_vexwoxmm) { 3232 wbit = LONG_OPND; 3233 } else if (dp->it_vexopmask) { 3234 wbit = KOPMASK_OPND; 3235 } else { 3236 if (vex_L) { 3237 wbit = YMM_OPND; 3238 } else { 3239 wbit = XMM_OPND; 3240 } 3241 } 3242 } 3243 3244 /* 3245 * Deal with selection of operand and address size now. 3246 * Note that the REX.W bit being set causes opnd_size_prefix to be 3247 * ignored. 3248 */ 3249 if (cpu_mode == SIZE64) { 3250 if ((rex_prefix & REX_W) || vex_W) 3251 opnd_size = SIZE64; 3252 else if (opnd_size_prefix) 3253 opnd_size = SIZE16; 3254 3255 if (addr_size_prefix) 3256 addr_size = SIZE32; 3257 } else if (cpu_mode == SIZE32) { 3258 if (opnd_size_prefix) 3259 opnd_size = SIZE16; 3260 if (addr_size_prefix) 3261 addr_size = SIZE16; 3262 } else { 3263 if (opnd_size_prefix) 3264 opnd_size = SIZE32; 3265 if (addr_size_prefix) 3266 addr_size = SIZE32; 3267 } 3268 /* 3269 * The pause instruction - a repz'd nop. This doesn't fit 3270 * with any of the other prefix goop added for SSE, so we'll 3271 * special-case it here. 3272 */ 3273 if (rep_prefix == 0xf3 && opcode1 == 0x9 && opcode2 == 0x0) { 3274 rep_prefix = 0; 3275 dp = (instable_t *)&dis_opPause; 3276 } 3277 3278 /* 3279 * Some 386 instructions have 2 bytes of opcode before the mod_r/m 3280 * byte so we may need to perform a table indirection. 3281 */ 3282 if (dp->it_indirect == (instable_t *)dis_op0F) { 3283 if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0) 3284 goto error; 3285 opcode_bytes = 2; 3286 if (opcode4 == 0x7 && opcode5 >= 0x1 && opcode5 <= 0x3) { 3287 uint_t subcode; 3288 3289 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 3290 goto error; 3291 opcode_bytes = 3; 3292 subcode = ((opcode6 & 0x3) << 1) | 3293 ((opcode7 & 0x8) >> 3); 3294 dp = (instable_t *)&dis_op0F7123[opcode5][subcode]; 3295 } else if ((opcode4 == 0xc) && (opcode5 >= 0x8)) { 3296 dp = (instable_t *)&dis_op0FC8[0]; 3297 } else if ((opcode4 == 0x3) && (opcode5 == 0xA)) { 3298 opcode_bytes = 3; 3299 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 3300 goto error; 3301 if (opnd_size == SIZE16) 3302 opnd_size = SIZE32; 3303 3304 dp = (instable_t *)&dis_op0F3A[(opcode6<<4)|opcode7]; 3305 #ifdef DIS_TEXT 3306 if (strcmp(dp->it_name, "INVALID") == 0) 3307 goto error; 3308 #endif 3309 switch (dp->it_adrmode) { 3310 case XMMP: 3311 break; 3312 case XMMP_66r: 3313 case XMMPRM_66r: 3314 case XMM3PM_66r: 3315 if (opnd_size_prefix == 0) { 3316 goto error; 3317 } 3318 3319 break; 3320 case XMMP_66o: 3321 if (opnd_size_prefix == 0) { 3322 /* SSSE3 MMX instructions */ 3323 dp_mmx = *dp; 3324 dp = &dp_mmx; 3325 dp->it_adrmode = MMOPM_66o; 3326 #ifdef DIS_MEM 3327 dp->it_size = 8; 3328 #endif 3329 } 3330 break; 3331 default: 3332 goto error; 3333 } 3334 } else if ((opcode4 == 0x3) && (opcode5 == 0x8)) { 3335 opcode_bytes = 3; 3336 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 3337 goto error; 3338 dp = (instable_t *)&dis_op0F38[(opcode6<<4)|opcode7]; 3339 3340 /* 3341 * Both crc32 and movbe have the same 3rd opcode 3342 * byte of either 0xF0 or 0xF1, so we use another 3343 * indirection to distinguish between the two. 3344 */ 3345 if (dp->it_indirect == (instable_t *)dis_op0F38F0 || 3346 dp->it_indirect == (instable_t *)dis_op0F38F1) { 3347 3348 dp = dp->it_indirect; 3349 if (rep_prefix != 0xF2) { 3350 /* It is movbe */ 3351 dp++; 3352 } 3353 } 3354 3355 /* 3356 * The adx family of instructions (adcx and adox) 3357 * continue the classic Intel tradition of abusing 3358 * arbitrary prefixes without actually meaning the 3359 * prefix bit. Therefore, if we find either the 3360 * opnd_size_prefix or rep_prefix we end up zeroing it 3361 * out after making our determination so as to ensure 3362 * that we don't get confused and accidentally print 3363 * repz prefixes and the like on these instructions. 3364 * 3365 * In addition, these instructions are actually much 3366 * closer to AVX instructions in semantics. Importantly, 3367 * they always default to having 32-bit operands. 3368 * However, if the CPU is in 64-bit mode, then and only 3369 * then, does it use REX.w promotes things to 64-bits 3370 * and REX.r allows 64-bit mode to use register r8-r15. 3371 */ 3372 if (dp->it_indirect == (instable_t *)dis_op0F38F6) { 3373 dp = dp->it_indirect; 3374 if (opnd_size_prefix == 0 && 3375 rep_prefix == 0xf3) { 3376 /* It is adox */ 3377 dp++; 3378 } else if (opnd_size_prefix != 0x66 && 3379 rep_prefix != 0) { 3380 /* It isn't adcx */ 3381 goto error; 3382 } 3383 opnd_size_prefix = 0; 3384 rep_prefix = 0; 3385 opnd_size = SIZE32; 3386 if (rex_prefix & REX_W) 3387 opnd_size = SIZE64; 3388 } 3389 3390 #ifdef DIS_TEXT 3391 if (strcmp(dp->it_name, "INVALID") == 0) 3392 goto error; 3393 #endif 3394 switch (dp->it_adrmode) { 3395 case ADX: 3396 case XMM: 3397 break; 3398 case RM_66r: 3399 case XMM_66r: 3400 case XMMM_66r: 3401 if (opnd_size_prefix == 0) { 3402 goto error; 3403 } 3404 break; 3405 case XMM_66o: 3406 if (opnd_size_prefix == 0) { 3407 /* SSSE3 MMX instructions */ 3408 dp_mmx = *dp; 3409 dp = &dp_mmx; 3410 dp->it_adrmode = MM; 3411 #ifdef DIS_MEM 3412 dp->it_size = 8; 3413 #endif 3414 } 3415 break; 3416 case CRC32: 3417 if (rep_prefix != 0xF2) { 3418 goto error; 3419 } 3420 rep_prefix = 0; 3421 break; 3422 case MOVBE: 3423 if (rep_prefix != 0x0) { 3424 goto error; 3425 } 3426 break; 3427 default: 3428 goto error; 3429 } 3430 } else { 3431 dp = (instable_t *)&dis_op0F[opcode4][opcode5]; 3432 } 3433 } 3434 3435 /* 3436 * If still not at a TERM decode entry, then a ModRM byte 3437 * exists and its fields further decode the instruction. 3438 */ 3439 x->d86_got_modrm = 0; 3440 if (dp->it_indirect != TERM) { 3441 dtrace_get_modrm(x, &mode, &opcode3, &r_m); 3442 if (x->d86_error) 3443 goto error; 3444 reg = opcode3; 3445 3446 /* 3447 * decode 287 instructions (D8-DF) from opcodeN 3448 */ 3449 if (opcode1 == 0xD && opcode2 >= 0x8) { 3450 if (opcode2 == 0xB && mode == 0x3 && opcode3 == 4) 3451 dp = (instable_t *)&dis_opFP5[r_m]; 3452 else if (opcode2 == 0xA && mode == 0x3 && opcode3 < 4) 3453 dp = (instable_t *)&dis_opFP7[opcode3]; 3454 else if (opcode2 == 0xB && mode == 0x3) 3455 dp = (instable_t *)&dis_opFP6[opcode3]; 3456 else if (opcode2 == 0x9 && mode == 0x3 && opcode3 >= 4) 3457 dp = (instable_t *)&dis_opFP4[opcode3 - 4][r_m]; 3458 else if (mode == 0x3) 3459 dp = (instable_t *) 3460 &dis_opFP3[opcode2 - 8][opcode3]; 3461 else 3462 dp = (instable_t *) 3463 &dis_opFP1n2[opcode2 - 8][opcode3]; 3464 } else { 3465 dp = (instable_t *)dp->it_indirect + opcode3; 3466 } 3467 } 3468 3469 /* 3470 * In amd64 bit mode, ARPL opcode is changed to MOVSXD 3471 * (sign extend 32bit to 64 bit) 3472 */ 3473 if ((vex_prefix == 0) && cpu_mode == SIZE64 && 3474 opcode1 == 0x6 && opcode2 == 0x3) 3475 dp = (instable_t *)&dis_opMOVSLD; 3476 3477 /* 3478 * at this point we should have a correct (or invalid) opcode 3479 */ 3480 if (cpu_mode == SIZE64 && dp->it_invalid64 || 3481 cpu_mode != SIZE64 && dp->it_invalid32) 3482 goto error; 3483 if (dp->it_indirect != TERM) 3484 goto error; 3485 3486 /* 3487 * Deal with MMX/SSE opcodes which are changed by prefixes. Note, we do 3488 * need to include UNKNOWN below, as we may have instructions that 3489 * actually have a prefix, but don't exist in any other form. 3490 */ 3491 switch (dp->it_adrmode) { 3492 case UNKNOWN: 3493 case MMO: 3494 case MMOIMPL: 3495 case MMO3P: 3496 case MMOM3: 3497 case MMOMS: 3498 case MMOPM: 3499 case MMOPRM: 3500 case MMOS: 3501 case XMMO: 3502 case XMMOM: 3503 case XMMOMS: 3504 case XMMOPM: 3505 case XMMOS: 3506 case XMMOMX: 3507 case XMMOX3: 3508 case XMMOXMM: 3509 /* 3510 * This is horrible. Some SIMD instructions take the 3511 * form 0x0F 0x?? ..., which is easily decoded using the 3512 * existing tables. Other SIMD instructions use various 3513 * prefix bytes to overload existing instructions. For 3514 * Example, addps is F0, 58, whereas addss is F3 (repz), 3515 * F0, 58. Presumably someone got a raise for this. 3516 * 3517 * If we see one of the instructions which can be 3518 * modified in this way (if we've got one of the SIMDO* 3519 * address modes), we'll check to see if the last prefix 3520 * was a repz. If it was, we strip the prefix from the 3521 * mnemonic, and we indirect using the dis_opSIMDrepz 3522 * table. 3523 */ 3524 3525 /* 3526 * Calculate our offset in dis_op0F 3527 */ 3528 if ((uintptr_t)dp - (uintptr_t)dis_op0F > sizeof (dis_op0F)) 3529 goto error; 3530 3531 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) / 3532 sizeof (instable_t); 3533 3534 /* 3535 * Rewrite if this instruction used one of the magic prefixes. 3536 */ 3537 if (rep_prefix) { 3538 if (rep_prefix == 0xf2) 3539 dp = (instable_t *)&dis_opSIMDrepnz[off]; 3540 else 3541 dp = (instable_t *)&dis_opSIMDrepz[off]; 3542 rep_prefix = 0; 3543 } else if (opnd_size_prefix) { 3544 dp = (instable_t *)&dis_opSIMDdata16[off]; 3545 opnd_size_prefix = 0; 3546 if (opnd_size == SIZE16) 3547 opnd_size = SIZE32; 3548 } 3549 break; 3550 3551 case MG9: 3552 /* 3553 * More horribleness: the group 9 (0xF0 0xC7) instructions are 3554 * allowed an optional prefix of 0x66 or 0xF3. This is similar 3555 * to the SIMD business described above, but with a different 3556 * addressing mode (and an indirect table), so we deal with it 3557 * separately (if similarly). 3558 * 3559 * Intel further complicated this with the release of Ivy Bridge 3560 * where they overloaded these instructions based on the ModR/M 3561 * bytes. The VMX instructions have a mode of 0 since they are 3562 * memory instructions but rdrand instructions have a mode of 3563 * 0b11 (REG_ONLY) because they only operate on registers. While 3564 * there are different prefix formats, for now it is sufficient 3565 * to use a single different table. 3566 */ 3567 3568 /* 3569 * Calculate our offset in dis_op0FC7 (the group 9 table) 3570 */ 3571 if ((uintptr_t)dp - (uintptr_t)dis_op0FC7 > sizeof (dis_op0FC7)) 3572 goto error; 3573 3574 off = ((uintptr_t)dp - (uintptr_t)dis_op0FC7) / 3575 sizeof (instable_t); 3576 3577 /* 3578 * If we have a mode of 0b11 then we have to rewrite this. 3579 */ 3580 dtrace_get_modrm(x, &mode, ®, &r_m); 3581 if (mode == REG_ONLY) { 3582 dp = (instable_t *)&dis_op0FC7m3[off]; 3583 break; 3584 } 3585 3586 /* 3587 * Rewrite if this instruction used one of the magic prefixes. 3588 */ 3589 if (rep_prefix) { 3590 if (rep_prefix == 0xf3) 3591 dp = (instable_t *)&dis_opF30FC7[off]; 3592 else 3593 goto error; 3594 rep_prefix = 0; 3595 } else if (opnd_size_prefix) { 3596 dp = (instable_t *)&dis_op660FC7[off]; 3597 opnd_size_prefix = 0; 3598 if (opnd_size == SIZE16) 3599 opnd_size = SIZE32; 3600 } else if (reg == 4 || reg == 5) { 3601 /* 3602 * We have xsavec (4) or xsaves (5), so rewrite. 3603 */ 3604 dp = (instable_t *)&dis_op0FC7[reg]; 3605 break; 3606 } 3607 break; 3608 3609 3610 case MMOSH: 3611 /* 3612 * As with the "normal" SIMD instructions, the MMX 3613 * shuffle instructions are overloaded. These 3614 * instructions, however, are special in that they use 3615 * an extra byte, and thus an extra table. As of this 3616 * writing, they only use the opnd_size prefix. 3617 */ 3618 3619 /* 3620 * Calculate our offset in dis_op0F7123 3621 */ 3622 if ((uintptr_t)dp - (uintptr_t)dis_op0F7123 > 3623 sizeof (dis_op0F7123)) 3624 goto error; 3625 3626 if (opnd_size_prefix) { 3627 off = ((uintptr_t)dp - (uintptr_t)dis_op0F7123) / 3628 sizeof (instable_t); 3629 dp = (instable_t *)&dis_opSIMD7123[off]; 3630 opnd_size_prefix = 0; 3631 if (opnd_size == SIZE16) 3632 opnd_size = SIZE32; 3633 } 3634 break; 3635 case MRw: 3636 if (rep_prefix) { 3637 if (rep_prefix == 0xf3) { 3638 3639 /* 3640 * Calculate our offset in dis_op0F 3641 */ 3642 if ((uintptr_t)dp - (uintptr_t)dis_op0F 3643 > sizeof (dis_op0F)) 3644 goto error; 3645 3646 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) / 3647 sizeof (instable_t); 3648 3649 dp = (instable_t *)&dis_opSIMDrepz[off]; 3650 rep_prefix = 0; 3651 } else { 3652 goto error; 3653 } 3654 } 3655 break; 3656 } 3657 3658 /* 3659 * In 64 bit mode, some opcodes automatically use opnd_size == SIZE64. 3660 */ 3661 if (cpu_mode == SIZE64) 3662 if (dp->it_always64 || (opnd_size == SIZE32 && dp->it_stackop)) 3663 opnd_size = SIZE64; 3664 3665 #ifdef DIS_TEXT 3666 /* 3667 * At this point most instructions can format the opcode mnemonic 3668 * including the prefixes. 3669 */ 3670 if (lock_prefix) 3671 (void) strlcat(x->d86_mnem, "lock ", OPLEN); 3672 3673 if (rep_prefix == 0xf2) 3674 (void) strlcat(x->d86_mnem, "repnz ", OPLEN); 3675 else if (rep_prefix == 0xf3) 3676 (void) strlcat(x->d86_mnem, "repz ", OPLEN); 3677 3678 if (cpu_mode == SIZE64 && addr_size_prefix) 3679 (void) strlcat(x->d86_mnem, "addr32 ", OPLEN); 3680 3681 if (dp->it_adrmode != CBW && 3682 dp->it_adrmode != CWD && 3683 dp->it_adrmode != XMMSFNC) { 3684 if (strcmp(dp->it_name, "INVALID") == 0) 3685 goto error; 3686 (void) strlcat(x->d86_mnem, dp->it_name, OPLEN); 3687 if (dp->it_avxsuf && dp->it_suffix) { 3688 (void) strlcat(x->d86_mnem, vex_W != 0 ? "q" : "d", 3689 OPLEN); 3690 } else if (dp->it_vexopmask && dp->it_suffix) { 3691 /* opmask instructions */ 3692 3693 if (opcode1 == 4 && opcode2 == 0xb) { 3694 /* It's a kunpck. */ 3695 if (vex_prefix == VEX_2bytes) { 3696 (void) strlcat(x->d86_mnem, 3697 vex_p == 0 ? "wd" : "bw", OPLEN); 3698 } else { 3699 /* vex_prefix == VEX_3bytes */ 3700 (void) strlcat(x->d86_mnem, 3701 "dq", OPLEN); 3702 } 3703 } else if (opcode1 == 3) { 3704 /* It's a kshift[l|r]. */ 3705 if (vex_W == 0) { 3706 (void) strlcat(x->d86_mnem, 3707 opcode2 == 2 || 3708 opcode2 == 0 ? 3709 "b" : "d", OPLEN); 3710 } else { 3711 /* W == 1 */ 3712 (void) strlcat(x->d86_mnem, 3713 opcode2 == 3 || opcode2 == 1 ? 3714 "q" : "w", OPLEN); 3715 } 3716 } else { 3717 /* if (vex_prefix == VEX_2bytes) { */ 3718 if ((cpu_mode == SIZE64 && opnd_size == 2) || 3719 vex_prefix == VEX_2bytes) { 3720 (void) strlcat(x->d86_mnem, 3721 vex_p == 0 ? "w" : 3722 vex_p == 1 ? "b" : "d", 3723 OPLEN); 3724 } else { 3725 /* vex_prefix == VEX_3bytes */ 3726 (void) strlcat(x->d86_mnem, 3727 vex_p == 1 ? "d" : "q", OPLEN); 3728 } 3729 } 3730 } else if (dp->it_suffix) { 3731 char *types[] = {"", "w", "l", "q"}; 3732 if (opcode_bytes == 2 && opcode4 == 4) { 3733 /* It's a cmovx.yy. Replace the suffix x */ 3734 for (i = 5; i < OPLEN; i++) { 3735 if (x->d86_mnem[i] == '.') 3736 break; 3737 } 3738 x->d86_mnem[i - 1] = *types[opnd_size]; 3739 } else if ((opnd_size == 2) && (opcode_bytes == 3) && 3740 ((opcode6 == 1 && opcode7 == 6) || 3741 (opcode6 == 2 && opcode7 == 2))) { 3742 /* 3743 * To handle PINSRD and PEXTRD 3744 */ 3745 (void) strlcat(x->d86_mnem, "d", OPLEN); 3746 } else { 3747 (void) strlcat(x->d86_mnem, types[opnd_size], 3748 OPLEN); 3749 } 3750 } 3751 } 3752 #endif 3753 3754 /* 3755 * Process operands based on the addressing modes. 3756 */ 3757 x->d86_mode = cpu_mode; 3758 /* 3759 * In vex mode the rex_prefix has no meaning 3760 */ 3761 if (!vex_prefix) 3762 x->d86_rex_prefix = rex_prefix; 3763 x->d86_opnd_size = opnd_size; 3764 x->d86_addr_size = addr_size; 3765 vbit = 0; /* initialize for mem/reg -> reg */ 3766 switch (dp->it_adrmode) { 3767 /* 3768 * amd64 instruction to sign extend 32 bit reg/mem operands 3769 * into 64 bit register values 3770 */ 3771 case MOVSXZ: 3772 #ifdef DIS_TEXT 3773 if (rex_prefix == 0) 3774 (void) strncpy(x->d86_mnem, "movzld", OPLEN); 3775 #endif 3776 dtrace_get_modrm(x, &mode, ®, &r_m); 3777 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3778 x->d86_opnd_size = SIZE64; 3779 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 3780 x->d86_opnd_size = opnd_size = SIZE32; 3781 wbit = LONG_OPND; 3782 dtrace_get_operand(x, mode, r_m, wbit, 0); 3783 break; 3784 3785 /* 3786 * movsbl movsbw movsbq (0x0FBE) or movswl movswq (0x0FBF) 3787 * movzbl movzbw movzbq (0x0FB6) or movzwl movzwq (0x0FB7) 3788 * wbit lives in 2nd byte, note that operands 3789 * are different sized 3790 */ 3791 case MOVZ: 3792 if (rex_prefix & REX_W) { 3793 /* target register size = 64 bit */ 3794 x->d86_mnem[5] = 'q'; 3795 } 3796 dtrace_get_modrm(x, &mode, ®, &r_m); 3797 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3798 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 3799 x->d86_opnd_size = opnd_size = SIZE16; 3800 wbit = WBIT(opcode5); 3801 dtrace_get_operand(x, mode, r_m, wbit, 0); 3802 break; 3803 case CRC32: 3804 opnd_size = SIZE32; 3805 if (rex_prefix & REX_W) 3806 opnd_size = SIZE64; 3807 x->d86_opnd_size = opnd_size; 3808 3809 dtrace_get_modrm(x, &mode, ®, &r_m); 3810 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3811 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 3812 wbit = WBIT(opcode7); 3813 if (opnd_size_prefix) 3814 x->d86_opnd_size = opnd_size = SIZE16; 3815 dtrace_get_operand(x, mode, r_m, wbit, 0); 3816 break; 3817 case MOVBE: 3818 opnd_size = SIZE32; 3819 if (rex_prefix & REX_W) 3820 opnd_size = SIZE64; 3821 x->d86_opnd_size = opnd_size; 3822 3823 dtrace_get_modrm(x, &mode, ®, &r_m); 3824 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3825 wbit = WBIT(opcode7); 3826 if (opnd_size_prefix) 3827 x->d86_opnd_size = opnd_size = SIZE16; 3828 if (wbit) { 3829 /* reg -> mem */ 3830 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 3831 dtrace_get_operand(x, mode, r_m, wbit, 1); 3832 } else { 3833 /* mem -> reg */ 3834 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 3835 dtrace_get_operand(x, mode, r_m, wbit, 0); 3836 } 3837 break; 3838 3839 /* 3840 * imul instruction, with either 8-bit or longer immediate 3841 * opcode 0x6B for byte, sign-extended displacement, 0x69 for word(s) 3842 */ 3843 case IMUL: 3844 wbit = LONG_OPND; 3845 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 3846 OPSIZE(opnd_size, opcode2 == 0x9), 1); 3847 break; 3848 3849 /* memory or register operand to register, with 'w' bit */ 3850 case MRw: 3851 case ADX: 3852 wbit = WBIT(opcode2); 3853 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 3854 break; 3855 3856 /* register to memory or register operand, with 'w' bit */ 3857 /* arpl happens to fit here also because it is odd */ 3858 case RMw: 3859 if (opcode_bytes == 2) 3860 wbit = WBIT(opcode5); 3861 else 3862 wbit = WBIT(opcode2); 3863 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 3864 break; 3865 3866 /* xaddb instruction */ 3867 case XADDB: 3868 wbit = 0; 3869 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 3870 break; 3871 3872 /* MMX register to memory or register operand */ 3873 case MMS: 3874 case MMOS: 3875 #ifdef DIS_TEXT 3876 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 3877 #else 3878 wbit = LONG_OPND; 3879 #endif 3880 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1); 3881 break; 3882 3883 /* MMX register to memory */ 3884 case MMOMS: 3885 dtrace_get_modrm(x, &mode, ®, &r_m); 3886 if (mode == REG_ONLY) 3887 goto error; 3888 wbit = MM_OPND; 3889 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1); 3890 break; 3891 3892 /* Double shift. Has immediate operand specifying the shift. */ 3893 case DSHIFT: 3894 wbit = LONG_OPND; 3895 dtrace_get_modrm(x, &mode, ®, &r_m); 3896 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3897 dtrace_get_operand(x, mode, r_m, wbit, 2); 3898 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 3899 dtrace_imm_opnd(x, wbit, 1, 0); 3900 break; 3901 3902 /* 3903 * Double shift. With no immediate operand, specifies using %cl. 3904 */ 3905 case DSHIFTcl: 3906 wbit = LONG_OPND; 3907 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 3908 break; 3909 3910 /* immediate to memory or register operand */ 3911 case IMlw: 3912 wbit = WBIT(opcode2); 3913 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 3914 dtrace_get_operand(x, mode, r_m, wbit, 1); 3915 /* 3916 * Have long immediate for opcode 0x81, but not 0x80 nor 0x83 3917 */ 3918 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, opcode2 == 1), 0); 3919 break; 3920 3921 /* immediate to memory or register operand with the */ 3922 /* 'w' bit present */ 3923 case IMw: 3924 wbit = WBIT(opcode2); 3925 dtrace_get_modrm(x, &mode, ®, &r_m); 3926 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 3927 dtrace_get_operand(x, mode, r_m, wbit, 1); 3928 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0); 3929 break; 3930 3931 /* immediate to register with register in low 3 bits */ 3932 /* of op code */ 3933 case IR: 3934 /* w-bit here (with regs) is bit 3 */ 3935 wbit = opcode2 >>3 & 0x1; 3936 reg = REGNO(opcode2); 3937 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 3938 mode = REG_ONLY; 3939 r_m = reg; 3940 dtrace_get_operand(x, mode, r_m, wbit, 1); 3941 dtrace_imm_opnd(x, wbit, OPSIZE64(opnd_size, wbit), 0); 3942 break; 3943 3944 /* MMX immediate shift of register */ 3945 case MMSH: 3946 case MMOSH: 3947 wbit = MM_OPND; 3948 goto mm_shift; /* in next case */ 3949 3950 /* SIMD immediate shift of register */ 3951 case XMMSH: 3952 wbit = XMM_OPND; 3953 mm_shift: 3954 reg = REGNO(opcode7); 3955 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 3956 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 3957 dtrace_imm_opnd(x, wbit, 1, 0); 3958 NOMEM; 3959 break; 3960 3961 /* accumulator to memory operand */ 3962 case AO: 3963 vbit = 1; 3964 /*FALLTHROUGH*/ 3965 3966 /* memory operand to accumulator */ 3967 case OA: 3968 wbit = WBIT(opcode2); 3969 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1 - vbit); 3970 dtrace_imm_opnd(x, wbit, OPSIZE64(addr_size, LONG_OPND), vbit); 3971 #ifdef DIS_TEXT 3972 x->d86_opnd[vbit].d86_mode = MODE_OFFSET; 3973 #endif 3974 break; 3975 3976 3977 /* segment register to memory or register operand */ 3978 case SM: 3979 vbit = 1; 3980 /*FALLTHROUGH*/ 3981 3982 /* memory or register operand to segment register */ 3983 case MS: 3984 dtrace_get_modrm(x, &mode, ®, &r_m); 3985 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 3986 dtrace_get_operand(x, mode, r_m, LONG_OPND, vbit); 3987 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 1 - vbit); 3988 break; 3989 3990 /* 3991 * rotate or shift instructions, which may shift by 1 or 3992 * consult the cl register, depending on the 'v' bit 3993 */ 3994 case Mv: 3995 vbit = VBIT(opcode2); 3996 wbit = WBIT(opcode2); 3997 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 3998 dtrace_get_operand(x, mode, r_m, wbit, 1); 3999 #ifdef DIS_TEXT 4000 if (vbit) { 4001 (void) strlcat(x->d86_opnd[0].d86_opnd, "%cl", OPLEN); 4002 } else { 4003 x->d86_opnd[0].d86_mode = MODE_SIGNED; 4004 x->d86_opnd[0].d86_value_size = 1; 4005 x->d86_opnd[0].d86_value = 1; 4006 } 4007 #endif 4008 break; 4009 /* 4010 * immediate rotate or shift instructions 4011 */ 4012 case MvI: 4013 wbit = WBIT(opcode2); 4014 normal_imm_mem: 4015 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4016 dtrace_get_operand(x, mode, r_m, wbit, 1); 4017 dtrace_imm_opnd(x, wbit, 1, 0); 4018 break; 4019 4020 /* bit test instructions */ 4021 case MIb: 4022 wbit = LONG_OPND; 4023 goto normal_imm_mem; 4024 4025 /* single memory or register operand with 'w' bit present */ 4026 case Mw: 4027 wbit = WBIT(opcode2); 4028 just_mem: 4029 dtrace_get_modrm(x, &mode, ®, &r_m); 4030 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4031 dtrace_get_operand(x, mode, r_m, wbit, 0); 4032 break; 4033 4034 case SWAPGS_RDTSCP: 4035 if (cpu_mode == SIZE64 && mode == 3 && r_m == 0) { 4036 #ifdef DIS_TEXT 4037 (void) strncpy(x->d86_mnem, "swapgs", OPLEN); 4038 #endif 4039 NOMEM; 4040 break; 4041 } else if (mode == 3 && r_m == 1) { 4042 #ifdef DIS_TEXT 4043 (void) strncpy(x->d86_mnem, "rdtscp", OPLEN); 4044 #endif 4045 NOMEM; 4046 break; 4047 } 4048 4049 /*FALLTHROUGH*/ 4050 4051 /* prefetch instruction - memory operand, but no memory acess */ 4052 case PREF: 4053 NOMEM; 4054 /*FALLTHROUGH*/ 4055 4056 /* single memory or register operand */ 4057 case M: 4058 case MG9: 4059 wbit = LONG_OPND; 4060 goto just_mem; 4061 4062 /* single memory or register byte operand */ 4063 case Mb: 4064 wbit = BYTE_OPND; 4065 goto just_mem; 4066 4067 case VMx: 4068 if (mode == 3) { 4069 #ifdef DIS_TEXT 4070 char *vminstr; 4071 4072 switch (r_m) { 4073 case 1: 4074 vminstr = "vmcall"; 4075 break; 4076 case 2: 4077 vminstr = "vmlaunch"; 4078 break; 4079 case 3: 4080 vminstr = "vmresume"; 4081 break; 4082 case 4: 4083 vminstr = "vmxoff"; 4084 break; 4085 default: 4086 goto error; 4087 } 4088 4089 (void) strncpy(x->d86_mnem, vminstr, OPLEN); 4090 #else 4091 if (r_m < 1 || r_m > 4) 4092 goto error; 4093 #endif 4094 4095 NOMEM; 4096 break; 4097 } 4098 /*FALLTHROUGH*/ 4099 case SVM: 4100 if (mode == 3) { 4101 #if DIS_TEXT 4102 char *vinstr; 4103 4104 switch (r_m) { 4105 case 0: 4106 vinstr = "vmrun"; 4107 break; 4108 case 1: 4109 vinstr = "vmmcall"; 4110 break; 4111 case 2: 4112 vinstr = "vmload"; 4113 break; 4114 case 3: 4115 vinstr = "vmsave"; 4116 break; 4117 case 4: 4118 vinstr = "stgi"; 4119 break; 4120 case 5: 4121 vinstr = "clgi"; 4122 break; 4123 case 6: 4124 vinstr = "skinit"; 4125 break; 4126 case 7: 4127 vinstr = "invlpga"; 4128 break; 4129 } 4130 4131 (void) strncpy(x->d86_mnem, vinstr, OPLEN); 4132 #endif 4133 NOMEM; 4134 break; 4135 } 4136 /*FALLTHROUGH*/ 4137 case MONITOR_MWAIT: 4138 if (mode == 3) { 4139 if (r_m == 0) { 4140 #ifdef DIS_TEXT 4141 (void) strncpy(x->d86_mnem, "monitor", OPLEN); 4142 #endif 4143 NOMEM; 4144 break; 4145 } else if (r_m == 1) { 4146 #ifdef DIS_TEXT 4147 (void) strncpy(x->d86_mnem, "mwait", OPLEN); 4148 #endif 4149 NOMEM; 4150 break; 4151 } else if (r_m == 2) { 4152 #ifdef DIS_TEXT 4153 (void) strncpy(x->d86_mnem, "clac", OPLEN); 4154 #endif 4155 NOMEM; 4156 break; 4157 } else if (r_m == 3) { 4158 #ifdef DIS_TEXT 4159 (void) strncpy(x->d86_mnem, "stac", OPLEN); 4160 #endif 4161 NOMEM; 4162 break; 4163 } else { 4164 goto error; 4165 } 4166 } 4167 /*FALLTHROUGH*/ 4168 case XGETBV_XSETBV: 4169 if (mode == 3) { 4170 if (r_m == 0) { 4171 #ifdef DIS_TEXT 4172 (void) strncpy(x->d86_mnem, "xgetbv", OPLEN); 4173 #endif 4174 NOMEM; 4175 break; 4176 } else if (r_m == 1) { 4177 #ifdef DIS_TEXT 4178 (void) strncpy(x->d86_mnem, "xsetbv", OPLEN); 4179 #endif 4180 NOMEM; 4181 break; 4182 } else { 4183 goto error; 4184 } 4185 4186 } 4187 /*FALLTHROUGH*/ 4188 case MO: 4189 /* Similar to M, but only memory (no direct registers) */ 4190 wbit = LONG_OPND; 4191 dtrace_get_modrm(x, &mode, ®, &r_m); 4192 if (mode == 3) 4193 goto error; 4194 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4195 dtrace_get_operand(x, mode, r_m, wbit, 0); 4196 break; 4197 4198 /* move special register to register or reverse if vbit */ 4199 case SREG: 4200 switch (opcode5) { 4201 4202 case 2: 4203 vbit = 1; 4204 /*FALLTHROUGH*/ 4205 case 0: 4206 wbit = CONTROL_OPND; 4207 break; 4208 4209 case 3: 4210 vbit = 1; 4211 /*FALLTHROUGH*/ 4212 case 1: 4213 wbit = DEBUG_OPND; 4214 break; 4215 4216 case 6: 4217 vbit = 1; 4218 /*FALLTHROUGH*/ 4219 case 4: 4220 wbit = TEST_OPND; 4221 break; 4222 4223 } 4224 dtrace_get_modrm(x, &mode, ®, &r_m); 4225 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4226 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit); 4227 dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 1 - vbit); 4228 NOMEM; 4229 break; 4230 4231 /* 4232 * single register operand with register in the low 3 4233 * bits of op code 4234 */ 4235 case R: 4236 if (opcode_bytes == 2) 4237 reg = REGNO(opcode5); 4238 else 4239 reg = REGNO(opcode2); 4240 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 4241 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 4242 NOMEM; 4243 break; 4244 4245 /* 4246 * register to accumulator with register in the low 3 4247 * bits of op code, xchg instructions 4248 */ 4249 case RA: 4250 NOMEM; 4251 reg = REGNO(opcode2); 4252 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 4253 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 4254 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, LONG_OPND, 1); 4255 break; 4256 4257 /* 4258 * single segment register operand, with register in 4259 * bits 3-4 of op code byte 4260 */ 4261 case SEG: 4262 NOMEM; 4263 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x3; 4264 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0); 4265 break; 4266 4267 /* 4268 * single segment register operand, with register in 4269 * bits 3-5 of op code 4270 */ 4271 case LSEG: 4272 NOMEM; 4273 /* long seg reg from opcode */ 4274 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x7; 4275 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0); 4276 break; 4277 4278 /* memory or register operand to register */ 4279 case MR: 4280 if (vex_prefetch) 4281 x->d86_got_modrm = 1; 4282 wbit = LONG_OPND; 4283 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 4284 break; 4285 4286 case RM: 4287 case RM_66r: 4288 wbit = LONG_OPND; 4289 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 4290 break; 4291 4292 /* MMX/SIMD-Int memory or mm reg to mm reg */ 4293 case MM: 4294 case MMO: 4295 #ifdef DIS_TEXT 4296 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 4297 #else 4298 wbit = LONG_OPND; 4299 #endif 4300 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0); 4301 break; 4302 4303 case MMOIMPL: 4304 #ifdef DIS_TEXT 4305 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 4306 #else 4307 wbit = LONG_OPND; 4308 #endif 4309 dtrace_get_modrm(x, &mode, ®, &r_m); 4310 if (mode != REG_ONLY) 4311 goto error; 4312 4313 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4314 dtrace_get_operand(x, mode, r_m, wbit, 0); 4315 dtrace_get_operand(x, REG_ONLY, reg, MM_OPND, 1); 4316 mode = 0; /* change for memory access size... */ 4317 break; 4318 4319 /* MMX/SIMD-Int and SIMD-FP predicated mm reg to r32 */ 4320 case MMO3P: 4321 wbit = MM_OPND; 4322 goto xmm3p; 4323 case XMM3P: 4324 wbit = XMM_OPND; 4325 xmm3p: 4326 dtrace_get_modrm(x, &mode, ®, &r_m); 4327 if (mode != REG_ONLY) 4328 goto error; 4329 4330 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 1, 4331 1); 4332 NOMEM; 4333 break; 4334 4335 case XMM3PM_66r: 4336 THREEOPERAND(x, mode, reg, r_m, rex_prefix, LONG_OPND, XMM_OPND, 4337 1, 0); 4338 break; 4339 4340 /* MMX/SIMD-Int predicated r32/mem to mm reg */ 4341 case MMOPRM: 4342 wbit = LONG_OPND; 4343 w2 = MM_OPND; 4344 goto xmmprm; 4345 case XMMPRM: 4346 case XMMPRM_66r: 4347 wbit = LONG_OPND; 4348 w2 = XMM_OPND; 4349 xmmprm: 4350 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, 1, 1); 4351 break; 4352 4353 /* MMX/SIMD-Int predicated mm/mem to mm reg */ 4354 case MMOPM: 4355 case MMOPM_66o: 4356 wbit = w2 = MM_OPND; 4357 goto xmmprm; 4358 4359 /* MMX/SIMD-Int mm reg to r32 */ 4360 case MMOM3: 4361 NOMEM; 4362 dtrace_get_modrm(x, &mode, ®, &r_m); 4363 if (mode != REG_ONLY) 4364 goto error; 4365 wbit = MM_OPND; 4366 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0); 4367 break; 4368 4369 /* SIMD memory or xmm reg operand to xmm reg */ 4370 case XMM: 4371 case XMM_66o: 4372 case XMM_66r: 4373 case XMMO: 4374 case XMMXIMPL: 4375 wbit = XMM_OPND; 4376 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 4377 4378 if (dp->it_adrmode == XMMXIMPL && mode != REG_ONLY) 4379 goto error; 4380 4381 #ifdef DIS_TEXT 4382 /* 4383 * movlps and movhlps share opcodes. They differ in the 4384 * addressing modes allowed for their operands. 4385 * movhps and movlhps behave similarly. 4386 */ 4387 if (mode == REG_ONLY) { 4388 if (strcmp(dp->it_name, "movlps") == 0) 4389 (void) strncpy(x->d86_mnem, "movhlps", OPLEN); 4390 else if (strcmp(dp->it_name, "movhps") == 0) 4391 (void) strncpy(x->d86_mnem, "movlhps", OPLEN); 4392 } 4393 #endif 4394 if (dp->it_adrmode == XMMXIMPL) 4395 mode = 0; /* change for memory access size... */ 4396 break; 4397 4398 /* SIMD xmm reg to memory or xmm reg */ 4399 case XMMS: 4400 case XMMOS: 4401 case XMMMS: 4402 case XMMOMS: 4403 dtrace_get_modrm(x, &mode, ®, &r_m); 4404 #ifdef DIS_TEXT 4405 if ((strcmp(dp->it_name, "movlps") == 0 || 4406 strcmp(dp->it_name, "movhps") == 0 || 4407 strcmp(dp->it_name, "movntps") == 0) && 4408 mode == REG_ONLY) 4409 goto error; 4410 #endif 4411 wbit = XMM_OPND; 4412 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1); 4413 break; 4414 4415 /* SIMD memory to xmm reg */ 4416 case XMMM: 4417 case XMMM_66r: 4418 case XMMOM: 4419 wbit = XMM_OPND; 4420 dtrace_get_modrm(x, &mode, ®, &r_m); 4421 #ifdef DIS_TEXT 4422 if (mode == REG_ONLY) { 4423 if (strcmp(dp->it_name, "movhps") == 0) 4424 (void) strncpy(x->d86_mnem, "movlhps", OPLEN); 4425 else 4426 goto error; 4427 } 4428 #endif 4429 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 4430 break; 4431 4432 /* SIMD memory or r32 to xmm reg */ 4433 case XMM3MX: 4434 wbit = LONG_OPND; 4435 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 4436 break; 4437 4438 case XMM3MXS: 4439 wbit = LONG_OPND; 4440 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1); 4441 break; 4442 4443 /* SIMD memory or mm reg to xmm reg */ 4444 case XMMOMX: 4445 /* SIMD mm to xmm */ 4446 case XMMMX: 4447 wbit = MM_OPND; 4448 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 4449 break; 4450 4451 /* SIMD memory or xmm reg to mm reg */ 4452 case XMMXMM: 4453 case XMMOXMM: 4454 case XMMXM: 4455 wbit = XMM_OPND; 4456 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0); 4457 break; 4458 4459 4460 /* SIMD memory or xmm reg to r32 */ 4461 case XMMXM3: 4462 wbit = XMM_OPND; 4463 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0); 4464 break; 4465 4466 /* SIMD xmm to r32 */ 4467 case XMMX3: 4468 case XMMOX3: 4469 dtrace_get_modrm(x, &mode, ®, &r_m); 4470 if (mode != REG_ONLY) 4471 goto error; 4472 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4473 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0); 4474 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4475 NOMEM; 4476 break; 4477 4478 /* SIMD predicated memory or xmm reg with/to xmm reg */ 4479 case XMMP: 4480 case XMMP_66r: 4481 case XMMP_66o: 4482 case XMMOPM: 4483 wbit = XMM_OPND; 4484 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1, 4485 1); 4486 4487 #ifdef DIS_TEXT 4488 /* 4489 * cmpps and cmpss vary their instruction name based 4490 * on the value of imm8. Other XMMP instructions, 4491 * such as shufps, require explicit specification of 4492 * the predicate. 4493 */ 4494 if (dp->it_name[0] == 'c' && 4495 dp->it_name[1] == 'm' && 4496 dp->it_name[2] == 'p' && 4497 strlen(dp->it_name) == 5) { 4498 uchar_t pred = x->d86_opnd[0].d86_value & 0xff; 4499 4500 if (pred >= (sizeof (dis_PREDSUFFIX) / sizeof (char *))) 4501 goto error; 4502 4503 (void) strncpy(x->d86_mnem, "cmp", OPLEN); 4504 (void) strlcat(x->d86_mnem, dis_PREDSUFFIX[pred], 4505 OPLEN); 4506 (void) strlcat(x->d86_mnem, 4507 dp->it_name + strlen(dp->it_name) - 2, 4508 OPLEN); 4509 x->d86_opnd[0] = x->d86_opnd[1]; 4510 x->d86_opnd[1] = x->d86_opnd[2]; 4511 x->d86_numopnds = 2; 4512 } 4513 4514 /* 4515 * The pclmulqdq instruction has a series of alternate names for 4516 * various encodings of the immediate byte. As such, if we 4517 * happen to find it and the immediate value matches, we'll 4518 * rewrite the mnemonic. 4519 */ 4520 if (strcmp(dp->it_name, "pclmulqdq") == 0) { 4521 boolean_t changed = B_TRUE; 4522 switch (x->d86_opnd[0].d86_value) { 4523 case 0x00: 4524 (void) strncpy(x->d86_mnem, "pclmullqlqdq", 4525 OPLEN); 4526 break; 4527 case 0x01: 4528 (void) strncpy(x->d86_mnem, "pclmulhqlqdq", 4529 OPLEN); 4530 break; 4531 case 0x10: 4532 (void) strncpy(x->d86_mnem, "pclmullqhqdq", 4533 OPLEN); 4534 break; 4535 case 0x11: 4536 (void) strncpy(x->d86_mnem, "pclmulhqhqdq", 4537 OPLEN); 4538 break; 4539 default: 4540 changed = B_FALSE; 4541 break; 4542 } 4543 4544 if (changed == B_TRUE) { 4545 x->d86_opnd[0].d86_value_size = 0; 4546 x->d86_opnd[0] = x->d86_opnd[1]; 4547 x->d86_opnd[1] = x->d86_opnd[2]; 4548 x->d86_numopnds = 2; 4549 } 4550 } 4551 #endif 4552 break; 4553 4554 case XMMX2I: 4555 FOUROPERAND(x, mode, reg, r_m, rex_prefix, XMM_OPND, XMM_OPND, 4556 1); 4557 NOMEM; 4558 break; 4559 4560 case XMM2I: 4561 ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, XMM_OPND, 1); 4562 NOMEM; 4563 break; 4564 4565 /* immediate operand to accumulator */ 4566 case IA: 4567 wbit = WBIT(opcode2); 4568 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1); 4569 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0); 4570 NOMEM; 4571 break; 4572 4573 /* memory or register operand to accumulator */ 4574 case MA: 4575 wbit = WBIT(opcode2); 4576 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4577 dtrace_get_operand(x, mode, r_m, wbit, 0); 4578 break; 4579 4580 /* si register to di register used to reference memory */ 4581 case SD: 4582 #ifdef DIS_TEXT 4583 dtrace_check_override(x, 0); 4584 x->d86_numopnds = 2; 4585 if (addr_size == SIZE64) { 4586 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)", 4587 OPLEN); 4588 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)", 4589 OPLEN); 4590 } else if (addr_size == SIZE32) { 4591 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)", 4592 OPLEN); 4593 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)", 4594 OPLEN); 4595 } else { 4596 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)", 4597 OPLEN); 4598 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)", 4599 OPLEN); 4600 } 4601 #endif 4602 wbit = LONG_OPND; 4603 break; 4604 4605 /* accumulator to di register */ 4606 case AD: 4607 wbit = WBIT(opcode2); 4608 #ifdef DIS_TEXT 4609 dtrace_check_override(x, 1); 4610 x->d86_numopnds = 2; 4611 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 0); 4612 if (addr_size == SIZE64) 4613 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)", 4614 OPLEN); 4615 else if (addr_size == SIZE32) 4616 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)", 4617 OPLEN); 4618 else 4619 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)", 4620 OPLEN); 4621 #endif 4622 break; 4623 4624 /* si register to accumulator */ 4625 case SA: 4626 wbit = WBIT(opcode2); 4627 #ifdef DIS_TEXT 4628 dtrace_check_override(x, 0); 4629 x->d86_numopnds = 2; 4630 if (addr_size == SIZE64) 4631 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)", 4632 OPLEN); 4633 else if (addr_size == SIZE32) 4634 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)", 4635 OPLEN); 4636 else 4637 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)", 4638 OPLEN); 4639 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1); 4640 #endif 4641 break; 4642 4643 /* 4644 * single operand, a 16/32 bit displacement 4645 */ 4646 case D: 4647 wbit = LONG_OPND; 4648 dtrace_disp_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0); 4649 NOMEM; 4650 break; 4651 4652 /* jmp/call indirect to memory or register operand */ 4653 case INM: 4654 #ifdef DIS_TEXT 4655 (void) strlcat(x->d86_opnd[0].d86_prefix, "*", OPLEN); 4656 #endif 4657 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4658 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 4659 wbit = LONG_OPND; 4660 break; 4661 4662 /* 4663 * for long jumps and long calls -- a new code segment 4664 * register and an offset in IP -- stored in object 4665 * code in reverse order. Note - not valid in amd64 4666 */ 4667 case SO: 4668 dtrace_check_override(x, 1); 4669 wbit = LONG_OPND; 4670 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 1); 4671 #ifdef DIS_TEXT 4672 x->d86_opnd[1].d86_mode = MODE_SIGNED; 4673 #endif 4674 /* will now get segment operand */ 4675 dtrace_imm_opnd(x, wbit, 2, 0); 4676 break; 4677 4678 /* 4679 * jmp/call. single operand, 8 bit displacement. 4680 * added to current EIP in 'compofff' 4681 */ 4682 case BD: 4683 dtrace_disp_opnd(x, BYTE_OPND, 1, 0); 4684 NOMEM; 4685 break; 4686 4687 /* single 32/16 bit immediate operand */ 4688 case I: 4689 wbit = LONG_OPND; 4690 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0); 4691 break; 4692 4693 /* single 8 bit immediate operand */ 4694 case Ib: 4695 wbit = LONG_OPND; 4696 dtrace_imm_opnd(x, wbit, 1, 0); 4697 break; 4698 4699 case ENTER: 4700 wbit = LONG_OPND; 4701 dtrace_imm_opnd(x, wbit, 2, 0); 4702 dtrace_imm_opnd(x, wbit, 1, 1); 4703 switch (opnd_size) { 4704 case SIZE64: 4705 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 8; 4706 break; 4707 case SIZE32: 4708 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 4; 4709 break; 4710 case SIZE16: 4711 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 2; 4712 break; 4713 } 4714 4715 break; 4716 4717 /* 16-bit immediate operand */ 4718 case RET: 4719 wbit = LONG_OPND; 4720 dtrace_imm_opnd(x, wbit, 2, 0); 4721 break; 4722 4723 /* single 8 bit port operand */ 4724 case P: 4725 dtrace_check_override(x, 0); 4726 dtrace_imm_opnd(x, BYTE_OPND, 1, 0); 4727 NOMEM; 4728 break; 4729 4730 /* single operand, dx register (variable port instruction) */ 4731 case V: 4732 x->d86_numopnds = 1; 4733 dtrace_check_override(x, 0); 4734 #ifdef DIS_TEXT 4735 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%dx)", OPLEN); 4736 #endif 4737 NOMEM; 4738 break; 4739 4740 /* 4741 * The int instruction, which has two forms: 4742 * int 3 (breakpoint) or 4743 * int n, where n is indicated in the subsequent 4744 * byte (format Ib). The int 3 instruction (opcode 0xCC), 4745 * where, although the 3 looks like an operand, 4746 * it is implied by the opcode. It must be converted 4747 * to the correct base and output. 4748 */ 4749 case INT3: 4750 #ifdef DIS_TEXT 4751 x->d86_numopnds = 1; 4752 x->d86_opnd[0].d86_mode = MODE_SIGNED; 4753 x->d86_opnd[0].d86_value_size = 1; 4754 x->d86_opnd[0].d86_value = 3; 4755 #endif 4756 NOMEM; 4757 break; 4758 4759 /* single 8 bit immediate operand */ 4760 case INTx: 4761 dtrace_imm_opnd(x, BYTE_OPND, 1, 0); 4762 NOMEM; 4763 break; 4764 4765 /* an unused byte must be discarded */ 4766 case U: 4767 if (x->d86_get_byte(x->d86_data) < 0) 4768 goto error; 4769 x->d86_len++; 4770 NOMEM; 4771 break; 4772 4773 case CBW: 4774 #ifdef DIS_TEXT 4775 if (opnd_size == SIZE16) 4776 (void) strlcat(x->d86_mnem, "cbtw", OPLEN); 4777 else if (opnd_size == SIZE32) 4778 (void) strlcat(x->d86_mnem, "cwtl", OPLEN); 4779 else 4780 (void) strlcat(x->d86_mnem, "cltq", OPLEN); 4781 #endif 4782 wbit = LONG_OPND; 4783 NOMEM; 4784 break; 4785 4786 case CWD: 4787 #ifdef DIS_TEXT 4788 if (opnd_size == SIZE16) 4789 (void) strlcat(x->d86_mnem, "cwtd", OPLEN); 4790 else if (opnd_size == SIZE32) 4791 (void) strlcat(x->d86_mnem, "cltd", OPLEN); 4792 else 4793 (void) strlcat(x->d86_mnem, "cqtd", OPLEN); 4794 #endif 4795 wbit = LONG_OPND; 4796 NOMEM; 4797 break; 4798 4799 case XMMSFNC: 4800 /* 4801 * sfence is sfence if mode is REG_ONLY. If mode isn't 4802 * REG_ONLY, mnemonic should be 'clflush'. 4803 */ 4804 dtrace_get_modrm(x, &mode, ®, &r_m); 4805 4806 /* sfence doesn't take operands */ 4807 #ifdef DIS_TEXT 4808 if (mode == REG_ONLY) { 4809 (void) strlcat(x->d86_mnem, "sfence", OPLEN); 4810 } else { 4811 (void) strlcat(x->d86_mnem, "clflush", OPLEN); 4812 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4813 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0); 4814 NOMEM; 4815 } 4816 #else 4817 if (mode != REG_ONLY) { 4818 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4819 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 4820 NOMEM; 4821 } 4822 #endif 4823 break; 4824 4825 /* 4826 * no disassembly, the mnemonic was all there was so go on 4827 */ 4828 case NORM: 4829 if (dp->it_invalid32 && cpu_mode != SIZE64) 4830 goto error; 4831 NOMEM; 4832 /*FALLTHROUGH*/ 4833 case IMPLMEM: 4834 break; 4835 4836 case XMMFENCE: 4837 /* 4838 * XRSTOR, XSAVEOPT and LFENCE share the same opcode but 4839 * differ in mode and reg. 4840 */ 4841 dtrace_get_modrm(x, &mode, ®, &r_m); 4842 4843 if (mode == REG_ONLY) { 4844 /* 4845 * Only the following exact byte sequences are allowed: 4846 * 4847 * 0f ae e8 lfence 4848 * 0f ae f0 mfence 4849 */ 4850 if ((uint8_t)x->d86_bytes[x->d86_len - 1] != 0xe8 && 4851 (uint8_t)x->d86_bytes[x->d86_len - 1] != 0xf0) 4852 goto error; 4853 } else { 4854 #ifdef DIS_TEXT 4855 if (reg == 5) { 4856 (void) strncpy(x->d86_mnem, "xrstor", OPLEN); 4857 } else if (reg == 6) { 4858 (void) strncpy(x->d86_mnem, "xsaveopt", OPLEN); 4859 } else { 4860 goto error; 4861 } 4862 #endif 4863 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4864 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0); 4865 } 4866 break; 4867 4868 /* float reg */ 4869 case F: 4870 #ifdef DIS_TEXT 4871 x->d86_numopnds = 1; 4872 (void) strlcat(x->d86_opnd[0].d86_opnd, "%st(X)", OPLEN); 4873 x->d86_opnd[0].d86_opnd[4] = r_m + '0'; 4874 #endif 4875 NOMEM; 4876 break; 4877 4878 /* float reg to float reg, with ret bit present */ 4879 case FF: 4880 vbit = opcode2 >> 2 & 0x1; /* vbit = 1: st -> st(i) */ 4881 /*FALLTHROUGH*/ 4882 case FFC: /* case for vbit always = 0 */ 4883 #ifdef DIS_TEXT 4884 x->d86_numopnds = 2; 4885 (void) strlcat(x->d86_opnd[1 - vbit].d86_opnd, "%st", OPLEN); 4886 (void) strlcat(x->d86_opnd[vbit].d86_opnd, "%st(X)", OPLEN); 4887 x->d86_opnd[vbit].d86_opnd[4] = r_m + '0'; 4888 #endif 4889 NOMEM; 4890 break; 4891 4892 /* AVX instructions */ 4893 case VEX_MO: 4894 /* op(ModR/M.r/m) */ 4895 x->d86_numopnds = 1; 4896 dtrace_get_modrm(x, &mode, ®, &r_m); 4897 #ifdef DIS_TEXT 4898 if ((dp == &dis_opAVX0F[0xA][0xE]) && (reg == 3)) 4899 (void) strncpy(x->d86_mnem, "vstmxcsr", OPLEN); 4900 #endif 4901 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4902 dtrace_get_operand(x, mode, r_m, wbit, 0); 4903 break; 4904 case VEX_RMrX: 4905 case FMA: 4906 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r/m) */ 4907 x->d86_numopnds = 3; 4908 dtrace_get_modrm(x, &mode, ®, &r_m); 4909 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4910 4911 /* 4912 * In classic Intel fashion, the opcodes for all of the FMA 4913 * instructions all have two possible mnemonics which vary by 4914 * one letter, which is selected based on the value of the wbit. 4915 * When wbit is one, they have the 'd' suffix and when 'wbit' is 4916 * 0, they have the 's' suffix. Otherwise, the FMA instructions 4917 * are all a standard VEX_RMrX. 4918 */ 4919 #ifdef DIS_TEXT 4920 if (dp->it_adrmode == FMA) { 4921 size_t len = strlen(dp->it_name); 4922 (void) strncpy(x->d86_mnem, dp->it_name, OPLEN); 4923 if (len + 1 < OPLEN) { 4924 (void) strncpy(x->d86_mnem + len, 4925 vex_W != 0 ? "d" : "s", OPLEN - len); 4926 } 4927 } 4928 #endif 4929 4930 if (mode != REG_ONLY) { 4931 if ((dp == &dis_opAVXF20F[0x10]) || 4932 (dp == &dis_opAVXF30F[0x10])) { 4933 /* vmovsd <m64>, <xmm> */ 4934 /* or vmovss <m64>, <xmm> */ 4935 x->d86_numopnds = 2; 4936 goto L_VEX_MX; 4937 } 4938 } 4939 4940 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 4941 /* 4942 * VEX prefix uses the 1's complement form to encode the 4943 * XMM/YMM regs 4944 */ 4945 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 4946 4947 if ((dp == &dis_opAVXF20F[0x2A]) || 4948 (dp == &dis_opAVXF30F[0x2A])) { 4949 /* 4950 * vcvtsi2si </r,m>, <xmm>, <xmm> or vcvtsi2ss </r,m>, 4951 * <xmm>, <xmm> 4952 */ 4953 wbit = LONG_OPND; 4954 } 4955 #ifdef DIS_TEXT 4956 else if ((mode == REG_ONLY) && 4957 (dp == &dis_opAVX0F[0x1][0x6])) { /* vmovlhps */ 4958 (void) strncpy(x->d86_mnem, "vmovlhps", OPLEN); 4959 } else if ((mode == REG_ONLY) && 4960 (dp == &dis_opAVX0F[0x1][0x2])) { /* vmovhlps */ 4961 (void) strncpy(x->d86_mnem, "vmovhlps", OPLEN); 4962 } 4963 #endif 4964 dtrace_get_operand(x, mode, r_m, wbit, 0); 4965 4966 break; 4967 4968 case VEX_VRMrX: 4969 /* ModR/M.reg := op(MODR/M.r/m, VEX.vvvv) */ 4970 x->d86_numopnds = 3; 4971 dtrace_get_modrm(x, &mode, ®, &r_m); 4972 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4973 4974 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 4975 /* 4976 * VEX prefix uses the 1's complement form to encode the 4977 * XMM/YMM regs 4978 */ 4979 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 0); 4980 4981 dtrace_get_operand(x, mode, r_m, wbit, 1); 4982 break; 4983 4984 case VEX_SbVM: 4985 /* ModR/M.reg := op(MODR/M.r/m, VSIB, VEX.vvvv) */ 4986 x->d86_numopnds = 3; 4987 x->d86_vsib = 1; 4988 4989 /* 4990 * All instructions that use VSIB are currently a mess. See the 4991 * comment around the dis_gather_regs_t structure definition. 4992 */ 4993 4994 vreg = &dis_vgather[opcode2][vex_W][vex_L]; 4995 4996 #ifdef DIS_TEXT 4997 (void) strncpy(x->d86_mnem, dp->it_name, OPLEN); 4998 (void) strlcat(x->d86_mnem + strlen(dp->it_name), 4999 vreg->dgr_suffix, OPLEN - strlen(dp->it_name)); 5000 #endif 5001 5002 dtrace_get_modrm(x, &mode, ®, &r_m); 5003 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5004 5005 dtrace_get_operand(x, REG_ONLY, reg, vreg->dgr_arg2, 2); 5006 /* 5007 * VEX prefix uses the 1's complement form to encode the 5008 * XMM/YMM regs 5009 */ 5010 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), vreg->dgr_arg0, 5011 0); 5012 dtrace_get_operand(x, mode, r_m, vreg->dgr_arg1, 1); 5013 break; 5014 5015 case VEX_RRX: 5016 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */ 5017 x->d86_numopnds = 3; 5018 5019 dtrace_get_modrm(x, &mode, ®, &r_m); 5020 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5021 5022 if (mode != REG_ONLY) { 5023 if ((dp == &dis_opAVXF20F[0x11]) || 5024 (dp == &dis_opAVXF30F[0x11])) { 5025 /* vmovsd <xmm>, <m64> */ 5026 /* or vmovss <xmm>, <m64> */ 5027 x->d86_numopnds = 2; 5028 goto L_VEX_RM; 5029 } 5030 } 5031 5032 dtrace_get_operand(x, mode, r_m, wbit, 2); 5033 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5034 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5035 break; 5036 5037 case VEX_RMRX: 5038 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r_m, imm8[7:4]) */ 5039 x->d86_numopnds = 4; 5040 5041 dtrace_get_modrm(x, &mode, ®, &r_m); 5042 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5043 dtrace_get_operand(x, REG_ONLY, reg, wbit, 3); 5044 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2); 5045 if (dp == &dis_opAVX660F3A[0x18]) { 5046 /* vinsertf128 <imm8>, <xmm>, <ymm>, <ymm> */ 5047 dtrace_get_operand(x, mode, r_m, XMM_OPND, 1); 5048 } else if ((dp == &dis_opAVX660F3A[0x20]) || 5049 (dp == & dis_opAVX660F[0xC4])) { 5050 /* vpinsrb <imm8>, <reg/mm>, <xmm>, <xmm> */ 5051 /* or vpinsrw <imm8>, <reg/mm>, <xmm>, <xmm> */ 5052 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 5053 } else if (dp == &dis_opAVX660F3A[0x22]) { 5054 /* vpinsrd/q <imm8>, <reg/mm>, <xmm>, <xmm> */ 5055 #ifdef DIS_TEXT 5056 if (vex_W) 5057 x->d86_mnem[6] = 'q'; 5058 #endif 5059 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 5060 } else { 5061 dtrace_get_operand(x, mode, r_m, wbit, 1); 5062 } 5063 5064 /* one byte immediate number */ 5065 dtrace_imm_opnd(x, wbit, 1, 0); 5066 5067 /* vblendvpd, vblendvps, vblendvb use the imm encode the regs */ 5068 if ((dp == &dis_opAVX660F3A[0x4A]) || 5069 (dp == &dis_opAVX660F3A[0x4B]) || 5070 (dp == &dis_opAVX660F3A[0x4C])) { 5071 #ifdef DIS_TEXT 5072 int regnum = (x->d86_opnd[0].d86_value & 0xF0) >> 4; 5073 #endif 5074 x->d86_opnd[0].d86_mode = MODE_NONE; 5075 #ifdef DIS_TEXT 5076 if (vex_L) 5077 (void) strncpy(x->d86_opnd[0].d86_opnd, 5078 dis_YMMREG[regnum], OPLEN); 5079 else 5080 (void) strncpy(x->d86_opnd[0].d86_opnd, 5081 dis_XMMREG[regnum], OPLEN); 5082 #endif 5083 } 5084 break; 5085 5086 case VEX_MX: 5087 /* ModR/M.reg := op(ModR/M.rm) */ 5088 x->d86_numopnds = 2; 5089 5090 dtrace_get_modrm(x, &mode, ®, &r_m); 5091 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5092 L_VEX_MX: 5093 5094 if ((dp == &dis_opAVXF20F[0xE6]) || 5095 (dp == &dis_opAVX660F[0x5A]) || 5096 (dp == &dis_opAVX660F[0xE6])) { 5097 /* vcvtpd2dq <ymm>, <xmm> */ 5098 /* or vcvtpd2ps <ymm>, <xmm> */ 5099 /* or vcvttpd2dq <ymm>, <xmm> */ 5100 dtrace_get_operand(x, REG_ONLY, reg, XMM_OPND, 1); 5101 dtrace_get_operand(x, mode, r_m, wbit, 0); 5102 } else if ((dp == &dis_opAVXF30F[0xE6]) || 5103 (dp == &dis_opAVX0F[0x5][0xA]) || 5104 (dp == &dis_opAVX660F38[0x13]) || 5105 (dp == &dis_opAVX660F38[0x18]) || 5106 (dp == &dis_opAVX660F38[0x19]) || 5107 (dp == &dis_opAVX660F38[0x58]) || 5108 (dp == &dis_opAVX660F38[0x78]) || 5109 (dp == &dis_opAVX660F38[0x79]) || 5110 (dp == &dis_opAVX660F38[0x59])) { 5111 /* vcvtdq2pd <xmm>, <ymm> */ 5112 /* or vcvtps2pd <xmm>, <ymm> */ 5113 /* or vcvtph2ps <xmm>, <ymm> */ 5114 /* or vbroadcasts* <xmm>, <ymm> */ 5115 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5116 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0); 5117 } else if (dp == &dis_opAVX660F[0x6E]) { 5118 /* vmovd/q <reg/mem 32/64>, <xmm> */ 5119 #ifdef DIS_TEXT 5120 if (vex_W) 5121 x->d86_mnem[4] = 'q'; 5122 #endif 5123 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5124 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 5125 } else { 5126 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5127 dtrace_get_operand(x, mode, r_m, wbit, 0); 5128 } 5129 5130 break; 5131 5132 case VEX_MXI: 5133 /* ModR/M.reg := op(ModR/M.rm, imm8) */ 5134 x->d86_numopnds = 3; 5135 5136 dtrace_get_modrm(x, &mode, ®, &r_m); 5137 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5138 5139 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5140 dtrace_get_operand(x, mode, r_m, wbit, 1); 5141 5142 /* one byte immediate number */ 5143 dtrace_imm_opnd(x, wbit, 1, 0); 5144 break; 5145 5146 case VEX_XXI: 5147 /* VEX.vvvv := op(ModR/M.rm, imm8) */ 5148 x->d86_numopnds = 3; 5149 5150 dtrace_get_modrm(x, &mode, ®, &r_m); 5151 #ifdef DIS_TEXT 5152 (void) strncpy(x->d86_mnem, dis_AVXvgrp7[opcode2 - 1][reg], 5153 OPLEN); 5154 #endif 5155 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5156 5157 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2); 5158 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 1); 5159 5160 /* one byte immediate number */ 5161 dtrace_imm_opnd(x, wbit, 1, 0); 5162 break; 5163 5164 case VEX_MR: 5165 /* ModR/M.reg (reg32/64) := op(ModR/M.rm) */ 5166 if (dp == &dis_opAVX660F[0xC5]) { 5167 /* vpextrw <imm8>, <xmm>, <reg> */ 5168 x->d86_numopnds = 2; 5169 vbit = 2; 5170 } else { 5171 x->d86_numopnds = 2; 5172 vbit = 1; 5173 } 5174 5175 dtrace_get_modrm(x, &mode, ®, &r_m); 5176 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5177 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, vbit); 5178 dtrace_get_operand(x, mode, r_m, wbit, vbit - 1); 5179 5180 if (vbit == 2) 5181 dtrace_imm_opnd(x, wbit, 1, 0); 5182 5183 break; 5184 5185 case VEX_KMR: 5186 /* opmask: mod_rm := %k */ 5187 x->d86_numopnds = 2; 5188 dtrace_get_modrm(x, &mode, ®, &r_m); 5189 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5190 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 5191 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5192 break; 5193 5194 case VEX_KRM: 5195 /* opmask: mod_reg := mod_rm */ 5196 x->d86_numopnds = 2; 5197 dtrace_get_modrm(x, &mode, ®, &r_m); 5198 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5199 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5200 if (mode == REG_ONLY) { 5201 dtrace_get_operand(x, mode, r_m, KOPMASK_OPND, 0); 5202 } else { 5203 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 5204 } 5205 break; 5206 5207 case VEX_KRR: 5208 /* opmask: mod_reg := mod_rm */ 5209 x->d86_numopnds = 2; 5210 dtrace_get_modrm(x, &mode, ®, &r_m); 5211 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5212 dtrace_get_operand(x, mode, reg, wbit, 1); 5213 dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 0); 5214 break; 5215 5216 case VEX_RRI: 5217 /* implicit(eflags/r32) := op(ModR/M.reg, ModR/M.rm) */ 5218 x->d86_numopnds = 2; 5219 5220 dtrace_get_modrm(x, &mode, ®, &r_m); 5221 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5222 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5223 dtrace_get_operand(x, mode, r_m, wbit, 0); 5224 break; 5225 5226 case VEX_RX: 5227 /* ModR/M.rm := op(ModR/M.reg) */ 5228 /* vextractf128 || vcvtps2ph */ 5229 if (dp == &dis_opAVX660F3A[0x19] || 5230 dp == &dis_opAVX660F3A[0x1d]) { 5231 x->d86_numopnds = 3; 5232 5233 dtrace_get_modrm(x, &mode, ®, &r_m); 5234 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5235 5236 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2); 5237 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5238 5239 /* one byte immediate number */ 5240 dtrace_imm_opnd(x, wbit, 1, 0); 5241 break; 5242 } 5243 5244 x->d86_numopnds = 2; 5245 5246 dtrace_get_modrm(x, &mode, ®, &r_m); 5247 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5248 dtrace_get_operand(x, mode, r_m, wbit, 1); 5249 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5250 break; 5251 5252 case VEX_RR: 5253 /* ModR/M.rm := op(ModR/M.reg) */ 5254 x->d86_numopnds = 2; 5255 5256 dtrace_get_modrm(x, &mode, ®, &r_m); 5257 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5258 5259 if (dp == &dis_opAVX660F[0x7E]) { 5260 /* vmovd/q <reg/mem 32/64>, <xmm> */ 5261 #ifdef DIS_TEXT 5262 if (vex_W) 5263 x->d86_mnem[4] = 'q'; 5264 #endif 5265 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 5266 } else 5267 dtrace_get_operand(x, mode, r_m, wbit, 1); 5268 5269 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5270 break; 5271 5272 case VEX_RRi: 5273 /* ModR/M.rm := op(ModR/M.reg, imm) */ 5274 x->d86_numopnds = 3; 5275 5276 dtrace_get_modrm(x, &mode, ®, &r_m); 5277 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5278 5279 #ifdef DIS_TEXT 5280 if (dp == &dis_opAVX660F3A[0x16]) { 5281 /* vpextrd/q <imm>, <xmm>, <reg/mem 32/64> */ 5282 if (vex_W) 5283 x->d86_mnem[6] = 'q'; 5284 } 5285 #endif 5286 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2); 5287 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5288 5289 /* one byte immediate number */ 5290 dtrace_imm_opnd(x, wbit, 1, 0); 5291 break; 5292 case VEX_RIM: 5293 /* ModR/M.rm := op(ModR/M.reg, imm) */ 5294 x->d86_numopnds = 3; 5295 5296 dtrace_get_modrm(x, &mode, ®, &r_m); 5297 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5298 5299 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2); 5300 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5301 /* one byte immediate number */ 5302 dtrace_imm_opnd(x, wbit, 1, 0); 5303 break; 5304 5305 case VEX_RM: 5306 /* ModR/M.rm := op(ModR/M.reg) */ 5307 if (dp == &dis_opAVX660F3A[0x17]) { /* vextractps */ 5308 x->d86_numopnds = 3; 5309 5310 dtrace_get_modrm(x, &mode, ®, &r_m); 5311 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5312 5313 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2); 5314 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5315 /* one byte immediate number */ 5316 dtrace_imm_opnd(x, wbit, 1, 0); 5317 break; 5318 } 5319 x->d86_numopnds = 2; 5320 5321 dtrace_get_modrm(x, &mode, ®, &r_m); 5322 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5323 L_VEX_RM: 5324 vbit = 1; 5325 dtrace_get_operand(x, mode, r_m, wbit, vbit); 5326 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit - 1); 5327 5328 break; 5329 5330 case VEX_RRM: 5331 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */ 5332 x->d86_numopnds = 3; 5333 5334 dtrace_get_modrm(x, &mode, ®, &r_m); 5335 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5336 dtrace_get_operand(x, mode, r_m, wbit, 2); 5337 /* VEX use the 1's complement form encode the XMM/YMM regs */ 5338 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5339 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5340 break; 5341 5342 case VEX_RMX: 5343 /* ModR/M.reg := op(VEX.vvvv, ModR/M.rm) */ 5344 x->d86_numopnds = 3; 5345 5346 dtrace_get_modrm(x, &mode, ®, &r_m); 5347 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5348 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5349 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5350 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 0); 5351 break; 5352 5353 case VEX_NONE: 5354 #ifdef DIS_TEXT 5355 if (vex_L) 5356 (void) strncpy(x->d86_mnem, "vzeroall", OPLEN); 5357 #endif 5358 break; 5359 case BLS: { 5360 5361 /* 5362 * The BLS instructions are VEX instructions that are based on 5363 * VEX.0F38.F3; however, they are considered special group 17 5364 * and like everything else, they use the bits in 3-5 of the 5365 * MOD R/M to determine the sub instruction. Unlike many others 5366 * like the VMX instructions, these are valid both for memory 5367 * and register forms. 5368 */ 5369 5370 dtrace_get_modrm(x, &mode, ®, &r_m); 5371 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5372 5373 switch (reg) { 5374 case 1: 5375 #ifdef DIS_TEXT 5376 blsinstr = "blsr"; 5377 #endif 5378 break; 5379 case 2: 5380 #ifdef DIS_TEXT 5381 blsinstr = "blsmsk"; 5382 #endif 5383 break; 5384 case 3: 5385 #ifdef DIS_TEXT 5386 blsinstr = "blsi"; 5387 #endif 5388 break; 5389 default: 5390 goto error; 5391 } 5392 5393 x->d86_numopnds = 2; 5394 #ifdef DIS_TEXT 5395 (void) strncpy(x->d86_mnem, blsinstr, OPLEN); 5396 #endif 5397 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5398 dtrace_get_operand(x, mode, r_m, wbit, 0); 5399 break; 5400 } 5401 /* an invalid op code */ 5402 case AM: 5403 case DM: 5404 case OVERRIDE: 5405 case PREFIX: 5406 case UNKNOWN: 5407 NOMEM; 5408 default: 5409 goto error; 5410 } /* end switch */ 5411 if (x->d86_error) 5412 goto error; 5413 5414 done: 5415 #ifdef DIS_MEM 5416 /* 5417 * compute the size of any memory accessed by the instruction 5418 */ 5419 if (x->d86_memsize != 0) { 5420 return (0); 5421 } else if (dp->it_stackop) { 5422 switch (opnd_size) { 5423 case SIZE16: 5424 x->d86_memsize = 2; 5425 break; 5426 case SIZE32: 5427 x->d86_memsize = 4; 5428 break; 5429 case SIZE64: 5430 x->d86_memsize = 8; 5431 break; 5432 } 5433 } else if (nomem || mode == REG_ONLY) { 5434 x->d86_memsize = 0; 5435 5436 } else if (dp->it_size != 0) { 5437 /* 5438 * In 64 bit mode descriptor table entries 5439 * go up to 10 bytes and popf/pushf are always 8 bytes 5440 */ 5441 if (x->d86_mode == SIZE64 && dp->it_size == 6) 5442 x->d86_memsize = 10; 5443 else if (x->d86_mode == SIZE64 && opcode1 == 0x9 && 5444 (opcode2 == 0xc || opcode2 == 0xd)) 5445 x->d86_memsize = 8; 5446 else 5447 x->d86_memsize = dp->it_size; 5448 5449 } else if (wbit == 0) { 5450 x->d86_memsize = 1; 5451 5452 } else if (wbit == LONG_OPND) { 5453 if (opnd_size == SIZE64) 5454 x->d86_memsize = 8; 5455 else if (opnd_size == SIZE32) 5456 x->d86_memsize = 4; 5457 else 5458 x->d86_memsize = 2; 5459 5460 } else if (wbit == SEG_OPND) { 5461 x->d86_memsize = 4; 5462 5463 } else { 5464 x->d86_memsize = 8; 5465 } 5466 #endif 5467 return (0); 5468 5469 error: 5470 #ifdef DIS_TEXT 5471 (void) strlcat(x->d86_mnem, "undef", OPLEN); 5472 #endif 5473 return (1); 5474 } 5475 5476 #ifdef DIS_TEXT 5477 5478 /* 5479 * Some instructions should have immediate operands printed 5480 * as unsigned integers. We compare against this table. 5481 */ 5482 static char *unsigned_ops[] = { 5483 "or", "and", "xor", "test", "in", "out", "lcall", "ljmp", 5484 "rcr", "rcl", "ror", "rol", "shl", "shr", "sal", "psr", "psl", 5485 0 5486 }; 5487 5488 5489 static int 5490 isunsigned_op(char *opcode) 5491 { 5492 char *where; 5493 int i; 5494 int is_unsigned = 0; 5495 5496 /* 5497 * Work back to start of last mnemonic, since we may have 5498 * prefixes on some opcodes. 5499 */ 5500 where = opcode + strlen(opcode) - 1; 5501 while (where > opcode && *where != ' ') 5502 --where; 5503 if (*where == ' ') 5504 ++where; 5505 5506 for (i = 0; unsigned_ops[i]; ++i) { 5507 if (strncmp(where, unsigned_ops[i], 5508 strlen(unsigned_ops[i]))) 5509 continue; 5510 is_unsigned = 1; 5511 break; 5512 } 5513 return (is_unsigned); 5514 } 5515 5516 /* 5517 * Print a numeric immediate into end of buf, maximum length buflen. 5518 * The immediate may be an address or a displacement. Mask is set 5519 * for address size. If the immediate is a "small negative", or 5520 * if it's a negative displacement of any magnitude, print as -<absval>. 5521 * Respect the "octal" flag. "Small negative" is defined as "in the 5522 * interval [NEG_LIMIT, 0)". 5523 * 5524 * Also, "isunsigned_op()" instructions never print negatives. 5525 * 5526 * Return whether we decided to print a negative value or not. 5527 */ 5528 5529 #define NEG_LIMIT -255 5530 enum {IMM, DISP}; 5531 enum {POS, TRY_NEG}; 5532 5533 static int 5534 print_imm(dis86_t *dis, uint64_t usv, uint64_t mask, char *buf, 5535 size_t buflen, int disp, int try_neg) 5536 { 5537 int curlen; 5538 int64_t sv = (int64_t)usv; 5539 int octal = dis->d86_flags & DIS_F_OCTAL; 5540 5541 curlen = strlen(buf); 5542 5543 if (try_neg == TRY_NEG && sv < 0 && 5544 (disp || sv >= NEG_LIMIT) && 5545 !isunsigned_op(dis->d86_mnem)) { 5546 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 5547 octal ? "-0%llo" : "-0x%llx", (-sv) & mask); 5548 return (1); 5549 } else { 5550 if (disp == DISP) 5551 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 5552 octal ? "+0%llo" : "+0x%llx", usv & mask); 5553 else 5554 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 5555 octal ? "0%llo" : "0x%llx", usv & mask); 5556 return (0); 5557 5558 } 5559 } 5560 5561 5562 static int 5563 log2(int size) 5564 { 5565 switch (size) { 5566 case 1: return (0); 5567 case 2: return (1); 5568 case 4: return (2); 5569 case 8: return (3); 5570 } 5571 return (0); 5572 } 5573 5574 /* ARGSUSED */ 5575 void 5576 dtrace_disx86_str(dis86_t *dis, uint_t mode, uint64_t pc, char *buf, 5577 size_t buflen) 5578 { 5579 uint64_t reltgt = 0; 5580 uint64_t tgt = 0; 5581 int curlen; 5582 int (*lookup)(void *, uint64_t, char *, size_t); 5583 int i; 5584 int64_t sv; 5585 uint64_t usv, mask, save_mask, save_usv; 5586 static uint64_t masks[] = 5587 {0xffU, 0xffffU, 0xffffffffU, 0xffffffffffffffffULL}; 5588 save_usv = 0; 5589 5590 dis->d86_sprintf_func(buf, buflen, "%-6s ", dis->d86_mnem); 5591 5592 /* 5593 * For PC-relative jumps, the pc is really the next pc after executing 5594 * this instruction, so increment it appropriately. 5595 */ 5596 pc += dis->d86_len; 5597 5598 for (i = 0; i < dis->d86_numopnds; i++) { 5599 d86opnd_t *op = &dis->d86_opnd[i]; 5600 5601 if (i != 0) 5602 (void) strlcat(buf, ",", buflen); 5603 5604 (void) strlcat(buf, op->d86_prefix, buflen); 5605 5606 /* 5607 * sv is for the signed, possibly-truncated immediate or 5608 * displacement; usv retains the original size and 5609 * unsignedness for symbol lookup. 5610 */ 5611 5612 sv = usv = op->d86_value; 5613 5614 /* 5615 * About masks: for immediates that represent 5616 * addresses, the appropriate display size is 5617 * the effective address size of the instruction. 5618 * This includes MODE_OFFSET, MODE_IPREL, and 5619 * MODE_RIPREL. Immediates that are simply 5620 * immediate values should display in the operand's 5621 * size, however, since they don't represent addresses. 5622 */ 5623 5624 /* d86_addr_size is SIZEnn, which is log2(real size) */ 5625 mask = masks[dis->d86_addr_size]; 5626 5627 /* d86_value_size and d86_imm_bytes are in bytes */ 5628 if (op->d86_mode == MODE_SIGNED || 5629 op->d86_mode == MODE_IMPLIED) 5630 mask = masks[log2(op->d86_value_size)]; 5631 5632 switch (op->d86_mode) { 5633 5634 case MODE_NONE: 5635 5636 (void) strlcat(buf, op->d86_opnd, buflen); 5637 break; 5638 5639 case MODE_SIGNED: 5640 case MODE_IMPLIED: 5641 case MODE_OFFSET: 5642 5643 tgt = usv; 5644 5645 if (dis->d86_seg_prefix) 5646 (void) strlcat(buf, dis->d86_seg_prefix, 5647 buflen); 5648 5649 if (op->d86_mode == MODE_SIGNED || 5650 op->d86_mode == MODE_IMPLIED) { 5651 (void) strlcat(buf, "$", buflen); 5652 } 5653 5654 if (print_imm(dis, usv, mask, buf, buflen, 5655 IMM, TRY_NEG) && 5656 (op->d86_mode == MODE_SIGNED || 5657 op->d86_mode == MODE_IMPLIED)) { 5658 5659 /* 5660 * We printed a negative value for an 5661 * immediate that wasn't a 5662 * displacement. Note that fact so we can 5663 * print the positive value as an 5664 * annotation. 5665 */ 5666 5667 save_usv = usv; 5668 save_mask = mask; 5669 } 5670 (void) strlcat(buf, op->d86_opnd, buflen); 5671 5672 break; 5673 5674 case MODE_IPREL: 5675 case MODE_RIPREL: 5676 5677 reltgt = pc + sv; 5678 5679 switch (mode) { 5680 case SIZE16: 5681 reltgt = (uint16_t)reltgt; 5682 break; 5683 case SIZE32: 5684 reltgt = (uint32_t)reltgt; 5685 break; 5686 } 5687 5688 (void) print_imm(dis, usv, mask, buf, buflen, 5689 DISP, TRY_NEG); 5690 5691 if (op->d86_mode == MODE_RIPREL) 5692 (void) strlcat(buf, "(%rip)", buflen); 5693 break; 5694 } 5695 } 5696 5697 /* 5698 * The symbol lookups may result in false positives, 5699 * particularly on object files, where small numbers may match 5700 * the 0-relative non-relocated addresses of symbols. 5701 */ 5702 5703 lookup = dis->d86_sym_lookup; 5704 if (tgt != 0) { 5705 if ((dis->d86_flags & DIS_F_NOIMMSYM) == 0 && 5706 lookup(dis->d86_data, tgt, NULL, 0) == 0) { 5707 (void) strlcat(buf, "\t<", buflen); 5708 curlen = strlen(buf); 5709 lookup(dis->d86_data, tgt, buf + curlen, 5710 buflen - curlen); 5711 (void) strlcat(buf, ">", buflen); 5712 } 5713 5714 /* 5715 * If we printed a negative immediate above, print the 5716 * positive in case our heuristic was unhelpful 5717 */ 5718 if (save_usv) { 5719 (void) strlcat(buf, "\t<", buflen); 5720 (void) print_imm(dis, save_usv, save_mask, buf, buflen, 5721 IMM, POS); 5722 (void) strlcat(buf, ">", buflen); 5723 } 5724 } 5725 5726 if (reltgt != 0) { 5727 /* Print symbol or effective address for reltgt */ 5728 5729 (void) strlcat(buf, "\t<", buflen); 5730 curlen = strlen(buf); 5731 lookup(dis->d86_data, reltgt, buf + curlen, 5732 buflen - curlen); 5733 (void) strlcat(buf, ">", buflen); 5734 } 5735 } 5736 5737 #endif /* DIS_TEXT */ 5738