1 /* 2 * 3 * CDDL HEADER START 4 * 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright (c) 2011, Joyent, Inc. All rights reserved. 25 */ 26 27 /* 28 * Copyright (c) 2010, Intel Corporation. 29 * All rights reserved. 30 */ 31 32 /* Copyright (c) 1988 AT&T */ 33 /* All Rights Reserved */ 34 35 36 #include "dis_tables.h" 37 38 /* BEGIN CSTYLED */ 39 40 /* 41 * Disassembly begins in dis_distable, which is equivalent to the One-byte 42 * Opcode Map in the Intel IA32 ISA Reference (page A-6 in my copy). The 43 * decoding loops then traverse out through the other tables as necessary to 44 * decode a given instruction. 45 * 46 * The behavior of this file can be controlled by one of the following flags: 47 * 48 * DIS_TEXT Include text for disassembly 49 * DIS_MEM Include memory-size calculations 50 * 51 * Either or both of these can be defined. 52 * 53 * This file is not, and will never be, cstyled. If anything, the tables should 54 * be taken out another tab stop or two so nothing overlaps. 55 */ 56 57 /* 58 * These functions must be provided for the consumer to do disassembly. 59 */ 60 #ifdef DIS_TEXT 61 extern char *strncpy(char *, const char *, size_t); 62 extern size_t strlen(const char *); 63 extern int strcmp(const char *, const char *); 64 extern int strncmp(const char *, const char *, size_t); 65 extern size_t strlcat(char *, const char *, size_t); 66 #endif 67 68 69 #define TERM 0 /* used to indicate that the 'indirect' */ 70 /* field terminates - no pointer. */ 71 72 /* Used to decode instructions. */ 73 typedef struct instable { 74 struct instable *it_indirect; /* for decode op codes */ 75 uchar_t it_adrmode; 76 #ifdef DIS_TEXT 77 char it_name[NCPS]; 78 uint_t it_suffix:1; /* mnem + "w", "l", or "d" */ 79 #endif 80 #ifdef DIS_MEM 81 uint_t it_size:16; 82 #endif 83 uint_t it_invalid64:1; /* opcode invalid in amd64 */ 84 uint_t it_always64:1; /* 64 bit when in 64 bit mode */ 85 uint_t it_invalid32:1; /* invalid in IA32 */ 86 uint_t it_stackop:1; /* push/pop stack operation */ 87 } instable_t; 88 89 /* 90 * Instruction formats. 91 */ 92 enum { 93 UNKNOWN, 94 MRw, 95 IMlw, 96 IMw, 97 IR, 98 OA, 99 AO, 100 MS, 101 SM, 102 Mv, 103 Mw, 104 M, /* register or memory */ 105 MG9, /* register or memory in group 9 (prefix optional) */ 106 Mb, /* register or memory, always byte sized */ 107 MO, /* memory only (no registers) */ 108 PREF, 109 SWAPGS, 110 MONITOR_MWAIT, 111 R, 112 RA, 113 SEG, 114 MR, 115 RM, 116 RM_66r, /* RM, but with a required 0x66 prefix */ 117 IA, 118 MA, 119 SD, 120 AD, 121 SA, 122 D, 123 INM, 124 SO, 125 BD, 126 I, 127 P, 128 V, 129 DSHIFT, /* for double shift that has an 8-bit immediate */ 130 U, 131 OVERRIDE, 132 NORM, /* instructions w/o ModR/M byte, no memory access */ 133 IMPLMEM, /* instructions w/o ModR/M byte, implicit mem access */ 134 O, /* for call */ 135 JTAB, /* jump table */ 136 IMUL, /* for 186 iimul instr */ 137 CBW, /* so data16 can be evaluated for cbw and variants */ 138 MvI, /* for 186 logicals */ 139 ENTER, /* for 186 enter instr */ 140 RMw, /* for 286 arpl instr */ 141 Ib, /* for push immediate byte */ 142 F, /* for 287 instructions */ 143 FF, /* for 287 instructions */ 144 FFC, /* for 287 instructions */ 145 DM, /* 16-bit data */ 146 AM, /* 16-bit addr */ 147 LSEG, /* for 3-bit seg reg encoding */ 148 MIb, /* for 386 logicals */ 149 SREG, /* for 386 special registers */ 150 PREFIX, /* a REP instruction prefix */ 151 LOCK, /* a LOCK instruction prefix */ 152 INT3, /* The int 3 instruction, which has a fake operand */ 153 INTx, /* The normal int instruction, with explicit int num */ 154 DSHIFTcl, /* for double shift that implicitly uses %cl */ 155 CWD, /* so data16 can be evaluated for cwd and variants */ 156 RET, /* single immediate 16-bit operand */ 157 MOVZ, /* for movs and movz, with different size operands */ 158 CRC32, /* for crc32, with different size operands */ 159 XADDB, /* for xaddb */ 160 MOVSXZ, /* AMD64 mov sign extend 32 to 64 bit instruction */ 161 MOVBE, /* movbe instruction */ 162 163 /* 164 * MMX/SIMD addressing modes. 165 */ 166 167 MMO, /* Prefixable MMX/SIMD-Int mm/mem -> mm */ 168 MMOIMPL, /* Prefixable MMX/SIMD-Int mm -> mm (mem) */ 169 MMO3P, /* Prefixable MMX/SIMD-Int mm -> r32,imm8 */ 170 MMOM3, /* Prefixable MMX/SIMD-Int mm -> r32 */ 171 MMOS, /* Prefixable MMX/SIMD-Int mm -> mm/mem */ 172 MMOMS, /* Prefixable MMX/SIMD-Int mm -> mem */ 173 MMOPM, /* MMX/SIMD-Int mm/mem -> mm,imm8 */ 174 MMOPM_66o, /* MMX/SIMD-Int 0x66 optional mm/mem -> mm,imm8 */ 175 MMOPRM, /* Prefixable MMX/SIMD-Int r32/mem -> mm,imm8 */ 176 MMOSH, /* Prefixable MMX mm,imm8 */ 177 MM, /* MMX/SIMD-Int mm/mem -> mm */ 178 MMS, /* MMX/SIMD-Int mm -> mm/mem */ 179 MMSH, /* MMX mm,imm8 */ 180 XMMO, /* Prefixable SIMD xmm/mem -> xmm */ 181 XMMOS, /* Prefixable SIMD xmm -> xmm/mem */ 182 XMMOPM, /* Prefixable SIMD xmm/mem w/to xmm,imm8 */ 183 XMMOMX, /* Prefixable SIMD mm/mem -> xmm */ 184 XMMOX3, /* Prefixable SIMD xmm -> r32 */ 185 XMMOXMM, /* Prefixable SIMD xmm/mem -> mm */ 186 XMMOM, /* Prefixable SIMD xmm -> mem */ 187 XMMOMS, /* Prefixable SIMD mem -> xmm */ 188 XMM, /* SIMD xmm/mem -> xmm */ 189 XMM_66r, /* SIMD 0x66 prefix required xmm/mem -> xmm */ 190 XMM_66o, /* SIMD 0x66 prefix optional xmm/mem -> xmm */ 191 XMMXIMPL, /* SIMD xmm -> xmm (mem) */ 192 XMM3P, /* SIMD xmm -> r32,imm8 */ 193 XMM3PM_66r, /* SIMD 0x66 prefix required xmm -> r32/mem,imm8 */ 194 XMMP, /* SIMD xmm/mem w/to xmm,imm8 */ 195 XMMP_66o, /* SIMD 0x66 prefix optional xmm/mem w/to xmm,imm8 */ 196 XMMP_66r, /* SIMD 0x66 prefix required xmm/mem w/to xmm,imm8 */ 197 XMMPRM, /* SIMD r32/mem -> xmm,imm8 */ 198 XMMPRM_66r, /* SIMD 0x66 prefix required r32/mem -> xmm,imm8 */ 199 XMMS, /* SIMD xmm -> xmm/mem */ 200 XMMM, /* SIMD mem -> xmm */ 201 XMMM_66r, /* SIMD 0x66 prefix required mem -> xmm */ 202 XMMMS, /* SIMD xmm -> mem */ 203 XMM3MX, /* SIMD r32/mem -> xmm */ 204 XMM3MXS, /* SIMD xmm -> r32/mem */ 205 XMMSH, /* SIMD xmm,imm8 */ 206 XMMXM3, /* SIMD xmm/mem -> r32 */ 207 XMMX3, /* SIMD xmm -> r32 */ 208 XMMXMM, /* SIMD xmm/mem -> mm */ 209 XMMMX, /* SIMD mm -> xmm */ 210 XMMXM, /* SIMD xmm -> mm */ 211 XMMX2I, /* SIMD xmm -> xmm, imm, imm */ 212 XMM2I, /* SIMD xmm, imm, imm */ 213 XMMFENCE, /* SIMD lfence or mfence */ 214 XMMSFNC, /* SIMD sfence (none or mem) */ 215 XGETBV_XSETBV, 216 VEX_NONE, /* VEX no operand */ 217 VEX_MO, /* VEX mod_rm -> implicit reg */ 218 VEX_RMrX, /* VEX VEX.vvvv, mod_rm -> mod_reg */ 219 VEX_RRX, /* VEX VEX.vvvv, mod_reg -> mod_rm */ 220 VEX_RMRX, /* VEX VEX.vvvv, mod_rm, imm8[7:4] -> mod_reg */ 221 VEX_MX, /* VEX mod_rm -> mod_reg */ 222 VEX_MXI, /* VEX mod_rm, imm8 -> mod_reg */ 223 VEX_XXI, /* VEX mod_rm, imm8 -> VEX.vvvv */ 224 VEX_MR, /* VEX mod_rm -> mod_reg */ 225 VEX_RRI, /* VEX mod_reg, mod_rm -> implicit(eflags/r32) */ 226 VEX_RX, /* VEX mod_reg -> mod_rm */ 227 VEX_RR, /* VEX mod_rm -> mod_reg */ 228 VEX_RRi, /* VEX mod_rm, imm8 -> mod_reg */ 229 VEX_RM, /* VEX mod_reg -> mod_rm */ 230 VEX_RRM, /* VEX VEX.vvvv, mod_reg -> mod_rm */ 231 VEX_RMX, /* VEX VEX.vvvv, mod_rm -> mod_reg */ 232 VMx, /* vmcall/vmlaunch/vmresume/vmxoff */ 233 VMxo /* VMx instruction with optional prefix */ 234 }; 235 236 /* 237 * VEX prefixes 238 */ 239 #define VEX_2bytes 0xC5 /* the first byte of two-byte form */ 240 #define VEX_3bytes 0xC4 /* the first byte of three-byte form */ 241 242 #define FILL 0x90 /* Fill byte used for alignment (nop) */ 243 244 /* 245 ** Register numbers for the i386 246 */ 247 #define EAX_REGNO 0 248 #define ECX_REGNO 1 249 #define EDX_REGNO 2 250 #define EBX_REGNO 3 251 #define ESP_REGNO 4 252 #define EBP_REGNO 5 253 #define ESI_REGNO 6 254 #define EDI_REGNO 7 255 256 /* 257 * modes for immediate values 258 */ 259 #define MODE_NONE 0 260 #define MODE_IPREL 1 /* signed IP relative value */ 261 #define MODE_SIGNED 2 /* sign extended immediate */ 262 #define MODE_IMPLIED 3 /* constant value implied from opcode */ 263 #define MODE_OFFSET 4 /* offset part of an address */ 264 #define MODE_RIPREL 5 /* like IPREL, but from %rip (amd64) */ 265 266 /* 267 * The letters used in these macros are: 268 * IND - indirect to another to another table 269 * "T" - means to Terminate indirections (this is the final opcode) 270 * "S" - means "operand length suffix required" 271 * "NS" - means "no suffix" which is the operand length suffix of the opcode 272 * "Z" - means instruction size arg required 273 * "u" - means the opcode is invalid in IA32 but valid in amd64 274 * "x" - means the opcode is invalid in amd64, but not IA32 275 * "y" - means the operand size is always 64 bits in 64 bit mode 276 * "p" - means push/pop stack operation 277 */ 278 279 #if defined(DIS_TEXT) && defined(DIS_MEM) 280 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0, 0} 281 #define INDx(table) {(instable_t *)table, 0, "", 0, 0, 1, 0, 0, 0} 282 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0} 283 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 0, 1, 0} 284 #define TNSx(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0, 0} 285 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 0} 286 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 1} 287 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0} 288 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, sz, 0, 1, 0, 0} 289 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0} 290 #define TSx(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0, 0} 291 #define TSy(name, amode) {TERM, amode, name, 1, 0, 0, 1, 0, 0} 292 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 1} 293 #define TSZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0} 294 #define TSZx(name, amode, sz) {TERM, amode, name, 1, sz, 1, 0, 0, 0} 295 #define TSZy(name, amode, sz) {TERM, amode, name, 1, sz, 0, 1, 0, 0} 296 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0} 297 #elif defined(DIS_TEXT) 298 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0} 299 #define INDx(table) {(instable_t *)table, 0, "", 0, 1, 0, 0, 0} 300 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0} 301 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0} 302 #define TNSx(name, amode) {TERM, amode, name, 0, 1, 0, 0, 0} 303 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0} 304 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 1, 0, 1} 305 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0} 306 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, 0, 1, 0, 0} 307 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0} 308 #define TSx(name, amode) {TERM, amode, name, 1, 1, 0, 0, 0} 309 #define TSy(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0} 310 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 1} 311 #define TSZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0} 312 #define TSZx(name, amode, sz) {TERM, amode, name, 1, 1, 0, 0, 0} 313 #define TSZy(name, amode, sz) {TERM, amode, name, 1, 0, 1, 0, 0} 314 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0} 315 #elif defined(DIS_MEM) 316 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0, 0} 317 #define INDx(table) {(instable_t *)table, 0, 0, 1, 0, 0, 0} 318 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0, 0} 319 #define TNSu(name, amode) {TERM, amode, 0, 0, 0, 1, 0} 320 #define TNSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0} 321 #define TNSyp(name, amode) {TERM, amode, 0, 0, 1, 0, 1} 322 #define TNSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0} 323 #define TNSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0} 324 #define TNSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0} 325 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0, 0} 326 #define TSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0} 327 #define TSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0} 328 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 0, 1} 329 #define TSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0} 330 #define TSZx(name, amode, sz) {TERM, amode, sz, 1, 0, 0, 0} 331 #define TSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0} 332 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0, 0} 333 #else 334 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0} 335 #define INDx(table) {(instable_t *)table, 0, 1, 0, 0, 0} 336 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0} 337 #define TNSu(name, amode) {TERM, amode, 0, 0, 1, 0} 338 #define TNSy(name, amode) {TERM, amode, 0, 1, 0, 0} 339 #define TNSyp(name, amode) {TERM, amode, 0, 1, 0, 1} 340 #define TNSx(name, amode) {TERM, amode, 1, 0, 0, 0} 341 #define TNSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0} 342 #define TNSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0} 343 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0} 344 #define TSx(name, amode) {TERM, amode, 1, 0, 0, 0} 345 #define TSy(name, amode) {TERM, amode, 0, 1, 0, 0} 346 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 1} 347 #define TSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0} 348 #define TSZx(name, amode, sz) {TERM, amode, 1, 0, 0, 0} 349 #define TSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0} 350 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0} 351 #endif 352 353 #ifdef DIS_TEXT 354 /* 355 * this decodes the r_m field for mode's 0, 1, 2 in 16 bit mode 356 */ 357 const char *const dis_addr16[3][8] = { 358 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "", 359 "(%bx)", 360 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di", "(%bp)", 361 "(%bx)", 362 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "(%bp)", 363 "(%bx)", 364 }; 365 366 367 /* 368 * This decodes 32 bit addressing mode r_m field for modes 0, 1, 2 369 */ 370 const char *const dis_addr32_mode0[16] = { 371 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "", "(%esi)", "(%edi)", 372 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "", "(%r14d)", "(%r15d)" 373 }; 374 375 const char *const dis_addr32_mode12[16] = { 376 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "(%ebp)", "(%esi)", "(%edi)", 377 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "(%r13d)", "(%r14d)", "(%r15d)" 378 }; 379 380 /* 381 * This decodes 64 bit addressing mode r_m field for modes 0, 1, 2 382 */ 383 const char *const dis_addr64_mode0[16] = { 384 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rip)", "(%rsi)", "(%rdi)", 385 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%rip)", "(%r14)", "(%r15)" 386 }; 387 const char *const dis_addr64_mode12[16] = { 388 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rbp)", "(%rsi)", "(%rdi)", 389 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%r13)", "(%r14)", "(%r15)" 390 }; 391 392 /* 393 * decode for scale from SIB byte 394 */ 395 const char *const dis_scale_factor[4] = { ")", ",2)", ",4)", ",8)" }; 396 397 /* 398 * register decoding for normal references to registers (ie. not addressing) 399 */ 400 const char *const dis_REG8[16] = { 401 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", 402 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 403 }; 404 405 const char *const dis_REG8_REX[16] = { 406 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", 407 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 408 }; 409 410 const char *const dis_REG16[16] = { 411 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", 412 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" 413 }; 414 415 const char *const dis_REG32[16] = { 416 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", 417 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" 418 }; 419 420 const char *const dis_REG64[16] = { 421 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", 422 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" 423 }; 424 425 const char *const dis_DEBUGREG[16] = { 426 "%db0", "%db1", "%db2", "%db3", "%db4", "%db5", "%db6", "%db7", 427 "%db8", "%db9", "%db10", "%db11", "%db12", "%db13", "%db14", "%db15" 428 }; 429 430 const char *const dis_CONTROLREG[16] = { 431 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5?", "%cr6?", "%cr7?", 432 "%cr8", "%cr9?", "%cr10?", "%cr11?", "%cr12?", "%cr13?", "%cr14?", "%cr15?" 433 }; 434 435 const char *const dis_TESTREG[16] = { 436 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7", 437 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7" 438 }; 439 440 const char *const dis_MMREG[16] = { 441 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7", 442 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7" 443 }; 444 445 const char *const dis_XMMREG[16] = { 446 "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7", 447 "%xmm8", "%xmm9", "%xmm10", "%xmm11", "%xmm12", "%xmm13", "%xmm14", "%xmm15" 448 }; 449 450 const char *const dis_YMMREG[16] = { 451 "%ymm0", "%ymm1", "%ymm2", "%ymm3", "%ymm4", "%ymm5", "%ymm6", "%ymm7", 452 "%ymm8", "%ymm9", "%ymm10", "%ymm11", "%ymm12", "%ymm13", "%ymm14", "%ymm15" 453 }; 454 455 const char *const dis_SEGREG[16] = { 456 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>", 457 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>" 458 }; 459 460 /* 461 * SIMD predicate suffixes 462 */ 463 const char *const dis_PREDSUFFIX[8] = { 464 "eq", "lt", "le", "unord", "neq", "nlt", "nle", "ord" 465 }; 466 467 const char *const dis_AVXvgrp7[3][8] = { 468 /*0 1 2 3 4 5 6 7*/ 469 /*71*/ {"", "", "vpsrlw", "", "vpsraw", "", "vpsllw", ""}, 470 /*72*/ {"", "", "vpsrld", "", "vpsrad", "", "vpslld", ""}, 471 /*73*/ {"", "", "vpsrlq", "vpsrldq", "", "", "vpsllq", "vpslldq"} 472 }; 473 474 #endif /* DIS_TEXT */ 475 476 /* 477 * "decode table" for 64 bit mode MOVSXD instruction (opcode 0x63) 478 */ 479 const instable_t dis_opMOVSLD = TNS("movslq",MOVSXZ); 480 481 /* 482 * "decode table" for pause and clflush instructions 483 */ 484 const instable_t dis_opPause = TNS("pause", NORM); 485 486 /* 487 * Decode table for 0x0F00 opcodes 488 */ 489 const instable_t dis_op0F00[8] = { 490 491 /* [0] */ TNS("sldt",M), TNS("str",M), TNSy("lldt",M), TNSy("ltr",M), 492 /* [4] */ TNSZ("verr",M,2), TNSZ("verw",M,2), INVALID, INVALID, 493 }; 494 495 496 /* 497 * Decode table for 0x0F01 opcodes 498 */ 499 const instable_t dis_op0F01[8] = { 500 501 /* [0] */ TNSZ("sgdt",VMx,6), TNSZ("sidt",MONITOR_MWAIT,6), TNSZ("lgdt",XGETBV_XSETBV,6), TNSZ("lidt",MO,6), 502 /* [4] */ TNSZ("smsw",M,2), INVALID, TNSZ("lmsw",M,2), TNS("invlpg",SWAPGS), 503 }; 504 505 /* 506 * Decode table for 0x0F18 opcodes -- SIMD prefetch 507 */ 508 const instable_t dis_op0F18[8] = { 509 510 /* [0] */ TNS("prefetchnta",PREF),TNS("prefetcht0",PREF), TNS("prefetcht1",PREF), TNS("prefetcht2",PREF), 511 /* [4] */ INVALID, INVALID, INVALID, INVALID, 512 }; 513 514 /* 515 * Decode table for 0x0FAE opcodes -- SIMD state save/restore 516 */ 517 const instable_t dis_op0FAE[8] = { 518 /* [0] */ TNSZ("fxsave",M,512), TNSZ("fxrstor",M,512), TNS("ldmxcsr",M), TNS("stmxcsr",M), 519 /* [4] */ TNSZ("xsave",M,512), TNS("lfence",XMMFENCE), TNS("mfence",XMMFENCE), TNS("sfence",XMMSFNC), 520 }; 521 522 /* 523 * Decode table for 0x0FBA opcodes 524 */ 525 526 const instable_t dis_op0FBA[8] = { 527 528 /* [0] */ INVALID, INVALID, INVALID, INVALID, 529 /* [4] */ TS("bt",MIb), TS("bts",MIb), TS("btr",MIb), TS("btc",MIb), 530 }; 531 532 /* 533 * Decode table for 0x0FC7 opcode (group 9) 534 */ 535 536 const instable_t dis_op0FC7[8] = { 537 538 /* [0] */ INVALID, TNS("cmpxchg8b",M), INVALID, INVALID, 539 /* [4] */ INVALID, INVALID, TNS("vmptrld",MG9), TNS("vmptrst",MG9), 540 }; 541 542 /* 543 * Decode table for 0x0FC7 opcode with 0x66 prefix 544 */ 545 546 const instable_t dis_op660FC7[8] = { 547 548 /* [0] */ INVALID, INVALID, INVALID, INVALID, 549 /* [4] */ INVALID, INVALID, TNS("vmclear",M), INVALID, 550 }; 551 552 /* 553 * Decode table for 0x0FC7 opcode with 0xF3 prefix 554 */ 555 556 const instable_t dis_opF30FC7[8] = { 557 558 /* [0] */ INVALID, INVALID, INVALID, INVALID, 559 /* [4] */ INVALID, INVALID, TNS("vmxon",M), INVALID, 560 }; 561 562 /* 563 * Decode table for 0x0FC8 opcode -- 486 bswap instruction 564 * 565 *bit pattern: 0000 1111 1100 1reg 566 */ 567 const instable_t dis_op0FC8[4] = { 568 /* [0] */ TNS("bswap",R), INVALID, INVALID, INVALID, 569 }; 570 571 /* 572 * Decode table for 0x0F71, 0x0F72, and 0x0F73 opcodes -- MMX instructions 573 */ 574 const instable_t dis_op0F7123[4][8] = { 575 { 576 /* [70].0 */ INVALID, INVALID, INVALID, INVALID, 577 /* .4 */ INVALID, INVALID, INVALID, INVALID, 578 }, { 579 /* [71].0 */ INVALID, INVALID, TNS("psrlw",MMOSH), INVALID, 580 /* .4 */ TNS("psraw",MMOSH), INVALID, TNS("psllw",MMOSH), INVALID, 581 }, { 582 /* [72].0 */ INVALID, INVALID, TNS("psrld",MMOSH), INVALID, 583 /* .4 */ TNS("psrad",MMOSH), INVALID, TNS("pslld",MMOSH), INVALID, 584 }, { 585 /* [73].0 */ INVALID, INVALID, TNS("psrlq",MMOSH), TNS("INVALID",MMOSH), 586 /* .4 */ INVALID, INVALID, TNS("psllq",MMOSH), TNS("INVALID",MMOSH), 587 } }; 588 589 /* 590 * Decode table for SIMD extensions to above 0x0F71-0x0F73 opcodes. 591 */ 592 const instable_t dis_opSIMD7123[32] = { 593 /* [70].0 */ INVALID, INVALID, INVALID, INVALID, 594 /* .4 */ INVALID, INVALID, INVALID, INVALID, 595 596 /* [71].0 */ INVALID, INVALID, TNS("psrlw",XMMSH), INVALID, 597 /* .4 */ TNS("psraw",XMMSH), INVALID, TNS("psllw",XMMSH), INVALID, 598 599 /* [72].0 */ INVALID, INVALID, TNS("psrld",XMMSH), INVALID, 600 /* .4 */ TNS("psrad",XMMSH), INVALID, TNS("pslld",XMMSH), INVALID, 601 602 /* [73].0 */ INVALID, INVALID, TNS("psrlq",XMMSH), TNS("psrldq",XMMSH), 603 /* .4 */ INVALID, INVALID, TNS("psllq",XMMSH), TNS("pslldq",XMMSH), 604 }; 605 606 /* 607 * SIMD instructions have been wedged into the existing IA32 instruction 608 * set through the use of prefixes. That is, while 0xf0 0x58 may be 609 * addps, 0xf3 0xf0 0x58 (literally, repz addps) is a completely different 610 * instruction - addss. At present, three prefixes have been coopted in 611 * this manner - address size (0x66), repnz (0xf2) and repz (0xf3). The 612 * following tables are used to provide the prefixed instruction names. 613 * The arrays are sparse, but they're fast. 614 */ 615 616 /* 617 * Decode table for SIMD instructions with the address size (0x66) prefix. 618 */ 619 const instable_t dis_opSIMDdata16[256] = { 620 /* [00] */ INVALID, INVALID, INVALID, INVALID, 621 /* [04] */ INVALID, INVALID, INVALID, INVALID, 622 /* [08] */ INVALID, INVALID, INVALID, INVALID, 623 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 624 625 /* [10] */ TNSZ("movupd",XMM,16), TNSZ("movupd",XMMS,16), TNSZ("movlpd",XMMM,8), TNSZ("movlpd",XMMMS,8), 626 /* [14] */ TNSZ("unpcklpd",XMM,16),TNSZ("unpckhpd",XMM,16),TNSZ("movhpd",XMMM,8), TNSZ("movhpd",XMMMS,8), 627 /* [18] */ INVALID, INVALID, INVALID, INVALID, 628 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 629 630 /* [20] */ INVALID, INVALID, INVALID, INVALID, 631 /* [24] */ INVALID, INVALID, INVALID, INVALID, 632 /* [28] */ TNSZ("movapd",XMM,16), TNSZ("movapd",XMMS,16), TNSZ("cvtpi2pd",XMMOMX,8),TNSZ("movntpd",XMMOMS,16), 633 /* [2C] */ TNSZ("cvttpd2pi",XMMXMM,16),TNSZ("cvtpd2pi",XMMXMM,16),TNSZ("ucomisd",XMM,8),TNSZ("comisd",XMM,8), 634 635 /* [30] */ INVALID, INVALID, INVALID, INVALID, 636 /* [34] */ INVALID, INVALID, INVALID, INVALID, 637 /* [38] */ INVALID, INVALID, INVALID, INVALID, 638 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 639 640 /* [40] */ INVALID, INVALID, INVALID, INVALID, 641 /* [44] */ INVALID, INVALID, INVALID, INVALID, 642 /* [48] */ INVALID, INVALID, INVALID, INVALID, 643 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 644 645 /* [50] */ TNS("movmskpd",XMMOX3), TNSZ("sqrtpd",XMM,16), INVALID, INVALID, 646 /* [54] */ TNSZ("andpd",XMM,16), TNSZ("andnpd",XMM,16), TNSZ("orpd",XMM,16), TNSZ("xorpd",XMM,16), 647 /* [58] */ TNSZ("addpd",XMM,16), TNSZ("mulpd",XMM,16), TNSZ("cvtpd2ps",XMM,16),TNSZ("cvtps2dq",XMM,16), 648 /* [5C] */ TNSZ("subpd",XMM,16), TNSZ("minpd",XMM,16), TNSZ("divpd",XMM,16), TNSZ("maxpd",XMM,16), 649 650 /* [60] */ TNSZ("punpcklbw",XMM,16),TNSZ("punpcklwd",XMM,16),TNSZ("punpckldq",XMM,16),TNSZ("packsswb",XMM,16), 651 /* [64] */ TNSZ("pcmpgtb",XMM,16), TNSZ("pcmpgtw",XMM,16), TNSZ("pcmpgtd",XMM,16), TNSZ("packuswb",XMM,16), 652 /* [68] */ TNSZ("punpckhbw",XMM,16),TNSZ("punpckhwd",XMM,16),TNSZ("punpckhdq",XMM,16),TNSZ("packssdw",XMM,16), 653 /* [6C] */ TNSZ("punpcklqdq",XMM,16),TNSZ("punpckhqdq",XMM,16),TNSZ("movd",XMM3MX,4),TNSZ("movdqa",XMM,16), 654 655 /* [70] */ TNSZ("pshufd",XMMP,16), INVALID, INVALID, INVALID, 656 /* [74] */ TNSZ("pcmpeqb",XMM,16), TNSZ("pcmpeqw",XMM,16), TNSZ("pcmpeqd",XMM,16), INVALID, 657 /* [78] */ TNSZ("extrq",XMM2I,16), TNSZ("extrq",XMM,16), INVALID, INVALID, 658 /* [7C] */ INVALID, INVALID, TNSZ("movd",XMM3MXS,4), TNSZ("movdqa",XMMS,16), 659 660 /* [80] */ INVALID, INVALID, INVALID, INVALID, 661 /* [84] */ INVALID, INVALID, INVALID, INVALID, 662 /* [88] */ INVALID, INVALID, INVALID, INVALID, 663 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 664 665 /* [90] */ INVALID, INVALID, INVALID, INVALID, 666 /* [94] */ INVALID, INVALID, INVALID, INVALID, 667 /* [98] */ INVALID, INVALID, INVALID, INVALID, 668 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 669 670 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 671 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 672 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 673 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 674 675 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 676 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 677 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 678 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 679 680 /* [C0] */ INVALID, INVALID, TNSZ("cmppd",XMMP,16), INVALID, 681 /* [C4] */ TNSZ("pinsrw",XMMPRM,2),TNS("pextrw",XMM3P), TNSZ("shufpd",XMMP,16), INVALID, 682 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 683 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 684 685 /* [D0] */ INVALID, TNSZ("psrlw",XMM,16), TNSZ("psrld",XMM,16), TNSZ("psrlq",XMM,16), 686 /* [D4] */ TNSZ("paddq",XMM,16), TNSZ("pmullw",XMM,16), TNSZ("movq",XMMS,8), TNS("pmovmskb",XMMX3), 687 /* [D8] */ TNSZ("psubusb",XMM,16), TNSZ("psubusw",XMM,16), TNSZ("pminub",XMM,16), TNSZ("pand",XMM,16), 688 /* [DC] */ TNSZ("paddusb",XMM,16), TNSZ("paddusw",XMM,16), TNSZ("pmaxub",XMM,16), TNSZ("pandn",XMM,16), 689 690 /* [E0] */ TNSZ("pavgb",XMM,16), TNSZ("psraw",XMM,16), TNSZ("psrad",XMM,16), TNSZ("pavgw",XMM,16), 691 /* [E4] */ TNSZ("pmulhuw",XMM,16), TNSZ("pmulhw",XMM,16), TNSZ("cvttpd2dq",XMM,16),TNSZ("movntdq",XMMS,16), 692 /* [E8] */ TNSZ("psubsb",XMM,16), TNSZ("psubsw",XMM,16), TNSZ("pminsw",XMM,16), TNSZ("por",XMM,16), 693 /* [EC] */ TNSZ("paddsb",XMM,16), TNSZ("paddsw",XMM,16), TNSZ("pmaxsw",XMM,16), TNSZ("pxor",XMM,16), 694 695 /* [F0] */ INVALID, TNSZ("psllw",XMM,16), TNSZ("pslld",XMM,16), TNSZ("psllq",XMM,16), 696 /* [F4] */ TNSZ("pmuludq",XMM,16), TNSZ("pmaddwd",XMM,16), TNSZ("psadbw",XMM,16), TNSZ("maskmovdqu", XMMXIMPL,16), 697 /* [F8] */ TNSZ("psubb",XMM,16), TNSZ("psubw",XMM,16), TNSZ("psubd",XMM,16), TNSZ("psubq",XMM,16), 698 /* [FC] */ TNSZ("paddb",XMM,16), TNSZ("paddw",XMM,16), TNSZ("paddd",XMM,16), INVALID, 699 }; 700 701 const instable_t dis_opAVX660F[256] = { 702 /* [00] */ INVALID, INVALID, INVALID, INVALID, 703 /* [04] */ INVALID, INVALID, INVALID, INVALID, 704 /* [08] */ INVALID, INVALID, INVALID, INVALID, 705 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 706 707 /* [10] */ TNSZ("vmovupd",VEX_MX,16), TNSZ("vmovupd",VEX_RX,16), TNSZ("vmovlpd",VEX_RMrX,8), TNSZ("vmovlpd",VEX_RM,8), 708 /* [14] */ TNSZ("vunpcklpd",VEX_RMrX,16),TNSZ("vunpckhpd",VEX_RMrX,16),TNSZ("vmovhpd",VEX_RMrX,8), TNSZ("vmovhpd",VEX_RM,8), 709 /* [18] */ INVALID, INVALID, INVALID, INVALID, 710 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 711 712 /* [20] */ INVALID, INVALID, INVALID, INVALID, 713 /* [24] */ INVALID, INVALID, INVALID, INVALID, 714 /* [28] */ TNSZ("vmovapd",VEX_MX,16), TNSZ("vmovapd",VEX_RX,16), INVALID, TNSZ("vmovntpd",VEX_RM,16), 715 /* [2C] */ INVALID, INVALID, TNSZ("vucomisd",VEX_MX,8),TNSZ("vcomisd",VEX_MX,8), 716 717 /* [30] */ INVALID, INVALID, INVALID, INVALID, 718 /* [34] */ INVALID, INVALID, INVALID, INVALID, 719 /* [38] */ INVALID, INVALID, INVALID, INVALID, 720 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 721 722 /* [40] */ INVALID, INVALID, INVALID, INVALID, 723 /* [44] */ INVALID, INVALID, INVALID, INVALID, 724 /* [48] */ INVALID, INVALID, INVALID, INVALID, 725 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 726 727 /* [50] */ TNS("vmovmskpd",VEX_MR), TNSZ("vsqrtpd",VEX_MX,16), INVALID, INVALID, 728 /* [54] */ TNSZ("vandpd",VEX_RMrX,16), TNSZ("vandnpd",VEX_RMrX,16), TNSZ("vorpd",VEX_RMrX,16), TNSZ("vxorpd",VEX_RMrX,16), 729 /* [58] */ TNSZ("vaddpd",VEX_RMrX,16), TNSZ("vmulpd",VEX_RMrX,16), TNSZ("vcvtpd2ps",VEX_MX,16),TNSZ("vcvtps2dq",VEX_MX,16), 730 /* [5C] */ TNSZ("vsubpd",VEX_RMrX,16), TNSZ("vminpd",VEX_RMrX,16), TNSZ("vdivpd",VEX_RMrX,16), TNSZ("vmaxpd",VEX_RMrX,16), 731 732 /* [60] */ TNSZ("vpunpcklbw",VEX_RMrX,16),TNSZ("vpunpcklwd",VEX_RMrX,16),TNSZ("vpunpckldq",VEX_RMrX,16),TNSZ("vpacksswb",VEX_RMrX,16), 733 /* [64] */ TNSZ("vpcmpgtb",VEX_RMrX,16), TNSZ("vpcmpgtw",VEX_RMrX,16), TNSZ("vpcmpgtd",VEX_RMrX,16), TNSZ("vpackuswb",VEX_RMrX,16), 734 /* [68] */ TNSZ("vpunpckhbw",VEX_RMrX,16),TNSZ("vpunpckhwd",VEX_RMrX,16),TNSZ("vpunpckhdq",VEX_RMrX,16),TNSZ("vpackssdw",VEX_RMrX,16), 735 /* [6C] */ TNSZ("vpunpcklqdq",VEX_RMrX,16),TNSZ("vpunpckhqdq",VEX_RMrX,16),TNSZ("vmovd",VEX_MX,4),TNSZ("vmovdqa",VEX_MX,16), 736 737 /* [70] */ TNSZ("vpshufd",VEX_MXI,16), TNSZ("vgrp71",VEX_XXI,16), TNSZ("vgrp72",VEX_XXI,16), TNSZ("vgrp73",VEX_XXI,16), 738 /* [74] */ TNSZ("vpcmpeqb",VEX_RMrX,16), TNSZ("vpcmpeqw",VEX_RMrX,16), TNSZ("vpcmpeqd",VEX_RMrX,16), INVALID, 739 /* [78] */ INVALID, INVALID, INVALID, INVALID, 740 /* [7C] */ TNSZ("vhaddpd",VEX_RMrX,16), TNSZ("vhsubpd",VEX_RMrX,16), TNSZ("vmovd",VEX_RR,4), TNSZ("vmovdqa",VEX_RX,16), 741 742 /* [80] */ INVALID, INVALID, INVALID, INVALID, 743 /* [84] */ INVALID, INVALID, INVALID, INVALID, 744 /* [88] */ INVALID, INVALID, INVALID, INVALID, 745 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 746 747 /* [90] */ INVALID, INVALID, INVALID, INVALID, 748 /* [94] */ INVALID, INVALID, INVALID, INVALID, 749 /* [98] */ INVALID, INVALID, INVALID, INVALID, 750 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 751 752 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 753 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 754 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 755 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 756 757 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 758 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 759 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 760 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 761 762 /* [C0] */ INVALID, INVALID, TNSZ("vcmppd",VEX_RMRX,16), INVALID, 763 /* [C4] */ TNSZ("vpinsrw",VEX_RMRX,2),TNS("vpextrw",VEX_MR), TNSZ("vshufpd",VEX_RMRX,16), INVALID, 764 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 765 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 766 767 /* [D0] */ TNSZ("vaddsubpd",VEX_RMrX,16),TNSZ("vpsrlw",VEX_RMrX,16), TNSZ("vpsrld",VEX_RMrX,16), TNSZ("vpsrlq",VEX_RMrX,16), 768 /* [D4] */ TNSZ("vpaddq",VEX_RMrX,16), TNSZ("vpmullw",VEX_RMrX,16), TNSZ("vmovq",VEX_RX,8), TNS("vpmovmskb",VEX_MR), 769 /* [D8] */ TNSZ("vpsubusb",VEX_RMrX,16), TNSZ("vpsubusw",VEX_RMrX,16), TNSZ("vpminub",VEX_RMrX,16), TNSZ("vpand",VEX_RMrX,16), 770 /* [DC] */ TNSZ("vpaddusb",VEX_RMrX,16), TNSZ("vpaddusw",VEX_RMrX,16), TNSZ("vpmaxub",VEX_RMrX,16), TNSZ("vpandn",VEX_RMrX,16), 771 772 /* [E0] */ TNSZ("vpavgb",VEX_RMrX,16), TNSZ("vpsraw",VEX_RMrX,16), TNSZ("vpsrad",VEX_RMrX,16), TNSZ("vpavgw",VEX_RMrX,16), 773 /* [E4] */ TNSZ("vpmulhuw",VEX_RMrX,16), TNSZ("vpmulhw",VEX_RMrX,16), TNSZ("vcvttpd2dq",VEX_MX,16),TNSZ("vmovntdq",VEX_RM,16), 774 /* [E8] */ TNSZ("vpsubsb",VEX_RMrX,16), TNSZ("vpsubsw",VEX_RMrX,16), TNSZ("vpminsw",VEX_RMrX,16), TNSZ("vpor",VEX_RMrX,16), 775 /* [EC] */ TNSZ("vpaddsb",VEX_RMrX,16), TNSZ("vpaddsw",VEX_RMrX,16), TNSZ("vpmaxsw",VEX_RMrX,16), TNSZ("vpxor",VEX_RMrX,16), 776 777 /* [F0] */ INVALID, TNSZ("vpsllw",VEX_RMrX,16), TNSZ("vpslld",VEX_RMrX,16), TNSZ("vpsllq",VEX_RMrX,16), 778 /* [F4] */ TNSZ("vpmuludq",VEX_RMrX,16), TNSZ("vpmaddwd",VEX_RMrX,16), TNSZ("vpsadbw",VEX_RMrX,16), TNS("vmaskmovdqu",VEX_MX), 779 /* [F8] */ TNSZ("vpsubb",VEX_RMrX,16), TNSZ("vpsubw",VEX_RMrX,16), TNSZ("vpsubd",VEX_RMrX,16), TNSZ("vpsubq",VEX_RMrX,16), 780 /* [FC] */ TNSZ("vpaddb",VEX_RMrX,16), TNSZ("vpaddw",VEX_RMrX,16), TNSZ("vpaddd",VEX_RMrX,16), INVALID, 781 }; 782 783 /* 784 * Decode table for SIMD instructions with the repnz (0xf2) prefix. 785 */ 786 const instable_t dis_opSIMDrepnz[256] = { 787 /* [00] */ INVALID, INVALID, INVALID, INVALID, 788 /* [04] */ INVALID, INVALID, INVALID, INVALID, 789 /* [08] */ INVALID, INVALID, INVALID, INVALID, 790 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 791 792 /* [10] */ TNSZ("movsd",XMM,8), TNSZ("movsd",XMMS,8), INVALID, INVALID, 793 /* [14] */ INVALID, INVALID, INVALID, INVALID, 794 /* [18] */ INVALID, INVALID, INVALID, INVALID, 795 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 796 797 /* [20] */ INVALID, INVALID, INVALID, INVALID, 798 /* [24] */ INVALID, INVALID, INVALID, INVALID, 799 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2sd",XMM3MX,4),TNSZ("movntsd",XMMMS,8), 800 /* [2C] */ TNSZ("cvttsd2si",XMMXM3,8),TNSZ("cvtsd2si",XMMXM3,8),INVALID, INVALID, 801 802 /* [30] */ INVALID, INVALID, INVALID, INVALID, 803 /* [34] */ INVALID, INVALID, INVALID, INVALID, 804 /* [38] */ INVALID, INVALID, INVALID, INVALID, 805 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 806 807 /* [40] */ INVALID, INVALID, INVALID, INVALID, 808 /* [44] */ INVALID, INVALID, INVALID, INVALID, 809 /* [48] */ INVALID, INVALID, INVALID, INVALID, 810 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 811 812 /* [50] */ INVALID, TNSZ("sqrtsd",XMM,8), INVALID, INVALID, 813 /* [54] */ INVALID, INVALID, INVALID, INVALID, 814 /* [58] */ TNSZ("addsd",XMM,8), TNSZ("mulsd",XMM,8), TNSZ("cvtsd2ss",XMM,8), INVALID, 815 /* [5C] */ TNSZ("subsd",XMM,8), TNSZ("minsd",XMM,8), TNSZ("divsd",XMM,8), TNSZ("maxsd",XMM,8), 816 817 /* [60] */ INVALID, INVALID, INVALID, INVALID, 818 /* [64] */ INVALID, INVALID, INVALID, INVALID, 819 /* [68] */ INVALID, INVALID, INVALID, INVALID, 820 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 821 822 /* [70] */ TNSZ("pshuflw",XMMP,16),INVALID, INVALID, INVALID, 823 /* [74] */ INVALID, INVALID, INVALID, INVALID, 824 /* [78] */ TNSZ("insertq",XMMX2I,16),TNSZ("insertq",XMM,8),INVALID, INVALID, 825 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 826 827 /* [80] */ INVALID, INVALID, INVALID, INVALID, 828 /* [84] */ INVALID, INVALID, INVALID, INVALID, 829 /* [88] */ INVALID, INVALID, INVALID, INVALID, 830 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 831 832 /* [90] */ INVALID, INVALID, INVALID, INVALID, 833 /* [94] */ INVALID, INVALID, INVALID, INVALID, 834 /* [98] */ INVALID, INVALID, INVALID, INVALID, 835 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 836 837 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 838 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 839 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 840 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 841 842 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 843 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 844 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 845 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 846 847 /* [C0] */ INVALID, INVALID, TNSZ("cmpsd",XMMP,8), INVALID, 848 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 849 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 850 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 851 852 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 853 /* [D4] */ INVALID, INVALID, TNS("movdq2q",XMMXM), INVALID, 854 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 855 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 856 857 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 858 /* [E4] */ INVALID, INVALID, TNSZ("cvtpd2dq",XMM,16),INVALID, 859 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 860 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 861 862 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 863 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 864 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 865 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 866 }; 867 868 const instable_t dis_opAVXF20F[256] = { 869 /* [00] */ INVALID, INVALID, INVALID, INVALID, 870 /* [04] */ INVALID, INVALID, INVALID, INVALID, 871 /* [08] */ INVALID, INVALID, INVALID, INVALID, 872 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 873 874 /* [10] */ TNSZ("vmovsd",VEX_RMrX,8), TNSZ("vmovsd",VEX_RRX,8), TNSZ("vmovddup",VEX_MX,8), INVALID, 875 /* [14] */ INVALID, INVALID, INVALID, INVALID, 876 /* [18] */ INVALID, INVALID, INVALID, INVALID, 877 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 878 879 /* [20] */ INVALID, INVALID, INVALID, INVALID, 880 /* [24] */ INVALID, INVALID, INVALID, INVALID, 881 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2sd",VEX_RMrX,4),INVALID, 882 /* [2C] */ TNSZ("vcvttsd2si",VEX_MR,8),TNSZ("vcvtsd2si",VEX_MR,8),INVALID, INVALID, 883 884 /* [30] */ INVALID, INVALID, INVALID, INVALID, 885 /* [34] */ INVALID, INVALID, INVALID, INVALID, 886 /* [38] */ INVALID, INVALID, INVALID, INVALID, 887 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 888 889 /* [40] */ INVALID, INVALID, INVALID, INVALID, 890 /* [44] */ INVALID, INVALID, INVALID, INVALID, 891 /* [48] */ INVALID, INVALID, INVALID, INVALID, 892 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 893 894 /* [50] */ INVALID, TNSZ("vsqrtsd",VEX_RMrX,8), INVALID, INVALID, 895 /* [54] */ INVALID, INVALID, INVALID, INVALID, 896 /* [58] */ TNSZ("vaddsd",VEX_RMrX,8), TNSZ("vmulsd",VEX_RMrX,8), TNSZ("vcvtsd2ss",VEX_RMrX,8), INVALID, 897 /* [5C] */ TNSZ("vsubsd",VEX_RMrX,8), TNSZ("vminsd",VEX_RMrX,8), TNSZ("vdivsd",VEX_RMrX,8), TNSZ("vmaxsd",VEX_RMrX,8), 898 899 /* [60] */ INVALID, INVALID, INVALID, INVALID, 900 /* [64] */ INVALID, INVALID, INVALID, INVALID, 901 /* [68] */ INVALID, INVALID, INVALID, INVALID, 902 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 903 904 /* [70] */ TNSZ("vpshuflw",VEX_MXI,16),INVALID, INVALID, INVALID, 905 /* [74] */ INVALID, INVALID, INVALID, INVALID, 906 /* [78] */ INVALID, INVALID, INVALID, INVALID, 907 /* [7C] */ TNSZ("vhaddps",VEX_RMrX,8), TNSZ("vhsubps",VEX_RMrX,8), INVALID, INVALID, 908 909 /* [80] */ INVALID, INVALID, INVALID, INVALID, 910 /* [84] */ INVALID, INVALID, INVALID, INVALID, 911 /* [88] */ INVALID, INVALID, INVALID, INVALID, 912 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 913 914 /* [90] */ INVALID, INVALID, INVALID, INVALID, 915 /* [94] */ INVALID, INVALID, INVALID, INVALID, 916 /* [98] */ INVALID, INVALID, INVALID, INVALID, 917 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 918 919 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 920 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 921 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 922 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 923 924 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 925 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 926 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 927 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 928 929 /* [C0] */ INVALID, INVALID, TNSZ("vcmpsd",VEX_RMRX,8), INVALID, 930 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 931 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 932 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 933 934 /* [D0] */ TNSZ("vaddsubps",VEX_RMrX,8), INVALID, INVALID, INVALID, 935 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 936 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 937 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 938 939 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 940 /* [E4] */ INVALID, INVALID, TNSZ("vcvtpd2dq",VEX_MX,16),INVALID, 941 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 942 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 943 944 /* [F0] */ TNSZ("vlddqu",VEX_MX,16), INVALID, INVALID, INVALID, 945 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 946 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 947 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 948 }; 949 950 /* 951 * Decode table for SIMD instructions with the repz (0xf3) prefix. 952 */ 953 const instable_t dis_opSIMDrepz[256] = { 954 /* [00] */ INVALID, INVALID, INVALID, INVALID, 955 /* [04] */ INVALID, INVALID, INVALID, INVALID, 956 /* [08] */ INVALID, INVALID, INVALID, INVALID, 957 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 958 959 /* [10] */ TNSZ("movss",XMM,4), TNSZ("movss",XMMS,4), INVALID, INVALID, 960 /* [14] */ INVALID, INVALID, INVALID, INVALID, 961 /* [18] */ INVALID, INVALID, INVALID, INVALID, 962 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 963 964 /* [20] */ INVALID, INVALID, INVALID, INVALID, 965 /* [24] */ INVALID, INVALID, INVALID, INVALID, 966 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2ss",XMM3MX,4),TNSZ("movntss",XMMMS,4), 967 /* [2C] */ TNSZ("cvttss2si",XMMXM3,4),TNSZ("cvtss2si",XMMXM3,4),INVALID, INVALID, 968 969 /* [30] */ INVALID, INVALID, INVALID, INVALID, 970 /* [34] */ INVALID, INVALID, INVALID, INVALID, 971 /* [38] */ INVALID, INVALID, INVALID, INVALID, 972 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 973 974 /* [40] */ INVALID, INVALID, INVALID, INVALID, 975 /* [44] */ INVALID, INVALID, INVALID, INVALID, 976 /* [48] */ INVALID, INVALID, INVALID, INVALID, 977 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 978 979 /* [50] */ INVALID, TNSZ("sqrtss",XMM,4), TNSZ("rsqrtss",XMM,4), TNSZ("rcpss",XMM,4), 980 /* [54] */ INVALID, INVALID, INVALID, INVALID, 981 /* [58] */ TNSZ("addss",XMM,4), TNSZ("mulss",XMM,4), TNSZ("cvtss2sd",XMM,4), TNSZ("cvttps2dq",XMM,16), 982 /* [5C] */ TNSZ("subss",XMM,4), TNSZ("minss",XMM,4), TNSZ("divss",XMM,4), TNSZ("maxss",XMM,4), 983 984 /* [60] */ INVALID, INVALID, INVALID, INVALID, 985 /* [64] */ INVALID, INVALID, INVALID, INVALID, 986 /* [68] */ INVALID, INVALID, INVALID, INVALID, 987 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("movdqu",XMM,16), 988 989 /* [70] */ TNSZ("pshufhw",XMMP,16),INVALID, INVALID, INVALID, 990 /* [74] */ INVALID, INVALID, INVALID, INVALID, 991 /* [78] */ INVALID, INVALID, INVALID, INVALID, 992 /* [7C] */ INVALID, INVALID, TNSZ("movq",XMM,8), TNSZ("movdqu",XMMS,16), 993 994 /* [80] */ INVALID, INVALID, INVALID, INVALID, 995 /* [84] */ INVALID, INVALID, INVALID, INVALID, 996 /* [88] */ INVALID, INVALID, INVALID, INVALID, 997 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 998 999 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1000 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1001 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1002 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1003 1004 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1005 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1006 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1007 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1008 1009 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1010 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1011 /* [B8] */ TS("popcnt",MRw), INVALID, INVALID, INVALID, 1012 /* [BC] */ INVALID, TS("lzcnt",MRw), INVALID, INVALID, 1013 1014 /* [C0] */ INVALID, INVALID, TNSZ("cmpss",XMMP,4), INVALID, 1015 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1016 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1017 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1018 1019 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1020 /* [D4] */ INVALID, INVALID, TNS("movq2dq",XMMMX), INVALID, 1021 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1022 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1023 1024 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1025 /* [E4] */ INVALID, INVALID, TNSZ("cvtdq2pd",XMM,8), INVALID, 1026 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1027 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1028 1029 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1030 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1031 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1032 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1033 }; 1034 1035 const instable_t dis_opAVXF30F[256] = { 1036 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1037 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1038 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1039 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1040 1041 /* [10] */ TNSZ("vmovss",VEX_RMrX,4), TNSZ("vmovss",VEX_RRX,4), TNSZ("vmovsldup",VEX_MX,4), INVALID, 1042 /* [14] */ INVALID, INVALID, TNSZ("vmovshdup",VEX_MX,4), INVALID, 1043 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1044 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1045 1046 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1047 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1048 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2ss",VEX_RMrX,4),INVALID, 1049 /* [2C] */ TNSZ("vcvttss2si",VEX_MR,4),TNSZ("vcvtss2si",VEX_MR,4),INVALID, INVALID, 1050 1051 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1052 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1053 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1054 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1055 1056 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1057 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1058 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1059 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1060 1061 /* [50] */ INVALID, TNSZ("vsqrtss",VEX_RMrX,4), TNSZ("vrsqrtss",VEX_RMrX,4), TNSZ("vrcpss",VEX_RMrX,4), 1062 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1063 /* [58] */ TNSZ("vaddss",VEX_RMrX,4), TNSZ("vmulss",VEX_RMrX,4), TNSZ("vcvtss2sd",VEX_RMrX,4), TNSZ("vcvttps2dq",VEX_MX,16), 1064 /* [5C] */ TNSZ("vsubss",VEX_RMrX,4), TNSZ("vminss",VEX_RMrX,4), TNSZ("vdivss",VEX_RMrX,4), TNSZ("vmaxss",VEX_RMrX,4), 1065 1066 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1067 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1068 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1069 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("vmovdqu",VEX_MX,16), 1070 1071 /* [70] */ TNSZ("vpshufhw",VEX_MXI,16),INVALID, INVALID, INVALID, 1072 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1073 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1074 /* [7C] */ INVALID, INVALID, TNSZ("vmovq",VEX_MX,8), TNSZ("vmovdqu",VEX_RX,16), 1075 1076 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1077 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1078 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1079 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1080 1081 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1082 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1083 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1084 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1085 1086 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1087 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1088 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1089 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1090 1091 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1092 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1093 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1094 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1095 1096 /* [C0] */ INVALID, INVALID, TNSZ("vcmpss",VEX_RMRX,4), INVALID, 1097 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1098 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1099 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1100 1101 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1102 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1103 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1104 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1105 1106 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1107 /* [E4] */ INVALID, INVALID, TNSZ("vcvtdq2pd",VEX_MX,8), INVALID, 1108 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1109 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1110 1111 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1112 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1113 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1114 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1115 }; 1116 /* 1117 * The following two tables are used to encode crc32 and movbe 1118 * since they share the same opcodes. 1119 */ 1120 const instable_t dis_op0F38F0[2] = { 1121 /* [00] */ TNS("crc32b",CRC32), 1122 TS("movbe",MOVBE), 1123 }; 1124 1125 const instable_t dis_op0F38F1[2] = { 1126 /* [00] */ TS("crc32",CRC32), 1127 TS("movbe",MOVBE), 1128 }; 1129 1130 const instable_t dis_op0F38[256] = { 1131 /* [00] */ TNSZ("pshufb",XMM_66o,16),TNSZ("phaddw",XMM_66o,16),TNSZ("phaddd",XMM_66o,16),TNSZ("phaddsw",XMM_66o,16), 1132 /* [04] */ TNSZ("pmaddubsw",XMM_66o,16),TNSZ("phsubw",XMM_66o,16), TNSZ("phsubd",XMM_66o,16),TNSZ("phsubsw",XMM_66o,16), 1133 /* [08] */ TNSZ("psignb",XMM_66o,16),TNSZ("psignw",XMM_66o,16),TNSZ("psignd",XMM_66o,16),TNSZ("pmulhrsw",XMM_66o,16), 1134 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1135 1136 /* [10] */ TNSZ("pblendvb",XMM_66r,16),INVALID, INVALID, INVALID, 1137 /* [14] */ TNSZ("blendvps",XMM_66r,16),TNSZ("blendvpd",XMM_66r,16),INVALID, TNSZ("ptest",XMM_66r,16), 1138 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1139 /* [1C] */ TNSZ("pabsb",XMM_66o,16),TNSZ("pabsw",XMM_66o,16),TNSZ("pabsd",XMM_66o,16),INVALID, 1140 1141 /* [20] */ TNSZ("pmovsxbw",XMM_66r,16),TNSZ("pmovsxbd",XMM_66r,16),TNSZ("pmovsxbq",XMM_66r,16),TNSZ("pmovsxwd",XMM_66r,16), 1142 /* [24] */ TNSZ("pmovsxwq",XMM_66r,16),TNSZ("pmovsxdq",XMM_66r,16),INVALID, INVALID, 1143 /* [28] */ TNSZ("pmuldq",XMM_66r,16),TNSZ("pcmpeqq",XMM_66r,16),TNSZ("movntdqa",XMMM_66r,16),TNSZ("packusdw",XMM_66r,16), 1144 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1145 1146 /* [30] */ TNSZ("pmovzxbw",XMM_66r,16),TNSZ("pmovzxbd",XMM_66r,16),TNSZ("pmovzxbq",XMM_66r,16),TNSZ("pmovzxwd",XMM_66r,16), 1147 /* [34] */ TNSZ("pmovzxwq",XMM_66r,16),TNSZ("pmovzxdq",XMM_66r,16),INVALID, TNSZ("pcmpgtq",XMM_66r,16), 1148 /* [38] */ TNSZ("pminsb",XMM_66r,16),TNSZ("pminsd",XMM_66r,16),TNSZ("pminuw",XMM_66r,16),TNSZ("pminud",XMM_66r,16), 1149 /* [3C] */ TNSZ("pmaxsb",XMM_66r,16),TNSZ("pmaxsd",XMM_66r,16),TNSZ("pmaxuw",XMM_66r,16),TNSZ("pmaxud",XMM_66r,16), 1150 1151 /* [40] */ TNSZ("pmulld",XMM_66r,16),TNSZ("phminposuw",XMM_66r,16),INVALID, INVALID, 1152 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1153 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1154 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1155 1156 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1157 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1158 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1159 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1160 1161 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1162 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1163 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1164 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1165 1166 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1167 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1168 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1169 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1170 1171 /* [80] */ TNSy("invept", RM_66r), TNSy("invvpid", RM_66r),INVALID, INVALID, 1172 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1173 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1174 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1175 1176 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1177 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1178 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1179 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1180 1181 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1182 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1183 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1184 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1185 1186 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1187 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1188 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1189 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1190 1191 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1192 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1193 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1194 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1195 1196 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1197 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1198 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("aesimc",XMM_66r,16), 1199 /* [DC] */ TNSZ("aesenc",XMM_66r,16),TNSZ("aesenclast",XMM_66r,16),TNSZ("aesdec",XMM_66r,16),TNSZ("aesdeclast",XMM_66r,16), 1200 1201 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1202 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1203 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1204 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1205 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID, 1206 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1207 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1208 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1209 }; 1210 1211 const instable_t dis_opAVX660F38[256] = { 1212 /* [00] */ TNSZ("vpshufb",VEX_RMrX,16),TNSZ("vphaddw",VEX_RMrX,16),TNSZ("vphaddd",VEX_RMrX,16),TNSZ("vphaddsw",VEX_RMrX,16), 1213 /* [04] */ TNSZ("vpmaddubsw",VEX_RMrX,16),TNSZ("vphsubw",VEX_RMrX,16), TNSZ("vphsubd",VEX_RMrX,16),TNSZ("vphsubsw",VEX_RMrX,16), 1214 /* [08] */ TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16), 1215 /* [0C] */ TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8), TNSZ("vtestpd",VEX_RRI,16), 1216 1217 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1218 /* [14] */ INVALID, INVALID, INVALID, TNSZ("vptest",VEX_RRI,16), 1219 /* [18] */ TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID, 1220 /* [1C] */ TNSZ("vpabsb",VEX_MX,16),TNSZ("vpabsw",VEX_MX,16),TNSZ("vpabsd",VEX_MX,16),INVALID, 1221 1222 /* [20] */ TNSZ("vpmovsxbw",VEX_MX,16),TNSZ("vpmovsxbd",VEX_MX,16),TNSZ("vpmovsxbq",VEX_MX,16),TNSZ("vpmovsxwd",VEX_MX,16), 1223 /* [24] */ TNSZ("vpmovsxwq",VEX_MX,16),TNSZ("vpmovsxdq",VEX_MX,16),INVALID, INVALID, 1224 /* [28] */ TNSZ("vpmuldq",VEX_RMrX,16),TNSZ("vpcmpeqq",VEX_RMrX,16),TNSZ("vmovntdqa",VEX_MX,16),TNSZ("vpackusdw",VEX_RMrX,16), 1225 /* [2C] */ TNSZ("vmaskmovps",VEX_RMrX,8),TNSZ("vmaskmovpd",VEX_RMrX,16),TNSZ("vmaskmovps",VEX_RRM,8),TNSZ("vmaskmovpd",VEX_RRM,16), 1226 1227 /* [30] */ TNSZ("vpmovzxbw",VEX_MX,16),TNSZ("vpmovzxbd",VEX_MX,16),TNSZ("vpmovzxbq",VEX_MX,16),TNSZ("vpmovzxwd",VEX_MX,16), 1228 /* [34] */ TNSZ("vpmovzxwq",VEX_MX,16),TNSZ("vpmovzxdq",VEX_MX,16),INVALID, TNSZ("vpcmpgtq",VEX_RMrX,16), 1229 /* [38] */ TNSZ("vpminsb",VEX_RMrX,16),TNSZ("vpminsd",VEX_RMrX,16),TNSZ("vpminuw",VEX_RMrX,16),TNSZ("vpminud",VEX_RMrX,16), 1230 /* [3C] */ TNSZ("vpmaxsb",VEX_RMrX,16),TNSZ("vpmaxsd",VEX_RMrX,16),TNSZ("vpmaxuw",VEX_RMrX,16),TNSZ("vpmaxud",VEX_RMrX,16), 1231 1232 /* [40] */ TNSZ("vpmulld",VEX_RMrX,16),TNSZ("vphminposuw",VEX_MX,16),INVALID, INVALID, 1233 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1234 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1235 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1236 1237 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1238 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1239 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1240 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1241 1242 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1243 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1244 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1245 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1246 1247 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1248 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1249 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1250 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1251 1252 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1253 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1254 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1255 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1256 1257 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1258 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1259 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1260 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1261 1262 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1263 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1264 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1265 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1266 1267 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1268 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1269 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1270 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1271 1272 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1273 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1274 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1275 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1276 1277 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1278 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1279 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("vaesimc",VEX_MX,16), 1280 /* [DC] */ TNSZ("vaesenc",VEX_RMrX,16),TNSZ("vaesenclast",VEX_RMrX,16),TNSZ("vaesdec",VEX_RMrX,16),TNSZ("vaesdeclast",VEX_RMrX,16), 1281 1282 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1283 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1284 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1285 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1286 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID, 1287 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1288 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1289 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1290 }; 1291 1292 const instable_t dis_op0F3A[256] = { 1293 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1294 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1295 /* [08] */ TNSZ("roundps",XMMP_66r,16),TNSZ("roundpd",XMMP_66r,16),TNSZ("roundss",XMMP_66r,16),TNSZ("roundsd",XMMP_66r,16), 1296 /* [0C] */ TNSZ("blendps",XMMP_66r,16),TNSZ("blendpd",XMMP_66r,16),TNSZ("pblendw",XMMP_66r,16),TNSZ("palignr",XMMP_66o,16), 1297 1298 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1299 /* [14] */ TNSZ("pextrb",XMM3PM_66r,8),TNSZ("pextrw",XMM3PM_66r,16),TSZ("pextr",XMM3PM_66r,16),TNSZ("extractps",XMM3PM_66r,16), 1300 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1301 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1302 1303 /* [20] */ TNSZ("pinsrb",XMMPRM_66r,8),TNSZ("insertps",XMMP_66r,16),TSZ("pinsr",XMMPRM_66r,16),INVALID, 1304 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1305 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1306 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1307 1308 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1309 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1310 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1311 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1312 1313 /* [40] */ TNSZ("dpps",XMMP_66r,16),TNSZ("dppd",XMMP_66r,16),TNSZ("mpsadbw",XMMP_66r,16),INVALID, 1314 /* [44] */ TNSZ("pclmulqdq",XMMP_66r,16),INVALID, INVALID, INVALID, 1315 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1316 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1317 1318 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1319 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1320 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1321 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1322 1323 /* [60] */ TNSZ("pcmpestrm",XMMP_66r,16),TNSZ("pcmpestri",XMMP_66r,16),TNSZ("pcmpistrm",XMMP_66r,16),TNSZ("pcmpistri",XMMP_66r,16), 1324 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1325 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1326 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1327 1328 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1329 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1330 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1331 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1332 1333 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1334 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1335 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1336 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1337 1338 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1339 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1340 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1341 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1342 1343 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1344 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1345 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1346 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1347 1348 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1349 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1350 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1351 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1352 1353 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1354 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1355 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1356 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1357 1358 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1359 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1360 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1361 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("aeskeygenassist",XMMP_66r,16), 1362 1363 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1364 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1365 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1366 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1367 1368 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1369 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1370 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1371 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1372 }; 1373 1374 const instable_t dis_opAVX660F3A[256] = { 1375 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1376 /* [04] */ TNSZ("vpermilps",VEX_MXI,8),TNSZ("vpermilpd",VEX_MXI,16),TNSZ("vperm2f128",VEX_RMRX,16),INVALID, 1377 /* [08] */ TNSZ("vroundps",VEX_MXI,16),TNSZ("vroundpd",VEX_MXI,16),TNSZ("vroundss",VEX_RMRX,16),TNSZ("vroundsd",VEX_RMRX,16), 1378 /* [0C] */ TNSZ("vblendps",VEX_RMRX,16),TNSZ("vblendpd",VEX_RMRX,16),TNSZ("vpblendw",VEX_RMRX,16),TNSZ("vpalignr",VEX_RMRX,16), 1379 1380 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1381 /* [14] */ TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16), 1382 /* [18] */ TNSZ("vinsertf128",VEX_RMRX,16),TNSZ("vextractf128",VEX_RX,16),INVALID, INVALID, 1383 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1384 1385 /* [20] */ TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID, 1386 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1387 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1388 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1389 1390 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1391 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1392 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1393 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1394 1395 /* [40] */ TNSZ("vdpps",VEX_RMRX,16),TNSZ("vdppd",VEX_RMRX,16),TNSZ("vmpsadbw",VEX_RMRX,16),INVALID, 1396 /* [44] */ TNSZ("vpclmulqdq",VEX_RMRX,16),INVALID, INVALID, INVALID, 1397 /* [48] */ INVALID, INVALID, TNSZ("vblendvps",VEX_RMRX,8), TNSZ("vblendvpd",VEX_RMRX,16), 1398 /* [4C] */ TNSZ("vpblendvb",VEX_RMRX,16),INVALID, INVALID, INVALID, 1399 1400 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1401 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1402 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1403 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1404 1405 /* [60] */ TNSZ("vpcmpestrm",VEX_MXI,16),TNSZ("vpcmpestri",VEX_MXI,16),TNSZ("vpcmpistrm",VEX_MXI,16),TNSZ("vpcmpistri",VEX_MXI,16), 1406 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1407 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1408 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1409 1410 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1411 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1412 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1413 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1414 1415 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1416 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1417 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1418 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1419 1420 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1421 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1422 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1423 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1424 1425 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1426 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1427 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1428 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1429 1430 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1431 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1432 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1433 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1434 1435 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1436 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1437 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1438 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1439 1440 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1441 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1442 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1443 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("vaeskeygenassist",VEX_MXI,16), 1444 1445 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1446 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1447 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1448 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1449 1450 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1451 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1452 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1453 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1454 }; 1455 1456 /* 1457 * Decode table for 0x0F opcodes 1458 */ 1459 1460 const instable_t dis_op0F[16][16] = { 1461 { 1462 /* [00] */ IND(dis_op0F00), IND(dis_op0F01), TNS("lar",MR), TNS("lsl",MR), 1463 /* [04] */ INVALID, TNS("syscall",NORM), TNS("clts",NORM), TNS("sysret",NORM), 1464 /* [08] */ TNS("invd",NORM), TNS("wbinvd",NORM), INVALID, TNS("ud2",NORM), 1465 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1466 }, { 1467 /* [10] */ TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8), TNSZ("movlps",XMMOS,8), 1468 /* [14] */ TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8), 1469 /* [18] */ IND(dis_op0F18), INVALID, INVALID, INVALID, 1470 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1471 }, { 1472 /* [20] */ TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), 1473 /* [24] */ TSx("mov",SREG), INVALID, TSx("mov",SREG), INVALID, 1474 /* [28] */ TNSZ("movaps",XMMO,16), TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16), 1475 /* [2C] */ TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4), 1476 }, { 1477 /* [30] */ TNS("wrmsr",NORM), TNS("rdtsc",NORM), TNS("rdmsr",NORM), TNS("rdpmc",NORM), 1478 /* [34] */ TNSx("sysenter",NORM), TNSx("sysexit",NORM), INVALID, INVALID, 1479 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1480 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1481 }, { 1482 /* [40] */ TS("cmovx.o",MR), TS("cmovx.no",MR), TS("cmovx.b",MR), TS("cmovx.ae",MR), 1483 /* [44] */ TS("cmovx.e",MR), TS("cmovx.ne",MR), TS("cmovx.be",MR), TS("cmovx.a",MR), 1484 /* [48] */ TS("cmovx.s",MR), TS("cmovx.ns",MR), TS("cmovx.pe",MR), TS("cmovx.po",MR), 1485 /* [4C] */ TS("cmovx.l",MR), TS("cmovx.ge",MR), TS("cmovx.le",MR), TS("cmovx.g",MR), 1486 }, { 1487 /* [50] */ TNS("movmskps",XMMOX3), TNSZ("sqrtps",XMMO,16), TNSZ("rsqrtps",XMMO,16),TNSZ("rcpps",XMMO,16), 1488 /* [54] */ TNSZ("andps",XMMO,16), TNSZ("andnps",XMMO,16), TNSZ("orps",XMMO,16), TNSZ("xorps",XMMO,16), 1489 /* [58] */ TNSZ("addps",XMMO,16), TNSZ("mulps",XMMO,16), TNSZ("cvtps2pd",XMMO,8),TNSZ("cvtdq2ps",XMMO,16), 1490 /* [5C] */ TNSZ("subps",XMMO,16), TNSZ("minps",XMMO,16), TNSZ("divps",XMMO,16), TNSZ("maxps",XMMO,16), 1491 }, { 1492 /* [60] */ TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8), 1493 /* [64] */ TNSZ("pcmpgtb",MMO,8), TNSZ("pcmpgtw",MMO,8), TNSZ("pcmpgtd",MMO,8), TNSZ("packuswb",MMO,8), 1494 /* [68] */ TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8), 1495 /* [6C] */ TNSZ("INVALID",MMO,0), TNSZ("INVALID",MMO,0), TNSZ("movd",MMO,4), TNSZ("movq",MMO,8), 1496 }, { 1497 /* [70] */ TNSZ("pshufw",MMOPM,8), TNS("psrXXX",MR), TNS("psrXXX",MR), TNS("psrXXX",MR), 1498 /* [74] */ TNSZ("pcmpeqb",MMO,8), TNSZ("pcmpeqw",MMO,8), TNSZ("pcmpeqd",MMO,8), TNS("emms",NORM), 1499 /* [78] */ TNSy("vmread",RM), TNSy("vmwrite",MR), INVALID, INVALID, 1500 /* [7C] */ INVALID, INVALID, TNSZ("movd",MMOS,4), TNSZ("movq",MMOS,8), 1501 }, { 1502 /* [80] */ TNS("jo",D), TNS("jno",D), TNS("jb",D), TNS("jae",D), 1503 /* [84] */ TNS("je",D), TNS("jne",D), TNS("jbe",D), TNS("ja",D), 1504 /* [88] */ TNS("js",D), TNS("jns",D), TNS("jp",D), TNS("jnp",D), 1505 /* [8C] */ TNS("jl",D), TNS("jge",D), TNS("jle",D), TNS("jg",D), 1506 }, { 1507 /* [90] */ TNS("seto",Mb), TNS("setno",Mb), TNS("setb",Mb), TNS("setae",Mb), 1508 /* [94] */ TNS("sete",Mb), TNS("setne",Mb), TNS("setbe",Mb), TNS("seta",Mb), 1509 /* [98] */ TNS("sets",Mb), TNS("setns",Mb), TNS("setp",Mb), TNS("setnp",Mb), 1510 /* [9C] */ TNS("setl",Mb), TNS("setge",Mb), TNS("setle",Mb), TNS("setg",Mb), 1511 }, { 1512 /* [A0] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("cpuid",NORM), TS("bt",RMw), 1513 /* [A4] */ TS("shld",DSHIFT), TS("shld",DSHIFTcl), INVALID, INVALID, 1514 /* [A8] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("rsm",NORM), TS("bts",RMw), 1515 /* [AC] */ TS("shrd",DSHIFT), TS("shrd",DSHIFTcl), IND(dis_op0FAE), TS("imul",MRw), 1516 }, { 1517 /* [B0] */ TNS("cmpxchgb",RMw), TS("cmpxchg",RMw), TS("lss",MR), TS("btr",RMw), 1518 /* [B4] */ TS("lfs",MR), TS("lgs",MR), TS("movzb",MOVZ), TNS("movzwl",MOVZ), 1519 /* [B8] */ TNS("INVALID",MRw), INVALID, IND(dis_op0FBA), TS("btc",RMw), 1520 /* [BC] */ TS("bsf",MRw), TS("bsr",MRw), TS("movsb",MOVZ), TNS("movswl",MOVZ), 1521 }, { 1522 /* [C0] */ TNS("xaddb",XADDB), TS("xadd",RMw), TNSZ("cmpps",XMMOPM,16),TNS("movnti",RM), 1523 /* [C4] */ TNSZ("pinsrw",MMOPRM,2),TNS("pextrw",MMO3P), TNSZ("shufps",XMMOPM,16),IND(dis_op0FC7), 1524 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1525 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1526 }, { 1527 /* [D0] */ INVALID, TNSZ("psrlw",MMO,8), TNSZ("psrld",MMO,8), TNSZ("psrlq",MMO,8), 1528 /* [D4] */ TNSZ("paddq",MMO,8), TNSZ("pmullw",MMO,8), TNSZ("INVALID",MMO,0), TNS("pmovmskb",MMOM3), 1529 /* [D8] */ TNSZ("psubusb",MMO,8), TNSZ("psubusw",MMO,8), TNSZ("pminub",MMO,8), TNSZ("pand",MMO,8), 1530 /* [DC] */ TNSZ("paddusb",MMO,8), TNSZ("paddusw",MMO,8), TNSZ("pmaxub",MMO,8), TNSZ("pandn",MMO,8), 1531 }, { 1532 /* [E0] */ TNSZ("pavgb",MMO,8), TNSZ("psraw",MMO,8), TNSZ("psrad",MMO,8), TNSZ("pavgw",MMO,8), 1533 /* [E4] */ TNSZ("pmulhuw",MMO,8), TNSZ("pmulhw",MMO,8), TNS("INVALID",XMMO), TNSZ("movntq",MMOMS,8), 1534 /* [E8] */ TNSZ("psubsb",MMO,8), TNSZ("psubsw",MMO,8), TNSZ("pminsw",MMO,8), TNSZ("por",MMO,8), 1535 /* [EC] */ TNSZ("paddsb",MMO,8), TNSZ("paddsw",MMO,8), TNSZ("pmaxsw",MMO,8), TNSZ("pxor",MMO,8), 1536 }, { 1537 /* [F0] */ INVALID, TNSZ("psllw",MMO,8), TNSZ("pslld",MMO,8), TNSZ("psllq",MMO,8), 1538 /* [F4] */ TNSZ("pmuludq",MMO,8), TNSZ("pmaddwd",MMO,8), TNSZ("psadbw",MMO,8), TNSZ("maskmovq",MMOIMPL,8), 1539 /* [F8] */ TNSZ("psubb",MMO,8), TNSZ("psubw",MMO,8), TNSZ("psubd",MMO,8), TNSZ("psubq",MMO,8), 1540 /* [FC] */ TNSZ("paddb",MMO,8), TNSZ("paddw",MMO,8), TNSZ("paddd",MMO,8), INVALID, 1541 } }; 1542 1543 const instable_t dis_opAVX0F[16][16] = { 1544 { 1545 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1546 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1547 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1548 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1549 }, { 1550 /* [10] */ TNSZ("vmovups",VEX_MX,16), TNSZ("vmovups",VEX_RM,16),TNSZ("vmovlps",VEX_RMrX,8), TNSZ("vmovlps",VEX_RM,8), 1551 /* [14] */ TNSZ("vunpcklps",VEX_RMrX,16),TNSZ("vunpckhps",VEX_RMrX,16),TNSZ("vmovhps",VEX_RMrX,8),TNSZ("vmovhps",VEX_RM,8), 1552 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1553 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1554 }, { 1555 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1556 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1557 /* [28] */ TNSZ("vmovaps",VEX_MX,16), TNSZ("vmovaps",VEX_RX,16),INVALID, TNSZ("vmovntps",VEX_RM,16), 1558 /* [2C] */ INVALID, INVALID, TNSZ("vucomiss",VEX_MX,4),TNSZ("vcomiss",VEX_MX,4), 1559 }, { 1560 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1561 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1562 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1563 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1564 }, { 1565 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1566 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1567 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1568 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1569 }, { 1570 /* [50] */ TNS("vmovmskps",VEX_MR), TNSZ("vsqrtps",VEX_MX,16), TNSZ("vrsqrtps",VEX_MX,16),TNSZ("vrcpps",VEX_MX,16), 1571 /* [54] */ TNSZ("vandps",VEX_RMrX,16), TNSZ("vandnps",VEX_RMrX,16), TNSZ("vorps",VEX_RMrX,16), TNSZ("vxorps",VEX_RMrX,16), 1572 /* [58] */ TNSZ("vaddps",VEX_RMrX,16), TNSZ("vmulps",VEX_RMrX,16), TNSZ("vcvtps2pd",VEX_MX,8),TNSZ("vcvtdq2ps",VEX_MX,16), 1573 /* [5C] */ TNSZ("vsubps",VEX_RMrX,16), TNSZ("vminps",VEX_RMrX,16), TNSZ("vdivps",VEX_RMrX,16), TNSZ("vmaxps",VEX_RMrX,16), 1574 }, { 1575 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1576 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1577 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1578 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1579 }, { 1580 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1581 /* [74] */ INVALID, INVALID, INVALID, TNS("vzeroupper", VEX_NONE), 1582 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1583 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1584 }, { 1585 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1586 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1587 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1588 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1589 }, { 1590 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1591 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1592 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1593 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1594 }, { 1595 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1596 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1597 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1598 /* [AC] */ INVALID, INVALID, TNSZ("vldmxcsr",VEX_MO,2), INVALID, 1599 }, { 1600 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1601 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1602 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1603 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1604 }, { 1605 /* [C0] */ INVALID, INVALID, TNSZ("vcmpps",VEX_RMRX,16),INVALID, 1606 /* [C4] */ INVALID, INVALID, TNSZ("vshufps",VEX_RMRX,16),INVALID, 1607 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1608 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1609 }, { 1610 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1611 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1612 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1613 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1614 }, { 1615 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1616 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1617 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1618 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1619 }, { 1620 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1621 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1622 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1623 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1624 } }; 1625 1626 /* 1627 * Decode table for 0x80 opcodes 1628 */ 1629 1630 const instable_t dis_op80[8] = { 1631 1632 /* [0] */ TNS("addb",IMlw), TNS("orb",IMw), TNS("adcb",IMlw), TNS("sbbb",IMlw), 1633 /* [4] */ TNS("andb",IMw), TNS("subb",IMlw), TNS("xorb",IMw), TNS("cmpb",IMlw), 1634 }; 1635 1636 1637 /* 1638 * Decode table for 0x81 opcodes. 1639 */ 1640 1641 const instable_t dis_op81[8] = { 1642 1643 /* [0] */ TS("add",IMlw), TS("or",IMw), TS("adc",IMlw), TS("sbb",IMlw), 1644 /* [4] */ TS("and",IMw), TS("sub",IMlw), TS("xor",IMw), TS("cmp",IMlw), 1645 }; 1646 1647 1648 /* 1649 * Decode table for 0x82 opcodes. 1650 */ 1651 1652 const instable_t dis_op82[8] = { 1653 1654 /* [0] */ TNSx("addb",IMlw), TNSx("orb",IMlw), TNSx("adcb",IMlw), TNSx("sbbb",IMlw), 1655 /* [4] */ TNSx("andb",IMlw), TNSx("subb",IMlw), TNSx("xorb",IMlw), TNSx("cmpb",IMlw), 1656 }; 1657 /* 1658 * Decode table for 0x83 opcodes. 1659 */ 1660 1661 const instable_t dis_op83[8] = { 1662 1663 /* [0] */ TS("add",IMlw), TS("or",IMlw), TS("adc",IMlw), TS("sbb",IMlw), 1664 /* [4] */ TS("and",IMlw), TS("sub",IMlw), TS("xor",IMlw), TS("cmp",IMlw), 1665 }; 1666 1667 /* 1668 * Decode table for 0xC0 opcodes. 1669 */ 1670 1671 const instable_t dis_opC0[8] = { 1672 1673 /* [0] */ TNS("rolb",MvI), TNS("rorb",MvI), TNS("rclb",MvI), TNS("rcrb",MvI), 1674 /* [4] */ TNS("shlb",MvI), TNS("shrb",MvI), INVALID, TNS("sarb",MvI), 1675 }; 1676 1677 /* 1678 * Decode table for 0xD0 opcodes. 1679 */ 1680 1681 const instable_t dis_opD0[8] = { 1682 1683 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv), 1684 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv), 1685 }; 1686 1687 /* 1688 * Decode table for 0xC1 opcodes. 1689 * 186 instruction set 1690 */ 1691 1692 const instable_t dis_opC1[8] = { 1693 1694 /* [0] */ TS("rol",MvI), TS("ror",MvI), TS("rcl",MvI), TS("rcr",MvI), 1695 /* [4] */ TS("shl",MvI), TS("shr",MvI), TS("sal",MvI), TS("sar",MvI), 1696 }; 1697 1698 /* 1699 * Decode table for 0xD1 opcodes. 1700 */ 1701 1702 const instable_t dis_opD1[8] = { 1703 1704 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv), 1705 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("sal",Mv), TS("sar",Mv), 1706 }; 1707 1708 1709 /* 1710 * Decode table for 0xD2 opcodes. 1711 */ 1712 1713 const instable_t dis_opD2[8] = { 1714 1715 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv), 1716 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv), 1717 }; 1718 /* 1719 * Decode table for 0xD3 opcodes. 1720 */ 1721 1722 const instable_t dis_opD3[8] = { 1723 1724 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv), 1725 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("salb",Mv), TS("sar",Mv), 1726 }; 1727 1728 1729 /* 1730 * Decode table for 0xF6 opcodes. 1731 */ 1732 1733 const instable_t dis_opF6[8] = { 1734 1735 /* [0] */ TNS("testb",IMw), TNS("testb",IMw), TNS("notb",Mw), TNS("negb",Mw), 1736 /* [4] */ TNS("mulb",MA), TNS("imulb",MA), TNS("divb",MA), TNS("idivb",MA), 1737 }; 1738 1739 1740 /* 1741 * Decode table for 0xF7 opcodes. 1742 */ 1743 1744 const instable_t dis_opF7[8] = { 1745 1746 /* [0] */ TS("test",IMw), TS("test",IMw), TS("not",Mw), TS("neg",Mw), 1747 /* [4] */ TS("mul",MA), TS("imul",MA), TS("div",MA), TS("idiv",MA), 1748 }; 1749 1750 1751 /* 1752 * Decode table for 0xFE opcodes. 1753 */ 1754 1755 const instable_t dis_opFE[8] = { 1756 1757 /* [0] */ TNS("incb",Mw), TNS("decb",Mw), INVALID, INVALID, 1758 /* [4] */ INVALID, INVALID, INVALID, INVALID, 1759 }; 1760 /* 1761 * Decode table for 0xFF opcodes. 1762 */ 1763 1764 const instable_t dis_opFF[8] = { 1765 1766 /* [0] */ TS("inc",Mw), TS("dec",Mw), TNSyp("call",INM), TNS("lcall",INM), 1767 /* [4] */ TNSy("jmp",INM), TNS("ljmp",INM), TSp("push",M), INVALID, 1768 }; 1769 1770 /* for 287 instructions, which are a mess to decode */ 1771 1772 const instable_t dis_opFP1n2[8][8] = { 1773 { 1774 /* bit pattern: 1101 1xxx MODxx xR/M */ 1775 /* [0,0] */ TNS("fadds",M), TNS("fmuls",M), TNS("fcoms",M), TNS("fcomps",M), 1776 /* [0,4] */ TNS("fsubs",M), TNS("fsubrs",M), TNS("fdivs",M), TNS("fdivrs",M), 1777 }, { 1778 /* [1,0] */ TNS("flds",M), INVALID, TNS("fsts",M), TNS("fstps",M), 1779 /* [1,4] */ TNSZ("fldenv",M,28), TNSZ("fldcw",M,2), TNSZ("fnstenv",M,28), TNSZ("fnstcw",M,2), 1780 }, { 1781 /* [2,0] */ TNS("fiaddl",M), TNS("fimull",M), TNS("ficoml",M), TNS("ficompl",M), 1782 /* [2,4] */ TNS("fisubl",M), TNS("fisubrl",M), TNS("fidivl",M), TNS("fidivrl",M), 1783 }, { 1784 /* [3,0] */ TNS("fildl",M), INVALID, TNS("fistl",M), TNS("fistpl",M), 1785 /* [3,4] */ INVALID, TNSZ("fldt",M,10), INVALID, TNSZ("fstpt",M,10), 1786 }, { 1787 /* [4,0] */ TNSZ("faddl",M,8), TNSZ("fmull",M,8), TNSZ("fcoml",M,8), TNSZ("fcompl",M,8), 1788 /* [4,1] */ TNSZ("fsubl",M,8), TNSZ("fsubrl",M,8), TNSZ("fdivl",M,8), TNSZ("fdivrl",M,8), 1789 }, { 1790 /* [5,0] */ TNSZ("fldl",M,8), INVALID, TNSZ("fstl",M,8), TNSZ("fstpl",M,8), 1791 /* [5,4] */ TNSZ("frstor",M,108), INVALID, TNSZ("fnsave",M,108), TNSZ("fnstsw",M,2), 1792 }, { 1793 /* [6,0] */ TNSZ("fiadd",M,2), TNSZ("fimul",M,2), TNSZ("ficom",M,2), TNSZ("ficomp",M,2), 1794 /* [6,4] */ TNSZ("fisub",M,2), TNSZ("fisubr",M,2), TNSZ("fidiv",M,2), TNSZ("fidivr",M,2), 1795 }, { 1796 /* [7,0] */ TNSZ("fild",M,2), INVALID, TNSZ("fist",M,2), TNSZ("fistp",M,2), 1797 /* [7,4] */ TNSZ("fbld",M,10), TNSZ("fildll",M,8), TNSZ("fbstp",M,10), TNSZ("fistpll",M,8), 1798 } }; 1799 1800 const instable_t dis_opFP3[8][8] = { 1801 { 1802 /* bit pattern: 1101 1xxx 11xx xREG */ 1803 /* [0,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F), 1804 /* [0,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF), 1805 }, { 1806 /* [1,0] */ TNS("fld",F), TNS("fxch",F), TNS("fnop",NORM), TNS("fstp",F), 1807 /* [1,4] */ INVALID, INVALID, INVALID, INVALID, 1808 }, { 1809 /* [2,0] */ INVALID, INVALID, INVALID, INVALID, 1810 /* [2,4] */ INVALID, TNS("fucompp",NORM), INVALID, INVALID, 1811 }, { 1812 /* [3,0] */ INVALID, INVALID, INVALID, INVALID, 1813 /* [3,4] */ INVALID, INVALID, INVALID, INVALID, 1814 }, { 1815 /* [4,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F), 1816 /* [4,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF), 1817 }, { 1818 /* [5,0] */ TNS("ffree",F), TNS("fxch",F), TNS("fst",F), TNS("fstp",F), 1819 /* [5,4] */ TNS("fucom",F), TNS("fucomp",F), INVALID, INVALID, 1820 }, { 1821 /* [6,0] */ TNS("faddp",FF), TNS("fmulp",FF), TNS("fcomp",F), TNS("fcompp",NORM), 1822 /* [6,4] */ TNS("fsubp",FF), TNS("fsubrp",FF), TNS("fdivp",FF), TNS("fdivrp",FF), 1823 }, { 1824 /* [7,0] */ TNS("ffreep",F), TNS("fxch",F), TNS("fstp",F), TNS("fstp",F), 1825 /* [7,4] */ TNS("fnstsw",M), TNS("fucomip",FFC), TNS("fcomip",FFC), INVALID, 1826 } }; 1827 1828 const instable_t dis_opFP4[4][8] = { 1829 { 1830 /* bit pattern: 1101 1001 111x xxxx */ 1831 /* [0,0] */ TNS("fchs",NORM), TNS("fabs",NORM), INVALID, INVALID, 1832 /* [0,4] */ TNS("ftst",NORM), TNS("fxam",NORM), TNS("ftstp",NORM), INVALID, 1833 }, { 1834 /* [1,0] */ TNS("fld1",NORM), TNS("fldl2t",NORM), TNS("fldl2e",NORM), TNS("fldpi",NORM), 1835 /* [1,4] */ TNS("fldlg2",NORM), TNS("fldln2",NORM), TNS("fldz",NORM), INVALID, 1836 }, { 1837 /* [2,0] */ TNS("f2xm1",NORM), TNS("fyl2x",NORM), TNS("fptan",NORM), TNS("fpatan",NORM), 1838 /* [2,4] */ TNS("fxtract",NORM), TNS("fprem1",NORM), TNS("fdecstp",NORM), TNS("fincstp",NORM), 1839 }, { 1840 /* [3,0] */ TNS("fprem",NORM), TNS("fyl2xp1",NORM), TNS("fsqrt",NORM), TNS("fsincos",NORM), 1841 /* [3,4] */ TNS("frndint",NORM), TNS("fscale",NORM), TNS("fsin",NORM), TNS("fcos",NORM), 1842 } }; 1843 1844 const instable_t dis_opFP5[8] = { 1845 /* bit pattern: 1101 1011 111x xxxx */ 1846 /* [0] */ TNS("feni",NORM), TNS("fdisi",NORM), TNS("fnclex",NORM), TNS("fninit",NORM), 1847 /* [4] */ TNS("fsetpm",NORM), TNS("frstpm",NORM), INVALID, INVALID, 1848 }; 1849 1850 const instable_t dis_opFP6[8] = { 1851 /* bit pattern: 1101 1011 11yy yxxx */ 1852 /* [00] */ TNS("fcmov.nb",FF), TNS("fcmov.ne",FF), TNS("fcmov.nbe",FF), TNS("fcmov.nu",FF), 1853 /* [04] */ INVALID, TNS("fucomi",F), TNS("fcomi",F), INVALID, 1854 }; 1855 1856 const instable_t dis_opFP7[8] = { 1857 /* bit pattern: 1101 1010 11yy yxxx */ 1858 /* [00] */ TNS("fcmov.b",FF), TNS("fcmov.e",FF), TNS("fcmov.be",FF), TNS("fcmov.u",FF), 1859 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1860 }; 1861 1862 /* 1863 * Main decode table for the op codes. The first two nibbles 1864 * will be used as an index into the table. If there is a 1865 * a need to further decode an instruction, the array to be 1866 * referenced is indicated with the other two entries being 1867 * empty. 1868 */ 1869 1870 const instable_t dis_distable[16][16] = { 1871 { 1872 /* [0,0] */ TNS("addb",RMw), TS("add",RMw), TNS("addb",MRw), TS("add",MRw), 1873 /* [0,4] */ TNS("addb",IA), TS("add",IA), TSx("push",SEG), TSx("pop",SEG), 1874 /* [0,8] */ TNS("orb",RMw), TS("or",RMw), TNS("orb",MRw), TS("or",MRw), 1875 /* [0,C] */ TNS("orb",IA), TS("or",IA), TSx("push",SEG), IND(dis_op0F), 1876 }, { 1877 /* [1,0] */ TNS("adcb",RMw), TS("adc",RMw), TNS("adcb",MRw), TS("adc",MRw), 1878 /* [1,4] */ TNS("adcb",IA), TS("adc",IA), TSx("push",SEG), TSx("pop",SEG), 1879 /* [1,8] */ TNS("sbbb",RMw), TS("sbb",RMw), TNS("sbbb",MRw), TS("sbb",MRw), 1880 /* [1,C] */ TNS("sbbb",IA), TS("sbb",IA), TSx("push",SEG), TSx("pop",SEG), 1881 }, { 1882 /* [2,0] */ TNS("andb",RMw), TS("and",RMw), TNS("andb",MRw), TS("and",MRw), 1883 /* [2,4] */ TNS("andb",IA), TS("and",IA), TNSx("%es:",OVERRIDE), TNSx("daa",NORM), 1884 /* [2,8] */ TNS("subb",RMw), TS("sub",RMw), TNS("subb",MRw), TS("sub",MRw), 1885 /* [2,C] */ TNS("subb",IA), TS("sub",IA), TNSx("%cs:",OVERRIDE), TNSx("das",NORM), 1886 }, { 1887 /* [3,0] */ TNS("xorb",RMw), TS("xor",RMw), TNS("xorb",MRw), TS("xor",MRw), 1888 /* [3,4] */ TNS("xorb",IA), TS("xor",IA), TNSx("%ss:",OVERRIDE), TNSx("aaa",NORM), 1889 /* [3,8] */ TNS("cmpb",RMw), TS("cmp",RMw), TNS("cmpb",MRw), TS("cmp",MRw), 1890 /* [3,C] */ TNS("cmpb",IA), TS("cmp",IA), TNSx("%ds:",OVERRIDE), TNSx("aas",NORM), 1891 }, { 1892 /* [4,0] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R), 1893 /* [4,4] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R), 1894 /* [4,8] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R), 1895 /* [4,C] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R), 1896 }, { 1897 /* [5,0] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R), 1898 /* [5,4] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R), 1899 /* [5,8] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R), 1900 /* [5,C] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R), 1901 }, { 1902 /* [6,0] */ TSZx("pusha",IMPLMEM,28),TSZx("popa",IMPLMEM,28), TSx("bound",MR), TNS("arpl",RMw), 1903 /* [6,4] */ TNS("%fs:",OVERRIDE), TNS("%gs:",OVERRIDE), TNS("data16",DM), TNS("addr16",AM), 1904 /* [6,8] */ TSp("push",I), TS("imul",IMUL), TSp("push",Ib), TS("imul",IMUL), 1905 /* [6,C] */ TNSZ("insb",IMPLMEM,1), TSZ("ins",IMPLMEM,4), TNSZ("outsb",IMPLMEM,1),TSZ("outs",IMPLMEM,4), 1906 }, { 1907 /* [7,0] */ TNSy("jo",BD), TNSy("jno",BD), TNSy("jb",BD), TNSy("jae",BD), 1908 /* [7,4] */ TNSy("je",BD), TNSy("jne",BD), TNSy("jbe",BD), TNSy("ja",BD), 1909 /* [7,8] */ TNSy("js",BD), TNSy("jns",BD), TNSy("jp",BD), TNSy("jnp",BD), 1910 /* [7,C] */ TNSy("jl",BD), TNSy("jge",BD), TNSy("jle",BD), TNSy("jg",BD), 1911 }, { 1912 /* [8,0] */ IND(dis_op80), IND(dis_op81), INDx(dis_op82), IND(dis_op83), 1913 /* [8,4] */ TNS("testb",RMw), TS("test",RMw), TNS("xchgb",RMw), TS("xchg",RMw), 1914 /* [8,8] */ TNS("movb",RMw), TS("mov",RMw), TNS("movb",MRw), TS("mov",MRw), 1915 /* [8,C] */ TNS("movw",SM), TS("lea",MR), TNS("movw",MS), TSp("pop",M), 1916 }, { 1917 /* [9,0] */ TNS("nop",NORM), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), 1918 /* [9,4] */ TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), 1919 /* [9,8] */ TNS("cXtX",CBW), TNS("cXtX",CWD), TNSx("lcall",SO), TNS("fwait",NORM), 1920 /* [9,C] */ TSZy("pushf",IMPLMEM,4),TSZy("popf",IMPLMEM,4), TNSx("sahf",NORM), TNSx("lahf",NORM), 1921 }, { 1922 /* [A,0] */ TNS("movb",OA), TS("mov",OA), TNS("movb",AO), TS("mov",AO), 1923 /* [A,4] */ TNSZ("movsb",SD,1), TS("movs",SD), TNSZ("cmpsb",SD,1), TS("cmps",SD), 1924 /* [A,8] */ TNS("testb",IA), TS("test",IA), TNS("stosb",AD), TS("stos",AD), 1925 /* [A,C] */ TNS("lodsb",SA), TS("lods",SA), TNS("scasb",AD), TS("scas",AD), 1926 }, { 1927 /* [B,0] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), 1928 /* [B,4] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), 1929 /* [B,8] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR), 1930 /* [B,C] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR), 1931 }, { 1932 /* [C,0] */ IND(dis_opC0), IND(dis_opC1), TNSyp("ret",RET), TNSyp("ret",NORM), 1933 /* [C,4] */ TNSx("les",MR), TNSx("lds",MR), TNS("movb",IMw), TS("mov",IMw), 1934 /* [C,8] */ TNSyp("enter",ENTER), TNSyp("leave",NORM), TNS("lret",RET), TNS("lret",NORM), 1935 /* [C,C] */ TNS("int",INT3), TNS("int",INTx), TNSx("into",NORM), TNS("iret",NORM), 1936 }, { 1937 /* [D,0] */ IND(dis_opD0), IND(dis_opD1), IND(dis_opD2), IND(dis_opD3), 1938 /* [D,4] */ TNSx("aam",U), TNSx("aad",U), TNSx("falc",NORM), TNSZ("xlat",IMPLMEM,1), 1939 1940 /* 287 instructions. Note that although the indirect field */ 1941 /* indicates opFP1n2 for further decoding, this is not necessarily */ 1942 /* the case since the opFP arrays are not partitioned according to key1 */ 1943 /* and key2. opFP1n2 is given only to indicate that we haven't */ 1944 /* finished decoding the instruction. */ 1945 /* [D,8] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), 1946 /* [D,C] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), 1947 }, { 1948 /* [E,0] */ TNSy("loopnz",BD), TNSy("loopz",BD), TNSy("loop",BD), TNSy("jcxz",BD), 1949 /* [E,4] */ TNS("inb",P), TS("in",P), TNS("outb",P), TS("out",P), 1950 /* [E,8] */ TNSyp("call",D), TNSy("jmp",D), TNSx("ljmp",SO), TNSy("jmp",BD), 1951 /* [E,C] */ TNS("inb",V), TS("in",V), TNS("outb",V), TS("out",V), 1952 }, { 1953 /* [F,0] */ TNS("lock",LOCK), TNS("icebp", NORM), TNS("repnz",PREFIX), TNS("repz",PREFIX), 1954 /* [F,4] */ TNS("hlt",NORM), TNS("cmc",NORM), IND(dis_opF6), IND(dis_opF7), 1955 /* [F,8] */ TNS("clc",NORM), TNS("stc",NORM), TNS("cli",NORM), TNS("sti",NORM), 1956 /* [F,C] */ TNS("cld",NORM), TNS("std",NORM), IND(dis_opFE), IND(dis_opFF), 1957 } }; 1958 1959 /* END CSTYLED */ 1960 1961 /* 1962 * common functions to decode and disassemble an x86 or amd64 instruction 1963 */ 1964 1965 /* 1966 * These are the individual fields of a REX prefix. Note that a REX 1967 * prefix with none of these set is still needed to: 1968 * - use the MOVSXD (sign extend 32 to 64 bits) instruction 1969 * - access the %sil, %dil, %bpl, %spl registers 1970 */ 1971 #define REX_W 0x08 /* 64 bit operand size when set */ 1972 #define REX_R 0x04 /* high order bit extension of ModRM reg field */ 1973 #define REX_X 0x02 /* high order bit extension of SIB index field */ 1974 #define REX_B 0x01 /* extends ModRM r_m, SIB base, or opcode reg */ 1975 1976 /* 1977 * These are the individual fields of a VEX prefix. 1978 */ 1979 #define VEX_R 0x08 /* REX.R in 1's complement form */ 1980 #define VEX_X 0x04 /* REX.X in 1's complement form */ 1981 #define VEX_B 0x02 /* REX.B in 1's complement form */ 1982 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector */ 1983 #define VEX_L 0x04 1984 #define VEX_W 0x08 /* opcode specific, use like REX.W */ 1985 #define VEX_m 0x1F /* VEX m-mmmm field */ 1986 #define VEX_v 0x78 /* VEX register specifier */ 1987 #define VEX_p 0x03 /* VEX pp field, opcode extension */ 1988 1989 /* VEX m-mmmm field, only used by three bytes prefix */ 1990 #define VEX_m_0F 0x01 /* implied 0F leading opcode byte */ 1991 #define VEX_m_0F38 0x02 /* implied 0F 38 leading opcode byte */ 1992 #define VEX_m_0F3A 0x03 /* implied 0F 3A leading opcode byte */ 1993 1994 /* VEX pp field, providing equivalent functionality of a SIMD prefix */ 1995 #define VEX_p_66 0x01 1996 #define VEX_p_F3 0x02 1997 #define VEX_p_F2 0x03 1998 1999 /* 2000 * Even in 64 bit mode, usually only 4 byte immediate operands are supported. 2001 */ 2002 static int isize[] = {1, 2, 4, 4}; 2003 static int isize64[] = {1, 2, 4, 8}; 2004 2005 /* 2006 * Just a bunch of useful macros. 2007 */ 2008 #define WBIT(x) (x & 0x1) /* to get w bit */ 2009 #define REGNO(x) (x & 0x7) /* to get 3 bit register */ 2010 #define VBIT(x) ((x)>>1 & 0x1) /* to get 'v' bit */ 2011 #define OPSIZE(osize, wbit) ((wbit) ? isize[osize] : 1) 2012 #define OPSIZE64(osize, wbit) ((wbit) ? isize64[osize] : 1) 2013 2014 #define REG_ONLY 3 /* mode to indicate a register operand (not memory) */ 2015 2016 #define BYTE_OPND 0 /* w-bit value indicating byte register */ 2017 #define LONG_OPND 1 /* w-bit value indicating opnd_size register */ 2018 #define MM_OPND 2 /* "value" used to indicate a mmx reg */ 2019 #define XMM_OPND 3 /* "value" used to indicate a xmm reg */ 2020 #define SEG_OPND 4 /* "value" used to indicate a segment reg */ 2021 #define CONTROL_OPND 5 /* "value" used to indicate a control reg */ 2022 #define DEBUG_OPND 6 /* "value" used to indicate a debug reg */ 2023 #define TEST_OPND 7 /* "value" used to indicate a test reg */ 2024 #define WORD_OPND 8 /* w-bit value indicating word size reg */ 2025 #define YMM_OPND 9 /* "value" used to indicate a ymm reg */ 2026 2027 /* 2028 * Get the next byte and separate the op code into the high and low nibbles. 2029 */ 2030 static int 2031 dtrace_get_opcode(dis86_t *x, uint_t *high, uint_t *low) 2032 { 2033 int byte; 2034 2035 /* 2036 * x86 instructions have a maximum length of 15 bytes. Bail out if 2037 * we try to read more. 2038 */ 2039 if (x->d86_len >= 15) 2040 return (x->d86_error = 1); 2041 2042 if (x->d86_error) 2043 return (1); 2044 byte = x->d86_get_byte(x->d86_data); 2045 if (byte < 0) 2046 return (x->d86_error = 1); 2047 x->d86_bytes[x->d86_len++] = byte; 2048 *low = byte & 0xf; /* ----xxxx low 4 bits */ 2049 *high = byte >> 4 & 0xf; /* xxxx---- bits 7 to 4 */ 2050 return (0); 2051 } 2052 2053 /* 2054 * Get and decode an SIB (scaled index base) byte 2055 */ 2056 static void 2057 dtrace_get_SIB(dis86_t *x, uint_t *ss, uint_t *index, uint_t *base) 2058 { 2059 int byte; 2060 2061 if (x->d86_error) 2062 return; 2063 2064 byte = x->d86_get_byte(x->d86_data); 2065 if (byte < 0) { 2066 x->d86_error = 1; 2067 return; 2068 } 2069 x->d86_bytes[x->d86_len++] = byte; 2070 2071 *base = byte & 0x7; 2072 *index = (byte >> 3) & 0x7; 2073 *ss = (byte >> 6) & 0x3; 2074 } 2075 2076 /* 2077 * Get the byte following the op code and separate it into the 2078 * mode, register, and r/m fields. 2079 */ 2080 static void 2081 dtrace_get_modrm(dis86_t *x, uint_t *mode, uint_t *reg, uint_t *r_m) 2082 { 2083 if (x->d86_got_modrm == 0) { 2084 if (x->d86_rmindex == -1) 2085 x->d86_rmindex = x->d86_len; 2086 dtrace_get_SIB(x, mode, reg, r_m); 2087 x->d86_got_modrm = 1; 2088 } 2089 } 2090 2091 /* 2092 * Adjust register selection based on any REX prefix bits present. 2093 */ 2094 /*ARGSUSED*/ 2095 static void 2096 dtrace_rex_adjust(uint_t rex_prefix, uint_t mode, uint_t *reg, uint_t *r_m) 2097 { 2098 if (reg != NULL && r_m == NULL) { 2099 if (rex_prefix & REX_B) 2100 *reg += 8; 2101 } else { 2102 if (reg != NULL && (REX_R & rex_prefix) != 0) 2103 *reg += 8; 2104 if (r_m != NULL && (REX_B & rex_prefix) != 0) 2105 *r_m += 8; 2106 } 2107 } 2108 2109 /* 2110 * Adjust register selection based on any VEX prefix bits present. 2111 * Notes: VEX.R, VEX.X and VEX.B use the inverted form compared with REX prefix 2112 */ 2113 /*ARGSUSED*/ 2114 static void 2115 dtrace_vex_adjust(uint_t vex_byte1, uint_t mode, uint_t *reg, uint_t *r_m) 2116 { 2117 if (reg != NULL && r_m == NULL) { 2118 if (!(vex_byte1 & VEX_B)) 2119 *reg += 8; 2120 } else { 2121 if (reg != NULL && ((VEX_R & vex_byte1) == 0)) 2122 *reg += 8; 2123 if (r_m != NULL && ((VEX_B & vex_byte1) == 0)) 2124 *r_m += 8; 2125 } 2126 } 2127 2128 /* 2129 * Get an immediate operand of the given size, with sign extension. 2130 */ 2131 static void 2132 dtrace_imm_opnd(dis86_t *x, int wbit, int size, int opindex) 2133 { 2134 int i; 2135 int byte; 2136 int valsize; 2137 2138 if (x->d86_numopnds < opindex + 1) 2139 x->d86_numopnds = opindex + 1; 2140 2141 switch (wbit) { 2142 case BYTE_OPND: 2143 valsize = 1; 2144 break; 2145 case LONG_OPND: 2146 if (x->d86_opnd_size == SIZE16) 2147 valsize = 2; 2148 else if (x->d86_opnd_size == SIZE32) 2149 valsize = 4; 2150 else 2151 valsize = 8; 2152 break; 2153 case MM_OPND: 2154 case XMM_OPND: 2155 case YMM_OPND: 2156 case SEG_OPND: 2157 case CONTROL_OPND: 2158 case DEBUG_OPND: 2159 case TEST_OPND: 2160 valsize = size; 2161 break; 2162 case WORD_OPND: 2163 valsize = 2; 2164 break; 2165 } 2166 if (valsize < size) 2167 valsize = size; 2168 2169 if (x->d86_error) 2170 return; 2171 x->d86_opnd[opindex].d86_value = 0; 2172 for (i = 0; i < size; ++i) { 2173 byte = x->d86_get_byte(x->d86_data); 2174 if (byte < 0) { 2175 x->d86_error = 1; 2176 return; 2177 } 2178 x->d86_bytes[x->d86_len++] = byte; 2179 x->d86_opnd[opindex].d86_value |= (uint64_t)byte << (i * 8); 2180 } 2181 /* Do sign extension */ 2182 if (x->d86_bytes[x->d86_len - 1] & 0x80) { 2183 for (; i < sizeof (uint64_t); i++) 2184 x->d86_opnd[opindex].d86_value |= 2185 (uint64_t)0xff << (i * 8); 2186 } 2187 #ifdef DIS_TEXT 2188 x->d86_opnd[opindex].d86_mode = MODE_SIGNED; 2189 x->d86_opnd[opindex].d86_value_size = valsize; 2190 x->d86_imm_bytes += size; 2191 #endif 2192 } 2193 2194 /* 2195 * Get an ip relative operand of the given size, with sign extension. 2196 */ 2197 static void 2198 dtrace_disp_opnd(dis86_t *x, int wbit, int size, int opindex) 2199 { 2200 dtrace_imm_opnd(x, wbit, size, opindex); 2201 #ifdef DIS_TEXT 2202 x->d86_opnd[opindex].d86_mode = MODE_IPREL; 2203 #endif 2204 } 2205 2206 /* 2207 * Check to see if there is a segment override prefix pending. 2208 * If so, print it in the current 'operand' location and set 2209 * the override flag back to false. 2210 */ 2211 /*ARGSUSED*/ 2212 static void 2213 dtrace_check_override(dis86_t *x, int opindex) 2214 { 2215 #ifdef DIS_TEXT 2216 if (x->d86_seg_prefix) { 2217 (void) strlcat(x->d86_opnd[opindex].d86_prefix, 2218 x->d86_seg_prefix, PFIXLEN); 2219 } 2220 #endif 2221 x->d86_seg_prefix = NULL; 2222 } 2223 2224 2225 /* 2226 * Process a single instruction Register or Memory operand. 2227 * 2228 * mode = addressing mode from ModRM byte 2229 * r_m = r_m (or reg if mode == 3) field from ModRM byte 2230 * wbit = indicates which register (8bit, 16bit, ... MMX, etc.) set to use. 2231 * o = index of operand that we are processing (0, 1 or 2) 2232 * 2233 * the value of reg or r_m must have already been adjusted for any REX prefix. 2234 */ 2235 /*ARGSUSED*/ 2236 static void 2237 dtrace_get_operand(dis86_t *x, uint_t mode, uint_t r_m, int wbit, int opindex) 2238 { 2239 int have_SIB = 0; /* flag presence of scale-index-byte */ 2240 uint_t ss; /* scale-factor from opcode */ 2241 uint_t index; /* index register number */ 2242 uint_t base; /* base register number */ 2243 int dispsize; /* size of displacement in bytes */ 2244 #ifdef DIS_TEXT 2245 char *opnd = x->d86_opnd[opindex].d86_opnd; 2246 #endif 2247 2248 if (x->d86_numopnds < opindex + 1) 2249 x->d86_numopnds = opindex + 1; 2250 2251 if (x->d86_error) 2252 return; 2253 2254 /* 2255 * first handle a simple register 2256 */ 2257 if (mode == REG_ONLY) { 2258 #ifdef DIS_TEXT 2259 switch (wbit) { 2260 case MM_OPND: 2261 (void) strlcat(opnd, dis_MMREG[r_m], OPLEN); 2262 break; 2263 case XMM_OPND: 2264 (void) strlcat(opnd, dis_XMMREG[r_m], OPLEN); 2265 break; 2266 case YMM_OPND: 2267 (void) strlcat(opnd, dis_YMMREG[r_m], OPLEN); 2268 break; 2269 case SEG_OPND: 2270 (void) strlcat(opnd, dis_SEGREG[r_m], OPLEN); 2271 break; 2272 case CONTROL_OPND: 2273 (void) strlcat(opnd, dis_CONTROLREG[r_m], OPLEN); 2274 break; 2275 case DEBUG_OPND: 2276 (void) strlcat(opnd, dis_DEBUGREG[r_m], OPLEN); 2277 break; 2278 case TEST_OPND: 2279 (void) strlcat(opnd, dis_TESTREG[r_m], OPLEN); 2280 break; 2281 case BYTE_OPND: 2282 if (x->d86_rex_prefix == 0) 2283 (void) strlcat(opnd, dis_REG8[r_m], OPLEN); 2284 else 2285 (void) strlcat(opnd, dis_REG8_REX[r_m], OPLEN); 2286 break; 2287 case WORD_OPND: 2288 (void) strlcat(opnd, dis_REG16[r_m], OPLEN); 2289 break; 2290 case LONG_OPND: 2291 if (x->d86_opnd_size == SIZE16) 2292 (void) strlcat(opnd, dis_REG16[r_m], OPLEN); 2293 else if (x->d86_opnd_size == SIZE32) 2294 (void) strlcat(opnd, dis_REG32[r_m], OPLEN); 2295 else 2296 (void) strlcat(opnd, dis_REG64[r_m], OPLEN); 2297 break; 2298 } 2299 #endif /* DIS_TEXT */ 2300 return; 2301 } 2302 2303 /* 2304 * if symbolic representation, skip override prefix, if any 2305 */ 2306 dtrace_check_override(x, opindex); 2307 2308 /* 2309 * Handle 16 bit memory references first, since they decode 2310 * the mode values more simply. 2311 * mode 1 is r_m + 8 bit displacement 2312 * mode 2 is r_m + 16 bit displacement 2313 * mode 0 is just r_m, unless r_m is 6 which is 16 bit disp 2314 */ 2315 if (x->d86_addr_size == SIZE16) { 2316 if ((mode == 0 && r_m == 6) || mode == 2) 2317 dtrace_imm_opnd(x, WORD_OPND, 2, opindex); 2318 else if (mode == 1) 2319 dtrace_imm_opnd(x, BYTE_OPND, 1, opindex); 2320 #ifdef DIS_TEXT 2321 if (mode == 0 && r_m == 6) 2322 x->d86_opnd[opindex].d86_mode = MODE_SIGNED; 2323 else if (mode == 0) 2324 x->d86_opnd[opindex].d86_mode = MODE_NONE; 2325 else 2326 x->d86_opnd[opindex].d86_mode = MODE_OFFSET; 2327 (void) strlcat(opnd, dis_addr16[mode][r_m], OPLEN); 2328 #endif 2329 return; 2330 } 2331 2332 /* 2333 * 32 and 64 bit addressing modes are more complex since they 2334 * can involve an SIB (scaled index and base) byte to decode. 2335 */ 2336 if (r_m == ESP_REGNO || r_m == ESP_REGNO + 8) { 2337 have_SIB = 1; 2338 dtrace_get_SIB(x, &ss, &index, &base); 2339 if (x->d86_error) 2340 return; 2341 if (base != 5 || mode != 0) 2342 if (x->d86_rex_prefix & REX_B) 2343 base += 8; 2344 if (x->d86_rex_prefix & REX_X) 2345 index += 8; 2346 } else { 2347 base = r_m; 2348 } 2349 2350 /* 2351 * Compute the displacement size and get its bytes 2352 */ 2353 dispsize = 0; 2354 2355 if (mode == 1) 2356 dispsize = 1; 2357 else if (mode == 2) 2358 dispsize = 4; 2359 else if ((r_m & 7) == EBP_REGNO || 2360 (have_SIB && (base & 7) == EBP_REGNO)) 2361 dispsize = 4; 2362 2363 if (dispsize > 0) { 2364 dtrace_imm_opnd(x, dispsize == 4 ? LONG_OPND : BYTE_OPND, 2365 dispsize, opindex); 2366 if (x->d86_error) 2367 return; 2368 } 2369 2370 #ifdef DIS_TEXT 2371 if (dispsize > 0) 2372 x->d86_opnd[opindex].d86_mode = MODE_OFFSET; 2373 2374 if (have_SIB == 0) { 2375 if (x->d86_mode == SIZE32) { 2376 if (mode == 0) 2377 (void) strlcat(opnd, dis_addr32_mode0[r_m], 2378 OPLEN); 2379 else 2380 (void) strlcat(opnd, dis_addr32_mode12[r_m], 2381 OPLEN); 2382 } else { 2383 if (mode == 0) { 2384 (void) strlcat(opnd, dis_addr64_mode0[r_m], 2385 OPLEN); 2386 if (r_m == 5) { 2387 x->d86_opnd[opindex].d86_mode = 2388 MODE_RIPREL; 2389 } 2390 } else { 2391 (void) strlcat(opnd, dis_addr64_mode12[r_m], 2392 OPLEN); 2393 } 2394 } 2395 } else { 2396 uint_t need_paren = 0; 2397 char **regs; 2398 if (x->d86_mode == SIZE32) /* NOTE this is not addr_size! */ 2399 regs = (char **)dis_REG32; 2400 else 2401 regs = (char **)dis_REG64; 2402 2403 /* 2404 * print the base (if any) 2405 */ 2406 if (base == EBP_REGNO && mode == 0) { 2407 if (index != ESP_REGNO) { 2408 (void) strlcat(opnd, "(", OPLEN); 2409 need_paren = 1; 2410 } 2411 } else { 2412 (void) strlcat(opnd, "(", OPLEN); 2413 (void) strlcat(opnd, regs[base], OPLEN); 2414 need_paren = 1; 2415 } 2416 2417 /* 2418 * print the index (if any) 2419 */ 2420 if (index != ESP_REGNO) { 2421 (void) strlcat(opnd, ",", OPLEN); 2422 (void) strlcat(opnd, regs[index], OPLEN); 2423 (void) strlcat(opnd, dis_scale_factor[ss], OPLEN); 2424 } else 2425 if (need_paren) 2426 (void) strlcat(opnd, ")", OPLEN); 2427 } 2428 #endif 2429 } 2430 2431 /* 2432 * Operand sequence for standard instruction involving one register 2433 * and one register/memory operand. 2434 * wbit indicates a byte(0) or opnd_size(1) operation 2435 * vbit indicates direction (0 for "opcode r,r_m") or (1 for "opcode r_m, r") 2436 */ 2437 #define STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, vbit) { \ 2438 dtrace_get_modrm(x, &mode, ®, &r_m); \ 2439 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 2440 dtrace_get_operand(x, mode, r_m, wbit, vbit); \ 2441 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1 - vbit); \ 2442 } 2443 2444 /* 2445 * Similar to above, but allows for the two operands to be of different 2446 * classes (ie. wbit). 2447 * wbit is for the r_m operand 2448 * w2 is for the reg operand 2449 */ 2450 #define MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, w2, vbit) { \ 2451 dtrace_get_modrm(x, &mode, ®, &r_m); \ 2452 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 2453 dtrace_get_operand(x, mode, r_m, wbit, vbit); \ 2454 dtrace_get_operand(x, REG_ONLY, reg, w2, 1 - vbit); \ 2455 } 2456 2457 /* 2458 * Similar, but for 2 operands plus an immediate. 2459 * vbit indicates direction 2460 * 0 for "opcode imm, r, r_m" or 2461 * 1 for "opcode imm, r_m, r" 2462 */ 2463 #define THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize, vbit) { \ 2464 dtrace_get_modrm(x, &mode, ®, &r_m); \ 2465 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 2466 dtrace_get_operand(x, mode, r_m, wbit, 2-vbit); \ 2467 dtrace_get_operand(x, REG_ONLY, reg, w2, 1+vbit); \ 2468 dtrace_imm_opnd(x, wbit, immsize, 0); \ 2469 } 2470 2471 /* 2472 * Similar, but for 2 operands plus two immediates. 2473 */ 2474 #define FOUROPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize) { \ 2475 dtrace_get_modrm(x, &mode, ®, &r_m); \ 2476 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 2477 dtrace_get_operand(x, mode, r_m, wbit, 2); \ 2478 dtrace_get_operand(x, REG_ONLY, reg, w2, 3); \ 2479 dtrace_imm_opnd(x, wbit, immsize, 1); \ 2480 dtrace_imm_opnd(x, wbit, immsize, 0); \ 2481 } 2482 2483 /* 2484 * 1 operands plus two immediates. 2485 */ 2486 #define ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, wbit, immsize) { \ 2487 dtrace_get_modrm(x, &mode, ®, &r_m); \ 2488 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 2489 dtrace_get_operand(x, mode, r_m, wbit, 2); \ 2490 dtrace_imm_opnd(x, wbit, immsize, 1); \ 2491 dtrace_imm_opnd(x, wbit, immsize, 0); \ 2492 } 2493 2494 /* 2495 * Dissassemble a single x86 or amd64 instruction. 2496 * 2497 * Mode determines the default operating mode (SIZE16, SIZE32 or SIZE64) 2498 * for interpreting instructions. 2499 * 2500 * returns non-zero for bad opcode 2501 */ 2502 int 2503 dtrace_disx86(dis86_t *x, uint_t cpu_mode) 2504 { 2505 instable_t *dp; /* decode table being used */ 2506 #ifdef DIS_TEXT 2507 uint_t i; 2508 #endif 2509 #ifdef DIS_MEM 2510 uint_t nomem = 0; 2511 #define NOMEM (nomem = 1) 2512 #else 2513 #define NOMEM /* nothing */ 2514 #endif 2515 uint_t opnd_size; /* SIZE16, SIZE32 or SIZE64 */ 2516 uint_t addr_size; /* SIZE16, SIZE32 or SIZE64 */ 2517 uint_t wbit; /* opcode wbit, 0 is 8 bit, !0 for opnd_size */ 2518 uint_t w2; /* wbit value for second operand */ 2519 uint_t vbit; 2520 uint_t mode = 0; /* mode value from ModRM byte */ 2521 uint_t reg; /* reg value from ModRM byte */ 2522 uint_t r_m; /* r_m value from ModRM byte */ 2523 2524 uint_t opcode1; /* high nibble of 1st byte */ 2525 uint_t opcode2; /* low nibble of 1st byte */ 2526 uint_t opcode3; /* extra opcode bits usually from ModRM byte */ 2527 uint_t opcode4; /* high nibble of 2nd byte */ 2528 uint_t opcode5; /* low nibble of 2nd byte */ 2529 uint_t opcode6; /* high nibble of 3rd byte */ 2530 uint_t opcode7; /* low nibble of 3rd byte */ 2531 uint_t opcode_bytes = 1; 2532 2533 /* 2534 * legacy prefixes come in 5 flavors, you should have only one of each 2535 */ 2536 uint_t opnd_size_prefix = 0; 2537 uint_t addr_size_prefix = 0; 2538 uint_t segment_prefix = 0; 2539 uint_t lock_prefix = 0; 2540 uint_t rep_prefix = 0; 2541 uint_t rex_prefix = 0; /* amd64 register extension prefix */ 2542 2543 /* 2544 * Intel VEX instruction encoding prefix and fields 2545 */ 2546 2547 /* 0xC4 means 3 bytes prefix, 0xC5 means 2 bytes prefix */ 2548 uint_t vex_prefix = 0; 2549 2550 /* 2551 * VEX prefix byte 1, includes vex.r, vex.x and vex.b 2552 * (for 3 bytes prefix) 2553 */ 2554 uint_t vex_byte1 = 0; 2555 2556 /* 2557 * For 32-bit mode, it should prefetch the next byte to 2558 * distinguish between AVX and les/lds 2559 */ 2560 uint_t vex_prefetch = 0; 2561 2562 uint_t vex_m = 0; 2563 uint_t vex_v = 0; 2564 uint_t vex_p = 0; 2565 uint_t vex_R = 1; 2566 uint_t vex_X = 1; 2567 uint_t vex_B = 1; 2568 uint_t vex_W = 0; 2569 uint_t vex_L; 2570 2571 2572 size_t off; 2573 2574 instable_t dp_mmx; 2575 2576 x->d86_len = 0; 2577 x->d86_rmindex = -1; 2578 x->d86_error = 0; 2579 #ifdef DIS_TEXT 2580 x->d86_numopnds = 0; 2581 x->d86_seg_prefix = NULL; 2582 x->d86_mnem[0] = 0; 2583 for (i = 0; i < 4; ++i) { 2584 x->d86_opnd[i].d86_opnd[0] = 0; 2585 x->d86_opnd[i].d86_prefix[0] = 0; 2586 x->d86_opnd[i].d86_value_size = 0; 2587 x->d86_opnd[i].d86_value = 0; 2588 x->d86_opnd[i].d86_mode = MODE_NONE; 2589 } 2590 #endif 2591 x->d86_rex_prefix = 0; 2592 x->d86_got_modrm = 0; 2593 x->d86_memsize = 0; 2594 2595 if (cpu_mode == SIZE16) { 2596 opnd_size = SIZE16; 2597 addr_size = SIZE16; 2598 } else if (cpu_mode == SIZE32) { 2599 opnd_size = SIZE32; 2600 addr_size = SIZE32; 2601 } else { 2602 opnd_size = SIZE32; 2603 addr_size = SIZE64; 2604 } 2605 2606 /* 2607 * Get one opcode byte and check for zero padding that follows 2608 * jump tables. 2609 */ 2610 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 2611 goto error; 2612 2613 if (opcode1 == 0 && opcode2 == 0 && 2614 x->d86_check_func != NULL && x->d86_check_func(x->d86_data)) { 2615 #ifdef DIS_TEXT 2616 (void) strncpy(x->d86_mnem, ".byte\t0", OPLEN); 2617 #endif 2618 goto done; 2619 } 2620 2621 /* 2622 * Gather up legacy x86 prefix bytes. 2623 */ 2624 for (;;) { 2625 uint_t *which_prefix = NULL; 2626 2627 dp = (instable_t *)&dis_distable[opcode1][opcode2]; 2628 2629 switch (dp->it_adrmode) { 2630 case PREFIX: 2631 which_prefix = &rep_prefix; 2632 break; 2633 case LOCK: 2634 which_prefix = &lock_prefix; 2635 break; 2636 case OVERRIDE: 2637 which_prefix = &segment_prefix; 2638 #ifdef DIS_TEXT 2639 x->d86_seg_prefix = (char *)dp->it_name; 2640 #endif 2641 if (dp->it_invalid64 && cpu_mode == SIZE64) 2642 goto error; 2643 break; 2644 case AM: 2645 which_prefix = &addr_size_prefix; 2646 break; 2647 case DM: 2648 which_prefix = &opnd_size_prefix; 2649 break; 2650 } 2651 if (which_prefix == NULL) 2652 break; 2653 *which_prefix = (opcode1 << 4) | opcode2; 2654 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 2655 goto error; 2656 } 2657 2658 /* 2659 * Handle amd64 mode PREFIX values. 2660 * Some of the segment prefixes are no-ops. (only FS/GS actually work) 2661 * We might have a REX prefix (opcodes 0x40-0x4f) 2662 */ 2663 if (cpu_mode == SIZE64) { 2664 if (segment_prefix != 0x64 && segment_prefix != 0x65) 2665 segment_prefix = 0; 2666 2667 if (opcode1 == 0x4) { 2668 rex_prefix = (opcode1 << 4) | opcode2; 2669 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 2670 goto error; 2671 dp = (instable_t *)&dis_distable[opcode1][opcode2]; 2672 } else if (opcode1 == 0xC && 2673 (opcode2 == 0x4 || opcode2 == 0x5)) { 2674 /* AVX instructions */ 2675 vex_prefix = (opcode1 << 4) | opcode2; 2676 x->d86_rex_prefix = 0x40; 2677 } 2678 } else if (opcode1 == 0xC && (opcode2 == 0x4 || opcode2 == 0x5)) { 2679 /* LDS, LES or AVX */ 2680 dtrace_get_modrm(x, &mode, ®, &r_m); 2681 vex_prefetch = 1; 2682 2683 if (mode == REG_ONLY) { 2684 /* AVX */ 2685 vex_prefix = (opcode1 << 4) | opcode2; 2686 x->d86_rex_prefix = 0x40; 2687 opcode3 = (((mode << 3) | reg)>>1) & 0x0F; 2688 opcode4 = ((reg << 3) | r_m) & 0x0F; 2689 } 2690 } 2691 2692 if (vex_prefix == VEX_2bytes) { 2693 if (!vex_prefetch) { 2694 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0) 2695 goto error; 2696 } 2697 vex_R = ((opcode3 & VEX_R) & 0x0F) >> 3; 2698 vex_L = ((opcode4 & VEX_L) & 0x0F) >> 2; 2699 vex_v = (((opcode3 << 4) | opcode4) & VEX_v) >> 3; 2700 vex_p = opcode4 & VEX_p; 2701 /* 2702 * The vex.x and vex.b bits are not defined in two bytes 2703 * mode vex prefix, their default values are 1 2704 */ 2705 vex_byte1 = (opcode3 & VEX_R) | VEX_X | VEX_B; 2706 2707 if (vex_R == 0) 2708 x->d86_rex_prefix |= REX_R; 2709 2710 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 2711 goto error; 2712 2713 switch (vex_p) { 2714 case VEX_p_66: 2715 dp = (instable_t *) 2716 &dis_opAVX660F[(opcode1 << 4) | opcode2]; 2717 break; 2718 case VEX_p_F3: 2719 dp = (instable_t *) 2720 &dis_opAVXF30F[(opcode1 << 4) | opcode2]; 2721 break; 2722 case VEX_p_F2: 2723 dp = (instable_t *) 2724 &dis_opAVXF20F [(opcode1 << 4) | opcode2]; 2725 break; 2726 default: 2727 dp = (instable_t *) 2728 &dis_opAVX0F[opcode1][opcode2]; 2729 2730 } 2731 2732 } else if (vex_prefix == VEX_3bytes) { 2733 if (!vex_prefetch) { 2734 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0) 2735 goto error; 2736 } 2737 vex_R = (opcode3 & VEX_R) >> 3; 2738 vex_X = (opcode3 & VEX_X) >> 2; 2739 vex_B = (opcode3 & VEX_B) >> 1; 2740 vex_m = (((opcode3 << 4) | opcode4) & VEX_m); 2741 vex_byte1 = opcode3 & (VEX_R | VEX_X | VEX_B); 2742 2743 if (vex_R == 0) 2744 x->d86_rex_prefix |= REX_R; 2745 if (vex_X == 0) 2746 x->d86_rex_prefix |= REX_X; 2747 if (vex_B == 0) 2748 x->d86_rex_prefix |= REX_B; 2749 2750 if (dtrace_get_opcode(x, &opcode5, &opcode6) != 0) 2751 goto error; 2752 vex_W = (opcode5 & VEX_W) >> 3; 2753 vex_L = (opcode6 & VEX_L) >> 2; 2754 vex_v = (((opcode5 << 4) | opcode6) & VEX_v) >> 3; 2755 vex_p = opcode6 & VEX_p; 2756 2757 if (vex_W) 2758 x->d86_rex_prefix |= REX_W; 2759 2760 /* Only these three vex_m values valid; others are reserved */ 2761 if ((vex_m != VEX_m_0F) && (vex_m != VEX_m_0F38) && 2762 (vex_m != VEX_m_0F3A)) 2763 goto error; 2764 2765 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 2766 goto error; 2767 2768 switch (vex_p) { 2769 case VEX_p_66: 2770 if (vex_m == VEX_m_0F) { 2771 dp = (instable_t *) 2772 &dis_opAVX660F 2773 [(opcode1 << 4) | opcode2]; 2774 } else if (vex_m == VEX_m_0F38) { 2775 dp = (instable_t *) 2776 &dis_opAVX660F38 2777 [(opcode1 << 4) | opcode2]; 2778 } else if (vex_m == VEX_m_0F3A) { 2779 dp = (instable_t *) 2780 &dis_opAVX660F3A 2781 [(opcode1 << 4) | opcode2]; 2782 } else { 2783 goto error; 2784 } 2785 break; 2786 case VEX_p_F3: 2787 if (vex_m == VEX_m_0F) { 2788 dp = (instable_t *) 2789 &dis_opAVXF30F 2790 [(opcode1 << 4) | opcode2]; 2791 } else { 2792 goto error; 2793 } 2794 break; 2795 case VEX_p_F2: 2796 if (vex_m == VEX_m_0F) { 2797 dp = (instable_t *) 2798 &dis_opAVXF20F 2799 [(opcode1 << 4) | opcode2]; 2800 } else { 2801 goto error; 2802 } 2803 break; 2804 default: 2805 dp = (instable_t *) 2806 &dis_opAVX0F[opcode1][opcode2]; 2807 2808 } 2809 } 2810 if (vex_prefix) { 2811 if (vex_L) 2812 wbit = YMM_OPND; 2813 else 2814 wbit = XMM_OPND; 2815 } 2816 2817 /* 2818 * Deal with selection of operand and address size now. 2819 * Note that the REX.W bit being set causes opnd_size_prefix to be 2820 * ignored. 2821 */ 2822 if (cpu_mode == SIZE64) { 2823 if ((rex_prefix & REX_W) || vex_W) 2824 opnd_size = SIZE64; 2825 else if (opnd_size_prefix) 2826 opnd_size = SIZE16; 2827 2828 if (addr_size_prefix) 2829 addr_size = SIZE32; 2830 } else if (cpu_mode == SIZE32) { 2831 if (opnd_size_prefix) 2832 opnd_size = SIZE16; 2833 if (addr_size_prefix) 2834 addr_size = SIZE16; 2835 } else { 2836 if (opnd_size_prefix) 2837 opnd_size = SIZE32; 2838 if (addr_size_prefix) 2839 addr_size = SIZE32; 2840 } 2841 /* 2842 * The pause instruction - a repz'd nop. This doesn't fit 2843 * with any of the other prefix goop added for SSE, so we'll 2844 * special-case it here. 2845 */ 2846 if (rep_prefix == 0xf3 && opcode1 == 0x9 && opcode2 == 0x0) { 2847 rep_prefix = 0; 2848 dp = (instable_t *)&dis_opPause; 2849 } 2850 2851 /* 2852 * Some 386 instructions have 2 bytes of opcode before the mod_r/m 2853 * byte so we may need to perform a table indirection. 2854 */ 2855 if (dp->it_indirect == (instable_t *)dis_op0F) { 2856 if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0) 2857 goto error; 2858 opcode_bytes = 2; 2859 if (opcode4 == 0x7 && opcode5 >= 0x1 && opcode5 <= 0x3) { 2860 uint_t subcode; 2861 2862 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 2863 goto error; 2864 opcode_bytes = 3; 2865 subcode = ((opcode6 & 0x3) << 1) | 2866 ((opcode7 & 0x8) >> 3); 2867 dp = (instable_t *)&dis_op0F7123[opcode5][subcode]; 2868 } else if ((opcode4 == 0xc) && (opcode5 >= 0x8)) { 2869 dp = (instable_t *)&dis_op0FC8[0]; 2870 } else if ((opcode4 == 0x3) && (opcode5 == 0xA)) { 2871 opcode_bytes = 3; 2872 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 2873 goto error; 2874 if (opnd_size == SIZE16) 2875 opnd_size = SIZE32; 2876 2877 dp = (instable_t *)&dis_op0F3A[(opcode6<<4)|opcode7]; 2878 #ifdef DIS_TEXT 2879 if (strcmp(dp->it_name, "INVALID") == 0) 2880 goto error; 2881 #endif 2882 switch (dp->it_adrmode) { 2883 case XMMP_66r: 2884 case XMMPRM_66r: 2885 case XMM3PM_66r: 2886 if (opnd_size_prefix == 0) { 2887 goto error; 2888 } 2889 break; 2890 case XMMP_66o: 2891 if (opnd_size_prefix == 0) { 2892 /* SSSE3 MMX instructions */ 2893 dp_mmx = *dp; 2894 dp = &dp_mmx; 2895 dp->it_adrmode = MMOPM_66o; 2896 #ifdef DIS_MEM 2897 dp->it_size = 8; 2898 #endif 2899 } 2900 break; 2901 default: 2902 goto error; 2903 } 2904 } else if ((opcode4 == 0x3) && (opcode5 == 0x8)) { 2905 opcode_bytes = 3; 2906 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 2907 goto error; 2908 dp = (instable_t *)&dis_op0F38[(opcode6<<4)|opcode7]; 2909 2910 /* 2911 * Both crc32 and movbe have the same 3rd opcode 2912 * byte of either 0xF0 or 0xF1, so we use another 2913 * indirection to distinguish between the two. 2914 */ 2915 if (dp->it_indirect == (instable_t *)dis_op0F38F0 || 2916 dp->it_indirect == (instable_t *)dis_op0F38F1) { 2917 2918 dp = dp->it_indirect; 2919 if (rep_prefix != 0xF2) { 2920 /* It is movbe */ 2921 dp++; 2922 } 2923 } 2924 #ifdef DIS_TEXT 2925 if (strcmp(dp->it_name, "INVALID") == 0) 2926 goto error; 2927 #endif 2928 switch (dp->it_adrmode) { 2929 case RM_66r: 2930 case XMM_66r: 2931 case XMMM_66r: 2932 if (opnd_size_prefix == 0) { 2933 goto error; 2934 } 2935 break; 2936 case XMM_66o: 2937 if (opnd_size_prefix == 0) { 2938 /* SSSE3 MMX instructions */ 2939 dp_mmx = *dp; 2940 dp = &dp_mmx; 2941 dp->it_adrmode = MM; 2942 #ifdef DIS_MEM 2943 dp->it_size = 8; 2944 #endif 2945 } 2946 break; 2947 case CRC32: 2948 if (rep_prefix != 0xF2) { 2949 goto error; 2950 } 2951 rep_prefix = 0; 2952 break; 2953 case MOVBE: 2954 if (rep_prefix != 0x0) { 2955 goto error; 2956 } 2957 break; 2958 default: 2959 goto error; 2960 } 2961 } else { 2962 dp = (instable_t *)&dis_op0F[opcode4][opcode5]; 2963 } 2964 } 2965 2966 /* 2967 * If still not at a TERM decode entry, then a ModRM byte 2968 * exists and its fields further decode the instruction. 2969 */ 2970 x->d86_got_modrm = 0; 2971 if (dp->it_indirect != TERM) { 2972 dtrace_get_modrm(x, &mode, &opcode3, &r_m); 2973 if (x->d86_error) 2974 goto error; 2975 reg = opcode3; 2976 2977 /* 2978 * decode 287 instructions (D8-DF) from opcodeN 2979 */ 2980 if (opcode1 == 0xD && opcode2 >= 0x8) { 2981 if (opcode2 == 0xB && mode == 0x3 && opcode3 == 4) 2982 dp = (instable_t *)&dis_opFP5[r_m]; 2983 else if (opcode2 == 0xA && mode == 0x3 && opcode3 < 4) 2984 dp = (instable_t *)&dis_opFP7[opcode3]; 2985 else if (opcode2 == 0xB && mode == 0x3) 2986 dp = (instable_t *)&dis_opFP6[opcode3]; 2987 else if (opcode2 == 0x9 && mode == 0x3 && opcode3 >= 4) 2988 dp = (instable_t *)&dis_opFP4[opcode3 - 4][r_m]; 2989 else if (mode == 0x3) 2990 dp = (instable_t *) 2991 &dis_opFP3[opcode2 - 8][opcode3]; 2992 else 2993 dp = (instable_t *) 2994 &dis_opFP1n2[opcode2 - 8][opcode3]; 2995 } else { 2996 dp = (instable_t *)dp->it_indirect + opcode3; 2997 } 2998 } 2999 3000 /* 3001 * In amd64 bit mode, ARPL opcode is changed to MOVSXD 3002 * (sign extend 32bit to 64 bit) 3003 */ 3004 if ((vex_prefix == 0) && cpu_mode == SIZE64 && 3005 opcode1 == 0x6 && opcode2 == 0x3) 3006 dp = (instable_t *)&dis_opMOVSLD; 3007 3008 /* 3009 * at this point we should have a correct (or invalid) opcode 3010 */ 3011 if (cpu_mode == SIZE64 && dp->it_invalid64 || 3012 cpu_mode != SIZE64 && dp->it_invalid32) 3013 goto error; 3014 if (dp->it_indirect != TERM) 3015 goto error; 3016 3017 /* 3018 * deal with MMX/SSE opcodes which are changed by prefixes 3019 */ 3020 switch (dp->it_adrmode) { 3021 case MMO: 3022 case MMOIMPL: 3023 case MMO3P: 3024 case MMOM3: 3025 case MMOMS: 3026 case MMOPM: 3027 case MMOPRM: 3028 case MMOS: 3029 case XMMO: 3030 case XMMOM: 3031 case XMMOMS: 3032 case XMMOPM: 3033 case XMMOS: 3034 case XMMOMX: 3035 case XMMOX3: 3036 case XMMOXMM: 3037 /* 3038 * This is horrible. Some SIMD instructions take the 3039 * form 0x0F 0x?? ..., which is easily decoded using the 3040 * existing tables. Other SIMD instructions use various 3041 * prefix bytes to overload existing instructions. For 3042 * Example, addps is F0, 58, whereas addss is F3 (repz), 3043 * F0, 58. Presumably someone got a raise for this. 3044 * 3045 * If we see one of the instructions which can be 3046 * modified in this way (if we've got one of the SIMDO* 3047 * address modes), we'll check to see if the last prefix 3048 * was a repz. If it was, we strip the prefix from the 3049 * mnemonic, and we indirect using the dis_opSIMDrepz 3050 * table. 3051 */ 3052 3053 /* 3054 * Calculate our offset in dis_op0F 3055 */ 3056 if ((uintptr_t)dp - (uintptr_t)dis_op0F > sizeof (dis_op0F)) 3057 goto error; 3058 3059 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) / 3060 sizeof (instable_t); 3061 3062 /* 3063 * Rewrite if this instruction used one of the magic prefixes. 3064 */ 3065 if (rep_prefix) { 3066 if (rep_prefix == 0xf2) 3067 dp = (instable_t *)&dis_opSIMDrepnz[off]; 3068 else 3069 dp = (instable_t *)&dis_opSIMDrepz[off]; 3070 rep_prefix = 0; 3071 } else if (opnd_size_prefix) { 3072 dp = (instable_t *)&dis_opSIMDdata16[off]; 3073 opnd_size_prefix = 0; 3074 if (opnd_size == SIZE16) 3075 opnd_size = SIZE32; 3076 } 3077 break; 3078 3079 case MG9: 3080 /* 3081 * More horribleness: the group 9 (0xF0 0xC7) instructions are 3082 * allowed an optional prefix of 0x66 or 0xF3. This is similar 3083 * to the SIMD business described above, but with a different 3084 * addressing mode (and an indirect table), so we deal with it 3085 * separately (if similarly). 3086 */ 3087 3088 /* 3089 * Calculate our offset in dis_op0FC7 (the group 9 table) 3090 */ 3091 if ((uintptr_t)dp - (uintptr_t)dis_op0FC7 > sizeof (dis_op0FC7)) 3092 goto error; 3093 3094 off = ((uintptr_t)dp - (uintptr_t)dis_op0FC7) / 3095 sizeof (instable_t); 3096 3097 /* 3098 * Rewrite if this instruction used one of the magic prefixes. 3099 */ 3100 if (rep_prefix) { 3101 if (rep_prefix == 0xf3) 3102 dp = (instable_t *)&dis_opF30FC7[off]; 3103 else 3104 goto error; 3105 rep_prefix = 0; 3106 } else if (opnd_size_prefix) { 3107 dp = (instable_t *)&dis_op660FC7[off]; 3108 opnd_size_prefix = 0; 3109 if (opnd_size == SIZE16) 3110 opnd_size = SIZE32; 3111 } 3112 break; 3113 3114 3115 case MMOSH: 3116 /* 3117 * As with the "normal" SIMD instructions, the MMX 3118 * shuffle instructions are overloaded. These 3119 * instructions, however, are special in that they use 3120 * an extra byte, and thus an extra table. As of this 3121 * writing, they only use the opnd_size prefix. 3122 */ 3123 3124 /* 3125 * Calculate our offset in dis_op0F7123 3126 */ 3127 if ((uintptr_t)dp - (uintptr_t)dis_op0F7123 > 3128 sizeof (dis_op0F7123)) 3129 goto error; 3130 3131 if (opnd_size_prefix) { 3132 off = ((uintptr_t)dp - (uintptr_t)dis_op0F7123) / 3133 sizeof (instable_t); 3134 dp = (instable_t *)&dis_opSIMD7123[off]; 3135 opnd_size_prefix = 0; 3136 if (opnd_size == SIZE16) 3137 opnd_size = SIZE32; 3138 } 3139 break; 3140 case MRw: 3141 if (rep_prefix) { 3142 if (rep_prefix == 0xf3) { 3143 3144 /* 3145 * Calculate our offset in dis_op0F 3146 */ 3147 if ((uintptr_t)dp - (uintptr_t)dis_op0F 3148 > sizeof (dis_op0F)) 3149 goto error; 3150 3151 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) / 3152 sizeof (instable_t); 3153 3154 dp = (instable_t *)&dis_opSIMDrepz[off]; 3155 rep_prefix = 0; 3156 } else { 3157 goto error; 3158 } 3159 } 3160 break; 3161 } 3162 3163 /* 3164 * In 64 bit mode, some opcodes automatically use opnd_size == SIZE64. 3165 */ 3166 if (cpu_mode == SIZE64) 3167 if (dp->it_always64 || (opnd_size == SIZE32 && dp->it_stackop)) 3168 opnd_size = SIZE64; 3169 3170 #ifdef DIS_TEXT 3171 /* 3172 * At this point most instructions can format the opcode mnemonic 3173 * including the prefixes. 3174 */ 3175 if (lock_prefix) 3176 (void) strlcat(x->d86_mnem, "lock ", OPLEN); 3177 3178 if (rep_prefix == 0xf2) 3179 (void) strlcat(x->d86_mnem, "repnz ", OPLEN); 3180 else if (rep_prefix == 0xf3) 3181 (void) strlcat(x->d86_mnem, "repz ", OPLEN); 3182 3183 if (cpu_mode == SIZE64 && addr_size_prefix) 3184 (void) strlcat(x->d86_mnem, "addr32 ", OPLEN); 3185 3186 if (dp->it_adrmode != CBW && 3187 dp->it_adrmode != CWD && 3188 dp->it_adrmode != XMMSFNC) { 3189 if (strcmp(dp->it_name, "INVALID") == 0) 3190 goto error; 3191 (void) strlcat(x->d86_mnem, dp->it_name, OPLEN); 3192 if (dp->it_suffix) { 3193 char *types[] = {"", "w", "l", "q"}; 3194 if (opcode_bytes == 2 && opcode4 == 4) { 3195 /* It's a cmovx.yy. Replace the suffix x */ 3196 for (i = 5; i < OPLEN; i++) { 3197 if (x->d86_mnem[i] == '.') 3198 break; 3199 } 3200 x->d86_mnem[i - 1] = *types[opnd_size]; 3201 } else if ((opnd_size == 2) && (opcode_bytes == 3) && 3202 ((opcode6 == 1 && opcode7 == 6) || 3203 (opcode6 == 2 && opcode7 == 2))) { 3204 /* 3205 * To handle PINSRD and PEXTRD 3206 */ 3207 (void) strlcat(x->d86_mnem, "d", OPLEN); 3208 } else { 3209 (void) strlcat(x->d86_mnem, types[opnd_size], 3210 OPLEN); 3211 } 3212 } 3213 } 3214 #endif 3215 3216 /* 3217 * Process operands based on the addressing modes. 3218 */ 3219 x->d86_mode = cpu_mode; 3220 /* 3221 * In vex mode the rex_prefix has no meaning 3222 */ 3223 if (!vex_prefix) 3224 x->d86_rex_prefix = rex_prefix; 3225 x->d86_opnd_size = opnd_size; 3226 x->d86_addr_size = addr_size; 3227 vbit = 0; /* initialize for mem/reg -> reg */ 3228 switch (dp->it_adrmode) { 3229 /* 3230 * amd64 instruction to sign extend 32 bit reg/mem operands 3231 * into 64 bit register values 3232 */ 3233 case MOVSXZ: 3234 #ifdef DIS_TEXT 3235 if (rex_prefix == 0) 3236 (void) strncpy(x->d86_mnem, "movzld", OPLEN); 3237 #endif 3238 dtrace_get_modrm(x, &mode, ®, &r_m); 3239 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3240 x->d86_opnd_size = SIZE64; 3241 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 3242 x->d86_opnd_size = opnd_size = SIZE32; 3243 wbit = LONG_OPND; 3244 dtrace_get_operand(x, mode, r_m, wbit, 0); 3245 break; 3246 3247 /* 3248 * movsbl movsbw movsbq (0x0FBE) or movswl movswq (0x0FBF) 3249 * movzbl movzbw movzbq (0x0FB6) or movzwl movzwq (0x0FB7) 3250 * wbit lives in 2nd byte, note that operands 3251 * are different sized 3252 */ 3253 case MOVZ: 3254 if (rex_prefix & REX_W) { 3255 /* target register size = 64 bit */ 3256 x->d86_mnem[5] = 'q'; 3257 } 3258 dtrace_get_modrm(x, &mode, ®, &r_m); 3259 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3260 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 3261 x->d86_opnd_size = opnd_size = SIZE16; 3262 wbit = WBIT(opcode5); 3263 dtrace_get_operand(x, mode, r_m, wbit, 0); 3264 break; 3265 case CRC32: 3266 opnd_size = SIZE32; 3267 if (rex_prefix & REX_W) 3268 opnd_size = SIZE64; 3269 x->d86_opnd_size = opnd_size; 3270 3271 dtrace_get_modrm(x, &mode, ®, &r_m); 3272 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3273 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 3274 wbit = WBIT(opcode7); 3275 if (opnd_size_prefix) 3276 x->d86_opnd_size = opnd_size = SIZE16; 3277 dtrace_get_operand(x, mode, r_m, wbit, 0); 3278 break; 3279 case MOVBE: 3280 opnd_size = SIZE32; 3281 if (rex_prefix & REX_W) 3282 opnd_size = SIZE64; 3283 x->d86_opnd_size = opnd_size; 3284 3285 dtrace_get_modrm(x, &mode, ®, &r_m); 3286 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3287 wbit = WBIT(opcode7); 3288 if (opnd_size_prefix) 3289 x->d86_opnd_size = opnd_size = SIZE16; 3290 if (wbit) { 3291 /* reg -> mem */ 3292 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 3293 dtrace_get_operand(x, mode, r_m, wbit, 1); 3294 } else { 3295 /* mem -> reg */ 3296 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 3297 dtrace_get_operand(x, mode, r_m, wbit, 0); 3298 } 3299 break; 3300 3301 /* 3302 * imul instruction, with either 8-bit or longer immediate 3303 * opcode 0x6B for byte, sign-extended displacement, 0x69 for word(s) 3304 */ 3305 case IMUL: 3306 wbit = LONG_OPND; 3307 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 3308 OPSIZE(opnd_size, opcode2 == 0x9), 1); 3309 break; 3310 3311 /* memory or register operand to register, with 'w' bit */ 3312 case MRw: 3313 wbit = WBIT(opcode2); 3314 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 3315 break; 3316 3317 /* register to memory or register operand, with 'w' bit */ 3318 /* arpl happens to fit here also because it is odd */ 3319 case RMw: 3320 if (opcode_bytes == 2) 3321 wbit = WBIT(opcode5); 3322 else 3323 wbit = WBIT(opcode2); 3324 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 3325 break; 3326 3327 /* xaddb instruction */ 3328 case XADDB: 3329 wbit = 0; 3330 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 3331 break; 3332 3333 /* MMX register to memory or register operand */ 3334 case MMS: 3335 case MMOS: 3336 #ifdef DIS_TEXT 3337 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 3338 #else 3339 wbit = LONG_OPND; 3340 #endif 3341 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1); 3342 break; 3343 3344 /* MMX register to memory */ 3345 case MMOMS: 3346 dtrace_get_modrm(x, &mode, ®, &r_m); 3347 if (mode == REG_ONLY) 3348 goto error; 3349 wbit = MM_OPND; 3350 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1); 3351 break; 3352 3353 /* Double shift. Has immediate operand specifying the shift. */ 3354 case DSHIFT: 3355 wbit = LONG_OPND; 3356 dtrace_get_modrm(x, &mode, ®, &r_m); 3357 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3358 dtrace_get_operand(x, mode, r_m, wbit, 2); 3359 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 3360 dtrace_imm_opnd(x, wbit, 1, 0); 3361 break; 3362 3363 /* 3364 * Double shift. With no immediate operand, specifies using %cl. 3365 */ 3366 case DSHIFTcl: 3367 wbit = LONG_OPND; 3368 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 3369 break; 3370 3371 /* immediate to memory or register operand */ 3372 case IMlw: 3373 wbit = WBIT(opcode2); 3374 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 3375 dtrace_get_operand(x, mode, r_m, wbit, 1); 3376 /* 3377 * Have long immediate for opcode 0x81, but not 0x80 nor 0x83 3378 */ 3379 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, opcode2 == 1), 0); 3380 break; 3381 3382 /* immediate to memory or register operand with the */ 3383 /* 'w' bit present */ 3384 case IMw: 3385 wbit = WBIT(opcode2); 3386 dtrace_get_modrm(x, &mode, ®, &r_m); 3387 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 3388 dtrace_get_operand(x, mode, r_m, wbit, 1); 3389 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0); 3390 break; 3391 3392 /* immediate to register with register in low 3 bits */ 3393 /* of op code */ 3394 case IR: 3395 /* w-bit here (with regs) is bit 3 */ 3396 wbit = opcode2 >>3 & 0x1; 3397 reg = REGNO(opcode2); 3398 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 3399 mode = REG_ONLY; 3400 r_m = reg; 3401 dtrace_get_operand(x, mode, r_m, wbit, 1); 3402 dtrace_imm_opnd(x, wbit, OPSIZE64(opnd_size, wbit), 0); 3403 break; 3404 3405 /* MMX immediate shift of register */ 3406 case MMSH: 3407 case MMOSH: 3408 wbit = MM_OPND; 3409 goto mm_shift; /* in next case */ 3410 3411 /* SIMD immediate shift of register */ 3412 case XMMSH: 3413 wbit = XMM_OPND; 3414 mm_shift: 3415 reg = REGNO(opcode7); 3416 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 3417 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 3418 dtrace_imm_opnd(x, wbit, 1, 0); 3419 NOMEM; 3420 break; 3421 3422 /* accumulator to memory operand */ 3423 case AO: 3424 vbit = 1; 3425 /*FALLTHROUGH*/ 3426 3427 /* memory operand to accumulator */ 3428 case OA: 3429 wbit = WBIT(opcode2); 3430 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1 - vbit); 3431 dtrace_imm_opnd(x, wbit, OPSIZE64(addr_size, LONG_OPND), vbit); 3432 #ifdef DIS_TEXT 3433 x->d86_opnd[vbit].d86_mode = MODE_OFFSET; 3434 #endif 3435 break; 3436 3437 3438 /* segment register to memory or register operand */ 3439 case SM: 3440 vbit = 1; 3441 /*FALLTHROUGH*/ 3442 3443 /* memory or register operand to segment register */ 3444 case MS: 3445 dtrace_get_modrm(x, &mode, ®, &r_m); 3446 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 3447 dtrace_get_operand(x, mode, r_m, LONG_OPND, vbit); 3448 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 1 - vbit); 3449 break; 3450 3451 /* 3452 * rotate or shift instructions, which may shift by 1 or 3453 * consult the cl register, depending on the 'v' bit 3454 */ 3455 case Mv: 3456 vbit = VBIT(opcode2); 3457 wbit = WBIT(opcode2); 3458 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 3459 dtrace_get_operand(x, mode, r_m, wbit, 1); 3460 #ifdef DIS_TEXT 3461 if (vbit) { 3462 (void) strlcat(x->d86_opnd[0].d86_opnd, "%cl", OPLEN); 3463 } else { 3464 x->d86_opnd[0].d86_mode = MODE_SIGNED; 3465 x->d86_opnd[0].d86_value_size = 1; 3466 x->d86_opnd[0].d86_value = 1; 3467 } 3468 #endif 3469 break; 3470 /* 3471 * immediate rotate or shift instructions 3472 */ 3473 case MvI: 3474 wbit = WBIT(opcode2); 3475 normal_imm_mem: 3476 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 3477 dtrace_get_operand(x, mode, r_m, wbit, 1); 3478 dtrace_imm_opnd(x, wbit, 1, 0); 3479 break; 3480 3481 /* bit test instructions */ 3482 case MIb: 3483 wbit = LONG_OPND; 3484 goto normal_imm_mem; 3485 3486 /* single memory or register operand with 'w' bit present */ 3487 case Mw: 3488 wbit = WBIT(opcode2); 3489 just_mem: 3490 dtrace_get_modrm(x, &mode, ®, &r_m); 3491 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 3492 dtrace_get_operand(x, mode, r_m, wbit, 0); 3493 break; 3494 3495 case SWAPGS: 3496 if (cpu_mode == SIZE64 && mode == 3 && r_m == 0) { 3497 #ifdef DIS_TEXT 3498 (void) strncpy(x->d86_mnem, "swapgs", OPLEN); 3499 #endif 3500 NOMEM; 3501 break; 3502 } 3503 /*FALLTHROUGH*/ 3504 3505 /* prefetch instruction - memory operand, but no memory acess */ 3506 case PREF: 3507 NOMEM; 3508 /*FALLTHROUGH*/ 3509 3510 /* single memory or register operand */ 3511 case M: 3512 case MG9: 3513 wbit = LONG_OPND; 3514 goto just_mem; 3515 3516 /* single memory or register byte operand */ 3517 case Mb: 3518 wbit = BYTE_OPND; 3519 goto just_mem; 3520 3521 case VMx: 3522 if (mode == 3) { 3523 #ifdef DIS_TEXT 3524 char *vminstr; 3525 3526 switch (r_m) { 3527 case 1: 3528 vminstr = "vmcall"; 3529 break; 3530 case 2: 3531 vminstr = "vmlaunch"; 3532 break; 3533 case 3: 3534 vminstr = "vmresume"; 3535 break; 3536 case 4: 3537 vminstr = "vmxoff"; 3538 break; 3539 default: 3540 goto error; 3541 } 3542 3543 (void) strncpy(x->d86_mnem, vminstr, OPLEN); 3544 #else 3545 if (r_m < 1 || r_m > 4) 3546 goto error; 3547 #endif 3548 3549 NOMEM; 3550 break; 3551 } 3552 /*FALLTHROUGH*/ 3553 case MONITOR_MWAIT: 3554 if (mode == 3) { 3555 if (r_m == 0) { 3556 #ifdef DIS_TEXT 3557 (void) strncpy(x->d86_mnem, "monitor", OPLEN); 3558 #endif 3559 NOMEM; 3560 break; 3561 } else if (r_m == 1) { 3562 #ifdef DIS_TEXT 3563 (void) strncpy(x->d86_mnem, "mwait", OPLEN); 3564 #endif 3565 NOMEM; 3566 break; 3567 } else { 3568 goto error; 3569 } 3570 } 3571 /*FALLTHROUGH*/ 3572 case XGETBV_XSETBV: 3573 if (mode == 3) { 3574 if (r_m == 0) { 3575 #ifdef DIS_TEXT 3576 (void) strncpy(x->d86_mnem, "xgetbv", OPLEN); 3577 #endif 3578 NOMEM; 3579 break; 3580 } else if (r_m == 1) { 3581 #ifdef DIS_TEXT 3582 (void) strncpy(x->d86_mnem, "xsetbv", OPLEN); 3583 #endif 3584 NOMEM; 3585 break; 3586 } else { 3587 goto error; 3588 } 3589 3590 } 3591 /*FALLTHROUGH*/ 3592 case MO: 3593 /* Similar to M, but only memory (no direct registers) */ 3594 wbit = LONG_OPND; 3595 dtrace_get_modrm(x, &mode, ®, &r_m); 3596 if (mode == 3) 3597 goto error; 3598 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 3599 dtrace_get_operand(x, mode, r_m, wbit, 0); 3600 break; 3601 3602 /* move special register to register or reverse if vbit */ 3603 case SREG: 3604 switch (opcode5) { 3605 3606 case 2: 3607 vbit = 1; 3608 /*FALLTHROUGH*/ 3609 case 0: 3610 wbit = CONTROL_OPND; 3611 break; 3612 3613 case 3: 3614 vbit = 1; 3615 /*FALLTHROUGH*/ 3616 case 1: 3617 wbit = DEBUG_OPND; 3618 break; 3619 3620 case 6: 3621 vbit = 1; 3622 /*FALLTHROUGH*/ 3623 case 4: 3624 wbit = TEST_OPND; 3625 break; 3626 3627 } 3628 dtrace_get_modrm(x, &mode, ®, &r_m); 3629 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3630 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit); 3631 dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 1 - vbit); 3632 NOMEM; 3633 break; 3634 3635 /* 3636 * single register operand with register in the low 3 3637 * bits of op code 3638 */ 3639 case R: 3640 if (opcode_bytes == 2) 3641 reg = REGNO(opcode5); 3642 else 3643 reg = REGNO(opcode2); 3644 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 3645 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 3646 NOMEM; 3647 break; 3648 3649 /* 3650 * register to accumulator with register in the low 3 3651 * bits of op code, xchg instructions 3652 */ 3653 case RA: 3654 NOMEM; 3655 reg = REGNO(opcode2); 3656 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 3657 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 3658 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, LONG_OPND, 1); 3659 break; 3660 3661 /* 3662 * single segment register operand, with register in 3663 * bits 3-4 of op code byte 3664 */ 3665 case SEG: 3666 NOMEM; 3667 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x3; 3668 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0); 3669 break; 3670 3671 /* 3672 * single segment register operand, with register in 3673 * bits 3-5 of op code 3674 */ 3675 case LSEG: 3676 NOMEM; 3677 /* long seg reg from opcode */ 3678 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x7; 3679 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0); 3680 break; 3681 3682 /* memory or register operand to register */ 3683 case MR: 3684 if (vex_prefetch) 3685 x->d86_got_modrm = 1; 3686 wbit = LONG_OPND; 3687 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 3688 break; 3689 3690 case RM: 3691 case RM_66r: 3692 wbit = LONG_OPND; 3693 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 3694 break; 3695 3696 /* MMX/SIMD-Int memory or mm reg to mm reg */ 3697 case MM: 3698 case MMO: 3699 #ifdef DIS_TEXT 3700 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 3701 #else 3702 wbit = LONG_OPND; 3703 #endif 3704 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0); 3705 break; 3706 3707 case MMOIMPL: 3708 #ifdef DIS_TEXT 3709 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 3710 #else 3711 wbit = LONG_OPND; 3712 #endif 3713 dtrace_get_modrm(x, &mode, ®, &r_m); 3714 if (mode != REG_ONLY) 3715 goto error; 3716 3717 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3718 dtrace_get_operand(x, mode, r_m, wbit, 0); 3719 dtrace_get_operand(x, REG_ONLY, reg, MM_OPND, 1); 3720 mode = 0; /* change for memory access size... */ 3721 break; 3722 3723 /* MMX/SIMD-Int and SIMD-FP predicated mm reg to r32 */ 3724 case MMO3P: 3725 wbit = MM_OPND; 3726 goto xmm3p; 3727 case XMM3P: 3728 wbit = XMM_OPND; 3729 xmm3p: 3730 dtrace_get_modrm(x, &mode, ®, &r_m); 3731 if (mode != REG_ONLY) 3732 goto error; 3733 3734 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 1, 3735 1); 3736 NOMEM; 3737 break; 3738 3739 case XMM3PM_66r: 3740 THREEOPERAND(x, mode, reg, r_m, rex_prefix, LONG_OPND, XMM_OPND, 3741 1, 0); 3742 break; 3743 3744 /* MMX/SIMD-Int predicated r32/mem to mm reg */ 3745 case MMOPRM: 3746 wbit = LONG_OPND; 3747 w2 = MM_OPND; 3748 goto xmmprm; 3749 case XMMPRM: 3750 case XMMPRM_66r: 3751 wbit = LONG_OPND; 3752 w2 = XMM_OPND; 3753 xmmprm: 3754 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, 1, 1); 3755 break; 3756 3757 /* MMX/SIMD-Int predicated mm/mem to mm reg */ 3758 case MMOPM: 3759 case MMOPM_66o: 3760 wbit = w2 = MM_OPND; 3761 goto xmmprm; 3762 3763 /* MMX/SIMD-Int mm reg to r32 */ 3764 case MMOM3: 3765 NOMEM; 3766 dtrace_get_modrm(x, &mode, ®, &r_m); 3767 if (mode != REG_ONLY) 3768 goto error; 3769 wbit = MM_OPND; 3770 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0); 3771 break; 3772 3773 /* SIMD memory or xmm reg operand to xmm reg */ 3774 case XMM: 3775 case XMM_66o: 3776 case XMM_66r: 3777 case XMMO: 3778 case XMMXIMPL: 3779 wbit = XMM_OPND; 3780 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 3781 3782 if (dp->it_adrmode == XMMXIMPL && mode != REG_ONLY) 3783 goto error; 3784 3785 #ifdef DIS_TEXT 3786 /* 3787 * movlps and movhlps share opcodes. They differ in the 3788 * addressing modes allowed for their operands. 3789 * movhps and movlhps behave similarly. 3790 */ 3791 if (mode == REG_ONLY) { 3792 if (strcmp(dp->it_name, "movlps") == 0) 3793 (void) strncpy(x->d86_mnem, "movhlps", OPLEN); 3794 else if (strcmp(dp->it_name, "movhps") == 0) 3795 (void) strncpy(x->d86_mnem, "movlhps", OPLEN); 3796 } 3797 #endif 3798 if (dp->it_adrmode == XMMXIMPL) 3799 mode = 0; /* change for memory access size... */ 3800 break; 3801 3802 /* SIMD xmm reg to memory or xmm reg */ 3803 case XMMS: 3804 case XMMOS: 3805 case XMMMS: 3806 case XMMOMS: 3807 dtrace_get_modrm(x, &mode, ®, &r_m); 3808 #ifdef DIS_TEXT 3809 if ((strcmp(dp->it_name, "movlps") == 0 || 3810 strcmp(dp->it_name, "movhps") == 0 || 3811 strcmp(dp->it_name, "movntps") == 0) && 3812 mode == REG_ONLY) 3813 goto error; 3814 #endif 3815 wbit = XMM_OPND; 3816 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1); 3817 break; 3818 3819 /* SIMD memory to xmm reg */ 3820 case XMMM: 3821 case XMMM_66r: 3822 case XMMOM: 3823 wbit = XMM_OPND; 3824 dtrace_get_modrm(x, &mode, ®, &r_m); 3825 #ifdef DIS_TEXT 3826 if (mode == REG_ONLY) { 3827 if (strcmp(dp->it_name, "movhps") == 0) 3828 (void) strncpy(x->d86_mnem, "movlhps", OPLEN); 3829 else 3830 goto error; 3831 } 3832 #endif 3833 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 3834 break; 3835 3836 /* SIMD memory or r32 to xmm reg */ 3837 case XMM3MX: 3838 wbit = LONG_OPND; 3839 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 3840 break; 3841 3842 case XMM3MXS: 3843 wbit = LONG_OPND; 3844 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1); 3845 break; 3846 3847 /* SIMD memory or mm reg to xmm reg */ 3848 case XMMOMX: 3849 /* SIMD mm to xmm */ 3850 case XMMMX: 3851 wbit = MM_OPND; 3852 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 3853 break; 3854 3855 /* SIMD memory or xmm reg to mm reg */ 3856 case XMMXMM: 3857 case XMMOXMM: 3858 case XMMXM: 3859 wbit = XMM_OPND; 3860 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0); 3861 break; 3862 3863 3864 /* SIMD memory or xmm reg to r32 */ 3865 case XMMXM3: 3866 wbit = XMM_OPND; 3867 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0); 3868 break; 3869 3870 /* SIMD xmm to r32 */ 3871 case XMMX3: 3872 case XMMOX3: 3873 dtrace_get_modrm(x, &mode, ®, &r_m); 3874 if (mode != REG_ONLY) 3875 goto error; 3876 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3877 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0); 3878 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 3879 NOMEM; 3880 break; 3881 3882 /* SIMD predicated memory or xmm reg with/to xmm reg */ 3883 case XMMP: 3884 case XMMP_66r: 3885 case XMMP_66o: 3886 case XMMOPM: 3887 wbit = XMM_OPND; 3888 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1, 3889 1); 3890 3891 #ifdef DIS_TEXT 3892 /* 3893 * cmpps and cmpss vary their instruction name based 3894 * on the value of imm8. Other XMMP instructions, 3895 * such as shufps, require explicit specification of 3896 * the predicate. 3897 */ 3898 if (dp->it_name[0] == 'c' && 3899 dp->it_name[1] == 'm' && 3900 dp->it_name[2] == 'p' && 3901 strlen(dp->it_name) == 5) { 3902 uchar_t pred = x->d86_opnd[0].d86_value & 0xff; 3903 3904 if (pred >= (sizeof (dis_PREDSUFFIX) / sizeof (char *))) 3905 goto error; 3906 3907 (void) strncpy(x->d86_mnem, "cmp", OPLEN); 3908 (void) strlcat(x->d86_mnem, dis_PREDSUFFIX[pred], 3909 OPLEN); 3910 (void) strlcat(x->d86_mnem, 3911 dp->it_name + strlen(dp->it_name) - 2, 3912 OPLEN); 3913 x->d86_opnd[0] = x->d86_opnd[1]; 3914 x->d86_opnd[1] = x->d86_opnd[2]; 3915 x->d86_numopnds = 2; 3916 } 3917 #endif 3918 break; 3919 3920 case XMMX2I: 3921 FOUROPERAND(x, mode, reg, r_m, rex_prefix, XMM_OPND, XMM_OPND, 3922 1); 3923 NOMEM; 3924 break; 3925 3926 case XMM2I: 3927 ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, XMM_OPND, 1); 3928 NOMEM; 3929 break; 3930 3931 /* immediate operand to accumulator */ 3932 case IA: 3933 wbit = WBIT(opcode2); 3934 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1); 3935 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0); 3936 NOMEM; 3937 break; 3938 3939 /* memory or register operand to accumulator */ 3940 case MA: 3941 wbit = WBIT(opcode2); 3942 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 3943 dtrace_get_operand(x, mode, r_m, wbit, 0); 3944 break; 3945 3946 /* si register to di register used to reference memory */ 3947 case SD: 3948 #ifdef DIS_TEXT 3949 dtrace_check_override(x, 0); 3950 x->d86_numopnds = 2; 3951 if (addr_size == SIZE64) { 3952 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)", 3953 OPLEN); 3954 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)", 3955 OPLEN); 3956 } else if (addr_size == SIZE32) { 3957 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)", 3958 OPLEN); 3959 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)", 3960 OPLEN); 3961 } else { 3962 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)", 3963 OPLEN); 3964 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)", 3965 OPLEN); 3966 } 3967 #endif 3968 wbit = LONG_OPND; 3969 break; 3970 3971 /* accumulator to di register */ 3972 case AD: 3973 wbit = WBIT(opcode2); 3974 #ifdef DIS_TEXT 3975 dtrace_check_override(x, 1); 3976 x->d86_numopnds = 2; 3977 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 0); 3978 if (addr_size == SIZE64) 3979 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)", 3980 OPLEN); 3981 else if (addr_size == SIZE32) 3982 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)", 3983 OPLEN); 3984 else 3985 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)", 3986 OPLEN); 3987 #endif 3988 break; 3989 3990 /* si register to accumulator */ 3991 case SA: 3992 wbit = WBIT(opcode2); 3993 #ifdef DIS_TEXT 3994 dtrace_check_override(x, 0); 3995 x->d86_numopnds = 2; 3996 if (addr_size == SIZE64) 3997 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)", 3998 OPLEN); 3999 else if (addr_size == SIZE32) 4000 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)", 4001 OPLEN); 4002 else 4003 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)", 4004 OPLEN); 4005 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1); 4006 #endif 4007 break; 4008 4009 /* 4010 * single operand, a 16/32 bit displacement 4011 */ 4012 case D: 4013 wbit = LONG_OPND; 4014 dtrace_disp_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0); 4015 NOMEM; 4016 break; 4017 4018 /* jmp/call indirect to memory or register operand */ 4019 case INM: 4020 #ifdef DIS_TEXT 4021 (void) strlcat(x->d86_opnd[0].d86_prefix, "*", OPLEN); 4022 #endif 4023 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4024 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 4025 wbit = LONG_OPND; 4026 break; 4027 4028 /* 4029 * for long jumps and long calls -- a new code segment 4030 * register and an offset in IP -- stored in object 4031 * code in reverse order. Note - not valid in amd64 4032 */ 4033 case SO: 4034 dtrace_check_override(x, 1); 4035 wbit = LONG_OPND; 4036 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 1); 4037 #ifdef DIS_TEXT 4038 x->d86_opnd[1].d86_mode = MODE_SIGNED; 4039 #endif 4040 /* will now get segment operand */ 4041 dtrace_imm_opnd(x, wbit, 2, 0); 4042 break; 4043 4044 /* 4045 * jmp/call. single operand, 8 bit displacement. 4046 * added to current EIP in 'compofff' 4047 */ 4048 case BD: 4049 dtrace_disp_opnd(x, BYTE_OPND, 1, 0); 4050 NOMEM; 4051 break; 4052 4053 /* single 32/16 bit immediate operand */ 4054 case I: 4055 wbit = LONG_OPND; 4056 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0); 4057 break; 4058 4059 /* single 8 bit immediate operand */ 4060 case Ib: 4061 wbit = LONG_OPND; 4062 dtrace_imm_opnd(x, wbit, 1, 0); 4063 break; 4064 4065 case ENTER: 4066 wbit = LONG_OPND; 4067 dtrace_imm_opnd(x, wbit, 2, 0); 4068 dtrace_imm_opnd(x, wbit, 1, 1); 4069 switch (opnd_size) { 4070 case SIZE64: 4071 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 8; 4072 break; 4073 case SIZE32: 4074 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 4; 4075 break; 4076 case SIZE16: 4077 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 2; 4078 break; 4079 } 4080 4081 break; 4082 4083 /* 16-bit immediate operand */ 4084 case RET: 4085 wbit = LONG_OPND; 4086 dtrace_imm_opnd(x, wbit, 2, 0); 4087 break; 4088 4089 /* single 8 bit port operand */ 4090 case P: 4091 dtrace_check_override(x, 0); 4092 dtrace_imm_opnd(x, BYTE_OPND, 1, 0); 4093 NOMEM; 4094 break; 4095 4096 /* single operand, dx register (variable port instruction) */ 4097 case V: 4098 x->d86_numopnds = 1; 4099 dtrace_check_override(x, 0); 4100 #ifdef DIS_TEXT 4101 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%dx)", OPLEN); 4102 #endif 4103 NOMEM; 4104 break; 4105 4106 /* 4107 * The int instruction, which has two forms: 4108 * int 3 (breakpoint) or 4109 * int n, where n is indicated in the subsequent 4110 * byte (format Ib). The int 3 instruction (opcode 0xCC), 4111 * where, although the 3 looks like an operand, 4112 * it is implied by the opcode. It must be converted 4113 * to the correct base and output. 4114 */ 4115 case INT3: 4116 #ifdef DIS_TEXT 4117 x->d86_numopnds = 1; 4118 x->d86_opnd[0].d86_mode = MODE_SIGNED; 4119 x->d86_opnd[0].d86_value_size = 1; 4120 x->d86_opnd[0].d86_value = 3; 4121 #endif 4122 NOMEM; 4123 break; 4124 4125 /* single 8 bit immediate operand */ 4126 case INTx: 4127 dtrace_imm_opnd(x, BYTE_OPND, 1, 0); 4128 NOMEM; 4129 break; 4130 4131 /* an unused byte must be discarded */ 4132 case U: 4133 if (x->d86_get_byte(x->d86_data) < 0) 4134 goto error; 4135 x->d86_len++; 4136 NOMEM; 4137 break; 4138 4139 case CBW: 4140 #ifdef DIS_TEXT 4141 if (opnd_size == SIZE16) 4142 (void) strlcat(x->d86_mnem, "cbtw", OPLEN); 4143 else if (opnd_size == SIZE32) 4144 (void) strlcat(x->d86_mnem, "cwtl", OPLEN); 4145 else 4146 (void) strlcat(x->d86_mnem, "cltq", OPLEN); 4147 #endif 4148 wbit = LONG_OPND; 4149 NOMEM; 4150 break; 4151 4152 case CWD: 4153 #ifdef DIS_TEXT 4154 if (opnd_size == SIZE16) 4155 (void) strlcat(x->d86_mnem, "cwtd", OPLEN); 4156 else if (opnd_size == SIZE32) 4157 (void) strlcat(x->d86_mnem, "cltd", OPLEN); 4158 else 4159 (void) strlcat(x->d86_mnem, "cqtd", OPLEN); 4160 #endif 4161 wbit = LONG_OPND; 4162 NOMEM; 4163 break; 4164 4165 case XMMSFNC: 4166 /* 4167 * sfence is sfence if mode is REG_ONLY. If mode isn't 4168 * REG_ONLY, mnemonic should be 'clflush'. 4169 */ 4170 dtrace_get_modrm(x, &mode, ®, &r_m); 4171 4172 /* sfence doesn't take operands */ 4173 #ifdef DIS_TEXT 4174 if (mode == REG_ONLY) { 4175 (void) strlcat(x->d86_mnem, "sfence", OPLEN); 4176 } else { 4177 (void) strlcat(x->d86_mnem, "clflush", OPLEN); 4178 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4179 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0); 4180 NOMEM; 4181 } 4182 #else 4183 if (mode != REG_ONLY) { 4184 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4185 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 4186 NOMEM; 4187 } 4188 #endif 4189 break; 4190 4191 /* 4192 * no disassembly, the mnemonic was all there was so go on 4193 */ 4194 case NORM: 4195 if (dp->it_invalid32 && cpu_mode != SIZE64) 4196 goto error; 4197 NOMEM; 4198 /*FALLTHROUGH*/ 4199 case IMPLMEM: 4200 break; 4201 4202 case XMMFENCE: 4203 /* 4204 * XRSTOR and LFENCE share the same opcode but differ in mode 4205 */ 4206 dtrace_get_modrm(x, &mode, ®, &r_m); 4207 4208 if (mode == REG_ONLY) { 4209 /* 4210 * Only the following exact byte sequences are allowed: 4211 * 4212 * 0f ae e8 lfence 4213 * 0f ae f0 mfence 4214 */ 4215 if ((uint8_t)x->d86_bytes[x->d86_len - 1] != 0xe8 && 4216 (uint8_t)x->d86_bytes[x->d86_len - 1] != 0xf0) 4217 goto error; 4218 } else { 4219 #ifdef DIS_TEXT 4220 (void) strncpy(x->d86_mnem, "xrstor", OPLEN); 4221 #endif 4222 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4223 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0); 4224 } 4225 break; 4226 4227 /* float reg */ 4228 case F: 4229 #ifdef DIS_TEXT 4230 x->d86_numopnds = 1; 4231 (void) strlcat(x->d86_opnd[0].d86_opnd, "%st(X)", OPLEN); 4232 x->d86_opnd[0].d86_opnd[4] = r_m + '0'; 4233 #endif 4234 NOMEM; 4235 break; 4236 4237 /* float reg to float reg, with ret bit present */ 4238 case FF: 4239 vbit = opcode2 >> 2 & 0x1; /* vbit = 1: st -> st(i) */ 4240 /*FALLTHROUGH*/ 4241 case FFC: /* case for vbit always = 0 */ 4242 #ifdef DIS_TEXT 4243 x->d86_numopnds = 2; 4244 (void) strlcat(x->d86_opnd[1 - vbit].d86_opnd, "%st", OPLEN); 4245 (void) strlcat(x->d86_opnd[vbit].d86_opnd, "%st(X)", OPLEN); 4246 x->d86_opnd[vbit].d86_opnd[4] = r_m + '0'; 4247 #endif 4248 NOMEM; 4249 break; 4250 4251 /* AVX instructions */ 4252 case VEX_MO: 4253 /* op(ModR/M.r/m) */ 4254 x->d86_numopnds = 1; 4255 dtrace_get_modrm(x, &mode, ®, &r_m); 4256 #ifdef DIS_TEXT 4257 if ((dp == &dis_opAVX0F[0xA][0xE]) && (reg == 3)) 4258 (void) strncpy(x->d86_mnem, "vstmxcsr", OPLEN); 4259 #endif 4260 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4261 dtrace_get_operand(x, mode, r_m, wbit, 0); 4262 break; 4263 case VEX_RMrX: 4264 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r/m) */ 4265 x->d86_numopnds = 3; 4266 dtrace_get_modrm(x, &mode, ®, &r_m); 4267 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4268 4269 if (mode != REG_ONLY) { 4270 if ((dp == &dis_opAVXF20F[0x10]) || 4271 (dp == &dis_opAVXF30F[0x10])) { 4272 /* vmovsd <m64>, <xmm> */ 4273 /* or vmovss <m64>, <xmm> */ 4274 x->d86_numopnds = 2; 4275 goto L_VEX_MX; 4276 } 4277 } 4278 4279 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 4280 /* 4281 * VEX prefix uses the 1's complement form to encode the 4282 * XMM/YMM regs 4283 */ 4284 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 4285 4286 if ((dp == &dis_opAVXF20F[0x2A]) || 4287 (dp == &dis_opAVXF30F[0x2A])) { 4288 /* 4289 * vcvtsi2si </r,m>, <xmm>, <xmm> or vcvtsi2ss </r,m>, 4290 * <xmm>, <xmm> 4291 */ 4292 wbit = LONG_OPND; 4293 } 4294 #ifdef DIS_TEXT 4295 else if ((mode == REG_ONLY) && 4296 (dp == &dis_opAVX0F[0x1][0x6])) { /* vmovlhps */ 4297 (void) strncpy(x->d86_mnem, "vmovlhps", OPLEN); 4298 } else if ((mode == REG_ONLY) && 4299 (dp == &dis_opAVX0F[0x1][0x2])) { /* vmovhlps */ 4300 (void) strncpy(x->d86_mnem, "vmovhlps", OPLEN); 4301 } 4302 #endif 4303 dtrace_get_operand(x, mode, r_m, wbit, 0); 4304 4305 break; 4306 4307 case VEX_RRX: 4308 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */ 4309 x->d86_numopnds = 3; 4310 4311 dtrace_get_modrm(x, &mode, ®, &r_m); 4312 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4313 4314 if (mode != REG_ONLY) { 4315 if ((dp == &dis_opAVXF20F[0x11]) || 4316 (dp == &dis_opAVXF30F[0x11])) { 4317 /* vmovsd <xmm>, <m64> */ 4318 /* or vmovss <xmm>, <m64> */ 4319 x->d86_numopnds = 2; 4320 goto L_VEX_RM; 4321 } 4322 } 4323 4324 dtrace_get_operand(x, mode, r_m, wbit, 2); 4325 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 4326 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 4327 break; 4328 4329 case VEX_RMRX: 4330 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r_m, imm8[7:4]) */ 4331 x->d86_numopnds = 4; 4332 4333 dtrace_get_modrm(x, &mode, ®, &r_m); 4334 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4335 dtrace_get_operand(x, REG_ONLY, reg, wbit, 3); 4336 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2); 4337 if (dp == &dis_opAVX660F3A[0x18]) { 4338 /* vinsertf128 <imm8>, <xmm>, <ymm>, <ymm> */ 4339 dtrace_get_operand(x, mode, r_m, XMM_OPND, 1); 4340 } else if ((dp == &dis_opAVX660F3A[0x20]) || 4341 (dp == & dis_opAVX660F[0xC4])) { 4342 /* vpinsrb <imm8>, <reg/mm>, <xmm>, <xmm> */ 4343 /* or vpinsrw <imm8>, <reg/mm>, <xmm>, <xmm> */ 4344 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 4345 } else if (dp == &dis_opAVX660F3A[0x22]) { 4346 /* vpinsrd/q <imm8>, <reg/mm>, <xmm>, <xmm> */ 4347 #ifdef DIS_TEXT 4348 if (vex_W) 4349 x->d86_mnem[6] = 'q'; 4350 #endif 4351 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 4352 } else { 4353 dtrace_get_operand(x, mode, r_m, wbit, 1); 4354 } 4355 4356 /* one byte immediate number */ 4357 dtrace_imm_opnd(x, wbit, 1, 0); 4358 4359 /* vblendvpd, vblendvps, vblendvb use the imm encode the regs */ 4360 if ((dp == &dis_opAVX660F3A[0x4A]) || 4361 (dp == &dis_opAVX660F3A[0x4B]) || 4362 (dp == &dis_opAVX660F3A[0x4C])) { 4363 #ifdef DIS_TEXT 4364 int regnum = (x->d86_opnd[0].d86_value & 0xF0) >> 4; 4365 #endif 4366 x->d86_opnd[0].d86_mode = MODE_NONE; 4367 #ifdef DIS_TEXT 4368 if (vex_L) 4369 (void) strncpy(x->d86_opnd[0].d86_opnd, 4370 dis_YMMREG[regnum], OPLEN); 4371 else 4372 (void) strncpy(x->d86_opnd[0].d86_opnd, 4373 dis_XMMREG[regnum], OPLEN); 4374 #endif 4375 } 4376 break; 4377 4378 case VEX_MX: 4379 /* ModR/M.reg := op(ModR/M.rm) */ 4380 x->d86_numopnds = 2; 4381 4382 dtrace_get_modrm(x, &mode, ®, &r_m); 4383 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4384 L_VEX_MX: 4385 4386 if ((dp == &dis_opAVXF20F[0xE6]) || 4387 (dp == &dis_opAVX660F[0x5A]) || 4388 (dp == &dis_opAVX660F[0xE6])) { 4389 /* vcvtpd2dq <ymm>, <xmm> */ 4390 /* or vcvtpd2ps <ymm>, <xmm> */ 4391 /* or vcvttpd2dq <ymm>, <xmm> */ 4392 dtrace_get_operand(x, REG_ONLY, reg, XMM_OPND, 1); 4393 dtrace_get_operand(x, mode, r_m, wbit, 0); 4394 } else if ((dp == &dis_opAVXF30F[0xE6]) || 4395 (dp == &dis_opAVX0F[0x5][0xA])) { 4396 /* vcvtdq2pd <xmm>, <ymm> */ 4397 /* or vcvtps2pd <xmm>, <ymm> */ 4398 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4399 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0); 4400 } else if (dp == &dis_opAVX660F[0x6E]) { 4401 /* vmovd/q <reg/mem 32/64>, <xmm> */ 4402 #ifdef DIS_TEXT 4403 if (vex_W) 4404 x->d86_mnem[4] = 'q'; 4405 #endif 4406 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4407 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 4408 } else { 4409 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4410 dtrace_get_operand(x, mode, r_m, wbit, 0); 4411 } 4412 4413 break; 4414 4415 case VEX_MXI: 4416 /* ModR/M.reg := op(ModR/M.rm, imm8) */ 4417 x->d86_numopnds = 3; 4418 4419 dtrace_get_modrm(x, &mode, ®, &r_m); 4420 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4421 4422 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 4423 dtrace_get_operand(x, mode, r_m, wbit, 1); 4424 4425 /* one byte immediate number */ 4426 dtrace_imm_opnd(x, wbit, 1, 0); 4427 break; 4428 4429 case VEX_XXI: 4430 /* VEX.vvvv := op(ModR/M.rm, imm8) */ 4431 x->d86_numopnds = 3; 4432 4433 dtrace_get_modrm(x, &mode, ®, &r_m); 4434 #ifdef DIS_TEXT 4435 (void) strncpy(x->d86_mnem, dis_AVXvgrp7[opcode2 - 1][reg], 4436 OPLEN); 4437 #endif 4438 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4439 4440 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2); 4441 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 1); 4442 4443 /* one byte immediate number */ 4444 dtrace_imm_opnd(x, wbit, 1, 0); 4445 break; 4446 4447 case VEX_MR: 4448 /* ModR/M.reg (reg32/64) := op(ModR/M.rm) */ 4449 if (dp == &dis_opAVX660F[0xC5]) { 4450 /* vpextrw <imm8>, <xmm>, <reg> */ 4451 x->d86_numopnds = 2; 4452 vbit = 2; 4453 } else { 4454 x->d86_numopnds = 2; 4455 vbit = 1; 4456 } 4457 4458 dtrace_get_modrm(x, &mode, ®, &r_m); 4459 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4460 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, vbit); 4461 dtrace_get_operand(x, mode, r_m, wbit, vbit - 1); 4462 4463 if (vbit == 2) 4464 dtrace_imm_opnd(x, wbit, 1, 0); 4465 4466 break; 4467 4468 case VEX_RRI: 4469 /* implicit(eflags/r32) := op(ModR/M.reg, ModR/M.rm) */ 4470 x->d86_numopnds = 2; 4471 4472 dtrace_get_modrm(x, &mode, ®, &r_m); 4473 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4474 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4475 dtrace_get_operand(x, mode, r_m, wbit, 0); 4476 break; 4477 4478 case VEX_RX: 4479 /* ModR/M.rm := op(ModR/M.reg) */ 4480 if (dp == &dis_opAVX660F3A[0x19]) { /* vextractf128 */ 4481 x->d86_numopnds = 3; 4482 4483 dtrace_get_modrm(x, &mode, ®, &r_m); 4484 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4485 4486 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2); 4487 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4488 4489 /* one byte immediate number */ 4490 dtrace_imm_opnd(x, wbit, 1, 0); 4491 break; 4492 } 4493 4494 x->d86_numopnds = 2; 4495 4496 dtrace_get_modrm(x, &mode, ®, &r_m); 4497 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4498 dtrace_get_operand(x, mode, r_m, wbit, 1); 4499 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 4500 break; 4501 4502 case VEX_RR: 4503 /* ModR/M.rm := op(ModR/M.reg) */ 4504 x->d86_numopnds = 2; 4505 4506 dtrace_get_modrm(x, &mode, ®, &r_m); 4507 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4508 4509 if (dp == &dis_opAVX660F[0x7E]) { 4510 /* vmovd/q <reg/mem 32/64>, <xmm> */ 4511 #ifdef DIS_TEXT 4512 if (vex_W) 4513 x->d86_mnem[4] = 'q'; 4514 #endif 4515 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 4516 } else 4517 dtrace_get_operand(x, mode, r_m, wbit, 1); 4518 4519 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 4520 break; 4521 4522 case VEX_RRi: 4523 /* ModR/M.rm := op(ModR/M.reg, imm) */ 4524 x->d86_numopnds = 3; 4525 4526 dtrace_get_modrm(x, &mode, ®, &r_m); 4527 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4528 4529 #ifdef DIS_TEXT 4530 if (dp == &dis_opAVX660F3A[0x16]) { 4531 /* vpextrd/q <imm>, <xmm>, <reg/mem 32/64> */ 4532 if (vex_W) 4533 x->d86_mnem[6] = 'q'; 4534 } 4535 #endif 4536 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2); 4537 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4538 4539 /* one byte immediate number */ 4540 dtrace_imm_opnd(x, wbit, 1, 0); 4541 break; 4542 4543 case VEX_RM: 4544 /* ModR/M.rm := op(ModR/M.reg) */ 4545 if (dp == &dis_opAVX660F3A[0x17]) { /* vextractps */ 4546 x->d86_numopnds = 3; 4547 4548 dtrace_get_modrm(x, &mode, ®, &r_m); 4549 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4550 4551 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2); 4552 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4553 /* one byte immediate number */ 4554 dtrace_imm_opnd(x, wbit, 1, 0); 4555 break; 4556 } 4557 x->d86_numopnds = 2; 4558 4559 dtrace_get_modrm(x, &mode, ®, &r_m); 4560 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4561 L_VEX_RM: 4562 vbit = 1; 4563 dtrace_get_operand(x, mode, r_m, wbit, vbit); 4564 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit - 1); 4565 4566 break; 4567 4568 case VEX_RRM: 4569 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */ 4570 x->d86_numopnds = 3; 4571 4572 dtrace_get_modrm(x, &mode, ®, &r_m); 4573 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4574 dtrace_get_operand(x, mode, r_m, wbit, 2); 4575 /* VEX use the 1's complement form encode the XMM/YMM regs */ 4576 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 4577 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 4578 break; 4579 4580 case VEX_RMX: 4581 /* ModR/M.reg := op(VEX.vvvv, ModR/M.rm) */ 4582 x->d86_numopnds = 3; 4583 4584 dtrace_get_modrm(x, &mode, ®, &r_m); 4585 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4586 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 4587 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 4588 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 0); 4589 break; 4590 4591 case VEX_NONE: 4592 #ifdef DIS_TEXT 4593 if (vex_L) 4594 (void) strncpy(x->d86_mnem, "vzeroall", OPLEN); 4595 #endif 4596 break; 4597 /* an invalid op code */ 4598 case AM: 4599 case DM: 4600 case OVERRIDE: 4601 case PREFIX: 4602 case UNKNOWN: 4603 NOMEM; 4604 default: 4605 goto error; 4606 } /* end switch */ 4607 if (x->d86_error) 4608 goto error; 4609 4610 done: 4611 #ifdef DIS_MEM 4612 /* 4613 * compute the size of any memory accessed by the instruction 4614 */ 4615 if (x->d86_memsize != 0) { 4616 return (0); 4617 } else if (dp->it_stackop) { 4618 switch (opnd_size) { 4619 case SIZE16: 4620 x->d86_memsize = 2; 4621 break; 4622 case SIZE32: 4623 x->d86_memsize = 4; 4624 break; 4625 case SIZE64: 4626 x->d86_memsize = 8; 4627 break; 4628 } 4629 } else if (nomem || mode == REG_ONLY) { 4630 x->d86_memsize = 0; 4631 4632 } else if (dp->it_size != 0) { 4633 /* 4634 * In 64 bit mode descriptor table entries 4635 * go up to 10 bytes and popf/pushf are always 8 bytes 4636 */ 4637 if (x->d86_mode == SIZE64 && dp->it_size == 6) 4638 x->d86_memsize = 10; 4639 else if (x->d86_mode == SIZE64 && opcode1 == 0x9 && 4640 (opcode2 == 0xc || opcode2 == 0xd)) 4641 x->d86_memsize = 8; 4642 else 4643 x->d86_memsize = dp->it_size; 4644 4645 } else if (wbit == 0) { 4646 x->d86_memsize = 1; 4647 4648 } else if (wbit == LONG_OPND) { 4649 if (opnd_size == SIZE64) 4650 x->d86_memsize = 8; 4651 else if (opnd_size == SIZE32) 4652 x->d86_memsize = 4; 4653 else 4654 x->d86_memsize = 2; 4655 4656 } else if (wbit == SEG_OPND) { 4657 x->d86_memsize = 4; 4658 4659 } else { 4660 x->d86_memsize = 8; 4661 } 4662 #endif 4663 return (0); 4664 4665 error: 4666 #ifdef DIS_TEXT 4667 (void) strlcat(x->d86_mnem, "undef", OPLEN); 4668 #endif 4669 return (1); 4670 } 4671 4672 #ifdef DIS_TEXT 4673 4674 /* 4675 * Some instructions should have immediate operands printed 4676 * as unsigned integers. We compare against this table. 4677 */ 4678 static char *unsigned_ops[] = { 4679 "or", "and", "xor", "test", "in", "out", "lcall", "ljmp", 4680 "rcr", "rcl", "ror", "rol", "shl", "shr", "sal", "psr", "psl", 4681 0 4682 }; 4683 4684 4685 static int 4686 isunsigned_op(char *opcode) 4687 { 4688 char *where; 4689 int i; 4690 int is_unsigned = 0; 4691 4692 /* 4693 * Work back to start of last mnemonic, since we may have 4694 * prefixes on some opcodes. 4695 */ 4696 where = opcode + strlen(opcode) - 1; 4697 while (where > opcode && *where != ' ') 4698 --where; 4699 if (*where == ' ') 4700 ++where; 4701 4702 for (i = 0; unsigned_ops[i]; ++i) { 4703 if (strncmp(where, unsigned_ops[i], 4704 strlen(unsigned_ops[i]))) 4705 continue; 4706 is_unsigned = 1; 4707 break; 4708 } 4709 return (is_unsigned); 4710 } 4711 4712 /* 4713 * Print a numeric immediate into end of buf, maximum length buflen. 4714 * The immediate may be an address or a displacement. Mask is set 4715 * for address size. If the immediate is a "small negative", or 4716 * if it's a negative displacement of any magnitude, print as -<absval>. 4717 * Respect the "octal" flag. "Small negative" is defined as "in the 4718 * interval [NEG_LIMIT, 0)". 4719 * 4720 * Also, "isunsigned_op()" instructions never print negatives. 4721 * 4722 * Return whether we decided to print a negative value or not. 4723 */ 4724 4725 #define NEG_LIMIT -255 4726 enum {IMM, DISP}; 4727 enum {POS, TRY_NEG}; 4728 4729 static int 4730 print_imm(dis86_t *dis, uint64_t usv, uint64_t mask, char *buf, 4731 size_t buflen, int disp, int try_neg) 4732 { 4733 int curlen; 4734 int64_t sv = (int64_t)usv; 4735 int octal = dis->d86_flags & DIS_F_OCTAL; 4736 4737 curlen = strlen(buf); 4738 4739 if (try_neg == TRY_NEG && sv < 0 && 4740 (disp || sv >= NEG_LIMIT) && 4741 !isunsigned_op(dis->d86_mnem)) { 4742 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 4743 octal ? "-0%llo" : "-0x%llx", (-sv) & mask); 4744 return (1); 4745 } else { 4746 if (disp == DISP) 4747 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 4748 octal ? "+0%llo" : "+0x%llx", usv & mask); 4749 else 4750 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 4751 octal ? "0%llo" : "0x%llx", usv & mask); 4752 return (0); 4753 4754 } 4755 } 4756 4757 4758 static int 4759 log2(int size) 4760 { 4761 switch (size) { 4762 case 1: return (0); 4763 case 2: return (1); 4764 case 4: return (2); 4765 case 8: return (3); 4766 } 4767 return (0); 4768 } 4769 4770 /* ARGSUSED */ 4771 void 4772 dtrace_disx86_str(dis86_t *dis, uint_t mode, uint64_t pc, char *buf, 4773 size_t buflen) 4774 { 4775 uint64_t reltgt = 0; 4776 uint64_t tgt = 0; 4777 int curlen; 4778 int (*lookup)(void *, uint64_t, char *, size_t); 4779 int i; 4780 int64_t sv; 4781 uint64_t usv, mask, save_mask, save_usv; 4782 static uint64_t masks[] = 4783 {0xffU, 0xffffU, 0xffffffffU, 0xffffffffffffffffULL}; 4784 save_usv = 0; 4785 4786 dis->d86_sprintf_func(buf, buflen, "%-6s ", dis->d86_mnem); 4787 4788 /* 4789 * For PC-relative jumps, the pc is really the next pc after executing 4790 * this instruction, so increment it appropriately. 4791 */ 4792 pc += dis->d86_len; 4793 4794 for (i = 0; i < dis->d86_numopnds; i++) { 4795 d86opnd_t *op = &dis->d86_opnd[i]; 4796 4797 if (i != 0) 4798 (void) strlcat(buf, ",", buflen); 4799 4800 (void) strlcat(buf, op->d86_prefix, buflen); 4801 4802 /* 4803 * sv is for the signed, possibly-truncated immediate or 4804 * displacement; usv retains the original size and 4805 * unsignedness for symbol lookup. 4806 */ 4807 4808 sv = usv = op->d86_value; 4809 4810 /* 4811 * About masks: for immediates that represent 4812 * addresses, the appropriate display size is 4813 * the effective address size of the instruction. 4814 * This includes MODE_OFFSET, MODE_IPREL, and 4815 * MODE_RIPREL. Immediates that are simply 4816 * immediate values should display in the operand's 4817 * size, however, since they don't represent addresses. 4818 */ 4819 4820 /* d86_addr_size is SIZEnn, which is log2(real size) */ 4821 mask = masks[dis->d86_addr_size]; 4822 4823 /* d86_value_size and d86_imm_bytes are in bytes */ 4824 if (op->d86_mode == MODE_SIGNED || 4825 op->d86_mode == MODE_IMPLIED) 4826 mask = masks[log2(op->d86_value_size)]; 4827 4828 switch (op->d86_mode) { 4829 4830 case MODE_NONE: 4831 4832 (void) strlcat(buf, op->d86_opnd, buflen); 4833 break; 4834 4835 case MODE_SIGNED: 4836 case MODE_IMPLIED: 4837 case MODE_OFFSET: 4838 4839 tgt = usv; 4840 4841 if (dis->d86_seg_prefix) 4842 (void) strlcat(buf, dis->d86_seg_prefix, 4843 buflen); 4844 4845 if (op->d86_mode == MODE_SIGNED || 4846 op->d86_mode == MODE_IMPLIED) { 4847 (void) strlcat(buf, "$", buflen); 4848 } 4849 4850 if (print_imm(dis, usv, mask, buf, buflen, 4851 IMM, TRY_NEG) && 4852 (op->d86_mode == MODE_SIGNED || 4853 op->d86_mode == MODE_IMPLIED)) { 4854 4855 /* 4856 * We printed a negative value for an 4857 * immediate that wasn't a 4858 * displacement. Note that fact so we can 4859 * print the positive value as an 4860 * annotation. 4861 */ 4862 4863 save_usv = usv; 4864 save_mask = mask; 4865 } 4866 (void) strlcat(buf, op->d86_opnd, buflen); 4867 4868 break; 4869 4870 case MODE_IPREL: 4871 case MODE_RIPREL: 4872 4873 reltgt = pc + sv; 4874 4875 switch (mode) { 4876 case SIZE16: 4877 reltgt = (uint16_t)reltgt; 4878 break; 4879 case SIZE32: 4880 reltgt = (uint32_t)reltgt; 4881 break; 4882 } 4883 4884 (void) print_imm(dis, usv, mask, buf, buflen, 4885 DISP, TRY_NEG); 4886 4887 if (op->d86_mode == MODE_RIPREL) 4888 (void) strlcat(buf, "(%rip)", buflen); 4889 break; 4890 } 4891 } 4892 4893 /* 4894 * The symbol lookups may result in false positives, 4895 * particularly on object files, where small numbers may match 4896 * the 0-relative non-relocated addresses of symbols. 4897 */ 4898 4899 lookup = dis->d86_sym_lookup; 4900 if (tgt != 0) { 4901 if ((dis->d86_flags & DIS_F_NOIMMSYM) == 0 && 4902 lookup(dis->d86_data, tgt, NULL, 0) == 0) { 4903 (void) strlcat(buf, "\t<", buflen); 4904 curlen = strlen(buf); 4905 lookup(dis->d86_data, tgt, buf + curlen, 4906 buflen - curlen); 4907 (void) strlcat(buf, ">", buflen); 4908 } 4909 4910 /* 4911 * If we printed a negative immediate above, print the 4912 * positive in case our heuristic was unhelpful 4913 */ 4914 if (save_usv) { 4915 (void) strlcat(buf, "\t<", buflen); 4916 (void) print_imm(dis, save_usv, save_mask, buf, buflen, 4917 IMM, POS); 4918 (void) strlcat(buf, ">", buflen); 4919 } 4920 } 4921 4922 if (reltgt != 0) { 4923 /* Print symbol or effective address for reltgt */ 4924 4925 (void) strlcat(buf, "\t<", buflen); 4926 curlen = strlen(buf); 4927 lookup(dis->d86_data, reltgt, buf + curlen, 4928 buflen - curlen); 4929 (void) strlcat(buf, ">", buflen); 4930 } 4931 } 4932 4933 #endif /* DIS_TEXT */ 4934