1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#pragma ident "%Z%%M% %I% %E% SMI" 27 28#pragma dictionary "SUN4U" 29 30#define HB_FIT 1000 31#define HBUS_FIT 1000 32#define PCI_BUS_FIT 500 33#define PCI_DEV_FIT 1000 34#define CPU_FIT 500 35 36#define PCI_HB_DEV_PATH hostbridge/pcibus/pcidev[32]/pcifn[0] 37 38fru hostbridge; 39asru hostbridge; 40 41event fault.io.tomatillo@hostbridge, 42 FITrate=HB_FIT, FRU=hostbridge, ASRU=hostbridge; 43 44event error.io.tom.jbus.um@hostbridge; 45event error.io.tom.jbus.to@hostbridge; 46event error.io.tom.jbus.bus@hostbridge; 47event error.io.tom.jbus.iis@hostbridge; 48event error.io.tom.mmu.inval@hostbridge/pcibus; 49event error.io.tom.mmu.prot@hostbridge/pcibus; 50event error.io.tom.mmu.bva@hostbridge/pcibus; 51event error.io.tom.mmu.btt@hostbridge/pcibus; 52event error.io.pci.device-ta@hostbridge/pcibus/pcidev/pcifn; 53 54event ereport.io.tom.jbus.um@hostbridge{within(5s)}; 55event ereport.io.tom.jbus.to@hostbridge{within(5s)}; 56event ereport.io.tom.jbus.bus@hostbridge{within(5s)}; 57event ereport.io.tom.jbus.to-exp@hostbridge{within(5s)}; 58event ereport.io.tom.jbus.iis@hostbridge{within(5s)}; 59event ereport.io.tom.mmu.btt@hostbridge/pcibus/pcidev/pcifn{within(5s)}; 60event ereport.io.tom.mmu.bva@hostbridge/pcibus/pcidev/pcifn{within(5s)}; 61event ereport.io.tom.mmu.prot@hostbridge/pcibus/pcidev/pcifn{within(5s)}; 62event ereport.io.tom.mmu.inval@hostbridge/pcibus/pcidev/pcifn{within(5s)}; 63event ereport.io.tom.jbus.srds@hostbridge{within(5s)}; 64event ereport.io.tom.jbus.srdsa@hostbridge{within(5s)}; 65event ereport.io.tom.jbus.sown@hostbridge{within(5s)}; 66event ereport.io.tom.jbus.srdo@hostbridge{within(5s)}; 67 68/* 69 * A faulty Tomatillo hostbridge may cause: 70 * 71 * - um: jbus unmapped address error. 72 * - to: jbus timeout. 73 * - bus: jbus bus error. 74 * - iis: illegal coherency install state error. 75 * - inval: iommu invalid entry error. 76 * - prot: iommu protection error, attempted to write a read-only page. 77 * - bva: iommu bad virtual address, address out of range. 78 * - btt: iommu bad tsb size tbw size combination. 79 * - srds: snoop error due to own RDS hitting cache line in S, O or M. 80 * - srdsa: snoop error due to own RDSA hitting cache line in S, O or M. 81 * - sown: snoop error due to own OWN hitting cache line in S or M. 82 * - srdo: snoop error due to own RDO hitting cache line in O or M. 83 * 84 * The um, to, bus, btt, inval, prot and bva errors can cause a target abort to 85 * be sent onto the pci bus in response to a dma request. We represent this 86 * using a device-ta error to propagate into the generic pci.esc rules. 87 */ 88prop fault.io.tomatillo@hostbridge (0)-> 89 error.io.tom.jbus.um@hostbridge, 90 error.io.tom.jbus.to@hostbridge, 91 error.io.tom.jbus.bus@hostbridge, 92 error.io.tom.jbus.iis@hostbridge, 93 error.io.tom.mmu.inval@hostbridge/pcibus, 94 error.io.tom.mmu.prot@hostbridge/pcibus, 95 error.io.tom.mmu.bva@hostbridge/pcibus, 96 error.io.tom.mmu.btt@hostbridge/pcibus, 97 ereport.io.tom.jbus.srds@hostbridge, 98 ereport.io.tom.jbus.srdsa@hostbridge, 99 ereport.io.tom.jbus.sown@hostbridge, 100 ereport.io.tom.jbus.srdo@hostbridge; 101 102prop error.io.tom.jbus.um@hostbridge (1)-> 103 ereport.io.tom.jbus.um@hostbridge; 104 105prop error.io.tom.jbus.um@hostbridge (0)-> 106 error.io.pci.device-ta@PCI_HB_DEV_PATH; 107 108prop error.io.tom.jbus.to@hostbridge (1)-> 109 ereport.io.tom.jbus.to@hostbridge, 110 ereport.io.tom.jbus.to-exp@hostbridge; 111 112prop error.io.tom.jbus.to@hostbridge (0)-> 113 error.io.pci.device-ta@PCI_HB_DEV_PATH; 114 115prop error.io.tom.jbus.bus@hostbridge (1)-> 116 ereport.io.tom.jbus.bus@hostbridge; 117 118prop error.io.tom.jbus.bus@hostbridge (0)-> 119 error.io.pci.device-ta@PCI_HB_DEV_PATH; 120 121prop error.io.tom.jbus.iis@hostbridge (1)-> 122 ereport.io.tom.jbus.iis@hostbridge; 123 124prop error.io.tom.mmu.btt@hostbridge/pcibus (1)-> 125 ereport.io.tom.mmu.btt@PCI_HB_DEV_PATH; 126 127prop error.io.tom.mmu.btt@hostbridge/pcibus (0)-> 128 error.io.pci.device-ta@PCI_HB_DEV_PATH, 129 error.io.tom.mmu.inval@hostbridge/pcibus; 130 131prop error.io.tom.mmu.inval@hostbridge/pcibus (1)-> 132 ereport.io.tom.mmu.inval@PCI_HB_DEV_PATH; 133 134prop error.io.tom.mmu.inval@hostbridge/pcibus (0)-> 135 error.io.pci.device-ta@PCI_HB_DEV_PATH; 136 137prop error.io.tom.mmu.prot@hostbridge/pcibus (1)-> 138 ereport.io.tom.mmu.prot@PCI_HB_DEV_PATH; 139 140prop error.io.tom.mmu.prot@hostbridge/pcibus (0)-> 141 error.io.pci.device-ta@PCI_HB_DEV_PATH; 142 143prop error.io.tom.mmu.bva@hostbridge/pcibus (1)-> 144 ereport.io.tom.mmu.bva@PCI_HB_DEV_PATH; 145 146prop error.io.tom.mmu.bva@hostbridge/pcibus (0)-> 147 error.io.pci.device-ta@PCI_HB_DEV_PATH; 148 149fru cpu; 150 151event fault.io.datapath@cpu, FITrate=CPU_FIT, FRU=cpu, retire=0; 152 153event error.io.tom.jbus.ibe@hostbridge; 154 155event ereport.io.tom.jbus.ibe@hostbridge{within(5s)}; 156event ereport.io.tom.jbus.srd@hostbridge{within(5s)}; 157event ereport.io.tom.jbus.bc@hostbridge{within(5s)}; 158 159/* 160 * A faulty CPU may cause: 161 * 162 * - to: jbus timeout error. 163 * - bus: jbus bus error. 164 * - ibe: illegal byte enable error. 165 * - iis: illegal coherency install state error. 166 * - um: jbus unmapped error. 167 * - srd: foreign RD hitting cache line in S, O or M. 168 * - bc: bad jbus command. 169 * 170 * The ibe error can cause a target abort to 171 * be sent onto the pci bus in response to a dma request. We represent this 172 * using a device-ta error to propagate into the generic pci.esc rules. 173 */ 174prop fault.io.datapath@cpu (0)-> 175 error.io.tom.jbus.to@hostbridge, 176 error.io.tom.jbus.bus@hostbridge, 177 error.io.tom.jbus.ibe@hostbridge, 178 error.io.tom.jbus.iis@hostbridge, 179 error.io.tom.jbus.um@hostbridge, 180 ereport.io.tom.jbus.srd@hostbridge, 181 ereport.io.tom.jbus.bc@hostbridge; 182 183prop error.io.tom.jbus.ibe@hostbridge (1)-> 184 ereport.io.tom.jbus.ibe@hostbridge; 185 186prop error.io.tom.jbus.ibe@hostbridge (0)-> 187 error.io.pci.device-ta@PCI_HB_DEV_PATH; 188 189event fault.io.hbus@hostbridge, 190 FITrate=HBUS_FIT, FRU=hostbridge, ASRU=hostbridge; 191 192event error.io.tom.jbus.drpe@hostbridge; 193event ereport.io.tom.jbus.ape@hostbridge{within(5s)}; 194event ereport.io.tom.jbus.pwpe@hostbridge{within(5s)}; 195event ereport.io.tom.jbus.drpe@hostbridge{within(5s)}; 196event ereport.io.tom.jbus.dwpe@hostbridge{within(5s)}; 197event ereport.io.tom.jbus.cpe@hostbridge{within(5s)}; 198 199/* 200 * A faulty host bus may cause: 201 * 202 * - ape: jbus address parity error. 203 * - pwpe: jbus PIO write parity error. 204 * - drpe: jbus DMA read parity error. 205 * - dwpe: jbus DMA write parity error. 206 * - cpe: jbus control parity error. 207 * 208 * The drpe error can cause a target abort to 209 * be sent onto the pci bus in response to a dma request. We represent this 210 * using a device-ta error to propagate into the generic pci.esc rules. 211 */ 212prop fault.io.hbus@hostbridge(0)-> 213 ereport.io.tom.jbus.ape@hostbridge, 214 ereport.io.tom.jbus.pwpe@hostbridge, 215 error.io.tom.jbus.drpe@hostbridge, 216 ereport.io.tom.jbus.dwpe@hostbridge, 217 ereport.io.tom.jbus.cpe@hostbridge; 218 219prop error.io.tom.jbus.drpe@hostbridge(1)-> 220 ereport.io.tom.jbus.drpe@hostbridge; 221 222prop error.io.tom.jbus.drpe@hostbridge(0)-> 223 error.io.pci.device-ta@PCI_HB_DEV_PATH; 224 225fru pcibus/pcidev; 226asru pcibus/pcidev/pcifn; 227 228event fault.io.pci.device-interr@hostbridge/pcibus/pcidev/pcifn, 229 FITrate=PCI_DEV_FIT, FRU=pcibus/pcidev, ASRU=pcibus/pcidev/pcifn; 230 231event fault.io.pci.device-interr@pcibus/pcidev/pcifn, 232 FITrate=PCI_DEV_FIT, FRU=pcibus/pcidev, ASRU=pcibus/pcidev/pcifn; 233 234event error.io.tom.pbm.rl@hostbridge/pcibus/pcidev/pcifn; 235event error.io.tom.pbm.rl@pcibus/pcidev/pcifn; 236event error.io.tom.pbm.rl@pcibus/pcidev/pcifn/pcibus/pcidev/pcifn; 237event error.io.tom.pbm.target-rl@pcibus/pcidev/pcifn; 238event error.io.tom.pbm.target-rl@pcibus/pcidev/pcifn/pcibus/pcidev/pcifn; 239event error.io.tom.pbm.tto@hostbridge/pcibus/pcidev/pcifn; 240event error.io.tom.pbm.target-tto@hostbridge/pcibus/pcidev/pcifn; 241event error.io.tom.pbm.target-tto@pcibus/pcidev/pcifn; 242event error.io.tom.pbm.target-tto@pcibus/pcidev/pcifn/pcibus/pcidev/pcifn; 243event error.tom.cpu.berr@cpu; 244event error.io.pci.ma-u@hostbridge/pcibus/pcidev/pcifn; 245event error.io.pci.perr-pw-u@hostbridge/pcibus/pcidev/pcifn; 246event error.io.pci.perr-dw-u@hostbridge/pcibus/pcidev/pcifn; 247event error.io.pci.dpdata-dr-u@hostbridge/pcibus/pcidev/pcifn; 248event error.io.pci.ta-u@hostbridge/pcibus/pcidev/pcifn; 249event error.io.pci.serr-u@hostbridge/pcibus/pcidev/pcifn; 250event error.io.pci.retry-to-d@hostbridge/pcibus/pcidev/pcifn; 251 252event ereport.io.tom.pbm.tto@hostbridge/pcibus/pcidev/pcifn{within(5s)}; 253event ereport.io.tom.pbm.rl@hostbridge/pcibus/pcidev/pcifn{within(5s)}; 254event ereport.io.tom.pbm.s-tto@hostbridge/pcibus/pcidev/pcifn{within(5s)}; 255event ereport.io.tom.pbm.s-rl@hostbridge/pcibus/pcidev/pcifn{within(5s)}; 256event ereport.io.tom.pbm.s-ma@hostbridge/pcibus/pcidev/pcifn{within(5s)}; 257event ereport.io.tom.pbm.s-rta@hostbridge/pcibus/pcidev/pcifn{within(5s)}; 258event ereport.io.tom.pbm.s-mdpe@hostbridge/pcibus/pcidev/pcifn{within(5s)}; 259event ereport.io.tom.pbm.target-tto@pcibus/pcidev/pcifn{within(5s)}; 260event ereport.io.tom.pbm.target-rl@pcibus/pcidev/pcifn{within(5s)}; 261event ereport.io.pci.rserr@hostbridge/pcibus/pcidev/pcifn{within(5s)}; 262 263/* 264 * A faulty PCI device may cause: 265 * 266 * - rl: it to exceed the limit on retrying a transaction. 267 * - tto: it to not assert trdy# within the set timeout. 268 * 269 * For rl and tto, there may be a target- ereport on a child device. For rl, 270 * there may also be an associated dto - the retry-to-d error propagates into 271 * the pci.esc rules to handle this. 272 */ 273prop fault.io.pci.device-interr@pcibus/pcidev[fromdev]/pcifn (0)-> 274 error.io.tom.pbm.rl@pcibus/pcidev<todev>/pcifn { 275 fromdev == todev && fromdev != 32 }, 276 error.io.tom.pbm.target-rl@pcibus/pcidev<todev>/pcifn { 277 fromdev == todev && fromdev != 32 }; 278 279prop error.io.tom.pbm.rl@pcibus/pcidev/pcifn/pcibus/pcidev/pcifn (1)-> 280 error.io.tom.pbm.rl@pcibus/pcidev/pcifn; 281 282prop error.io.tom.pbm.rl@hostbridge/pcibus/pcidev/pcifn (1)-> 283 ereport.io.tom.pbm.rl@PCI_HB_DEV_PATH, 284 ereport.io.tom.pbm.s-rl@PCI_HB_DEV_PATH; 285 286prop error.io.tom.pbm.target-rl@pcibus/pcidev/pcifn (1)-> 287 error.io.tom.pbm.target-rl@pcibus/pcidev/pcifn/pcibus<>/pcidev<>/pcifn<>; 288 289prop error.io.tom.pbm.target-rl@pcibus/pcidev/pcifn (0)-> 290 ereport.io.tom.pbm.target-rl@pcibus/pcidev/pcifn; 291 292prop error.io.tom.pbm.rl@hostbridge/pcibus/pcidev/pcifn (0)-> 293 error.tom.cpu.berr@cpu; 294 295prop error.io.tom.pbm.rl@hostbridge/pcibus/pcidev/pcifn (0)-> 296 error.io.pci.retry-to-d@hostbridge/pcibus/pcidev/pcifn; 297 298prop fault.io.pci.device-interr@hostbridge/pcibus/pcidev[fromdev]/pcifn (0)-> 299 error.io.tom.pbm.tto@hostbridge/pcibus/pcidev<todev>/pcifn { 300 fromdev == todev && fromdev != 32}; 301 302prop error.io.tom.pbm.tto@hostbridge/pcibus/pcidev/pcifn (1)-> 303 ereport.io.tom.pbm.tto@PCI_HB_DEV_PATH, 304 ereport.io.tom.pbm.s-tto@PCI_HB_DEV_PATH; 305 306prop error.io.tom.pbm.tto@hostbridge/pcibus/pcidev/pcifn (1)-> 307 error.io.tom.pbm.target-tto@hostbridge/pcibus/pcidev/pcifn; 308 309prop error.io.tom.pbm.target-tto@pcibus/pcidev/pcifn (0)-> 310 ereport.io.tom.pbm.target-tto@pcibus/pcidev/pcifn; 311 312prop error.io.tom.pbm.target-tto@pcibus/pcidev/pcifn (1)-> 313 error.io.tom.pbm.target-tto@pcibus/pcidev/pcifn/pcibus<>/pcidev<>/pcifn<>; 314 315/* 316 * Need to add the following tomatillo specific propagations to complete the 317 * fault tree. These are to allow propagations to secondary errors and cpu 318 * bus errors, and to represent the way the chip raises rserr 319 * on detection of SERR# 320 */ 321prop error.io.pci.ma-u@hostbridge/pcibus/pcidev/pcifn (0)-> 322 ereport.io.tom.pbm.s-ma@PCI_HB_DEV_PATH; 323 324prop error.io.pci.ta-u@hostbridge/pcibus/pcidev/pcifn (0)-> 325 ereport.io.tom.pbm.s-rta@PCI_HB_DEV_PATH; 326 327prop error.io.pci.perr-pw-u@hostbridge/pcibus/pcidev/pcifn (0)-> 328 ereport.io.tom.pbm.s-mdpe@PCI_HB_DEV_PATH; 329 330prop error.io.pci.perr-dw-u@hostbridge/pcibus/pcidev/pcifn (0)-> 331 ereport.io.tom.pbm.s-mdpe@PCI_HB_DEV_PATH; 332 333prop error.io.pci.dpdata-dr-u@hostbridge/pcibus/pcidev/pcifn (0)-> 334 ereport.io.tom.pbm.s-mdpe@PCI_HB_DEV_PATH; 335 336prop error.io.pci.ta-u@hostbridge/pcibus/pcidev/pcifn (0)-> 337 error.tom.cpu.berr@cpu; 338 339prop error.io.pci.dpdata-dr-u@hostbridge/pcibus/pcidev/pcifn (0)-> 340 error.tom.cpu.berr@cpu; 341 342prop error.io.pci.ma-u@hostbridge/pcibus/pcidev/pcifn (0)-> 343 error.tom.cpu.berr@cpu; 344 345prop error.io.pci.serr-u@hostbridge/pcibus/pcidev/pcifn (1)-> 346 ereport.io.pci.rserr@PCI_HB_DEV_PATH; 347 348event ereport.cpu.ultraSPARC-IIIi.berr@cpu{within(5s)}; 349 350prop error.tom.cpu.berr@cpu (1)-> 351 ereport.cpu.ultraSPARC-IIIi.berr@cpu; 352 353/* 354 * A bad request from a downstream device/driver may cause 355 * 356 * - inval: iommu invalid entry error. 357 * - prot: iommu protection error, attempted to write a read-only page. 358 * - bva: iommu bad virtual address, address out of range. 359 * - btt: iommu bad tsb size tbw size combination. 360 */ 361event error.io.pci.badreq-pw-u@hostbridge/pcibus/pcidev/pcifn; 362 363prop error.io.pci.badreq-pw-u@hostbridge/pcibus/pcidev/pcifn (0)-> 364 ereport.io.tom.mmu.inval@PCI_HB_DEV_PATH, 365 ereport.io.tom.mmu.prot@PCI_HB_DEV_PATH, 366 ereport.io.tom.mmu.bva@PCI_HB_DEV_PATH, 367 ereport.io.tom.mmu.btt@PCI_HB_DEV_PATH; 368 369event error.io.pci.badreq-drw-u@hostbridge/pcibus/pcidev/pcifn; 370 371prop error.io.pci.badreq-drw-u@hostbridge/pcibus/pcidev/pcifn (0)-> 372 ereport.io.tom.mmu.inval@PCI_HB_DEV_PATH, 373 ereport.io.tom.mmu.prot@PCI_HB_DEV_PATH, 374 ereport.io.tom.mmu.bva@PCI_HB_DEV_PATH, 375 ereport.io.tom.mmu.btt@PCI_HB_DEV_PATH; 376 377event error.io.tom.ecc.drue@hostbridge; 378event error.io.tom.mmu.ue@hostbridge/pcibus; 379event error.io.tom.mmu.to@hostbridge/pcibus; 380event ereport.io.tom.jbus.sgr@hostbridge{within(5s)}; 381event ereport.io.tom.jbus.spci@hostbridge{within(5s)}; 382event ereport.io.tom.jbus.snp@hostbridge{within(5s)}; 383event ereport.io.tom.ecc.drue@hostbridge{within(5s)}; 384event ereport.io.tom.mmu.ue@hostbridge/pcibus/pcidev/pcifn{within(5s)}; 385event ereport.io.tom.mmu.to@hostbridge/pcibus/pcidev/pcifn{within(5s)}; 386 387event ereport.io.tom.nodiag@hostbridge; 388 389/* 390 * Upset used to hide ereports that can not be currently diagnosed. 391 * 392 * The ue, to and drue errors can cause a target abort to 393 * be sent onto the pci bus in response to a dma request. We represent this 394 * using a device-ta error to propagate into the generic pci.esc rules. 395 */ 396engine serd.io.tom.nodiag@hostbridge, 397 N=1000, T=1hour, method=persistent, 398 trip=ereport.io.tom.nodiag@hostbridge; 399 400event upset.io.tom.nodiag@hostbridge, 401 engine=serd.io.tom.nodiag@hostbridge; 402 403prop upset.io.tom.nodiag@hostbridge (0)-> 404 ereport.io.tom.jbus.sgr@hostbridge, 405 ereport.io.tom.jbus.spci@hostbridge, 406 ereport.io.tom.jbus.snp@hostbridge, 407 ereport.io.tom.nodiag@hostbridge; 408 409prop upset.io.tom.nodiag@hostbridge (0)-> 410 error.io.tom.ecc.drue@hostbridge, 411 error.io.tom.mmu.to@hostbridge/pcibus, 412 error.io.tom.mmu.ue@hostbridge/pcibus; 413 414prop error.io.tom.mmu.ue@hostbridge/pcibus (1)-> 415 ereport.io.tom.mmu.ue@PCI_HB_DEV_PATH; 416 417prop error.io.tom.mmu.ue@hostbridge/pcibus (0)-> 418 error.io.pci.device-ta@PCI_HB_DEV_PATH; 419 420prop error.io.tom.mmu.to@hostbridge/pcibus (1)-> 421 ereport.io.tom.mmu.to@PCI_HB_DEV_PATH; 422 423prop error.io.tom.mmu.to@hostbridge/pcibus (0)-> 424 error.io.pci.device-ta@PCI_HB_DEV_PATH; 425 426prop error.io.tom.ecc.drue@hostbridge (1)-> 427 ereport.io.tom.ecc.drue@hostbridge; 428 429prop error.io.tom.ecc.drue@hostbridge (0)-> 430 error.io.pci.device-ta@PCI_HB_DEV_PATH; 431