1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#pragma dictionary "INTEL" 28 29/* 30 * Eversholt rules for the intel CPU/Memory 31 */ 32 33/* 34 * Ereports for Simple error codes. 35 */ 36 37#define SMPL_EVENT(leafclass, t) \ 38 event ereport.cpu.intel.leafclass@chip/core/strand { within(t) } 39 40SMPL_EVENT(unknown, 1s); 41SMPL_EVENT(unclassified, 1s); 42SMPL_EVENT(microcode_rom_parity, 1s); 43SMPL_EVENT(external, 1s); 44SMPL_EVENT(frc, 1s); 45SMPL_EVENT(internal_timer, 1s); 46SMPL_EVENT(internal_parity, 1s); 47SMPL_EVENT(internal_unclassified, 1s); 48 49/* 50 * Propogations for all but "external" and "unknown" simple errors. 51 * If the error is uncorrected we produce a fault immediately, otherwise 52 * we diagnose it to an upset and decalre a fault when the SERD engine 53 * trips. 54 */ 55 56engine serd.cpu.intel.simple@chip/core/strand, N=3, T=72h; 57event fault.cpu.intel.internal@chip/core/strand, 58 engine=serd.cpu.intel.simple@chip/core/strand; 59 60prop fault.cpu.intel.internal@chip/core/strand 61 { payloadprop("error_uncorrected") == 1 ? setserdincrement(4) : 1} (0)-> 62 ereport.cpu.intel.microcode_rom_parity@chip/core/strand, 63 ereport.cpu.intel.internal_timer@chip/core/strand, 64 ereport.cpu.intel.internal_parity@chip/core/strand, 65 ereport.cpu.intel.unclassified@chip/core/strand, 66 ereport.cpu.intel.internal_unclassified@chip/core/strand, 67 ereport.cpu.intel.frc@chip/core/strand; 68 69/* 70 * Ereports for Compound error codes. These are in pairs "foo" and "foo_uc" 71 * for the corrected and uncorrected version of each error type. All are 72 * detected at chip/core/strand. 73 */ 74 75#define CMPND_EVENT(leafclass, t) \ 76 event ereport.cpu.intel.leafclass@chip/core/strand { within(t) }; \ 77 event ereport.cpu.intel.leafclass/**/_uc@chip/core/strand { within(t) } 78 79/* 80 * Ereports for Compound error codes - intel errors 81 */ 82CMPND_EVENT(l0cache, 1s); 83CMPND_EVENT(l1cache, 1s); 84CMPND_EVENT(l2cache, 1s); 85CMPND_EVENT(cache, 1s); 86 87/* 88 * Ereports for Compound error codes - TLB errors 89 */ 90CMPND_EVENT(l0dtlb, 1s); 91CMPND_EVENT(l1dtlb, 1s); 92CMPND_EVENT(l2dtlb, 1s); 93CMPND_EVENT(dtlb, 1s); 94 95CMPND_EVENT(l0itlb, 1s); 96CMPND_EVENT(l1itlb, 1s); 97CMPND_EVENT(l2itlb, 1s); 98CMPND_EVENT(itlb, 1s); 99 100CMPND_EVENT(l0tlb, 1s); 101CMPND_EVENT(l1tlb, 1s); 102CMPND_EVENT(l2tlb, 1s); 103CMPND_EVENT(tlb, 1s); 104 105/* 106 * Ereports for Compound error codes - memory hierarchy errors 107 */ 108CMPND_EVENT(l0dcache, 1s); 109CMPND_EVENT(l1dcache, 1s); 110CMPND_EVENT(l2dcache, 1s); 111CMPND_EVENT(dcache, 1s); 112 113CMPND_EVENT(l0icache, 1s); 114CMPND_EVENT(l1icache, 1s); 115CMPND_EVENT(l2icache, 1s); 116CMPND_EVENT(icache, 1s); 117 118/* 119 * Ereports for Compound error codes - bus and interconnect errors 120 */ 121CMPND_EVENT(bus_interconnect, 1s); 122CMPND_EVENT(bus_interconnect_memory, 1s); 123CMPND_EVENT(bus_interconnect_io, 1s); 124 125/* 126 * Compound error propogations. 127 * 128 * We resist the temptation propogate, for example, a single dcache fault 129 * to all ereports mentioning dcache (l0dcache, l1dcache, l2dcache, dcache). 130 * Instead we will diagnose a distinct fault for each possible cache level, 131 * whether or not current chips have dcaches at all levels. 132 * 133 * Corrected errors are SERDed and produce a fault when the engine fires; 134 * the same fault is diagnosed immediately for a corresponding uncorrected 135 * error. 136 */ 137 138#define CMPND_FLT_PROP_1(erptleaf, fltleaf, n, t) \ 139 engine serd.cpu.intel.fltleaf@chip/core/strand, N=n, T=t; \ 140 event fault.cpu.intel.fltleaf@chip/core/strand, \ 141 engine=serd.cpu.intel.fltleaf@chip/core/strand; \ 142 \ 143 prop fault.cpu.intel.fltleaf@chip/core/strand (0)-> \ 144 ereport.cpu.intel.erptleaf@chip/core/strand; \ 145 \ 146 prop fault.cpu.intel.fltleaf@chip/core/strand \ 147 { setserdincrement(n + 1) } (0)-> \ 148 ereport.cpu.intel.erptleaf/**/_uc@chip/core/strand 149 150#define CMPND_FLT_PROP_2(erptleaf, fltleaf, n, t) \ 151 engine serd.cpu.intel.fltleaf@chip/core/strand, N=n, T=t; \ 152 event fault.cpu.intel.fltleaf@chip/core/strand, retire=0, response=0,\ 153 engine=serd.cpu.intel.fltleaf@chip/core/strand; \ 154 \ 155 prop fault.cpu.intel.fltleaf@chip/core/strand (0)-> \ 156 ereport.cpu.intel.erptleaf@chip/core/strand; \ 157 \ 158 prop fault.cpu.intel.fltleaf@chip/core/strand \ 159 { setserdincrement(n + 1) } (0)-> \ 160 ereport.cpu.intel.erptleaf/**/_uc@chip/core/strand 161 162CMPND_FLT_PROP_1(l0cache, l0cache, 3, 72h); 163CMPND_FLT_PROP_1(l1cache, l1cache, 3, 72h); 164CMPND_FLT_PROP_1(l2cache, l2cache, 3, 72h); 165CMPND_FLT_PROP_1(cache, cache, 12, 72h); 166 167CMPND_FLT_PROP_1(l0dtlb, l0dtlb, 3, 72h); 168CMPND_FLT_PROP_1(l1dtlb, l1dtlb, 3, 72h); 169CMPND_FLT_PROP_1(l2dtlb, l2dtlb, 3, 72h); 170CMPND_FLT_PROP_1(dtlb, dtlb, 12, 72h); 171 172CMPND_FLT_PROP_1(l0itlb, l0itlb, 3, 72h); 173CMPND_FLT_PROP_1(l1itlb, l1itlb, 3, 72h); 174CMPND_FLT_PROP_1(l2itlb, l2itlb, 3, 72h); 175CMPND_FLT_PROP_1(itlb, itlb, 12, 72h); 176 177CMPND_FLT_PROP_1(l0tlb, litlb, 3, 72h); 178CMPND_FLT_PROP_1(l1tlb, litlb, 3, 72h); 179CMPND_FLT_PROP_1(l2tlb, litlb, 3, 72h); 180CMPND_FLT_PROP_1(tlb, tlb, 12, 72h); 181 182CMPND_FLT_PROP_1(l0dcache, l0dcache, 3, 72h); 183CMPND_FLT_PROP_1(l1dcache, l1dcache, 3, 72h); 184CMPND_FLT_PROP_1(l2dcache, l2dcache, 3, 72h); 185CMPND_FLT_PROP_1(dcache, dcache, 12, 72h); 186 187CMPND_FLT_PROP_1(l0icache, l0icache, 3, 72h); 188CMPND_FLT_PROP_1(l1icache, l1icache, 3, 72h); 189CMPND_FLT_PROP_1(l2icache, l2icache, 3, 72h); 190CMPND_FLT_PROP_1(icache, icache, 12, 72h); 191 192CMPND_FLT_PROP_2(bus_interconnect, bus_interconnect, 10, 72h); 193CMPND_FLT_PROP_2(bus_interconnect_memory, bus_interconnect_memory, 10, 72h); 194CMPND_FLT_PROP_2(bus_interconnect_io, bus_interconnect_io, 10, 72h); 195 196event upset.discard@chip/core/strand; 197 198prop upset.discard@chip/core/strand (0)-> 199 ereport.cpu.intel.external@chip/core/strand, 200 ereport.cpu.intel.unknown@chip/core/strand; 201 202/* errors detected in northbridge */ 203 204 205/* 206 * SET_ADDR and SET_OFFSET are used to set a payload value in the fault that 207 * we diagnose for page faults, to record the physical address of the faulting 208 * page. 209 */ 210#define SET_ADDR (!payloadprop_defined("physaddr") || \ 211 setpayloadprop("asru-physaddr", payloadprop("physaddr"))) 212 213#define SET_OFFSET (!payloadprop_defined("offset") || \ 214 setpayloadprop("asru-offset", payloadprop("offset"))) 215 216#define EREPORT_BUS_ERROR \ 217 ereport.cpu.intel.bus_interconnect_memory_uc@chip/core/strand, \ 218 ereport.cpu.intel.bus_interconnect_uc@chip/core/strand, \ 219 ereport.cpu.intel.bus_interconnect_memory@chip/core/strand, \ 220 ereport.cpu.intel.bus_interconnect@chip/core/strand, \ 221 ereport.cpu.intel.external@chip/core/strand 222 223engine stat.ce_pgflt@memory-controller/dram-channel/dimm; 224 225event ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller{within(12s)}; 226event ereport.cpu.intel.nb.ddr2_mem_ue@ 227 motherboard/memory-controller{within(12s)}; 228event ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller{within(12s)}; 229event fault.memory.intel.page_ue@ 230 motherboard/memory-controller/dram-channel/dimm/rank, 231 message=0, response=0; 232event fault.memory.intel.dimm_ue@ 233 motherboard/memory-controller/dram-channel/dimm/rank; 234 235prop fault.memory.intel.page_ue@ 236 motherboard/memory-controller/dram-channel/dimm/rank[rank_num] 237 { payloadprop_defined("rank") && rank_num == payloadprop("rank") && 238 (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 239 SET_ADDR && SET_OFFSET } (1)-> 240 ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller, 241 ereport.cpu.intel.nb.ddr2_mem_ue@motherboard/memory-controller, 242 ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller; 243 244prop fault.memory.intel.dimm_ue@ 245 motherboard/memory-controller/dram-channel/dimm/rank[rank_num] 246 { payloadprop_defined("rank") && rank_num == payloadprop("rank") } (1)-> 247 ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller, 248 ereport.cpu.intel.nb.ddr2_mem_ue@motherboard/memory-controller, 249 ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller; 250 251event upset.memory.intel.discard@motherboard/memory-controller{within(1s)}; 252 253prop upset.memory.intel.discard@motherboard/memory-controller (0)-> 254 ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller, 255 ereport.cpu.intel.nb.ddr2_mem_ue@motherboard/memory-controller, 256 ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller; 257 258prop upset.memory.intel.discard@motherboard/memory-controller (0)-> 259 EREPORT_BUS_ERROR; 260 261#define PAGE_CE_COUNT 2 262#define PAGE_CE_TIME 72h 263#define DIMM_CE_COUNT 10 264#define DIMM_CE_TIME 1week 265 266#define MBDIMM motherboard/memory-controller/dram-channel/dimm 267event ereport.cpu.intel.nb.mem_ce@MBDIMM/rank{within(12s)}; 268event ereport.cpu.intel.nb.ddr2_mem_ce@MBDIMM/rank{within(12s)}; 269event ereport.cpu.intel.nb.ddr2_mem_ce@ 270 motherboard/memory-controller{within(12s)}; 271 272engine serd.memory.intel.page_ce@MBDIMM/rank, N=PAGE_CE_COUNT, T=PAGE_CE_TIME; 273event fault.memory.intel.page_ce@MBDIMM/rank, message=0, response=0, 274 count=stat.ce_pgflt@MBDIMM, engine=serd.memory.intel.page_ce@MBDIMM/rank; 275prop fault.memory.intel.page_ce@MBDIMM/rank 276 { (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 277 SET_ADDR && SET_OFFSET } (0)-> 278 ereport.cpu.intel.nb.mem_ce@MBDIMM/rank, 279 ereport.cpu.intel.nb.ddr2_mem_ce@MBDIMM/rank; 280 281engine serd.memory.intel.dimm_ce@MBDIMM/rank, N=DIMM_CE_COUNT, T=DIMM_CE_TIME; 282event fault.memory.intel.dimm_ce@MBDIMM/rank, 283 engine=serd.memory.intel.dimm_ce@MBDIMM/rank; 284prop fault.memory.intel.dimm_ce@MBDIMM/rank 285 { !confprop_defined(MBDIMM, "dimm-size") && 286 count(stat.ce_pgflt@MBDIMM) > 512 } (1)-> 287 ereport.cpu.intel.nb.mem_ce@MBDIMM/rank, 288 ereport.cpu.intel.nb.ddr2_mem_ce@MBDIMM/rank; 289#define DIMM_CE(dimm_size, n, t, fault_rate) \ 290 prop fault.memory.intel.dimm_ce@MBDIMM/rank { \ 291 confprop(MBDIMM, "dimm-size") == dimm_size && \ 292 count(stat.ce_pgflt@MBDIMM) > fault_rate && \ 293 setserdn(n) & setserdt(t) } (1)-> \ 294 ereport.cpu.intel.nb.mem_ce@MBDIMM/rank, \ 295 ereport.cpu.intel.nb.ddr2_mem_ce@MBDIMM/rank; 296 297DIMM_CE("8G", 8, 1week, 2000) 298DIMM_CE("4G", 4, 1week, 1500) 299DIMM_CE("2G", 4, 2week, 1000) 300DIMM_CE("1G", 4, 4week, 500) 301DIMM_CE("512M", 4, 8week, 250) 302DIMM_CE("256M", 4, 16week, 125) 303 304prop upset.memory.intel.discard@motherboard/memory-controller (0)-> 305 ereport.cpu.intel.nb.ddr2_mem_ce@motherboard/memory-controller; 306 307event ereport.cpu.intel.nb.fbd.alert@rank{within(12s)}; 308event fault.memory.intel.fbd.alert@rank, retire=0; 309 310prop fault.memory.intel.fbd.alert@rank (1)-> 311 ereport.cpu.intel.nb.fbd.alert@rank; 312 313prop fault.memory.intel.fbd.alert@rank (0)-> 314 EREPORT_BUS_ERROR; 315 316event ereport.cpu.intel.nb.fbd.crc@rank{within(12s)}; 317event fault.memory.intel.fbd.crc@rank, retire=0; 318 319prop fault.memory.intel.fbd.crc@rank (1)-> 320 ereport.cpu.intel.nb.fbd.crc@rank; 321 322prop fault.memory.intel.fbd.crc@rank (0)-> EREPORT_BUS_ERROR; 323 324event ereport.cpu.intel.nb.fbd.reset_timeout@memory-controller {within(12s)}; 325event fault.memory.intel.fbd.reset_timeout@memory-controller, retire=0; 326 327prop fault.memory.intel.fbd.reset_timeout@memory-controller (1)-> 328 ereport.cpu.intel.nb.fbd.reset_timeout@memory-controller; 329 330prop fault.memory.intel.fbd.reset_timeout@memory-controller (0)-> 331 EREPORT_BUS_ERROR; 332 333event ereport.cpu.intel.nb.fbd.ch@dram-channel {within(12s)}; 334engine serd.cpu.intel.nb.fbd.ch@dram-channel, N=2, T=1month; 335event fault.memory.intel.fbd.ch@dram-channel, retire=0, 336 engine=serd.cpu.intel.nb.fbd.ch@dram-channel; 337 338prop fault.memory.intel.fbd.ch@dram-channel (1)-> 339 ereport.cpu.intel.nb.fbd.ch@dram-channel; 340 341prop fault.memory.intel.fbd.ch@dram-channel (0)-> 342 EREPORT_BUS_ERROR; 343 344event ereport.cpu.intel.nb.fbd.otf@dram-channel {within(12s)}; 345engine serd.cpu.intel.nb.fbd_otf@dram-channel, N=2, T=1week; 346event fault.memory.intel.fbd.otf@dram-channel, retire=0, response=0, 347 engine=serd.cpu.intel.nb.fbd_otf@dram-channel; 348 349prop fault.memory.intel.fbd.otf@dram-channel (1)-> 350 ereport.cpu.intel.nb.fbd.otf@dram-channel; 351 352event ereport.cpu.intel.nb.otf@motherboard {within(12s)}; 353event fault.cpu.intel.nb.otf@motherboard, retire=0, response=0; 354 355prop fault.cpu.intel.nb.otf@motherboard (1)-> 356 ereport.cpu.intel.nb.otf@motherboard; 357 358event ereport.cpu.intel.nb.unknown@motherboard {within(12s)}; 359event ereport.cpu.intel.nb.unknown@memory-controller {within(12s)}; 360event ereport.cpu.intel.nb.unknown@memory-controller/dram-channel {within(12s)}; 361event ereport.cpu.intel.nb.spd@memory-controller/dram-channel {within(12s)}; 362event ereport.cpu.intel.nb.ddr2_spd@ 363 memory-controller/dram-channel {within(12s)}; 364event upset.discard@memory-controller; 365 366prop upset.discard@memory-controller (0)-> 367 ereport.cpu.intel.nb.unknown@motherboard, 368 ereport.cpu.intel.nb.unknown@memory-controller, 369 ereport.cpu.intel.nb.unknown@memory-controller/dram-channel, 370 ereport.cpu.intel.nb.spd@memory-controller/dram-channel, 371 ereport.cpu.intel.nb.ddr2_spd@memory-controller/dram-channel; 372 373event ereport.cpu.intel.nb.mem_ds@memory-controller{within(30s)}; 374event ereport.cpu.intel.nb.ddr2_mem_ds@memory-controller{within(30s)}; 375event fault.memory.intel.fbd.mem_ds@memory-controller/dram-channel/dimm/rank, 376 retire=0; 377 378prop fault.memory.intel.fbd.mem_ds@ 379 memory-controller/dram-channel/dimm/rank[rank_num] 380 { payloadprop_defined("rank") && rank_num == payloadprop("rank") } (1)-> 381 ereport.cpu.intel.nb.mem_ds@memory-controller, 382 ereport.cpu.intel.nb.ddr2_mem_ds@memory-controller; 383 384event ereport.cpu.intel.nb.fsb@chip{within(12s)}; 385event fault.cpu.intel.nb.fsb@chip, retire=0; 386 387prop fault.cpu.intel.nb.fsb@chip (1)-> 388 ereport.cpu.intel.nb.fsb@chip; 389 390prop fault.cpu.intel.nb.fsb@chip (0)-> EREPORT_BUS_ERROR; 391 392event ereport.cpu.intel.nb.ie@motherboard{within(12s)}; 393event fault.cpu.intel.nb.ie@motherboard, retire=0; 394event upset.cpu.intel.nb.ie_ce@motherboard{within(12s)}; 395 396prop upset.cpu.intel.nb.ie_ce@motherboard 397 { payloadprop("intel-error-list") == "B6" } (0)-> 398 ereport.cpu.intel.nb.ie@motherboard; 399 400prop fault.cpu.intel.nb.ie@motherboard 401 { payloadprop("intel-error-list") != "B6" } (1)-> 402 ereport.cpu.intel.nb.ie@motherboard; 403 404prop fault.cpu.intel.nb.ie@motherboard (0)-> EREPORT_BUS_ERROR; 405 406event ereport.cpu.intel.nb.dma@motherboard{within(12s)}; 407event fault.cpu.intel.nb.dma@motherboard, retire=0, response=0; 408 409prop fault.cpu.intel.nb.dma@motherboard (1)-> 410 ereport.cpu.intel.nb.dma@motherboard; 411 412prop fault.cpu.intel.nb.dma@motherboard (0)-> EREPORT_BUS_ERROR; 413 414event ereport.cpu.intel.nb.esi@motherboard{within(12s)}; 415event ereport.cpu.intel.nb.pex@hostbridge{within(12s)}; 416event upset.cpu.intel.nb.pex@hostbridge; 417 418prop upset.cpu.intel.nb.pex@hostbridge (1)-> 419 ereport.cpu.intel.nb.esi@motherboard, 420 ereport.cpu.intel.nb.pex@hostbridge; 421 422prop upset.cpu.intel.nb.pex@hostbridge (0)-> EREPORT_BUS_ERROR; 423 424event ereport.cpu.intel.nb.unknown@rank{within(12s)}; 425event upset.discard@rank; 426 427prop upset.discard@rank (1)-> 428 ereport.cpu.intel.nb.unknown@rank; 429 430prop upset.discard@rank (0)-> EREPORT_BUS_ERROR; 431 432/* 433 * CPU integrated memory controller 434 */ 435 436#define CONTAINS_RANK (payloadprop_contains("resource", \ 437 asru(motherboard/chip/memory-controller/dram-channel/dimm/rank)) || \ 438 payloadprop_contains("resource", \ 439 asru(motherboard/chip/memory-controller/dram-channel/dimm))) 440 441#define STAT_CPU_MEM_CE_PGFLTS \ 442 stat.ce_pgflt@motherboard/chip/memory-controller/dram-channel/dimm 443 444#define SET_RES_OFFSET \ 445 (!payloadprop_defined("resource[0].hc-specific.offset") || \ 446 setpayloadprop("asru-offset", \ 447 payloadprop("resource[0].hc-specific.offset"))) 448 449engine STAT_CPU_MEM_CE_PGFLTS; 450 451event ereport.cpu.intel.quickpath.mem_ue@motherboard/chip/memory-controller 452 {within(12s)}; 453 454event fault.memory.intel.page_ue@ 455 motherboard/chip/memory-controller/dram-channel/dimm/rank, 456 message=0, response=0; /* do not message individual pageflts */ 457 458prop fault.memory.intel.page_ue@ 459 motherboard/chip/memory-controller/dram-channel/dimm/rank 460 { CONTAINS_RANK && (payloadprop_defined("physaddr") || 461 payloadprop_defined("resource[0].hc-specific.offset")) && 462 SET_ADDR && SET_RES_OFFSET } (1)-> 463 ereport.cpu.intel.quickpath.mem_ue@motherboard/chip/memory-controller; 464 465event fault.memory.intel.dimm_ue@ 466 motherboard/chip/memory-controller/dram-channel/dimm/rank; 467 468prop fault.memory.intel.dimm_ue@ 469 motherboard/chip/memory-controller/dram-channel/dimm/rank 470 { CONTAINS_RANK } (1)-> 471 ereport.cpu.intel.quickpath.mem_ue@motherboard/chip/memory-controller; 472 473prop fault.memory.intel.dimm_ue@ 474 motherboard/chip/memory-controller/dram-channel/dimm/rank (0)-> 475 EREPORT_BUS_ERROR; 476 477#define CHIPDIMM motherboard/chip/memory-controller/dram-channel/dimm 478event ereport.cpu.intel.quickpath.mem_ce@ 479 motherboard/chip/memory-controller{within(12s)}; 480 481engine serd.memory.intel.page_ce@CHIPDIMM/rank, N=PAGE_CE_COUNT, T=PAGE_CE_TIME; 482event fault.memory.intel.page_ce@CHIPDIMM/rank, message=0, response=0, 483 count=STAT_CPU_MEM_CE_PGFLTS, 484 engine=serd.memory.intel.page_ce@CHIPDIMM/rank; 485prop fault.memory.intel.page_ce@CHIPDIMM/rank 486 { CONTAINS_RANK && (payloadprop_defined("physaddr") || 487 payloadprop_defined("resource[0].hc-specific.offset")) && 488 SET_ADDR && SET_RES_OFFSET } (1)-> 489 ereport.cpu.intel.quickpath.mem_ce@motherboard/chip/memory-controller; 490 491engine serd.memory.intel.dimm_ce@CHIPDIMM, N=PAGE_CE_COUNT, T=PAGE_CE_TIME; 492event fault.memory.intel.dimm_ce@CHIPDIMM, 493 engine=serd.memory.intel.dimm_ce@CHIPDIMM; 494prop fault.memory.intel.dimm_ce@CHIPDIMM 495 { !confprop_defined(CHIPDIMM, "dimm-size") && 496 count(STAT_CPU_MEM_CE_PGFLTS) > 512 } (1)-> 497 ereport.cpu.intel.quickpath.mem_ce@motherboard/chip/memory-controller; 498 499#define CPU_MEM_DIMM_CE(dimm_size, n, t, fault_rate) \ 500 prop fault.memory.intel.dimm_ce@CHIPDIMM { \ 501 confprop(CHIPDIMM, "dimm-size") == dimm_size && \ 502 count(STAT_CPU_MEM_CE_PGFLTS) > fault_rate && \ 503 setserdn(n) & setserdt(t) } (1)-> \ 504 ereport.cpu.intel.quickpath.mem_ce@ \ 505 motherboard/chip/memory-controller; 506 507CPU_MEM_DIMM_CE("16G", 16, 1week, 2000) 508CPU_MEM_DIMM_CE("8G", 8, 1week, 2000) 509CPU_MEM_DIMM_CE("4G", 4, 1week, 1500) 510CPU_MEM_DIMM_CE("2G", 4, 2week, 1000) 511CPU_MEM_DIMM_CE("1G", 4, 4week, 500) 512CPU_MEM_DIMM_CE("512M", 4, 8week, 250) 513 514event ereport.cpu.intel.quickpath.mem_unknown@motherboard/chip/memory-controller {within(12s)}; 515event ereport.cpu.intel.quickpath.mem_unknown@motherboard/chip/memory-controller/dram-channel 516 {within(12s)}; 517event ereport.cpu.intel.quickpath.mem_unknown@ 518 motherboard/chip/memory-controller/dram-channel/dimm/rank{within(12s)}; 519event upset.discard@motherboard/chip/memory-controller; 520event upset.discard@motherboard/chip/memory-controller/dram-channel/dimm/rank; 521 522prop upset.discard@motherboard/chip/memory-controller (0)-> 523 ereport.cpu.intel.quickpath.mem_unknown@motherboard/chip/memory-controller, 524 ereport.cpu.intel.quickpath.mem_unknown@ 525 motherboard/chip/memory-controller/dram-channel; 526 527prop upset.discard@ 528 motherboard/chip/memory-controller/dram-channel/dimm/rank (1)-> 529 ereport.cpu.intel.quickpath.mem_unknown@ 530 motherboard/chip/memory-controller/dram-channel/dimm/rank; 531 532event ereport.cpu.intel.quickpath.mem_parity@motherboard/chip/memory-controller {within(1s)}; 533event fault.cpu.intel.quickpath.mem_parity@motherboard/chip/memory-controller; 534 535prop fault.cpu.intel.quickpath.mem_parity@motherboard/chip/memory-controller (1)-> 536 ereport.cpu.intel.quickpath.mem_parity@motherboard/chip/memory-controller; 537 538event ereport.cpu.intel.quickpath.mem_addr_parity@motherboard/chip/memory-controller {within(1s)}; 539event fault.cpu.intel.quickpath.mem_addr_parity@ 540 motherboard/chip/memory-controller; 541event fault.cpu.intel.quickpath.mem_addr_parity@CHIPDIMM; 542event fault.cpu.intel.quickpath.mem_addr_parity@CHIPDIMM/rank; 543 544prop fault.cpu.intel.quickpath.mem_addr_parity@ 545 motherboard/chip/memory-controller (1)-> 546 ereport.cpu.intel.quickpath.mem_addr_parity@motherboard/chip/memory-controller; 547 548prop fault.cpu.intel.quickpath.mem_addr_parity@CHIPDIMM 549 { payloadprop_contains("resource", asru(CHIPDIMM)) } (1)-> 550 ereport.cpu.intel.quickpath.mem_addr_parity@motherboard/chip/memory-controller; 551 552prop fault.cpu.intel.quickpath.mem_addr_parity@CHIPDIMM/rank 553 { payloadprop_contains("resource", asru(CHIPDIMM/rank)) } (1)-> 554 ereport.cpu.intel.quickpath.mem_addr_parity@motherboard/chip/memory-controller; 555 556event ereport.cpu.intel.quickpath.mem_bad_addr@motherboard/chip/memory-controller {within(1s)}; 557event fault.cpu.intel.quickpath.mem_bad_addr@motherboard/chip/memory-controller; 558 559prop fault.cpu.intel.quickpath.mem_bad_addr@motherboard/chip/memory-controller (1)-> 560 ereport.cpu.intel.quickpath.mem_bad_addr@motherboard/chip/memory-controller; 561 562event ereport.cpu.intel.quickpath.mem_spare@motherboard/chip/memory-controller {within(1s)}; 563event fault.cpu.intel.quickpath.mem_spare@ 564 motherboard/chip/memory-controller/dram-channel/dimm; 565 566prop fault.cpu.intel.quickpath.mem_spare@ 567 motherboard/chip/memory-controller/dram-channel/dimm (1)-> 568 ereport.cpu.intel.quickpath.mem_spare@motherboard/chip/memory-controller; 569 570event ereport.cpu.intel.quickpath.mem_bad_id@motherboard/chip/memory-controller {within(1s)}; 571event fault.cpu.intel.quickpath.mem_bad_id@motherboard/chip/memory-controller; 572 573prop fault.cpu.intel.quickpath.mem_bad_id@motherboard/chip/memory-controller (1)-> 574 ereport.cpu.intel.quickpath.mem_bad_id@motherboard/chip/memory-controller; 575 576event ereport.cpu.intel.quickpath.mem_redundant@motherboard/chip/memory-controller {within(1s)}; 577engine serd.cpu.intel.quickpath.mem_redundant@CHIPDIMM, N=2, T=72h; 578event fault.cpu.intel.quickpath.mem_redundant@CHIPDIMM, 579 engine=serd.cpu.intel.quickpath.mem_redundant@CHIPDIMM; 580 581event error.cpu.intel.quickpath.mem_redundant@CHIPDIMM/rank; 582 583prop fault.cpu.intel.quickpath.mem_redundant@CHIPDIMM (1)-> 584 error.cpu.intel.quickpath.mem_redundant@CHIPDIMM/rank 585 { is_under(CHIPDIMM, CHIPDIMM/rank) }; 586prop error.cpu.intel.quickpath.mem_redundant@CHIPDIMM/rank 587 { CONTAINS_RANK } (1)-> 588 ereport.cpu.intel.quickpath.mem_redundant@ 589 motherboard/chip/memory-controller; 590 591#define STATUS_UC (payloadprop("error_uncorrected") == 1) 592event ereport.cpu.intel.quickpath.interconnect@motherboard/chip 593 {within(1s)}; 594event upset.cpu.intel.quickpath.interconnect@motherboard/chip; 595/* Diagnose corrected events to upsets */ 596prop upset.cpu.intel.quickpath.interconnect@motherboard/chip 597 { !STATUS_UC } (1)-> 598 ereport.cpu.intel.quickpath.interconnect@motherboard/chip; 599 600 601engine serd.cpu.intel.quickpath.interconnect@motherboard/chip, 602 N=3, T=72h; 603event fault.cpu.intel.quickpath.interconnect@motherboard/chip, 604 engine=serd.cpu.intel.quickpath.interconnect@motherboard/chip; 605 606/* Diagnose uncorrected events to faults */ 607prop fault.cpu.intel.quickpath.interconnect@motherboard/chip 608 { STATUS_UC } (0)-> 609 ereport.cpu.intel.quickpath.interconnect@motherboard/chip; 610