1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22/*
23 * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25
26#pragma dictionary "INTEL"
27
28/*
29 * Eversholt rules for the intel CPU/Memory
30 */
31
32/*
33 * Ereports for Simple error codes.
34 */
35
36#define SMPL_EVENT(leafclass, t) \
37	event ereport.cpu.intel.leafclass@chip/core/strand { within(t) }
38
39SMPL_EVENT(unknown, 1s);
40SMPL_EVENT(unclassified, 1s);
41SMPL_EVENT(microcode_rom_parity, 1s);
42SMPL_EVENT(external, 1s);
43SMPL_EVENT(frc, 1s);
44SMPL_EVENT(internal_timer, 1s);
45SMPL_EVENT(internal_parity, 1s);
46SMPL_EVENT(internal_unclassified, 1s);
47
48/*
49 * Propogations for all but "external" and "unknown" simple errors.
50 * If the error is uncorrected we produce a fault immediately, otherwise
51 * we diagnose it to an upset and decalre a fault when the SERD engine
52 * trips. prop statement for ereport.cpu.intel.internal_unclassified is
53 * moved to the Nehalem EX section to deal with poison case.
54 */
55
56engine serd.cpu.intel.simple@chip/core/strand, N=3, T=72h;
57event fault.cpu.intel.internal@chip/core/strand,
58    engine=serd.cpu.intel.simple@chip/core/strand;
59
60prop fault.cpu.intel.internal@chip/core/strand
61    { payloadprop("error_uncorrected") == 1 ? setserdincrement(4) : 1} (0)->
62    ereport.cpu.intel.microcode_rom_parity@chip/core/strand,
63    ereport.cpu.intel.internal_timer@chip/core/strand,
64    ereport.cpu.intel.internal_parity@chip/core/strand,
65    ereport.cpu.intel.unclassified@chip/core/strand,
66    ereport.cpu.intel.frc@chip/core/strand;
67
68/*
69 * Ereports for Compound error codes.  These are in pairs "foo" and "foo_uc"
70 * for the corrected and uncorrected version of each error type.  All are
71 * detected at chip/core/strand.
72 */
73
74#define	CMPND_EVENT(leafclass, t) \
75	event ereport.cpu.intel.leafclass@chip/core/strand { within(t) }; \
76	event ereport.cpu.intel.leafclass/**/_uc@chip/core/strand { within(t) }
77
78/*
79 * Ereports for Compound error codes - intel errors
80 */
81CMPND_EVENT(l0cache, 1s);
82CMPND_EVENT(l1cache, 1s);
83CMPND_EVENT(l2cache, 1s);
84CMPND_EVENT(cache, 1s);
85
86/*
87 * Ereports for Compound error codes - TLB errors
88 */
89CMPND_EVENT(l0dtlb, 1s);
90CMPND_EVENT(l1dtlb, 1s);
91CMPND_EVENT(l2dtlb, 1s);
92CMPND_EVENT(dtlb, 1s);
93
94CMPND_EVENT(l0itlb, 1s);
95CMPND_EVENT(l1itlb, 1s);
96CMPND_EVENT(l2itlb, 1s);
97CMPND_EVENT(itlb, 1s);
98
99CMPND_EVENT(l0tlb, 1s);
100CMPND_EVENT(l1tlb, 1s);
101CMPND_EVENT(l2tlb, 1s);
102CMPND_EVENT(tlb, 1s);
103
104/*
105 * Ereports for Compound error codes - memory hierarchy errors
106 */
107CMPND_EVENT(l0dcache, 1s);
108CMPND_EVENT(l1dcache, 1s);
109CMPND_EVENT(l2dcache, 1s);
110CMPND_EVENT(dcache, 1s);
111
112CMPND_EVENT(l0icache, 1s);
113CMPND_EVENT(l1icache, 1s);
114CMPND_EVENT(l2icache, 1s);
115CMPND_EVENT(icache, 1s);
116
117/*
118 * Ereports for Compound error codes - bus and interconnect errors
119 */
120CMPND_EVENT(bus_interconnect, 1s);
121CMPND_EVENT(bus_interconnect_memory, 1s);
122CMPND_EVENT(bus_interconnect_io, 1s);
123
124/*
125 * Compound error propogations.
126 *
127 * We resist the temptation propogate, for example, a single dcache fault
128 * to all ereports mentioning dcache (l0dcache, l1dcache, l2dcache, dcache).
129 * Instead we will diagnose a distinct fault for each possible cache level,
130 * whether or not current chips have dcaches at all levels.
131 *
132 * Corrected errors are SERDed and produce a fault when the engine fires;
133 * the same fault is diagnosed immediately for a corresponding uncorrected
134 * error.
135 */
136
137#define	CMPND_FLT_PROP_1(erptleaf, fltleaf, n, t)			\
138	engine serd.cpu.intel.fltleaf@chip/core/strand, N=n, T=t;	\
139	event fault.cpu.intel.fltleaf@chip/core/strand,			\
140	    engine=serd.cpu.intel.fltleaf@chip/core/strand;		\
141									\
142	prop fault.cpu.intel.fltleaf@chip/core/strand (0)->		\
143	    ereport.cpu.intel.erptleaf@chip/core/strand;		\
144									\
145	prop fault.cpu.intel.fltleaf@chip/core/strand			\
146	    { setserdincrement(n + 1) } (0)->				\
147	    ereport.cpu.intel.erptleaf/**/_uc@chip/core/strand
148
149#define	CMPND_FLT_PROP_2(erptleaf, fltleaf, n, t)			\
150	engine serd.cpu.intel.fltleaf@chip/core/strand, N=n, T=t;	\
151	event fault.cpu.intel.fltleaf@chip/core/strand, retire=0, response=0,\
152	    engine=serd.cpu.intel.fltleaf@chip/core/strand;		\
153									\
154	prop fault.cpu.intel.fltleaf@chip/core/strand (0)->		\
155	    ereport.cpu.intel.erptleaf@chip/core/strand;		\
156									\
157	prop fault.cpu.intel.fltleaf@chip/core/strand 			\
158	    { setserdincrement(n + 1) } (0)->				\
159	    ereport.cpu.intel.erptleaf/**/_uc@chip/core/strand
160
161CMPND_FLT_PROP_1(l0cache, l0cache, 3, 72h);
162CMPND_FLT_PROP_1(l1cache, l1cache, 3, 72h);
163CMPND_FLT_PROP_1(l2cache, l2cache, 3, 72h);
164CMPND_FLT_PROP_1(cache, cache, 12, 72h);
165
166CMPND_FLT_PROP_1(l0dtlb, l0dtlb, 3, 72h);
167CMPND_FLT_PROP_1(l1dtlb, l1dtlb, 3, 72h);
168CMPND_FLT_PROP_1(l2dtlb, l2dtlb, 3, 72h);
169CMPND_FLT_PROP_1(dtlb, dtlb, 12, 72h);
170
171CMPND_FLT_PROP_1(l0itlb, l0itlb, 3, 72h);
172CMPND_FLT_PROP_1(l1itlb, l1itlb, 3, 72h);
173CMPND_FLT_PROP_1(l2itlb, l2itlb, 3, 72h);
174CMPND_FLT_PROP_1(itlb, itlb, 12, 72h);
175
176CMPND_FLT_PROP_1(l0tlb, l0tlb, 3, 72h);
177CMPND_FLT_PROP_1(l1tlb, l1tlb, 3, 72h);
178CMPND_FLT_PROP_1(l2tlb, l2tlb, 3, 72h);
179CMPND_FLT_PROP_1(tlb, tlb, 12, 72h);
180
181CMPND_FLT_PROP_1(l0dcache, l0dcache, 3, 72h);
182CMPND_FLT_PROP_1(l1dcache, l1dcache, 3, 72h);
183CMPND_FLT_PROP_1(l2dcache, l2dcache, 3, 72h);
184CMPND_FLT_PROP_1(dcache, dcache, 12, 72h);
185
186CMPND_FLT_PROP_1(l0icache, l0icache, 3, 72h);
187CMPND_FLT_PROP_1(l1icache, l1icache, 3, 72h);
188CMPND_FLT_PROP_1(l2icache, l2icache, 3, 72h);
189CMPND_FLT_PROP_1(icache, icache, 12, 72h);
190
191CMPND_FLT_PROP_2(bus_interconnect, bus_interconnect, 10, 72h);
192CMPND_FLT_PROP_2(bus_interconnect_memory, bus_interconnect_memory, 10, 72h);
193CMPND_FLT_PROP_2(bus_interconnect_io, bus_interconnect_io, 10, 72h);
194
195event upset.discard@chip/core/strand;
196
197event ereport.cpu.intel.unknown@chip {within(15s)};
198prop upset.discard@chip/core/strand (0)->
199    ereport.cpu.intel.external@chip/core/strand,
200    ereport.cpu.intel.unknown@chip/core/strand,
201    ereport.cpu.intel.unknown@chip;
202
203/* errors detected in northbridge */
204
205
206/*
207 * SET_ADDR and SET_OFFSET are used to set a payload value in the fault that
208 * we diagnose for page faults, to record the physical address of the faulting
209 * page.
210 */
211#define	SET_ADDR (!payloadprop_defined("physaddr") || \
212    setpayloadprop("asru-physaddr", payloadprop("physaddr")))
213
214#define SET_OFFSET (!payloadprop_defined("offset") || \
215    setpayloadprop("asru-offset", payloadprop("offset")))
216
217#define EREPORT_BUS_ERROR						\
218    ereport.cpu.intel.bus_interconnect_memory_uc@chip/core/strand,	\
219    ereport.cpu.intel.bus_interconnect_uc@chip/core/strand,		\
220    ereport.cpu.intel.bus_interconnect_memory@chip/core/strand,		\
221    ereport.cpu.intel.bus_interconnect@chip/core/strand,		\
222    ereport.cpu.intel.external@chip/core/strand
223
224engine stat.ce_pgflt@memory-controller/dram-channel/dimm;
225
226event ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller{within(12s)};
227event ereport.cpu.intel.nb.ddr2_mem_ue@
228    motherboard/memory-controller{within(12s)};
229event ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller{within(12s)};
230event fault.memory.intel.page_ue@
231    motherboard/memory-controller/dram-channel/dimm/rank,
232    message=0, response=0;
233event fault.memory.intel.dimm_ue@
234    motherboard/memory-controller/dram-channel/dimm/rank;
235
236prop fault.memory.intel.page_ue@
237    motherboard/memory-controller/dram-channel/dimm/rank[rank_num]
238    { payloadprop_defined("rank") && rank_num == payloadprop("rank") &&
239    (payloadprop_defined("physaddr") || payloadprop_defined("offset")) &&
240    SET_ADDR && SET_OFFSET } (1)->
241    ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller,
242    ereport.cpu.intel.nb.ddr2_mem_ue@motherboard/memory-controller,
243    ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller;
244
245prop fault.memory.intel.dimm_ue@
246    motherboard/memory-controller/dram-channel/dimm/rank[rank_num]
247    { payloadprop_defined("rank") && rank_num == payloadprop("rank") } (1)->
248    ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller,
249    ereport.cpu.intel.nb.ddr2_mem_ue@motherboard/memory-controller,
250    ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller;
251
252event upset.memory.intel.discard@motherboard/memory-controller{within(1s)};
253
254prop upset.memory.intel.discard@motherboard/memory-controller (0)->
255    ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller,
256    ereport.cpu.intel.nb.ddr2_mem_ue@motherboard/memory-controller,
257    ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller;
258
259prop upset.memory.intel.discard@motherboard/memory-controller (0)->
260    EREPORT_BUS_ERROR;
261
262#define PAGE_CE_COUNT   2
263#define PAGE_CE_TIME    72h
264#define DIMM_CE_COUNT   10
265#define DIMM_CE_TIME    1week
266
267#define MBDIMM motherboard/memory-controller/dram-channel/dimm
268event ereport.cpu.intel.nb.mem_ce@MBDIMM/rank{within(12s)};
269event ereport.cpu.intel.nb.ddr2_mem_ce@MBDIMM/rank{within(12s)};
270event ereport.cpu.intel.nb.ddr2_mem_ce@
271    motherboard/memory-controller{within(12s)};
272
273engine serd.memory.intel.page_ce@MBDIMM/rank, N=PAGE_CE_COUNT, T=PAGE_CE_TIME;
274event fault.memory.intel.page_ce@MBDIMM/rank, message=0, response=0,
275    count=stat.ce_pgflt@MBDIMM, engine=serd.memory.intel.page_ce@MBDIMM/rank;
276prop fault.memory.intel.page_ce@MBDIMM/rank
277    { (payloadprop_defined("physaddr") || payloadprop_defined("offset")) &&
278    SET_ADDR && SET_OFFSET } (0)->
279    ereport.cpu.intel.nb.mem_ce@MBDIMM/rank,
280    ereport.cpu.intel.nb.ddr2_mem_ce@MBDIMM/rank;
281
282engine serd.memory.intel.dimm_ce@MBDIMM/rank, N=DIMM_CE_COUNT, T=DIMM_CE_TIME;
283event fault.memory.intel.dimm_ce@MBDIMM/rank,
284    engine=serd.memory.intel.dimm_ce@MBDIMM/rank;
285prop fault.memory.intel.dimm_ce@MBDIMM/rank
286    { !confprop_defined(MBDIMM, "dimm-size") &&
287    count(stat.ce_pgflt@MBDIMM) > 512 } (1)->
288    ereport.cpu.intel.nb.mem_ce@MBDIMM/rank,
289    ereport.cpu.intel.nb.ddr2_mem_ce@MBDIMM/rank;
290#define DIMM_CE(dimm_size, n, t, fault_rate) \
291	prop fault.memory.intel.dimm_ce@MBDIMM/rank { \
292	    confprop(MBDIMM, "dimm-size") == dimm_size && \
293	    count(stat.ce_pgflt@MBDIMM) > fault_rate && \
294	    setserdn(n) & setserdt(t) } (1)-> \
295    	    ereport.cpu.intel.nb.mem_ce@MBDIMM/rank, \
296	    ereport.cpu.intel.nb.ddr2_mem_ce@MBDIMM/rank;
297
298DIMM_CE("8G", 8, 1week, 2000)
299DIMM_CE("4G", 4, 1week, 1500)
300DIMM_CE("2G", 4, 2week, 1000)
301DIMM_CE("1G", 4, 4week, 500)
302DIMM_CE("512M", 4, 8week, 250)
303DIMM_CE("256M", 4, 16week, 125)
304
305prop upset.memory.intel.discard@motherboard/memory-controller (0)->
306    ereport.cpu.intel.nb.ddr2_mem_ce@motherboard/memory-controller;
307
308event ereport.cpu.intel.nb.fbd.alert@rank{within(12s)};
309event fault.memory.intel.fbd.alert@rank, retire=0;
310
311prop fault.memory.intel.fbd.alert@rank (1)->
312    ereport.cpu.intel.nb.fbd.alert@rank;
313
314prop fault.memory.intel.fbd.alert@rank (0)->
315    EREPORT_BUS_ERROR;
316
317event ereport.cpu.intel.nb.fbd.crc@rank{within(12s)};
318event fault.memory.intel.fbd.crc@rank, retire=0;
319
320prop fault.memory.intel.fbd.crc@rank (1)->
321    ereport.cpu.intel.nb.fbd.crc@rank;
322
323prop fault.memory.intel.fbd.crc@rank (0)-> EREPORT_BUS_ERROR;
324
325event ereport.cpu.intel.nb.fbd.reset_timeout@memory-controller {within(12s)};
326event fault.memory.intel.fbd.reset_timeout@memory-controller, retire=0;
327
328prop fault.memory.intel.fbd.reset_timeout@memory-controller (1)->
329    ereport.cpu.intel.nb.fbd.reset_timeout@memory-controller;
330
331prop fault.memory.intel.fbd.reset_timeout@memory-controller (0)->
332    EREPORT_BUS_ERROR;
333
334event ereport.cpu.intel.nb.fbd.ch@dram-channel {within(12s)};
335engine serd.cpu.intel.nb.fbd.ch@dram-channel, N=2, T=1month;
336event fault.memory.intel.fbd.ch@dram-channel, retire=0,
337    engine=serd.cpu.intel.nb.fbd.ch@dram-channel;
338
339prop fault.memory.intel.fbd.ch@dram-channel (1)->
340    ereport.cpu.intel.nb.fbd.ch@dram-channel;
341
342prop fault.memory.intel.fbd.ch@dram-channel (0)->
343    EREPORT_BUS_ERROR;
344
345event ereport.cpu.intel.nb.fbd.otf@dram-channel {within(12s)};
346engine serd.cpu.intel.nb.fbd_otf@dram-channel, N=2, T=1week;
347event fault.memory.intel.fbd.otf@dram-channel, retire=0, response=0,
348    engine=serd.cpu.intel.nb.fbd_otf@dram-channel;
349
350prop fault.memory.intel.fbd.otf@dram-channel (1)->
351    ereport.cpu.intel.nb.fbd.otf@dram-channel;
352
353event ereport.cpu.intel.nb.otf@motherboard {within(12s)};
354event fault.cpu.intel.nb.otf@motherboard, retire=0, response=0;
355
356prop fault.cpu.intel.nb.otf@motherboard (1)->
357    ereport.cpu.intel.nb.otf@motherboard;
358
359event ereport.cpu.intel.nb.unknown@motherboard {within(12s)};
360event ereport.cpu.intel.nb.unknown@memory-controller {within(12s)};
361event ereport.cpu.intel.nb.unknown@memory-controller/dram-channel {within(12s)};
362event ereport.cpu.intel.nb.spd@memory-controller/dram-channel {within(12s)};
363event ereport.cpu.intel.nb.ddr2_spd@
364    memory-controller/dram-channel {within(12s)};
365event upset.discard@memory-controller;
366
367prop upset.discard@memory-controller (0)->
368    ereport.cpu.intel.nb.unknown@motherboard,
369    ereport.cpu.intel.nb.unknown@memory-controller,
370    ereport.cpu.intel.nb.unknown@memory-controller/dram-channel,
371    ereport.cpu.intel.nb.spd@memory-controller/dram-channel,
372    ereport.cpu.intel.nb.ddr2_spd@memory-controller/dram-channel;
373
374event ereport.cpu.intel.nb.mem_ds@memory-controller{within(30s)};
375event ereport.cpu.intel.nb.ddr2_mem_ds@memory-controller{within(30s)};
376event fault.memory.intel.fbd.mem_ds@memory-controller/dram-channel/dimm/rank,
377    retire=0;
378
379prop fault.memory.intel.fbd.mem_ds@
380    memory-controller/dram-channel/dimm/rank[rank_num]
381    { payloadprop_defined("rank") && rank_num == payloadprop("rank") } (1)->
382    ereport.cpu.intel.nb.mem_ds@memory-controller,
383    ereport.cpu.intel.nb.ddr2_mem_ds@memory-controller;
384
385event ereport.cpu.intel.nb.fsb@chip{within(12s)};
386event fault.cpu.intel.nb.fsb@chip, retire=0;
387
388prop fault.cpu.intel.nb.fsb@chip (1)->
389    ereport.cpu.intel.nb.fsb@chip;
390
391prop fault.cpu.intel.nb.fsb@chip (0)-> EREPORT_BUS_ERROR;
392
393event ereport.cpu.intel.nb.ie@motherboard{within(12s)};
394event fault.cpu.intel.nb.ie@motherboard, retire=0;
395event upset.cpu.intel.nb.ie_ce@motherboard{within(12s)};
396
397prop upset.cpu.intel.nb.ie_ce@motherboard
398    { payloadprop("intel-error-list") == "B6" } (0)->
399    ereport.cpu.intel.nb.ie@motherboard;
400
401prop fault.cpu.intel.nb.ie@motherboard
402    { payloadprop("intel-error-list") != "B6" } (1)->
403    ereport.cpu.intel.nb.ie@motherboard;
404
405prop fault.cpu.intel.nb.ie@motherboard (0)-> EREPORT_BUS_ERROR;
406
407event ereport.cpu.intel.nb.dma@motherboard{within(12s)};
408event upset.cpu.intel.nb.dma@motherboard;
409
410prop upset.cpu.intel.nb.dma@motherboard (1)->
411    ereport.cpu.intel.nb.dma@motherboard;
412
413event ereport.cpu.intel.nb.esi@motherboard{within(12s)};
414event ereport.cpu.intel.nb.pex@hostbridge{within(12s)};
415event upset.cpu.intel.nb.pex@hostbridge;
416
417prop upset.cpu.intel.nb.pex@hostbridge (1)->
418    ereport.cpu.intel.nb.esi@motherboard,
419    ereport.cpu.intel.nb.pex@hostbridge;
420
421prop upset.cpu.intel.nb.pex@hostbridge (0)-> EREPORT_BUS_ERROR;
422
423event ereport.cpu.intel.nb.unknown@rank{within(12s)};
424event upset.discard@rank;
425
426prop upset.discard@rank (1)->
427    ereport.cpu.intel.nb.unknown@rank;
428
429prop upset.discard@rank (0)-> EREPORT_BUS_ERROR;
430
431/*
432 * CPU integrated memory controller
433 */
434
435#define CONTAINS_RANK (payloadprop_contains("resource", \
436    asru(chip/memory-controller/dram-channel/dimm/rank)) || \
437    payloadprop_contains("resource", \
438    asru(chip/memory-controller/dram-channel/dimm)))
439
440#define	STAT_CPU_MEM_CE_PGFLTS \
441    stat.ce_pgflt@chip/memory-controller/dram-channel/dimm
442
443#define SET_RES_OFFSET \
444    (!payloadprop_defined("resource[0].hc-specific.offset") || \
445    setpayloadprop("asru-offset", \
446    payloadprop("resource[0].hc-specific.offset")))
447
448engine STAT_CPU_MEM_CE_PGFLTS;
449
450event ereport.cpu.intel.quickpath.mem_ue@chip/memory-controller
451    {within(12s)}, discard_if_config_unknown=1;
452
453event fault.memory.intel.page_ue@
454    chip/memory-controller/dram-channel/dimm/rank,
455    message=0, response=0;		/* do not message individual pageflts */
456
457prop fault.memory.intel.page_ue@
458    chip/memory-controller/dram-channel/dimm/rank
459    { CONTAINS_RANK && (payloadprop_defined("physaddr") ||
460    payloadprop_defined("resource[0].hc-specific.offset")) &&
461    SET_ADDR && SET_RES_OFFSET } (0)->
462    ereport.cpu.intel.quickpath.mem_ue@chip/memory-controller;
463
464#define	CHIPDIMM chip/memory-controller/dram-channel/dimm
465
466event fault.memory.intel.dimm_ue@CHIPDIMM/rank;
467
468event error.memory.intel.dimm_ue_ep@CHIPDIMM/rank;
469event error.memory.intel.dimm_ue_ex@CHIPDIMM/rank;
470
471prop fault.memory.intel.dimm_ue@CHIPDIMM/rank (1)->
472   error.memory.intel.dimm_ue_ep@CHIPDIMM/rank,
473   error.memory.intel.dimm_ue_ex@CHIPDIMM/rank;
474
475prop error.memory.intel.dimm_ue_ep@CHIPDIMM/rank
476    { CONTAINS_RANK } (1)->
477    ereport.cpu.intel.quickpath.mem_ue@chip/memory-controller;
478
479prop fault.memory.intel.dimm_ue@CHIPDIMM/rank (0)-> EREPORT_BUS_ERROR;
480
481event ereport.cpu.intel.quickpath.mem_ce@
482    chip/memory-controller {within(12s)}, discard_if_config_unknown=1;
483
484engine serd.memory.intel.page_ce@CHIPDIMM/rank, N=PAGE_CE_COUNT, T=PAGE_CE_TIME;
485event fault.memory.intel.page_ce@CHIPDIMM/rank, message=0, response=0,
486    count=STAT_CPU_MEM_CE_PGFLTS,
487    engine=serd.memory.intel.page_ce@CHIPDIMM/rank;
488prop fault.memory.intel.page_ce@CHIPDIMM/rank
489    { CONTAINS_RANK && (payloadprop_defined("physaddr") ||
490    payloadprop_defined("resource[0].hc-specific.offset")) &&
491    SET_ADDR && SET_RES_OFFSET } (0)->
492    ereport.cpu.intel.quickpath.mem_ce@chip/memory-controller;
493
494engine serd.memory.intel.dimm_ce@CHIPDIMM, N=PAGE_CE_COUNT, T=PAGE_CE_TIME;
495event fault.memory.intel.dimm_ce@CHIPDIMM,
496    engine=serd.memory.intel.dimm_ce@CHIPDIMM;
497prop fault.memory.intel.dimm_ce@CHIPDIMM
498    { !confprop_defined(CHIPDIMM, "dimm-size") &&
499    count(STAT_CPU_MEM_CE_PGFLTS) > 512 } (0)->
500    ereport.cpu.intel.quickpath.mem_ce@chip/memory-controller;
501
502#define	CPU_MEM_DIMM_CE(dimm_size, n, t, fault_rate) \
503	prop fault.memory.intel.dimm_ce@CHIPDIMM { \
504	    confprop(CHIPDIMM, "dimm-size") == dimm_size && \
505	    count(STAT_CPU_MEM_CE_PGFLTS) > fault_rate && \
506	    setserdn(n) & setserdt(t) } (0)-> \
507	    ereport.cpu.intel.quickpath.mem_ce@ \
508	    chip/memory-controller;
509
510CPU_MEM_DIMM_CE("16G", 16, 1week, 2000)
511CPU_MEM_DIMM_CE("8G", 8, 1week, 2000)
512CPU_MEM_DIMM_CE("4G", 4, 1week, 1500)
513CPU_MEM_DIMM_CE("2G", 4, 2week, 1000)
514CPU_MEM_DIMM_CE("1G", 4, 4week, 500)
515CPU_MEM_DIMM_CE("512M", 4, 8week, 250)
516
517event ereport.cpu.intel.quickpath.mem_unknown@chip/memory-controller
518    {within(12s)}, discard_if_config_unknown=1;
519event ereport.cpu.intel.quickpath.mem_unknown@
520    chip/memory-controller/dram-channel {within(12s)},
521    discard_if_config_unknown=1;
522event ereport.cpu.intel.quickpath.mem_unknown@
523    chip/memory-controller/dram-channel/dimm/rank{within(12s)};
524event upset.discard@chip/memory-controller;
525event upset.discard@chip/memory-controller/dram-channel/dimm/rank;
526
527prop upset.discard@chip/memory-controller (0)->
528    ereport.cpu.intel.quickpath.mem_unknown@chip/memory-controller,
529    ereport.cpu.intel.quickpath.mem_unknown@
530    chip/memory-controller/dram-channel;
531
532prop upset.discard@
533    chip/memory-controller/dram-channel/dimm/rank (1)->
534    ereport.cpu.intel.quickpath.mem_unknown@
535    chip/memory-controller/dram-channel/dimm/rank;
536
537event ereport.cpu.intel.quickpath.mem_parity@chip/memory-controller
538    {within(1s)}, discard_if_config_unknown=1;
539event fault.cpu.intel.quickpath.mem_parity@chip/memory-controller;
540
541prop fault.cpu.intel.quickpath.mem_parity@chip/memory-controller (1)->
542    ereport.cpu.intel.quickpath.mem_parity@chip/memory-controller;
543
544event ereport.cpu.intel.quickpath.mem_addr_parity@chip/memory-controller
545    {within(1s)}, discard_if_config_unknown=1;
546event fault.cpu.intel.quickpath.mem_addr_parity@
547    chip/memory-controller;
548event fault.cpu.intel.quickpath.mem_addr_parity@CHIPDIMM;
549event fault.cpu.intel.quickpath.mem_addr_parity@CHIPDIMM/rank;
550
551prop fault.cpu.intel.quickpath.mem_addr_parity@
552    chip/memory-controller (1)->
553    ereport.cpu.intel.quickpath.mem_addr_parity@chip/memory-controller;
554
555prop fault.cpu.intel.quickpath.mem_addr_parity@CHIPDIMM
556    { payloadprop_contains("resource", asru(CHIPDIMM)) } (1)->
557    ereport.cpu.intel.quickpath.mem_addr_parity@chip/memory-controller;
558
559prop fault.cpu.intel.quickpath.mem_addr_parity@CHIPDIMM/rank
560    { payloadprop_contains("resource", asru(CHIPDIMM/rank)) } (1)->
561    ereport.cpu.intel.quickpath.mem_addr_parity@chip/memory-controller;
562
563event ereport.cpu.intel.quickpath.mem_bad_addr@chip/memory-controller
564    {within(1s)}, discard_if_config_unknown=1;
565event fault.cpu.intel.quickpath.mem_bad_addr@chip/memory-controller;
566
567prop fault.cpu.intel.quickpath.mem_bad_addr@chip/memory-controller (1)->
568    ereport.cpu.intel.quickpath.mem_bad_addr@chip/memory-controller;
569
570event ereport.cpu.intel.quickpath.mem_spare@chip/memory-controller
571    {within(1s)}, discard_if_config_unknown=1;
572event fault.cpu.intel.quickpath.mem_spare@
573    chip/memory-controller/dram-channel/dimm;
574
575prop fault.cpu.intel.quickpath.mem_spare@
576    chip/memory-controller/dram-channel/dimm (1)->
577    ereport.cpu.intel.quickpath.mem_spare@chip/memory-controller;
578
579event ereport.cpu.intel.quickpath.mem_bad_id@chip/memory-controller
580    {within(1s)}, discard_if_config_unknown=1;
581event fault.cpu.intel.quickpath.mem_bad_id@chip/memory-controller;
582
583prop fault.cpu.intel.quickpath.mem_bad_id@chip/memory-controller (1)->
584    ereport.cpu.intel.quickpath.mem_bad_id@chip/memory-controller;
585
586event ereport.cpu.intel.quickpath.mem_redundant@chip/memory-controller
587    {within(1s)}, discard_if_config_unknown=1;
588engine serd.cpu.intel.quickpath.mem_redundant@CHIPDIMM, N=2, T=72h;
589event fault.cpu.intel.quickpath.mem_redundant@CHIPDIMM,
590    engine=serd.cpu.intel.quickpath.mem_redundant@CHIPDIMM;
591
592event error.cpu.intel.quickpath.mem_redundant@CHIPDIMM/rank;
593
594prop fault.cpu.intel.quickpath.mem_redundant@CHIPDIMM (1)->
595    error.cpu.intel.quickpath.mem_redundant@CHIPDIMM/rank<>;
596prop error.cpu.intel.quickpath.mem_redundant@CHIPDIMM/rank
597    { CONTAINS_RANK } (1)->
598    ereport.cpu.intel.quickpath.mem_redundant@
599    chip/memory-controller;
600
601#define	STATUS_UC	(payloadprop("error_uncorrected") == 1)
602event ereport.cpu.intel.quickpath.interconnect@chip
603    {within(1s)};
604event upset.cpu.intel.quickpath.interconnect@chip;
605/* Diagnose corrected events to upsets */
606prop upset.cpu.intel.quickpath.interconnect@chip
607    { !STATUS_UC } (1)->
608    ereport.cpu.intel.quickpath.interconnect@chip;
609
610engine serd.cpu.intel.quickpath.interconnect@chip,
611	N=3, T=72h;
612event fault.cpu.intel.quickpath.interconnect@chip,
613    engine=serd.cpu.intel.quickpath.interconnect@chip;
614
615/* Diagnose uncorrected events to faults */
616prop fault.cpu.intel.quickpath.interconnect@chip
617    { STATUS_UC } (0)->
618    ereport.cpu.intel.quickpath.interconnect@chip;
619
620
621/*
622 * Nehalem EX specific rules
623 */
624/* MBox errors */
625#define EX_MEM_EVENT(leafclass, t) \
626	event ereport.cpu.intel.quickpath.leafclass@ \
627        chip/memory-controller { within(t) }, discard_if_config_unknown=1
628
629EX_MEM_EVENT(mem_lnktrns, 1s);
630EX_MEM_EVENT(mem_lnkpers, 1s);
631EX_MEM_EVENT(mem_sbfbdlinkerr, 1s);
632EX_MEM_EVENT(mem_nbfbdlnkerr, 1s);
633EX_MEM_EVENT(mem_lnkcrcvld, 1s);
634
635engine serd.cpu.intel.quickpath.mem_link_ce@chip/memory-controller,
636      N=500, T=1week;
637event fault.cpu.intel.quickpath.mem_link_ce@chip/memory-controller,
638      engine=serd.cpu.intel.quickpath.mem_link_ce@chip/memory-controller,
639      retire=0, response=0;
640
641prop fault.cpu.intel.quickpath.mem_link_ce@chip/memory-controller ->
642    ereport.cpu.intel.quickpath.mem_lnktrns@chip/memory-controller,
643    ereport.cpu.intel.quickpath.mem_lnkpers@chip/memory-controller,
644    ereport.cpu.intel.quickpath.mem_sbfbdlinkerr@chip/memory-controller,
645    ereport.cpu.intel.quickpath.mem_nbfbdlnkerr@chip/memory-controller,
646    ereport.cpu.intel.quickpath.mem_lnkcrcvld@chip/memory-controller;
647
648EX_MEM_EVENT(mem_lnkuncorr_uc, 1s);
649EX_MEM_EVENT(mem_lnkpers_uc, 1s);
650EX_MEM_EVENT(mem_sbfbdlinkerr_uc, 1s);
651EX_MEM_EVENT(mem_nbfbdlnkerr_uc, 1s);
652EX_MEM_EVENT(mem_lnkcrcvld_uc, 1s);
653
654event fault.cpu.intel.quickpath.mem_link_ue@chip/memory-controller,
655      retire=0;
656
657prop fault.cpu.intel.quickpath.mem_link_ue@chip/memory-controller ->
658    ereport.cpu.intel.quickpath.mem_lnkuncorr_uc@chip/memory-controller,
659    ereport.cpu.intel.quickpath.mem_lnkpers_uc@chip/memory-controller,
660    ereport.cpu.intel.quickpath.mem_sbfbdlinkerr_uc@chip/memory-controller,
661    ereport.cpu.intel.quickpath.mem_nbfbdlnkerr_uc@chip/memory-controller,
662    ereport.cpu.intel.quickpath.mem_lnkcrcvld_uc@chip/memory-controller;
663
664EX_MEM_EVENT(mem_ptrl_fsm_err, 1s);
665EX_MEM_EVENT(mem_errflw_fsm_fail, 1s);
666EX_MEM_EVENT(mem_vberr, 1s);
667
668engine serd.cpu.intel.quickpath.mem_controller_ce@chip/memory-controller,
669      N=500, T=1week;
670event fault.cpu.intel.quickpath.mem_controller_ce@chip/memory-controller,
671      engine=serd.cpu.intel.quickpath.mem_controller_ce@chip/memory-controller,
672      retire=0, response=0;
673
674prop fault.cpu.intel.quickpath.mem_controller_ce@chip/memory-controller ->
675    ereport.cpu.intel.quickpath.mem_ptrl_fsm_err@chip/memory-controller,
676    ereport.cpu.intel.quickpath.mem_errflw_fsm_fail@chip/memory-controller,
677    ereport.cpu.intel.quickpath.mem_vberr@chip/memory-controller;
678
679EX_MEM_EVENT(mem_ptrl_fsm_err_uc, 1s);
680EX_MEM_EVENT(mem_errflw_fsm_fail_uc, 1s);
681EX_MEM_EVENT(mem_mcpar_fsmerr_uc, 1s);
682EX_MEM_EVENT(mem_vberr_uc, 1s);
683EX_MEM_EVENT(mem_fberr_uc, 1s);
684
685event fault.cpu.intel.quickpath.mem_controller_ue@chip/memory-controller,
686      retire=0;
687
688prop fault.cpu.intel.quickpath.mem_controller_ue@chip/memory-controller ->
689    ereport.cpu.intel.quickpath.mem_ptrl_fsm_err_uc@chip/memory-controller,
690    ereport.cpu.intel.quickpath.mem_errflw_fsm_fail_uc@chip/memory-controller,
691    ereport.cpu.intel.quickpath.mem_mcpar_fsmerr_uc@chip/memory-controller,
692    ereport.cpu.intel.quickpath.mem_vberr_uc@chip/memory-controller,
693    ereport.cpu.intel.quickpath.mem_fberr_uc@chip/memory-controller;
694
695EX_MEM_EVENT(mem_scrubbing_uc, 1s);
696event fault.cpu.intel.quickpath.mem_scrubbing@
697    chip/memory-controller/dram-channel/dimm/rank,
698    response=0;
699
700prop fault.cpu.intel.quickpath.mem_scrubbing@
701    chip/memory-controller/dram-channel/dimm/rank[rank_num]
702    { payloadprop_defined("rank") && rank_num == payloadprop("rank") &&
703      (payloadprop_defined("physaddr") || payloadprop_defined("offset")) &&
704      SET_ADDR && SET_OFFSET } (1)->
705    ereport.cpu.intel.quickpath.mem_scrubbing_uc@chip/memory-controller;
706
707EX_MEM_EVENT(mem_ecc_uc, 12s);
708EX_MEM_EVENT(mem_even_parity_uc, 1s);
709
710EX_MEM_EVENT(mem_ecc, 12s);
711EX_MEM_EVENT(mem_even_parity, 1s);
712
713event error.memory.intel.ex_dimm_ce@
714    chip/memory-controller/dram-channel/dimm/rank;
715
716prop fault.memory.intel.page_ue@
717    chip/memory-controller/dram-channel/dimm/rank[rank_num]
718    { payloadprop_defined("rank") && rank_num == payloadprop("rank") &&
719      (payloadprop_defined("physaddr") || payloadprop_defined("offset")) &&
720      SET_ADDR && SET_OFFSET } (0)->
721    ereport.cpu.intel.quickpath.mem_ecc_uc@chip/memory-controller,
722    ereport.cpu.intel.quickpath.mem_even_parity_uc@chip/memory-controller;
723
724prop fault.memory.intel.page_ce@
725    chip/memory-controller/dram-channel/dimm/rank[rank_num]
726    { payloadprop_defined("rank") && rank_num == payloadprop("rank") &&
727      (payloadprop_defined("physaddr") || payloadprop_defined("offset")) &&
728      SET_ADDR && SET_OFFSET } (0)->
729    ereport.cpu.intel.quickpath.mem_ecc@chip/memory-controller,
730    ereport.cpu.intel.quickpath.mem_even_parity@chip/memory-controller;
731
732prop error.memory.intel.dimm_ue_ex@
733    chip/memory-controller/dram-channel/dimm/rank[rank_num]
734    { payloadprop_defined("rank") && rank_num == payloadprop("rank") } (1)->
735    ereport.cpu.intel.quickpath.mem_ecc_uc@chip/memory-controller,
736    ereport.cpu.intel.quickpath.mem_even_parity_uc@chip/memory-controller;
737
738prop fault.memory.intel.dimm_ce@
739    chip/memory-controller/dram-channel/dimm
740    { !confprop_defined(chip/memory-controller/dram-channel/dimm,
741    "dimm-size") && setserdn(10) & setserdt(1week) } (0)->
742    error.memory.intel.ex_dimm_ce@
743     chip/memory-controller/dram-channel/dimm/rank;
744prop error.memory.intel.ex_dimm_ce@
745    chip/memory-controller/dram-channel/dimm/rank[rank_num]
746    { payloadprop_defined("rank") && rank_num == payloadprop("rank") &&
747      !confprop_defined(chip/memory-controller/dram-channel/dimm,
748    "dimm-size") &&
749    count(STAT_CPU_MEM_CE_PGFLTS) > 512 } (1)->
750    ereport.cpu.intel.quickpath.mem_ecc@chip/memory-controller,
751    ereport.cpu.intel.quickpath.mem_even_parity@chip/memory-controller;
752
753#define	EX_CPU_MEM_DIMM_CE(dimm_size, n, t, fault_rate) \
754	prop fault.memory.intel.dimm_ce@ \
755	    chip/memory-controller/dram-channel/dimm { \
756	    confprop(chip/memory-controller/dram-channel/dimm, \
757	    "dimm-size") == dimm_size && \
758	    setserdn(n) & setserdt(t) } (0)-> \
759	    error.memory.intel.ex_dimm_ce@ \
760	    chip/memory-controller/dram-channel/dimm/rank; \
761	prop error.memory.intel.ex_dimm_ce@ \
762	    chip/memory-controller/dram-channel/dimm/rank[rank_num] { \
763            payloadprop_defined("rank") && rank_num == payloadprop("rank") && \
764	    confprop(chip/memory-controller/dram-channel/dimm, \
765	    "dimm-size") == dimm_size && \
766	    count(STAT_CPU_MEM_CE_PGFLTS) > fault_rate } (1)-> \
767            ereport.cpu.intel.quickpath.mem_ecc@chip/memory-controller, \
768            ereport.cpu.intel.quickpath.mem_even_parity@chip/memory-controller;
769
770EX_CPU_MEM_DIMM_CE("16G", 16, 1week, 2000)
771EX_CPU_MEM_DIMM_CE("8G", 8, 1week, 2000)
772EX_CPU_MEM_DIMM_CE("4G", 4, 1week, 1500)
773EX_CPU_MEM_DIMM_CE("2G", 4, 2week, 1000)
774EX_CPU_MEM_DIMM_CE("1G", 4, 4week, 500)
775
776event upset.memory.intel.discard@chip/memory-controller{within(1s)};
777
778prop upset.memory.intel.discard@chip/memory-controller (0)->
779    ereport.cpu.intel.quickpath.mem_scrubbing_uc@chip/memory-controller,
780    ereport.cpu.intel.quickpath.mem_ecc_uc@chip/memory-controller,
781    ereport.cpu.intel.quickpath.mem_even_parity_uc@chip/memory-controller,
782    ereport.cpu.intel.quickpath.mem_ecc@chip/memory-controller,
783    ereport.cpu.intel.quickpath.mem_even_parity@chip/memory-controller;
784
785EX_MEM_EVENT(mem_failover_mir, 1s);
786event fault.cpu.intel.quickpath.mem_failover_mir@chip/memory-controller,
787      retire=0;
788
789prop fault.cpu.intel.quickpath.mem_failover_mir@chip/memory-controller ->
790    ereport.cpu.intel.quickpath.mem_failover_mir@chip/memory-controller;
791
792/*
793 * RBox errors
794 */
795#define EX_EVENT(leafclass, t) \
796	event ereport.cpu.intel.quickpath.leafclass@chip { within(t) }
797
798engine serd.cpu.intel.quickpath.bus_interconnect@chip,
799	N=3, T=72h;
800event fault.cpu.intel.quickpath.bus_interconnect@chip,
801    engine=serd.cpu.intel.quickpath.bus_interconnect@chip,
802    retire=0;
803
804EX_EVENT(bus_retry_abort, 1s);
805EX_EVENT(bus_link_init_ce, 1s);
806event upset.cpu.intel.quickpath.discard@chip;
807
808prop upset.cpu.intel.quickpath.discard@chip (0)->
809    ereport.cpu.intel.quickpath.bus_retry_abort@chip,
810    ereport.cpu.intel.quickpath.bus_link_init_ce@chip;
811
812EX_EVENT(bus_unknown, 1s);
813EX_EVENT(bus_single_ecc, 1s);
814EX_EVENT(bus_crc_flit, 1s);
815
816prop fault.cpu.intel.quickpath.bus_interconnect@chip (0)->
817    ereport.cpu.intel.quickpath.bus_unknown@chip,
818    ereport.cpu.intel.quickpath.bus_single_ecc@chip,
819    ereport.cpu.intel.quickpath.bus_crc_flit@chip;
820
821EX_EVENT(bus_unknown_external, 1s);
822EX_EVENT(bus_crc_flit_external, 1s);
823prop upset.cpu.intel.quickpath.discard@chip (0)->
824    ereport.cpu.intel.quickpath.bus_unknown_external@chip,
825    ereport.cpu.intel.quickpath.bus_crc_flit_external@chip;
826
827EX_EVENT(bus_unknown_uc, 1s);
828EX_EVENT(bus_opr_poison_err, 1s);
829EX_EVENT(bus_eot_parity, 1s);
830EX_EVENT(bus_rta_parity, 1s);
831EX_EVENT(bus_bad_sbu_route, 1s);
832EX_EVENT(bus_bad_msg, 1s);
833EX_EVENT(bus_bad_vn_credit, 1s);
834EX_EVENT(bus_hdr_double_ecc, 1s);
835EX_EVENT(bus_link_retry_err, 1s);
836
837prop fault.cpu.intel.quickpath.bus_interconnect@chip
838    { setserdincrement(4) } (0)->
839    ereport.cpu.intel.quickpath.bus_unknown_uc@chip,
840    ereport.cpu.intel.quickpath.bus_opr_poison_err@chip,
841    ereport.cpu.intel.quickpath.bus_eot_parity@chip,
842    ereport.cpu.intel.quickpath.bus_rta_parity@chip,
843    ereport.cpu.intel.quickpath.bus_bad_sbu_route@chip,
844    ereport.cpu.intel.quickpath.bus_bad_msg@chip,
845    ereport.cpu.intel.quickpath.bus_bad_vn_credit@chip,
846    ereport.cpu.intel.quickpath.bus_hdr_double_ecc@chip,
847    ereport.cpu.intel.quickpath.bus_link_retry_err@chip;
848
849EX_EVENT(bus_unknown_uc_external, 1s);
850EX_EVENT(bus_opr_poison_err_external, 1s);
851EX_EVENT(bus_eot_parity_external, 1s);
852EX_EVENT(bus_rta_parity_external, 1s);
853EX_EVENT(bus_bad_sbu_route_external, 1s);
854EX_EVENT(bus_bad_msg_external, 1s);
855EX_EVENT(bus_bad_vn_credit_external, 1s);
856EX_EVENT(bus_hdr_double_ecc_external, 1s);
857EX_EVENT(bus_link_retry_err_external, 1s);
858
859prop upset.cpu.intel.quickpath.discard@chip (0)->
860    ereport.cpu.intel.quickpath.bus_unknown_uc_external@chip,
861    ereport.cpu.intel.quickpath.bus_opr_poison_err_external@chip,
862    ereport.cpu.intel.quickpath.bus_eot_parity_external@chip,
863    ereport.cpu.intel.quickpath.bus_rta_parity_external@chip,
864    ereport.cpu.intel.quickpath.bus_bad_sbu_route_external@chip,
865    ereport.cpu.intel.quickpath.bus_bad_msg_external@chip,
866    ereport.cpu.intel.quickpath.bus_bad_vn_credit_external@chip,
867    ereport.cpu.intel.quickpath.bus_hdr_double_ecc_external@chip,
868    ereport.cpu.intel.quickpath.bus_link_retry_err_external@chip;
869
870/*
871 * CBox errors
872 */
873EX_EVENT(llc_ewb_uc, 1s);
874event fault.cpu.intel.quickpath.llc_ewb@chip,
875      retire=0, response=0;
876
877prop fault.cpu.intel.quickpath.llc_ewb@chip
878    { (payloadprop_defined("physaddr") || payloadprop_defined("offset")) &&
879    SET_ADDR && SET_OFFSET } (1)->
880    ereport.cpu.intel.quickpath.llc_ewb_uc@chip;
881
882prop upset.cpu.intel.quickpath.discard@chip (0)->
883    ereport.cpu.intel.quickpath.llc_ewb_uc@chip;
884
885/*
886 * SBox errors
887 */
888EX_EVENT(system_cache_uc, 1s);
889event fault.cpu.intel.quickpath.system_cache@chip,
890      retire=0, response=0;
891prop fault.cpu.intel.quickpath.system_cache@chip ->
892    ereport.cpu.intel.quickpath.system_cache_uc@chip;
893
894/*
895 * BBox errors
896 */
897EX_EVENT(home_agent_uc, 1s);
898event fault.cpu.intel.quickpath.home_agent@chip,
899      retire=0, response=0;
900prop fault.cpu.intel.quickpath.home_agent@chip ->
901    ereport.cpu.intel.quickpath.home_agent_uc@chip;
902
903/*
904 * UBox errors
905 */
906EX_EVENT(sys_cfg_cfa_ecc, 1s);
907EX_EVENT(sys_cfg_uc, 1s);
908
909engine serd.cpu.intel.quickpath.sys_cfg@chip,
910      N=2, T=72h;
911event fault.cpu.intel.quickpath.sys_cfg@chip,
912      engine=serd.cpu.intel.quickpath.sys_cfg@chip,
913      retire=0, response=0;
914
915prop fault.cpu.intel.quickpath.sys_cfg@chip (0)->
916    ereport.cpu.intel.quickpath.sys_cfg_cfa_ecc@chip;
917
918prop fault.cpu.intel.quickpath.sys_cfg@chip
919    { setserdincrement(3) } (0)->
920    ereport.cpu.intel.quickpath.sys_cfg_uc@chip;
921
922/*
923 * Handling poison errors
924 */
925engine stat.has_poison@motherboard;
926event fault.cpu.intel.has_poison@motherboard,
927      count=stat.has_poison@motherboard[0],
928      message=0, retire=0, response=0;
929engine stat.discard_fatal@motherboard;
930event fault.cpu.intel.discard_fatal@motherboard,
931      count=stat.discard_fatal@motherboard[0],
932      message=0, retire=0, response=0;
933
934prop fault.cpu.intel.has_poison@motherboard
935    { payloadprop_defined("poison") && 1 == payloadprop("poison") } (1)->
936    ereport.cpu.intel.quickpath.mem_scrubbing_uc@chip<>/memory-controller<>,
937    ereport.cpu.intel.quickpath.llc_ewb_uc@chip<>,
938    ereport.cpu.intel.quickpath.system_cache_uc@chip<>,
939    ereport.cpu.intel.quickpath.bus_opr_poison_err@chip<>,
940    ereport.cpu.intel.quickpath.bus_opr_poison_err_external@chip<>;
941
942prop fault.cpu.intel.discard_fatal@motherboard
943    { count(stat.has_poison@motherboard[0]) > count(stat.discard_fatal@motherboard[0]) &&
944      payloadprop_defined("bank_number") && 5 == payloadprop("bank_number") &&
945      payloadprop_defined("processor_context_corrupt") &&
946      1 == payloadprop("processor_context_corrupt") } (0)->
947    ereport.cpu.intel.internal_unclassified@chip<>/core<>/strand<> {within(10s)};
948
949prop fault.cpu.intel.internal@chip/core/strand
950    { (count(stat.has_poison@motherboard[0]) <= count(stat.discard_fatal@motherboard[0]) ||
951      !payloadprop_defined("bank_number") || 5 != payloadprop("bank_number") ||
952      !payloadprop_defined("processor_context_corrupt") ||
953      0 == payloadprop("processor_context_corrupt")) &&
954      (payloadprop("error_uncorrected") == 1 ? setserdincrement(4) : 1) } (0)->
955    ereport.cpu.intel.internal_unclassified@chip/core/strand;
956