1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2014 Leon Dang <ldang@nahannisys.com> 5 * Copyright 2018 Joyent, Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 /* 30 XHCI options: 31 -s <n>,xhci,{devices} 32 33 devices: 34 tablet USB tablet mouse 35 */ 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include <sys/param.h> 40 #include <sys/uio.h> 41 #include <sys/types.h> 42 #include <sys/queue.h> 43 44 #include <stdio.h> 45 #include <stdlib.h> 46 #include <stdint.h> 47 #include <string.h> 48 #include <errno.h> 49 #include <pthread.h> 50 #include <unistd.h> 51 52 #include <dev/usb/usbdi.h> 53 #include <dev/usb/usb.h> 54 #include <dev/usb/usb_freebsd.h> 55 #include <xhcireg.h> 56 57 #include "bhyverun.h" 58 #include "config.h" 59 #include "debug.h" 60 #include "pci_emul.h" 61 #include "pci_xhci.h" 62 #include "usb_emul.h" 63 64 65 static int xhci_debug = 0; 66 #define DPRINTF(params) if (xhci_debug) PRINTLN params 67 #define WPRINTF(params) PRINTLN params 68 69 70 #define XHCI_NAME "xhci" 71 #define XHCI_MAX_DEVS 8 /* 4 USB3 + 4 USB2 devs */ 72 73 #define XHCI_MAX_SLOTS 64 /* min allowed by Windows drivers */ 74 75 /* 76 * XHCI data structures can be up to 64k, but limit paddr_guest2host mapping 77 * to 4k to avoid going over the guest physical memory barrier. 78 */ 79 #define XHCI_PADDR_SZ 4096 /* paddr_guest2host max size */ 80 81 #define XHCI_ERST_MAX 0 /* max 2^entries event ring seg tbl */ 82 83 #define XHCI_CAPLEN (4*8) /* offset of op register space */ 84 #define XHCI_HCCPRAMS2 0x1C /* offset of HCCPARAMS2 register */ 85 #define XHCI_PORTREGS_START 0x400 86 #define XHCI_DOORBELL_MAX 256 87 88 #define XHCI_STREAMS_MAX 1 /* 4-15 in XHCI spec */ 89 90 /* caplength and hci-version registers */ 91 #define XHCI_SET_CAPLEN(x) ((x) & 0xFF) 92 #define XHCI_SET_HCIVERSION(x) (((x) & 0xFFFF) << 16) 93 #define XHCI_GET_HCIVERSION(x) (((x) >> 16) & 0xFFFF) 94 95 /* hcsparams1 register */ 96 #define XHCI_SET_HCSP1_MAXSLOTS(x) ((x) & 0xFF) 97 #define XHCI_SET_HCSP1_MAXINTR(x) (((x) & 0x7FF) << 8) 98 #define XHCI_SET_HCSP1_MAXPORTS(x) (((x) & 0xFF) << 24) 99 100 /* hcsparams2 register */ 101 #define XHCI_SET_HCSP2_IST(x) ((x) & 0x0F) 102 #define XHCI_SET_HCSP2_ERSTMAX(x) (((x) & 0x0F) << 4) 103 #define XHCI_SET_HCSP2_MAXSCRATCH_HI(x) (((x) & 0x1F) << 21) 104 #define XHCI_SET_HCSP2_MAXSCRATCH_LO(x) (((x) & 0x1F) << 27) 105 106 /* hcsparams3 register */ 107 #define XHCI_SET_HCSP3_U1EXITLATENCY(x) ((x) & 0xFF) 108 #define XHCI_SET_HCSP3_U2EXITLATENCY(x) (((x) & 0xFFFF) << 16) 109 110 /* hccparams1 register */ 111 #define XHCI_SET_HCCP1_AC64(x) ((x) & 0x01) 112 #define XHCI_SET_HCCP1_BNC(x) (((x) & 0x01) << 1) 113 #define XHCI_SET_HCCP1_CSZ(x) (((x) & 0x01) << 2) 114 #define XHCI_SET_HCCP1_PPC(x) (((x) & 0x01) << 3) 115 #define XHCI_SET_HCCP1_PIND(x) (((x) & 0x01) << 4) 116 #define XHCI_SET_HCCP1_LHRC(x) (((x) & 0x01) << 5) 117 #define XHCI_SET_HCCP1_LTC(x) (((x) & 0x01) << 6) 118 #define XHCI_SET_HCCP1_NSS(x) (((x) & 0x01) << 7) 119 #define XHCI_SET_HCCP1_PAE(x) (((x) & 0x01) << 8) 120 #define XHCI_SET_HCCP1_SPC(x) (((x) & 0x01) << 9) 121 #define XHCI_SET_HCCP1_SEC(x) (((x) & 0x01) << 10) 122 #define XHCI_SET_HCCP1_CFC(x) (((x) & 0x01) << 11) 123 #define XHCI_SET_HCCP1_MAXPSA(x) (((x) & 0x0F) << 12) 124 #define XHCI_SET_HCCP1_XECP(x) (((x) & 0xFFFF) << 16) 125 126 /* hccparams2 register */ 127 #define XHCI_SET_HCCP2_U3C(x) ((x) & 0x01) 128 #define XHCI_SET_HCCP2_CMC(x) (((x) & 0x01) << 1) 129 #define XHCI_SET_HCCP2_FSC(x) (((x) & 0x01) << 2) 130 #define XHCI_SET_HCCP2_CTC(x) (((x) & 0x01) << 3) 131 #define XHCI_SET_HCCP2_LEC(x) (((x) & 0x01) << 4) 132 #define XHCI_SET_HCCP2_CIC(x) (((x) & 0x01) << 5) 133 134 /* other registers */ 135 #define XHCI_SET_DOORBELL(x) ((x) & ~0x03) 136 #define XHCI_SET_RTSOFFSET(x) ((x) & ~0x0F) 137 138 /* register masks */ 139 #define XHCI_PS_PLS_MASK (0xF << 5) /* port link state */ 140 #define XHCI_PS_SPEED_MASK (0xF << 10) /* port speed */ 141 #define XHCI_PS_PIC_MASK (0x3 << 14) /* port indicator */ 142 143 /* port register set */ 144 #define XHCI_PORTREGS_BASE 0x400 /* base offset */ 145 #define XHCI_PORTREGS_PORT0 0x3F0 146 #define XHCI_PORTREGS_SETSZ 0x10 /* size of a set */ 147 148 #define MASK_64_HI(x) ((x) & ~0xFFFFFFFFULL) 149 #define MASK_64_LO(x) ((x) & 0xFFFFFFFFULL) 150 151 #define FIELD_REPLACE(a,b,m,s) (((a) & ~((m) << (s))) | \ 152 (((b) & (m)) << (s))) 153 #define FIELD_COPY(a,b,m,s) (((a) & ~((m) << (s))) | \ 154 (((b) & ((m) << (s))))) 155 156 struct pci_xhci_trb_ring { 157 uint64_t ringaddr; /* current dequeue guest address */ 158 uint32_t ccs; /* consumer cycle state */ 159 }; 160 161 /* device endpoint transfer/stream rings */ 162 struct pci_xhci_dev_ep { 163 union { 164 struct xhci_trb *_epu_tr; 165 struct xhci_stream_ctx *_epu_sctx; 166 } _ep_trbsctx; 167 #define ep_tr _ep_trbsctx._epu_tr 168 #define ep_sctx _ep_trbsctx._epu_sctx 169 170 union { 171 struct pci_xhci_trb_ring _epu_trb; 172 struct pci_xhci_trb_ring *_epu_sctx_trbs; 173 } _ep_trb_rings; 174 #define ep_ringaddr _ep_trb_rings._epu_trb.ringaddr 175 #define ep_ccs _ep_trb_rings._epu_trb.ccs 176 #define ep_sctx_trbs _ep_trb_rings._epu_sctx_trbs 177 178 struct usb_data_xfer *ep_xfer; /* transfer chain */ 179 }; 180 181 /* device context base address array: maps slot->device context */ 182 struct xhci_dcbaa { 183 uint64_t dcba[USB_MAX_DEVICES+1]; /* xhci_dev_ctx ptrs */ 184 }; 185 186 /* port status registers */ 187 struct pci_xhci_portregs { 188 uint32_t portsc; /* port status and control */ 189 uint32_t portpmsc; /* port pwr mgmt status & control */ 190 uint32_t portli; /* port link info */ 191 uint32_t porthlpmc; /* port hardware LPM control */ 192 } __packed; 193 #define XHCI_PS_SPEED_SET(x) (((x) & 0xF) << 10) 194 195 /* xHC operational registers */ 196 struct pci_xhci_opregs { 197 uint32_t usbcmd; /* usb command */ 198 uint32_t usbsts; /* usb status */ 199 uint32_t pgsz; /* page size */ 200 uint32_t dnctrl; /* device notification control */ 201 uint64_t crcr; /* command ring control */ 202 uint64_t dcbaap; /* device ctx base addr array ptr */ 203 uint32_t config; /* configure */ 204 205 /* guest mapped addresses: */ 206 struct xhci_trb *cr_p; /* crcr dequeue */ 207 struct xhci_dcbaa *dcbaa_p; /* dev ctx array ptr */ 208 }; 209 210 /* xHC runtime registers */ 211 struct pci_xhci_rtsregs { 212 uint32_t mfindex; /* microframe index */ 213 struct { /* interrupter register set */ 214 uint32_t iman; /* interrupter management */ 215 uint32_t imod; /* interrupter moderation */ 216 uint32_t erstsz; /* event ring segment table size */ 217 uint32_t rsvd; 218 uint64_t erstba; /* event ring seg-tbl base addr */ 219 uint64_t erdp; /* event ring dequeue ptr */ 220 } intrreg __packed; 221 222 /* guest mapped addresses */ 223 struct xhci_event_ring_seg *erstba_p; 224 struct xhci_trb *erst_p; /* event ring segment tbl */ 225 int er_deq_seg; /* event ring dequeue segment */ 226 int er_enq_idx; /* event ring enqueue index - xHCI */ 227 int er_enq_seg; /* event ring enqueue segment */ 228 uint32_t er_events_cnt; /* number of events in ER */ 229 uint32_t event_pcs; /* producer cycle state flag */ 230 }; 231 232 233 struct pci_xhci_softc; 234 235 236 /* 237 * USB device emulation container. 238 * This is referenced from usb_hci->hci_sc; 1 pci_xhci_dev_emu for each 239 * emulated device instance. 240 */ 241 struct pci_xhci_dev_emu { 242 struct pci_xhci_softc *xsc; 243 244 /* XHCI contexts */ 245 struct xhci_dev_ctx *dev_ctx; 246 struct pci_xhci_dev_ep eps[XHCI_MAX_ENDPOINTS]; 247 int dev_slotstate; 248 249 struct usb_devemu *dev_ue; /* USB emulated dev */ 250 void *dev_sc; /* device's softc */ 251 252 struct usb_hci hci; 253 }; 254 255 struct pci_xhci_softc { 256 struct pci_devinst *xsc_pi; 257 258 pthread_mutex_t mtx; 259 260 uint32_t caplength; /* caplen & hciversion */ 261 uint32_t hcsparams1; /* structural parameters 1 */ 262 uint32_t hcsparams2; /* structural parameters 2 */ 263 uint32_t hcsparams3; /* structural parameters 3 */ 264 uint32_t hccparams1; /* capability parameters 1 */ 265 uint32_t dboff; /* doorbell offset */ 266 uint32_t rtsoff; /* runtime register space offset */ 267 uint32_t hccparams2; /* capability parameters 2 */ 268 269 uint32_t regsend; /* end of configuration registers */ 270 271 struct pci_xhci_opregs opregs; 272 struct pci_xhci_rtsregs rtsregs; 273 274 struct pci_xhci_portregs *portregs; 275 struct pci_xhci_dev_emu **devices; /* XHCI[port] = device */ 276 struct pci_xhci_dev_emu **slots; /* slots assigned from 1 */ 277 278 int usb2_port_start; 279 int usb3_port_start; 280 }; 281 282 283 /* portregs and devices arrays are set up to start from idx=1 */ 284 #define XHCI_PORTREG_PTR(x,n) &(x)->portregs[(n)] 285 #define XHCI_DEVINST_PTR(x,n) (x)->devices[(n)] 286 #define XHCI_SLOTDEV_PTR(x,n) (x)->slots[(n)] 287 288 #define XHCI_HALTED(sc) ((sc)->opregs.usbsts & XHCI_STS_HCH) 289 290 #define XHCI_GADDR(sc,a) paddr_guest2host((sc)->xsc_pi->pi_vmctx, \ 291 (a), \ 292 XHCI_PADDR_SZ - ((a) & (XHCI_PADDR_SZ-1))) 293 294 static int xhci_in_use; 295 296 /* map USB errors to XHCI */ 297 static const int xhci_usb_errors[USB_ERR_MAX] = { 298 [USB_ERR_NORMAL_COMPLETION] = XHCI_TRB_ERROR_SUCCESS, 299 [USB_ERR_PENDING_REQUESTS] = XHCI_TRB_ERROR_RESOURCE, 300 [USB_ERR_NOT_STARTED] = XHCI_TRB_ERROR_ENDP_NOT_ON, 301 [USB_ERR_INVAL] = XHCI_TRB_ERROR_INVALID, 302 [USB_ERR_NOMEM] = XHCI_TRB_ERROR_RESOURCE, 303 [USB_ERR_CANCELLED] = XHCI_TRB_ERROR_STOPPED, 304 [USB_ERR_BAD_ADDRESS] = XHCI_TRB_ERROR_PARAMETER, 305 [USB_ERR_BAD_BUFSIZE] = XHCI_TRB_ERROR_PARAMETER, 306 [USB_ERR_BAD_FLAG] = XHCI_TRB_ERROR_PARAMETER, 307 [USB_ERR_NO_CALLBACK] = XHCI_TRB_ERROR_STALL, 308 [USB_ERR_IN_USE] = XHCI_TRB_ERROR_RESOURCE, 309 [USB_ERR_NO_ADDR] = XHCI_TRB_ERROR_RESOURCE, 310 [USB_ERR_NO_PIPE] = XHCI_TRB_ERROR_RESOURCE, 311 [USB_ERR_ZERO_NFRAMES] = XHCI_TRB_ERROR_UNDEFINED, 312 [USB_ERR_ZERO_MAXP] = XHCI_TRB_ERROR_UNDEFINED, 313 [USB_ERR_SET_ADDR_FAILED] = XHCI_TRB_ERROR_RESOURCE, 314 [USB_ERR_NO_POWER] = XHCI_TRB_ERROR_ENDP_NOT_ON, 315 [USB_ERR_TOO_DEEP] = XHCI_TRB_ERROR_RESOURCE, 316 [USB_ERR_IOERROR] = XHCI_TRB_ERROR_TRB, 317 [USB_ERR_NOT_CONFIGURED] = XHCI_TRB_ERROR_ENDP_NOT_ON, 318 [USB_ERR_TIMEOUT] = XHCI_TRB_ERROR_CMD_ABORTED, 319 [USB_ERR_SHORT_XFER] = XHCI_TRB_ERROR_SHORT_PKT, 320 [USB_ERR_STALLED] = XHCI_TRB_ERROR_STALL, 321 [USB_ERR_INTERRUPTED] = XHCI_TRB_ERROR_CMD_ABORTED, 322 [USB_ERR_DMA_LOAD_FAILED] = XHCI_TRB_ERROR_DATA_BUF, 323 [USB_ERR_BAD_CONTEXT] = XHCI_TRB_ERROR_TRB, 324 [USB_ERR_NO_ROOT_HUB] = XHCI_TRB_ERROR_UNDEFINED, 325 [USB_ERR_NO_INTR_THREAD] = XHCI_TRB_ERROR_UNDEFINED, 326 [USB_ERR_NOT_LOCKED] = XHCI_TRB_ERROR_UNDEFINED, 327 }; 328 #define USB_TO_XHCI_ERR(e) ((e) < USB_ERR_MAX ? xhci_usb_errors[(e)] : \ 329 XHCI_TRB_ERROR_INVALID) 330 331 static int pci_xhci_insert_event(struct pci_xhci_softc *sc, 332 struct xhci_trb *evtrb, int do_intr); 333 static void pci_xhci_dump_trb(struct xhci_trb *trb); 334 static void pci_xhci_assert_interrupt(struct pci_xhci_softc *sc); 335 static void pci_xhci_reset_slot(struct pci_xhci_softc *sc, int slot); 336 static void pci_xhci_reset_port(struct pci_xhci_softc *sc, int portn, int warm); 337 static void pci_xhci_update_ep_ring(struct pci_xhci_softc *sc, 338 struct pci_xhci_dev_emu *dev, struct pci_xhci_dev_ep *devep, 339 struct xhci_endp_ctx *ep_ctx, uint32_t streamid, 340 uint64_t ringaddr, int ccs); 341 342 static void 343 pci_xhci_set_evtrb(struct xhci_trb *evtrb, uint64_t port, uint32_t errcode, 344 uint32_t evtype) 345 { 346 evtrb->qwTrb0 = port << 24; 347 evtrb->dwTrb2 = XHCI_TRB_2_ERROR_SET(errcode); 348 evtrb->dwTrb3 = XHCI_TRB_3_TYPE_SET(evtype); 349 } 350 351 352 /* controller reset */ 353 static void 354 pci_xhci_reset(struct pci_xhci_softc *sc) 355 { 356 int i; 357 358 sc->rtsregs.er_enq_idx = 0; 359 sc->rtsregs.er_events_cnt = 0; 360 sc->rtsregs.event_pcs = 1; 361 362 for (i = 1; i <= XHCI_MAX_SLOTS; i++) { 363 pci_xhci_reset_slot(sc, i); 364 } 365 } 366 367 static uint32_t 368 pci_xhci_usbcmd_write(struct pci_xhci_softc *sc, uint32_t cmd) 369 { 370 int do_intr = 0; 371 int i; 372 373 if (cmd & XHCI_CMD_RS) { 374 do_intr = (sc->opregs.usbcmd & XHCI_CMD_RS) == 0; 375 376 sc->opregs.usbcmd |= XHCI_CMD_RS; 377 sc->opregs.usbsts &= ~XHCI_STS_HCH; 378 sc->opregs.usbsts |= XHCI_STS_PCD; 379 380 /* Queue port change event on controller run from stop */ 381 if (do_intr) 382 for (i = 1; i <= XHCI_MAX_DEVS; i++) { 383 struct pci_xhci_dev_emu *dev; 384 struct pci_xhci_portregs *port; 385 struct xhci_trb evtrb; 386 387 if ((dev = XHCI_DEVINST_PTR(sc, i)) == NULL) 388 continue; 389 390 port = XHCI_PORTREG_PTR(sc, i); 391 port->portsc |= XHCI_PS_CSC | XHCI_PS_CCS; 392 port->portsc &= ~XHCI_PS_PLS_MASK; 393 394 /* 395 * XHCI 4.19.3 USB2 RxDetect->Polling, 396 * USB3 Polling->U0 397 */ 398 if (dev->dev_ue->ue_usbver == 2) 399 port->portsc |= 400 XHCI_PS_PLS_SET(UPS_PORT_LS_POLL); 401 else 402 port->portsc |= 403 XHCI_PS_PLS_SET(UPS_PORT_LS_U0); 404 405 pci_xhci_set_evtrb(&evtrb, i, 406 XHCI_TRB_ERROR_SUCCESS, 407 XHCI_TRB_EVENT_PORT_STS_CHANGE); 408 409 if (pci_xhci_insert_event(sc, &evtrb, 0) != 410 XHCI_TRB_ERROR_SUCCESS) 411 break; 412 } 413 } else { 414 sc->opregs.usbcmd &= ~XHCI_CMD_RS; 415 sc->opregs.usbsts |= XHCI_STS_HCH; 416 sc->opregs.usbsts &= ~XHCI_STS_PCD; 417 } 418 419 /* start execution of schedule; stop when set to 0 */ 420 cmd |= sc->opregs.usbcmd & XHCI_CMD_RS; 421 422 if (cmd & XHCI_CMD_HCRST) { 423 /* reset controller */ 424 pci_xhci_reset(sc); 425 cmd &= ~XHCI_CMD_HCRST; 426 } 427 428 cmd &= ~(XHCI_CMD_CSS | XHCI_CMD_CRS); 429 430 if (do_intr) 431 pci_xhci_assert_interrupt(sc); 432 433 return (cmd); 434 } 435 436 static void 437 pci_xhci_portregs_write(struct pci_xhci_softc *sc, uint64_t offset, 438 uint64_t value) 439 { 440 struct xhci_trb evtrb; 441 struct pci_xhci_portregs *p; 442 int port; 443 uint32_t oldpls, newpls; 444 445 if (sc->portregs == NULL) 446 return; 447 448 port = (offset - XHCI_PORTREGS_PORT0) / XHCI_PORTREGS_SETSZ; 449 offset = (offset - XHCI_PORTREGS_PORT0) % XHCI_PORTREGS_SETSZ; 450 451 DPRINTF(("pci_xhci: portregs wr offset 0x%lx, port %u: 0x%lx", 452 offset, port, value)); 453 454 assert(port >= 0); 455 456 if (port > XHCI_MAX_DEVS) { 457 DPRINTF(("pci_xhci: portregs_write port %d > ndevices", 458 port)); 459 return; 460 } 461 462 if (XHCI_DEVINST_PTR(sc, port) == NULL) { 463 DPRINTF(("pci_xhci: portregs_write to unattached port %d", 464 port)); 465 } 466 467 p = XHCI_PORTREG_PTR(sc, port); 468 switch (offset) { 469 case 0: 470 /* port reset or warm reset */ 471 if (value & (XHCI_PS_PR | XHCI_PS_WPR)) { 472 pci_xhci_reset_port(sc, port, value & XHCI_PS_WPR); 473 break; 474 } 475 476 if ((p->portsc & XHCI_PS_PP) == 0) { 477 WPRINTF(("pci_xhci: portregs_write to unpowered " 478 "port %d", port)); 479 break; 480 } 481 482 /* Port status and control register */ 483 oldpls = XHCI_PS_PLS_GET(p->portsc); 484 newpls = XHCI_PS_PLS_GET(value); 485 486 p->portsc &= XHCI_PS_PED | XHCI_PS_PLS_MASK | 487 XHCI_PS_SPEED_MASK | XHCI_PS_PIC_MASK; 488 489 if (XHCI_DEVINST_PTR(sc, port)) 490 p->portsc |= XHCI_PS_CCS; 491 492 p->portsc |= (value & 493 ~(XHCI_PS_OCA | 494 XHCI_PS_PR | 495 XHCI_PS_PED | 496 XHCI_PS_PLS_MASK | /* link state */ 497 XHCI_PS_SPEED_MASK | 498 XHCI_PS_PIC_MASK | /* port indicator */ 499 XHCI_PS_LWS | XHCI_PS_DR | XHCI_PS_WPR)); 500 501 /* clear control bits */ 502 p->portsc &= ~(value & 503 (XHCI_PS_CSC | 504 XHCI_PS_PEC | 505 XHCI_PS_WRC | 506 XHCI_PS_OCC | 507 XHCI_PS_PRC | 508 XHCI_PS_PLC | 509 XHCI_PS_CEC | 510 XHCI_PS_CAS)); 511 512 /* port disable request; for USB3, don't care */ 513 if (value & XHCI_PS_PED) 514 DPRINTF(("Disable port %d request", port)); 515 516 if (!(value & XHCI_PS_LWS)) 517 break; 518 519 DPRINTF(("Port new PLS: %d", newpls)); 520 switch (newpls) { 521 case 0: /* U0 */ 522 case 3: /* U3 */ 523 if (oldpls != newpls) { 524 p->portsc &= ~XHCI_PS_PLS_MASK; 525 p->portsc |= XHCI_PS_PLS_SET(newpls) | 526 XHCI_PS_PLC; 527 528 if (oldpls != 0 && newpls == 0) { 529 pci_xhci_set_evtrb(&evtrb, port, 530 XHCI_TRB_ERROR_SUCCESS, 531 XHCI_TRB_EVENT_PORT_STS_CHANGE); 532 533 pci_xhci_insert_event(sc, &evtrb, 1); 534 } 535 } 536 break; 537 538 default: 539 DPRINTF(("Unhandled change port %d PLS %u", 540 port, newpls)); 541 break; 542 } 543 break; 544 case 4: 545 /* Port power management status and control register */ 546 p->portpmsc = value; 547 break; 548 case 8: 549 /* Port link information register */ 550 DPRINTF(("pci_xhci attempted write to PORTLI, port %d", 551 port)); 552 break; 553 case 12: 554 /* 555 * Port hardware LPM control register. 556 * For USB3, this register is reserved. 557 */ 558 p->porthlpmc = value; 559 break; 560 } 561 } 562 563 struct xhci_dev_ctx * 564 pci_xhci_get_dev_ctx(struct pci_xhci_softc *sc, uint32_t slot) 565 { 566 uint64_t devctx_addr; 567 struct xhci_dev_ctx *devctx; 568 569 assert(slot > 0 && slot <= XHCI_MAX_DEVS); 570 assert(XHCI_SLOTDEV_PTR(sc, slot) != NULL); 571 assert(sc->opregs.dcbaa_p != NULL); 572 573 devctx_addr = sc->opregs.dcbaa_p->dcba[slot]; 574 575 if (devctx_addr == 0) { 576 DPRINTF(("get_dev_ctx devctx_addr == 0")); 577 return (NULL); 578 } 579 580 DPRINTF(("pci_xhci: get dev ctx, slot %u devctx addr %016lx", 581 slot, devctx_addr)); 582 devctx = XHCI_GADDR(sc, devctx_addr & ~0x3FUL); 583 584 return (devctx); 585 } 586 587 struct xhci_trb * 588 pci_xhci_trb_next(struct pci_xhci_softc *sc, struct xhci_trb *curtrb, 589 uint64_t *guestaddr) 590 { 591 struct xhci_trb *next; 592 593 assert(curtrb != NULL); 594 595 if (XHCI_TRB_3_TYPE_GET(curtrb->dwTrb3) == XHCI_TRB_TYPE_LINK) { 596 if (guestaddr) 597 *guestaddr = curtrb->qwTrb0 & ~0xFUL; 598 599 next = XHCI_GADDR(sc, curtrb->qwTrb0 & ~0xFUL); 600 } else { 601 if (guestaddr) 602 *guestaddr += sizeof(struct xhci_trb) & ~0xFUL; 603 604 next = curtrb + 1; 605 } 606 607 return (next); 608 } 609 610 static void 611 pci_xhci_assert_interrupt(struct pci_xhci_softc *sc) 612 { 613 614 sc->rtsregs.intrreg.erdp |= XHCI_ERDP_LO_BUSY; 615 sc->rtsregs.intrreg.iman |= XHCI_IMAN_INTR_PEND; 616 sc->opregs.usbsts |= XHCI_STS_EINT; 617 618 /* only trigger interrupt if permitted */ 619 if ((sc->opregs.usbcmd & XHCI_CMD_INTE) && 620 (sc->rtsregs.intrreg.iman & XHCI_IMAN_INTR_ENA)) { 621 if (pci_msi_enabled(sc->xsc_pi)) 622 pci_generate_msi(sc->xsc_pi, 0); 623 else 624 pci_lintr_assert(sc->xsc_pi); 625 } 626 } 627 628 static void 629 pci_xhci_deassert_interrupt(struct pci_xhci_softc *sc) 630 { 631 632 if (!pci_msi_enabled(sc->xsc_pi)) 633 pci_lintr_assert(sc->xsc_pi); 634 } 635 636 static void 637 pci_xhci_init_ep(struct pci_xhci_dev_emu *dev, int epid) 638 { 639 struct xhci_dev_ctx *dev_ctx; 640 struct pci_xhci_dev_ep *devep; 641 struct xhci_endp_ctx *ep_ctx; 642 uint32_t pstreams; 643 int i; 644 645 dev_ctx = dev->dev_ctx; 646 ep_ctx = &dev_ctx->ctx_ep[epid]; 647 devep = &dev->eps[epid]; 648 pstreams = XHCI_EPCTX_0_MAXP_STREAMS_GET(ep_ctx->dwEpCtx0); 649 if (pstreams > 0) { 650 DPRINTF(("init_ep %d with pstreams %d", epid, pstreams)); 651 assert(devep->ep_sctx_trbs == NULL); 652 653 devep->ep_sctx = XHCI_GADDR(dev->xsc, ep_ctx->qwEpCtx2 & 654 XHCI_EPCTX_2_TR_DQ_PTR_MASK); 655 devep->ep_sctx_trbs = calloc(pstreams, 656 sizeof(struct pci_xhci_trb_ring)); 657 for (i = 0; i < pstreams; i++) { 658 devep->ep_sctx_trbs[i].ringaddr = 659 devep->ep_sctx[i].qwSctx0 & 660 XHCI_SCTX_0_TR_DQ_PTR_MASK; 661 devep->ep_sctx_trbs[i].ccs = 662 XHCI_SCTX_0_DCS_GET(devep->ep_sctx[i].qwSctx0); 663 } 664 } else { 665 DPRINTF(("init_ep %d with no pstreams", epid)); 666 devep->ep_ringaddr = ep_ctx->qwEpCtx2 & 667 XHCI_EPCTX_2_TR_DQ_PTR_MASK; 668 devep->ep_ccs = XHCI_EPCTX_2_DCS_GET(ep_ctx->qwEpCtx2); 669 devep->ep_tr = XHCI_GADDR(dev->xsc, devep->ep_ringaddr); 670 DPRINTF(("init_ep tr DCS %x", devep->ep_ccs)); 671 } 672 673 if (devep->ep_xfer == NULL) { 674 devep->ep_xfer = malloc(sizeof(struct usb_data_xfer)); 675 USB_DATA_XFER_INIT(devep->ep_xfer); 676 } 677 } 678 679 static void 680 pci_xhci_disable_ep(struct pci_xhci_dev_emu *dev, int epid) 681 { 682 struct xhci_dev_ctx *dev_ctx; 683 struct pci_xhci_dev_ep *devep; 684 struct xhci_endp_ctx *ep_ctx; 685 686 DPRINTF(("pci_xhci disable_ep %d", epid)); 687 688 dev_ctx = dev->dev_ctx; 689 ep_ctx = &dev_ctx->ctx_ep[epid]; 690 ep_ctx->dwEpCtx0 = (ep_ctx->dwEpCtx0 & ~0x7) | XHCI_ST_EPCTX_DISABLED; 691 692 devep = &dev->eps[epid]; 693 if (XHCI_EPCTX_0_MAXP_STREAMS_GET(ep_ctx->dwEpCtx0) > 0 && 694 devep->ep_sctx_trbs != NULL) 695 free(devep->ep_sctx_trbs); 696 697 if (devep->ep_xfer != NULL) { 698 free(devep->ep_xfer); 699 devep->ep_xfer = NULL; 700 } 701 702 memset(devep, 0, sizeof(struct pci_xhci_dev_ep)); 703 } 704 705 706 /* reset device at slot and data structures related to it */ 707 static void 708 pci_xhci_reset_slot(struct pci_xhci_softc *sc, int slot) 709 { 710 struct pci_xhci_dev_emu *dev; 711 712 dev = XHCI_SLOTDEV_PTR(sc, slot); 713 714 if (!dev) { 715 DPRINTF(("xhci reset unassigned slot (%d)?", slot)); 716 } else { 717 dev->dev_slotstate = XHCI_ST_DISABLED; 718 } 719 720 /* TODO: reset ring buffer pointers */ 721 } 722 723 static int 724 pci_xhci_insert_event(struct pci_xhci_softc *sc, struct xhci_trb *evtrb, 725 int do_intr) 726 { 727 struct pci_xhci_rtsregs *rts; 728 uint64_t erdp; 729 int erdp_idx; 730 int err; 731 struct xhci_trb *evtrbptr; 732 733 err = XHCI_TRB_ERROR_SUCCESS; 734 735 rts = &sc->rtsregs; 736 737 erdp = rts->intrreg.erdp & ~0xF; 738 erdp_idx = (erdp - rts->erstba_p[rts->er_deq_seg].qwEvrsTablePtr) / 739 sizeof(struct xhci_trb); 740 741 DPRINTF(("pci_xhci: insert event 0[%lx] 2[%x] 3[%x]", 742 evtrb->qwTrb0, evtrb->dwTrb2, evtrb->dwTrb3)); 743 DPRINTF(("\terdp idx %d/seg %d, enq idx %d/seg %d, pcs %u", 744 erdp_idx, rts->er_deq_seg, rts->er_enq_idx, 745 rts->er_enq_seg, rts->event_pcs)); 746 DPRINTF(("\t(erdp=0x%lx, erst=0x%lx, tblsz=%u, do_intr %d)", 747 erdp, rts->erstba_p->qwEvrsTablePtr, 748 rts->erstba_p->dwEvrsTableSize, do_intr)); 749 750 evtrbptr = &rts->erst_p[rts->er_enq_idx]; 751 752 /* TODO: multi-segment table */ 753 if (rts->er_events_cnt >= rts->erstba_p->dwEvrsTableSize) { 754 DPRINTF(("pci_xhci[%d] cannot insert event; ring full", 755 __LINE__)); 756 err = XHCI_TRB_ERROR_EV_RING_FULL; 757 goto done; 758 } 759 760 if (rts->er_events_cnt == rts->erstba_p->dwEvrsTableSize - 1) { 761 struct xhci_trb errev; 762 763 if ((evtrbptr->dwTrb3 & 0x1) == (rts->event_pcs & 0x1)) { 764 765 DPRINTF(("pci_xhci[%d] insert evt err: ring full", 766 __LINE__)); 767 768 errev.qwTrb0 = 0; 769 errev.dwTrb2 = XHCI_TRB_2_ERROR_SET( 770 XHCI_TRB_ERROR_EV_RING_FULL); 771 errev.dwTrb3 = XHCI_TRB_3_TYPE_SET( 772 XHCI_TRB_EVENT_HOST_CTRL) | 773 rts->event_pcs; 774 rts->er_events_cnt++; 775 memcpy(&rts->erst_p[rts->er_enq_idx], &errev, 776 sizeof(struct xhci_trb)); 777 rts->er_enq_idx = (rts->er_enq_idx + 1) % 778 rts->erstba_p->dwEvrsTableSize; 779 err = XHCI_TRB_ERROR_EV_RING_FULL; 780 do_intr = 1; 781 782 goto done; 783 } 784 } else { 785 rts->er_events_cnt++; 786 } 787 788 evtrb->dwTrb3 &= ~XHCI_TRB_3_CYCLE_BIT; 789 evtrb->dwTrb3 |= rts->event_pcs; 790 791 memcpy(&rts->erst_p[rts->er_enq_idx], evtrb, sizeof(struct xhci_trb)); 792 rts->er_enq_idx = (rts->er_enq_idx + 1) % 793 rts->erstba_p->dwEvrsTableSize; 794 795 if (rts->er_enq_idx == 0) 796 rts->event_pcs ^= 1; 797 798 done: 799 if (do_intr) 800 pci_xhci_assert_interrupt(sc); 801 802 return (err); 803 } 804 805 static uint32_t 806 pci_xhci_cmd_enable_slot(struct pci_xhci_softc *sc, uint32_t *slot) 807 { 808 struct pci_xhci_dev_emu *dev; 809 uint32_t cmderr; 810 int i; 811 812 cmderr = XHCI_TRB_ERROR_NO_SLOTS; 813 if (sc->portregs != NULL) 814 for (i = 1; i <= XHCI_MAX_SLOTS; i++) { 815 dev = XHCI_SLOTDEV_PTR(sc, i); 816 if (dev && dev->dev_slotstate == XHCI_ST_DISABLED) { 817 *slot = i; 818 dev->dev_slotstate = XHCI_ST_ENABLED; 819 cmderr = XHCI_TRB_ERROR_SUCCESS; 820 dev->hci.hci_address = i; 821 break; 822 } 823 } 824 825 DPRINTF(("pci_xhci enable slot (error=%d) slot %u", 826 cmderr != XHCI_TRB_ERROR_SUCCESS, *slot)); 827 828 return (cmderr); 829 } 830 831 static uint32_t 832 pci_xhci_cmd_disable_slot(struct pci_xhci_softc *sc, uint32_t slot) 833 { 834 struct pci_xhci_dev_emu *dev; 835 uint32_t cmderr; 836 837 DPRINTF(("pci_xhci disable slot %u", slot)); 838 839 cmderr = XHCI_TRB_ERROR_NO_SLOTS; 840 if (sc->portregs == NULL) 841 goto done; 842 843 if (slot > XHCI_MAX_SLOTS) { 844 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON; 845 goto done; 846 } 847 848 dev = XHCI_SLOTDEV_PTR(sc, slot); 849 if (dev) { 850 if (dev->dev_slotstate == XHCI_ST_DISABLED) { 851 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON; 852 } else { 853 dev->dev_slotstate = XHCI_ST_DISABLED; 854 cmderr = XHCI_TRB_ERROR_SUCCESS; 855 /* TODO: reset events and endpoints */ 856 } 857 } else 858 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON; 859 860 done: 861 return (cmderr); 862 } 863 864 static uint32_t 865 pci_xhci_cmd_reset_device(struct pci_xhci_softc *sc, uint32_t slot) 866 { 867 struct pci_xhci_dev_emu *dev; 868 struct xhci_dev_ctx *dev_ctx; 869 struct xhci_endp_ctx *ep_ctx; 870 uint32_t cmderr; 871 int i; 872 873 cmderr = XHCI_TRB_ERROR_NO_SLOTS; 874 if (sc->portregs == NULL) 875 goto done; 876 877 DPRINTF(("pci_xhci reset device slot %u", slot)); 878 879 dev = XHCI_SLOTDEV_PTR(sc, slot); 880 if (!dev || dev->dev_slotstate == XHCI_ST_DISABLED) 881 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON; 882 else { 883 dev->dev_slotstate = XHCI_ST_DEFAULT; 884 885 dev->hci.hci_address = 0; 886 dev_ctx = pci_xhci_get_dev_ctx(sc, slot); 887 888 /* slot state */ 889 dev_ctx->ctx_slot.dwSctx3 = FIELD_REPLACE( 890 dev_ctx->ctx_slot.dwSctx3, XHCI_ST_SLCTX_DEFAULT, 891 0x1F, 27); 892 893 /* number of contexts */ 894 dev_ctx->ctx_slot.dwSctx0 = FIELD_REPLACE( 895 dev_ctx->ctx_slot.dwSctx0, 1, 0x1F, 27); 896 897 /* reset all eps other than ep-0 */ 898 for (i = 2; i <= 31; i++) { 899 ep_ctx = &dev_ctx->ctx_ep[i]; 900 ep_ctx->dwEpCtx0 = FIELD_REPLACE( ep_ctx->dwEpCtx0, 901 XHCI_ST_EPCTX_DISABLED, 0x7, 0); 902 } 903 904 cmderr = XHCI_TRB_ERROR_SUCCESS; 905 } 906 907 pci_xhci_reset_slot(sc, slot); 908 909 done: 910 return (cmderr); 911 } 912 913 static uint32_t 914 pci_xhci_cmd_address_device(struct pci_xhci_softc *sc, uint32_t slot, 915 struct xhci_trb *trb) 916 { 917 struct pci_xhci_dev_emu *dev; 918 struct xhci_input_dev_ctx *input_ctx; 919 struct xhci_slot_ctx *islot_ctx; 920 struct xhci_dev_ctx *dev_ctx; 921 struct xhci_endp_ctx *ep0_ctx; 922 uint32_t cmderr; 923 924 input_ctx = XHCI_GADDR(sc, trb->qwTrb0 & ~0xFUL); 925 islot_ctx = &input_ctx->ctx_slot; 926 ep0_ctx = &input_ctx->ctx_ep[1]; 927 928 cmderr = XHCI_TRB_ERROR_SUCCESS; 929 930 DPRINTF(("pci_xhci: address device, input ctl: D 0x%08x A 0x%08x,", 931 input_ctx->ctx_input.dwInCtx0, input_ctx->ctx_input.dwInCtx1)); 932 DPRINTF((" slot %08x %08x %08x %08x", 933 islot_ctx->dwSctx0, islot_ctx->dwSctx1, 934 islot_ctx->dwSctx2, islot_ctx->dwSctx3)); 935 DPRINTF((" ep0 %08x %08x %016lx %08x", 936 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2, 937 ep0_ctx->dwEpCtx4)); 938 939 /* when setting address: drop-ctx=0, add-ctx=slot+ep0 */ 940 if ((input_ctx->ctx_input.dwInCtx0 != 0) || 941 (input_ctx->ctx_input.dwInCtx1 & 0x03) != 0x03) { 942 DPRINTF(("pci_xhci: address device, input ctl invalid")); 943 cmderr = XHCI_TRB_ERROR_TRB; 944 goto done; 945 } 946 947 /* assign address to slot */ 948 dev_ctx = pci_xhci_get_dev_ctx(sc, slot); 949 950 DPRINTF(("pci_xhci: address device, dev ctx")); 951 DPRINTF((" slot %08x %08x %08x %08x", 952 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1, 953 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3)); 954 955 dev = XHCI_SLOTDEV_PTR(sc, slot); 956 assert(dev != NULL); 957 958 dev->hci.hci_address = slot; 959 dev->dev_ctx = dev_ctx; 960 961 if (dev->dev_ue->ue_reset == NULL || 962 dev->dev_ue->ue_reset(dev->dev_sc) < 0) { 963 cmderr = XHCI_TRB_ERROR_ENDP_NOT_ON; 964 goto done; 965 } 966 967 memcpy(&dev_ctx->ctx_slot, islot_ctx, sizeof(struct xhci_slot_ctx)); 968 969 dev_ctx->ctx_slot.dwSctx3 = 970 XHCI_SCTX_3_SLOT_STATE_SET(XHCI_ST_SLCTX_ADDRESSED) | 971 XHCI_SCTX_3_DEV_ADDR_SET(slot); 972 973 memcpy(&dev_ctx->ctx_ep[1], ep0_ctx, sizeof(struct xhci_endp_ctx)); 974 ep0_ctx = &dev_ctx->ctx_ep[1]; 975 ep0_ctx->dwEpCtx0 = (ep0_ctx->dwEpCtx0 & ~0x7) | 976 XHCI_EPCTX_0_EPSTATE_SET(XHCI_ST_EPCTX_RUNNING); 977 978 pci_xhci_init_ep(dev, 1); 979 980 dev->dev_slotstate = XHCI_ST_ADDRESSED; 981 982 DPRINTF(("pci_xhci: address device, output ctx")); 983 DPRINTF((" slot %08x %08x %08x %08x", 984 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1, 985 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3)); 986 DPRINTF((" ep0 %08x %08x %016lx %08x", 987 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2, 988 ep0_ctx->dwEpCtx4)); 989 990 done: 991 return (cmderr); 992 } 993 994 static uint32_t 995 pci_xhci_cmd_config_ep(struct pci_xhci_softc *sc, uint32_t slot, 996 struct xhci_trb *trb) 997 { 998 struct xhci_input_dev_ctx *input_ctx; 999 struct pci_xhci_dev_emu *dev; 1000 struct xhci_dev_ctx *dev_ctx; 1001 struct xhci_endp_ctx *ep_ctx, *iep_ctx; 1002 uint32_t cmderr; 1003 int i; 1004 1005 cmderr = XHCI_TRB_ERROR_SUCCESS; 1006 1007 DPRINTF(("pci_xhci config_ep slot %u", slot)); 1008 1009 dev = XHCI_SLOTDEV_PTR(sc, slot); 1010 assert(dev != NULL); 1011 1012 if ((trb->dwTrb3 & XHCI_TRB_3_DCEP_BIT) != 0) { 1013 DPRINTF(("pci_xhci config_ep - deconfigure ep slot %u", 1014 slot)); 1015 if (dev->dev_ue->ue_stop != NULL) 1016 dev->dev_ue->ue_stop(dev->dev_sc); 1017 1018 dev->dev_slotstate = XHCI_ST_ADDRESSED; 1019 1020 dev->hci.hci_address = 0; 1021 dev_ctx = pci_xhci_get_dev_ctx(sc, slot); 1022 1023 /* number of contexts */ 1024 dev_ctx->ctx_slot.dwSctx0 = FIELD_REPLACE( 1025 dev_ctx->ctx_slot.dwSctx0, 1, 0x1F, 27); 1026 1027 /* slot state */ 1028 dev_ctx->ctx_slot.dwSctx3 = FIELD_REPLACE( 1029 dev_ctx->ctx_slot.dwSctx3, XHCI_ST_SLCTX_ADDRESSED, 1030 0x1F, 27); 1031 1032 /* disable endpoints */ 1033 for (i = 2; i < 32; i++) 1034 pci_xhci_disable_ep(dev, i); 1035 1036 cmderr = XHCI_TRB_ERROR_SUCCESS; 1037 1038 goto done; 1039 } 1040 1041 if (dev->dev_slotstate < XHCI_ST_ADDRESSED) { 1042 DPRINTF(("pci_xhci: config_ep slotstate x%x != addressed", 1043 dev->dev_slotstate)); 1044 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON; 1045 goto done; 1046 } 1047 1048 /* In addressed/configured state; 1049 * for each drop endpoint ctx flag: 1050 * ep->state = DISABLED 1051 * for each add endpoint ctx flag: 1052 * cp(ep-in, ep-out) 1053 * ep->state = RUNNING 1054 * for each drop+add endpoint flag: 1055 * reset ep resources 1056 * cp(ep-in, ep-out) 1057 * ep->state = RUNNING 1058 * if input->DisabledCtx[2-31] < 30: (at least 1 ep not disabled) 1059 * slot->state = configured 1060 */ 1061 1062 input_ctx = XHCI_GADDR(sc, trb->qwTrb0 & ~0xFUL); 1063 dev_ctx = dev->dev_ctx; 1064 DPRINTF(("pci_xhci: config_ep inputctx: D:x%08x A:x%08x 7:x%08x", 1065 input_ctx->ctx_input.dwInCtx0, input_ctx->ctx_input.dwInCtx1, 1066 input_ctx->ctx_input.dwInCtx7)); 1067 1068 for (i = 2; i <= 31; i++) { 1069 ep_ctx = &dev_ctx->ctx_ep[i]; 1070 1071 if (input_ctx->ctx_input.dwInCtx0 & 1072 XHCI_INCTX_0_DROP_MASK(i)) { 1073 DPRINTF((" config ep - dropping ep %d", i)); 1074 pci_xhci_disable_ep(dev, i); 1075 } 1076 1077 if (input_ctx->ctx_input.dwInCtx1 & 1078 XHCI_INCTX_1_ADD_MASK(i)) { 1079 iep_ctx = &input_ctx->ctx_ep[i]; 1080 1081 DPRINTF((" enable ep[%d] %08x %08x %016lx %08x", 1082 i, iep_ctx->dwEpCtx0, iep_ctx->dwEpCtx1, 1083 iep_ctx->qwEpCtx2, iep_ctx->dwEpCtx4)); 1084 1085 memcpy(ep_ctx, iep_ctx, sizeof(struct xhci_endp_ctx)); 1086 1087 pci_xhci_init_ep(dev, i); 1088 1089 /* ep state */ 1090 ep_ctx->dwEpCtx0 = FIELD_REPLACE( 1091 ep_ctx->dwEpCtx0, XHCI_ST_EPCTX_RUNNING, 0x7, 0); 1092 } 1093 } 1094 1095 /* slot state to configured */ 1096 dev_ctx->ctx_slot.dwSctx3 = FIELD_REPLACE( 1097 dev_ctx->ctx_slot.dwSctx3, XHCI_ST_SLCTX_CONFIGURED, 0x1F, 27); 1098 dev_ctx->ctx_slot.dwSctx0 = FIELD_COPY( 1099 dev_ctx->ctx_slot.dwSctx0, input_ctx->ctx_slot.dwSctx0, 0x1F, 27); 1100 dev->dev_slotstate = XHCI_ST_CONFIGURED; 1101 1102 DPRINTF(("EP configured; slot %u [0]=0x%08x [1]=0x%08x [2]=0x%08x " 1103 "[3]=0x%08x", 1104 slot, dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1, 1105 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3)); 1106 1107 done: 1108 return (cmderr); 1109 } 1110 1111 static uint32_t 1112 pci_xhci_cmd_reset_ep(struct pci_xhci_softc *sc, uint32_t slot, 1113 struct xhci_trb *trb) 1114 { 1115 struct pci_xhci_dev_emu *dev; 1116 struct pci_xhci_dev_ep *devep; 1117 struct xhci_dev_ctx *dev_ctx; 1118 struct xhci_endp_ctx *ep_ctx; 1119 uint32_t cmderr, epid; 1120 uint32_t type; 1121 1122 epid = XHCI_TRB_3_EP_GET(trb->dwTrb3); 1123 1124 DPRINTF(("pci_xhci: reset ep %u: slot %u", epid, slot)); 1125 1126 cmderr = XHCI_TRB_ERROR_SUCCESS; 1127 1128 type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3); 1129 1130 dev = XHCI_SLOTDEV_PTR(sc, slot); 1131 assert(dev != NULL); 1132 1133 if (type == XHCI_TRB_TYPE_STOP_EP && 1134 (trb->dwTrb3 & XHCI_TRB_3_SUSP_EP_BIT) != 0) { 1135 /* XXX suspend endpoint for 10ms */ 1136 } 1137 1138 if (epid < 1 || epid > 31) { 1139 DPRINTF(("pci_xhci: reset ep: invalid epid %u", epid)); 1140 cmderr = XHCI_TRB_ERROR_TRB; 1141 goto done; 1142 } 1143 1144 devep = &dev->eps[epid]; 1145 if (devep->ep_xfer != NULL) 1146 USB_DATA_XFER_RESET(devep->ep_xfer); 1147 1148 dev_ctx = dev->dev_ctx; 1149 assert(dev_ctx != NULL); 1150 1151 ep_ctx = &dev_ctx->ctx_ep[epid]; 1152 1153 ep_ctx->dwEpCtx0 = (ep_ctx->dwEpCtx0 & ~0x7) | XHCI_ST_EPCTX_STOPPED; 1154 1155 if (XHCI_EPCTX_0_MAXP_STREAMS_GET(ep_ctx->dwEpCtx0) == 0) 1156 ep_ctx->qwEpCtx2 = devep->ep_ringaddr | devep->ep_ccs; 1157 1158 DPRINTF(("pci_xhci: reset ep[%u] %08x %08x %016lx %08x", 1159 epid, ep_ctx->dwEpCtx0, ep_ctx->dwEpCtx1, ep_ctx->qwEpCtx2, 1160 ep_ctx->dwEpCtx4)); 1161 1162 if (type == XHCI_TRB_TYPE_RESET_EP && 1163 (dev->dev_ue->ue_reset == NULL || 1164 dev->dev_ue->ue_reset(dev->dev_sc) < 0)) { 1165 cmderr = XHCI_TRB_ERROR_ENDP_NOT_ON; 1166 goto done; 1167 } 1168 1169 done: 1170 return (cmderr); 1171 } 1172 1173 1174 static uint32_t 1175 pci_xhci_find_stream(struct pci_xhci_softc *sc, struct xhci_endp_ctx *ep, 1176 uint32_t streamid, struct xhci_stream_ctx **osctx) 1177 { 1178 struct xhci_stream_ctx *sctx; 1179 uint32_t maxpstreams; 1180 1181 maxpstreams = XHCI_EPCTX_0_MAXP_STREAMS_GET(ep->dwEpCtx0); 1182 if (maxpstreams == 0) 1183 return (XHCI_TRB_ERROR_TRB); 1184 1185 if (maxpstreams > XHCI_STREAMS_MAX) 1186 return (XHCI_TRB_ERROR_INVALID_SID); 1187 1188 if (XHCI_EPCTX_0_LSA_GET(ep->dwEpCtx0) == 0) { 1189 DPRINTF(("pci_xhci: find_stream; LSA bit not set")); 1190 return (XHCI_TRB_ERROR_INVALID_SID); 1191 } 1192 1193 /* only support primary stream */ 1194 if (streamid > maxpstreams) 1195 return (XHCI_TRB_ERROR_STREAM_TYPE); 1196 1197 sctx = XHCI_GADDR(sc, ep->qwEpCtx2 & ~0xFUL) + streamid; 1198 if (!XHCI_SCTX_0_SCT_GET(sctx->qwSctx0)) 1199 return (XHCI_TRB_ERROR_STREAM_TYPE); 1200 1201 *osctx = sctx; 1202 1203 return (XHCI_TRB_ERROR_SUCCESS); 1204 } 1205 1206 1207 static uint32_t 1208 pci_xhci_cmd_set_tr(struct pci_xhci_softc *sc, uint32_t slot, 1209 struct xhci_trb *trb) 1210 { 1211 struct pci_xhci_dev_emu *dev; 1212 struct pci_xhci_dev_ep *devep; 1213 struct xhci_dev_ctx *dev_ctx; 1214 struct xhci_endp_ctx *ep_ctx; 1215 uint32_t cmderr, epid; 1216 uint32_t streamid; 1217 1218 cmderr = XHCI_TRB_ERROR_SUCCESS; 1219 1220 dev = XHCI_SLOTDEV_PTR(sc, slot); 1221 assert(dev != NULL); 1222 1223 DPRINTF(("pci_xhci set_tr: new-tr x%016lx, SCT %u DCS %u", 1224 (trb->qwTrb0 & ~0xF), (uint32_t)((trb->qwTrb0 >> 1) & 0x7), 1225 (uint32_t)(trb->qwTrb0 & 0x1))); 1226 DPRINTF((" stream-id %u, slot %u, epid %u, C %u", 1227 (trb->dwTrb2 >> 16) & 0xFFFF, 1228 XHCI_TRB_3_SLOT_GET(trb->dwTrb3), 1229 XHCI_TRB_3_EP_GET(trb->dwTrb3), trb->dwTrb3 & 0x1)); 1230 1231 epid = XHCI_TRB_3_EP_GET(trb->dwTrb3); 1232 if (epid < 1 || epid > 31) { 1233 DPRINTF(("pci_xhci: set_tr_deq: invalid epid %u", epid)); 1234 cmderr = XHCI_TRB_ERROR_TRB; 1235 goto done; 1236 } 1237 1238 dev_ctx = dev->dev_ctx; 1239 assert(dev_ctx != NULL); 1240 1241 ep_ctx = &dev_ctx->ctx_ep[epid]; 1242 devep = &dev->eps[epid]; 1243 1244 switch (XHCI_EPCTX_0_EPSTATE_GET(ep_ctx->dwEpCtx0)) { 1245 case XHCI_ST_EPCTX_STOPPED: 1246 case XHCI_ST_EPCTX_ERROR: 1247 break; 1248 default: 1249 DPRINTF(("pci_xhci cmd set_tr invalid state %x", 1250 XHCI_EPCTX_0_EPSTATE_GET(ep_ctx->dwEpCtx0))); 1251 cmderr = XHCI_TRB_ERROR_CONTEXT_STATE; 1252 goto done; 1253 } 1254 1255 streamid = XHCI_TRB_2_STREAM_GET(trb->dwTrb2); 1256 if (XHCI_EPCTX_0_MAXP_STREAMS_GET(ep_ctx->dwEpCtx0) > 0) { 1257 struct xhci_stream_ctx *sctx; 1258 1259 sctx = NULL; 1260 cmderr = pci_xhci_find_stream(sc, ep_ctx, streamid, &sctx); 1261 if (sctx != NULL) { 1262 assert(devep->ep_sctx != NULL); 1263 1264 devep->ep_sctx[streamid].qwSctx0 = trb->qwTrb0; 1265 devep->ep_sctx_trbs[streamid].ringaddr = 1266 trb->qwTrb0 & ~0xF; 1267 devep->ep_sctx_trbs[streamid].ccs = 1268 XHCI_EPCTX_2_DCS_GET(trb->qwTrb0); 1269 } 1270 } else { 1271 if (streamid != 0) { 1272 DPRINTF(("pci_xhci cmd set_tr streamid %x != 0", 1273 streamid)); 1274 } 1275 ep_ctx->qwEpCtx2 = trb->qwTrb0 & ~0xFUL; 1276 devep->ep_ringaddr = ep_ctx->qwEpCtx2 & ~0xFUL; 1277 devep->ep_ccs = trb->qwTrb0 & 0x1; 1278 devep->ep_tr = XHCI_GADDR(sc, devep->ep_ringaddr); 1279 1280 DPRINTF(("pci_xhci set_tr first TRB:")); 1281 pci_xhci_dump_trb(devep->ep_tr); 1282 } 1283 ep_ctx->dwEpCtx0 = (ep_ctx->dwEpCtx0 & ~0x7) | XHCI_ST_EPCTX_STOPPED; 1284 1285 done: 1286 return (cmderr); 1287 } 1288 1289 static uint32_t 1290 pci_xhci_cmd_eval_ctx(struct pci_xhci_softc *sc, uint32_t slot, 1291 struct xhci_trb *trb) 1292 { 1293 struct xhci_input_dev_ctx *input_ctx; 1294 struct xhci_slot_ctx *islot_ctx; 1295 struct xhci_dev_ctx *dev_ctx; 1296 struct xhci_endp_ctx *ep0_ctx; 1297 uint32_t cmderr; 1298 1299 input_ctx = XHCI_GADDR(sc, trb->qwTrb0 & ~0xFUL); 1300 islot_ctx = &input_ctx->ctx_slot; 1301 ep0_ctx = &input_ctx->ctx_ep[1]; 1302 1303 cmderr = XHCI_TRB_ERROR_SUCCESS; 1304 DPRINTF(("pci_xhci: eval ctx, input ctl: D 0x%08x A 0x%08x,", 1305 input_ctx->ctx_input.dwInCtx0, input_ctx->ctx_input.dwInCtx1)); 1306 DPRINTF((" slot %08x %08x %08x %08x", 1307 islot_ctx->dwSctx0, islot_ctx->dwSctx1, 1308 islot_ctx->dwSctx2, islot_ctx->dwSctx3)); 1309 DPRINTF((" ep0 %08x %08x %016lx %08x", 1310 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2, 1311 ep0_ctx->dwEpCtx4)); 1312 1313 /* this command expects drop-ctx=0 & add-ctx=slot+ep0 */ 1314 if ((input_ctx->ctx_input.dwInCtx0 != 0) || 1315 (input_ctx->ctx_input.dwInCtx1 & 0x03) == 0) { 1316 DPRINTF(("pci_xhci: eval ctx, input ctl invalid")); 1317 cmderr = XHCI_TRB_ERROR_TRB; 1318 goto done; 1319 } 1320 1321 /* assign address to slot; in this emulation, slot_id = address */ 1322 dev_ctx = pci_xhci_get_dev_ctx(sc, slot); 1323 1324 DPRINTF(("pci_xhci: eval ctx, dev ctx")); 1325 DPRINTF((" slot %08x %08x %08x %08x", 1326 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1, 1327 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3)); 1328 1329 if (input_ctx->ctx_input.dwInCtx1 & 0x01) { /* slot ctx */ 1330 /* set max exit latency */ 1331 dev_ctx->ctx_slot.dwSctx1 = FIELD_COPY( 1332 dev_ctx->ctx_slot.dwSctx1, input_ctx->ctx_slot.dwSctx1, 1333 0xFFFF, 0); 1334 1335 /* set interrupter target */ 1336 dev_ctx->ctx_slot.dwSctx2 = FIELD_COPY( 1337 dev_ctx->ctx_slot.dwSctx2, input_ctx->ctx_slot.dwSctx2, 1338 0x3FF, 22); 1339 } 1340 if (input_ctx->ctx_input.dwInCtx1 & 0x02) { /* control ctx */ 1341 /* set max packet size */ 1342 dev_ctx->ctx_ep[1].dwEpCtx1 = FIELD_COPY( 1343 dev_ctx->ctx_ep[1].dwEpCtx1, ep0_ctx->dwEpCtx1, 1344 0xFFFF, 16); 1345 1346 ep0_ctx = &dev_ctx->ctx_ep[1]; 1347 } 1348 1349 DPRINTF(("pci_xhci: eval ctx, output ctx")); 1350 DPRINTF((" slot %08x %08x %08x %08x", 1351 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1, 1352 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3)); 1353 DPRINTF((" ep0 %08x %08x %016lx %08x", 1354 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2, 1355 ep0_ctx->dwEpCtx4)); 1356 1357 done: 1358 return (cmderr); 1359 } 1360 1361 static int 1362 pci_xhci_complete_commands(struct pci_xhci_softc *sc) 1363 { 1364 struct xhci_trb evtrb; 1365 struct xhci_trb *trb; 1366 uint64_t crcr; 1367 uint32_t ccs; /* cycle state (XHCI 4.9.2) */ 1368 uint32_t type; 1369 uint32_t slot; 1370 uint32_t cmderr; 1371 int error; 1372 1373 error = 0; 1374 sc->opregs.crcr |= XHCI_CRCR_LO_CRR; 1375 1376 trb = sc->opregs.cr_p; 1377 ccs = sc->opregs.crcr & XHCI_CRCR_LO_RCS; 1378 crcr = sc->opregs.crcr & ~0xF; 1379 1380 while (1) { 1381 sc->opregs.cr_p = trb; 1382 1383 type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3); 1384 1385 if ((trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT) != 1386 (ccs & XHCI_TRB_3_CYCLE_BIT)) 1387 break; 1388 1389 DPRINTF(("pci_xhci: cmd type 0x%x, Trb0 x%016lx dwTrb2 x%08x" 1390 " dwTrb3 x%08x, TRB_CYCLE %u/ccs %u", 1391 type, trb->qwTrb0, trb->dwTrb2, trb->dwTrb3, 1392 trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT, ccs)); 1393 1394 cmderr = XHCI_TRB_ERROR_SUCCESS; 1395 evtrb.dwTrb2 = 0; 1396 evtrb.dwTrb3 = (ccs & XHCI_TRB_3_CYCLE_BIT) | 1397 XHCI_TRB_3_TYPE_SET(XHCI_TRB_EVENT_CMD_COMPLETE); 1398 slot = 0; 1399 1400 switch (type) { 1401 case XHCI_TRB_TYPE_LINK: /* 0x06 */ 1402 if (trb->dwTrb3 & XHCI_TRB_3_TC_BIT) 1403 ccs ^= XHCI_CRCR_LO_RCS; 1404 break; 1405 1406 case XHCI_TRB_TYPE_ENABLE_SLOT: /* 0x09 */ 1407 cmderr = pci_xhci_cmd_enable_slot(sc, &slot); 1408 break; 1409 1410 case XHCI_TRB_TYPE_DISABLE_SLOT: /* 0x0A */ 1411 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); 1412 cmderr = pci_xhci_cmd_disable_slot(sc, slot); 1413 break; 1414 1415 case XHCI_TRB_TYPE_ADDRESS_DEVICE: /* 0x0B */ 1416 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); 1417 cmderr = pci_xhci_cmd_address_device(sc, slot, trb); 1418 break; 1419 1420 case XHCI_TRB_TYPE_CONFIGURE_EP: /* 0x0C */ 1421 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); 1422 cmderr = pci_xhci_cmd_config_ep(sc, slot, trb); 1423 break; 1424 1425 case XHCI_TRB_TYPE_EVALUATE_CTX: /* 0x0D */ 1426 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); 1427 cmderr = pci_xhci_cmd_eval_ctx(sc, slot, trb); 1428 break; 1429 1430 case XHCI_TRB_TYPE_RESET_EP: /* 0x0E */ 1431 DPRINTF(("Reset Endpoint on slot %d", slot)); 1432 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); 1433 cmderr = pci_xhci_cmd_reset_ep(sc, slot, trb); 1434 break; 1435 1436 case XHCI_TRB_TYPE_STOP_EP: /* 0x0F */ 1437 DPRINTF(("Stop Endpoint on slot %d", slot)); 1438 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); 1439 cmderr = pci_xhci_cmd_reset_ep(sc, slot, trb); 1440 break; 1441 1442 case XHCI_TRB_TYPE_SET_TR_DEQUEUE: /* 0x10 */ 1443 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); 1444 cmderr = pci_xhci_cmd_set_tr(sc, slot, trb); 1445 break; 1446 1447 case XHCI_TRB_TYPE_RESET_DEVICE: /* 0x11 */ 1448 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); 1449 cmderr = pci_xhci_cmd_reset_device(sc, slot); 1450 break; 1451 1452 case XHCI_TRB_TYPE_FORCE_EVENT: /* 0x12 */ 1453 /* TODO: */ 1454 break; 1455 1456 case XHCI_TRB_TYPE_NEGOTIATE_BW: /* 0x13 */ 1457 break; 1458 1459 case XHCI_TRB_TYPE_SET_LATENCY_TOL: /* 0x14 */ 1460 break; 1461 1462 case XHCI_TRB_TYPE_GET_PORT_BW: /* 0x15 */ 1463 break; 1464 1465 case XHCI_TRB_TYPE_FORCE_HEADER: /* 0x16 */ 1466 break; 1467 1468 case XHCI_TRB_TYPE_NOOP_CMD: /* 0x17 */ 1469 break; 1470 1471 default: 1472 DPRINTF(("pci_xhci: unsupported cmd %x", type)); 1473 break; 1474 } 1475 1476 if (type != XHCI_TRB_TYPE_LINK) { 1477 /* 1478 * insert command completion event and assert intr 1479 */ 1480 evtrb.qwTrb0 = crcr; 1481 evtrb.dwTrb2 |= XHCI_TRB_2_ERROR_SET(cmderr); 1482 evtrb.dwTrb3 |= XHCI_TRB_3_SLOT_SET(slot); 1483 DPRINTF(("pci_xhci: command 0x%x result: 0x%x", 1484 type, cmderr)); 1485 pci_xhci_insert_event(sc, &evtrb, 1); 1486 } 1487 1488 trb = pci_xhci_trb_next(sc, trb, &crcr); 1489 } 1490 1491 sc->opregs.crcr = crcr | (sc->opregs.crcr & XHCI_CRCR_LO_CA) | ccs; 1492 sc->opregs.crcr &= ~XHCI_CRCR_LO_CRR; 1493 return (error); 1494 } 1495 1496 static void 1497 pci_xhci_dump_trb(struct xhci_trb *trb) 1498 { 1499 static const char *trbtypes[] = { 1500 "RESERVED", 1501 "NORMAL", 1502 "SETUP_STAGE", 1503 "DATA_STAGE", 1504 "STATUS_STAGE", 1505 "ISOCH", 1506 "LINK", 1507 "EVENT_DATA", 1508 "NOOP", 1509 "ENABLE_SLOT", 1510 "DISABLE_SLOT", 1511 "ADDRESS_DEVICE", 1512 "CONFIGURE_EP", 1513 "EVALUATE_CTX", 1514 "RESET_EP", 1515 "STOP_EP", 1516 "SET_TR_DEQUEUE", 1517 "RESET_DEVICE", 1518 "FORCE_EVENT", 1519 "NEGOTIATE_BW", 1520 "SET_LATENCY_TOL", 1521 "GET_PORT_BW", 1522 "FORCE_HEADER", 1523 "NOOP_CMD" 1524 }; 1525 uint32_t type; 1526 1527 type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3); 1528 DPRINTF(("pci_xhci: trb[@%p] type x%02x %s 0:x%016lx 2:x%08x 3:x%08x", 1529 trb, type, 1530 type <= XHCI_TRB_TYPE_NOOP_CMD ? trbtypes[type] : "INVALID", 1531 trb->qwTrb0, trb->dwTrb2, trb->dwTrb3)); 1532 } 1533 1534 static int 1535 pci_xhci_xfer_complete(struct pci_xhci_softc *sc, struct usb_data_xfer *xfer, 1536 uint32_t slot, uint32_t epid, int *do_intr) 1537 { 1538 struct pci_xhci_dev_emu *dev; 1539 struct pci_xhci_dev_ep *devep; 1540 struct xhci_dev_ctx *dev_ctx; 1541 struct xhci_endp_ctx *ep_ctx; 1542 struct xhci_trb *trb; 1543 struct xhci_trb evtrb; 1544 uint32_t trbflags; 1545 uint32_t edtla; 1546 int i, err; 1547 1548 dev = XHCI_SLOTDEV_PTR(sc, slot); 1549 devep = &dev->eps[epid]; 1550 dev_ctx = pci_xhci_get_dev_ctx(sc, slot); 1551 1552 assert(dev_ctx != NULL); 1553 1554 ep_ctx = &dev_ctx->ctx_ep[epid]; 1555 1556 err = XHCI_TRB_ERROR_SUCCESS; 1557 *do_intr = 0; 1558 edtla = 0; 1559 1560 /* go through list of TRBs and insert event(s) */ 1561 for (i = xfer->head; xfer->ndata > 0; ) { 1562 evtrb.qwTrb0 = (uint64_t)xfer->data[i].hci_data; 1563 trb = XHCI_GADDR(sc, evtrb.qwTrb0); 1564 trbflags = trb->dwTrb3; 1565 1566 DPRINTF(("pci_xhci: xfer[%d] done?%u:%d trb %x %016lx %x " 1567 "(err %d) IOC?%d", 1568 i, xfer->data[i].processed, xfer->data[i].blen, 1569 XHCI_TRB_3_TYPE_GET(trbflags), evtrb.qwTrb0, 1570 trbflags, err, 1571 trb->dwTrb3 & XHCI_TRB_3_IOC_BIT ? 1 : 0)); 1572 1573 if (!xfer->data[i].processed) { 1574 xfer->head = i; 1575 break; 1576 } 1577 1578 xfer->ndata--; 1579 edtla += xfer->data[i].bdone; 1580 1581 trb->dwTrb3 = (trb->dwTrb3 & ~0x1) | (xfer->data[i].ccs); 1582 1583 pci_xhci_update_ep_ring(sc, dev, devep, ep_ctx, 1584 xfer->data[i].streamid, xfer->data[i].trbnext, 1585 xfer->data[i].ccs); 1586 1587 /* Only interrupt if IOC or short packet */ 1588 if (!(trb->dwTrb3 & XHCI_TRB_3_IOC_BIT) && 1589 !((err == XHCI_TRB_ERROR_SHORT_PKT) && 1590 (trb->dwTrb3 & XHCI_TRB_3_ISP_BIT))) { 1591 1592 i = (i + 1) % USB_MAX_XFER_BLOCKS; 1593 continue; 1594 } 1595 1596 evtrb.dwTrb2 = XHCI_TRB_2_ERROR_SET(err) | 1597 XHCI_TRB_2_REM_SET(xfer->data[i].blen); 1598 1599 evtrb.dwTrb3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_EVENT_TRANSFER) | 1600 XHCI_TRB_3_SLOT_SET(slot) | XHCI_TRB_3_EP_SET(epid); 1601 1602 if (XHCI_TRB_3_TYPE_GET(trbflags) == XHCI_TRB_TYPE_EVENT_DATA) { 1603 DPRINTF(("pci_xhci EVENT_DATA edtla %u", edtla)); 1604 evtrb.qwTrb0 = trb->qwTrb0; 1605 evtrb.dwTrb2 = (edtla & 0xFFFFF) | 1606 XHCI_TRB_2_ERROR_SET(err); 1607 evtrb.dwTrb3 |= XHCI_TRB_3_ED_BIT; 1608 edtla = 0; 1609 } 1610 1611 *do_intr = 1; 1612 1613 err = pci_xhci_insert_event(sc, &evtrb, 0); 1614 if (err != XHCI_TRB_ERROR_SUCCESS) { 1615 break; 1616 } 1617 1618 i = (i + 1) % USB_MAX_XFER_BLOCKS; 1619 } 1620 1621 return (err); 1622 } 1623 1624 static void 1625 pci_xhci_update_ep_ring(struct pci_xhci_softc *sc, struct pci_xhci_dev_emu *dev, 1626 struct pci_xhci_dev_ep *devep, struct xhci_endp_ctx *ep_ctx, 1627 uint32_t streamid, uint64_t ringaddr, int ccs) 1628 { 1629 1630 if (XHCI_EPCTX_0_MAXP_STREAMS_GET(ep_ctx->dwEpCtx0) != 0) { 1631 devep->ep_sctx[streamid].qwSctx0 = (ringaddr & ~0xFUL) | 1632 (ccs & 0x1); 1633 1634 devep->ep_sctx_trbs[streamid].ringaddr = ringaddr & ~0xFUL; 1635 devep->ep_sctx_trbs[streamid].ccs = ccs & 0x1; 1636 ep_ctx->qwEpCtx2 = (ep_ctx->qwEpCtx2 & ~0x1) | (ccs & 0x1); 1637 1638 DPRINTF(("xhci update ep-ring stream %d, addr %lx", 1639 streamid, devep->ep_sctx[streamid].qwSctx0)); 1640 } else { 1641 devep->ep_ringaddr = ringaddr & ~0xFUL; 1642 devep->ep_ccs = ccs & 0x1; 1643 devep->ep_tr = XHCI_GADDR(sc, ringaddr & ~0xFUL); 1644 ep_ctx->qwEpCtx2 = (ringaddr & ~0xFUL) | (ccs & 0x1); 1645 1646 DPRINTF(("xhci update ep-ring, addr %lx", 1647 (devep->ep_ringaddr | devep->ep_ccs))); 1648 } 1649 } 1650 1651 /* 1652 * Outstanding transfer still in progress (device NAK'd earlier) so retry 1653 * the transfer again to see if it succeeds. 1654 */ 1655 static int 1656 pci_xhci_try_usb_xfer(struct pci_xhci_softc *sc, 1657 struct pci_xhci_dev_emu *dev, struct pci_xhci_dev_ep *devep, 1658 struct xhci_endp_ctx *ep_ctx, uint32_t slot, uint32_t epid) 1659 { 1660 struct usb_data_xfer *xfer; 1661 int err; 1662 int do_intr; 1663 1664 ep_ctx->dwEpCtx0 = FIELD_REPLACE( 1665 ep_ctx->dwEpCtx0, XHCI_ST_EPCTX_RUNNING, 0x7, 0); 1666 1667 err = 0; 1668 do_intr = 0; 1669 1670 xfer = devep->ep_xfer; 1671 #ifdef __FreeBSD__ 1672 USB_DATA_XFER_LOCK(xfer); 1673 #else 1674 /* 1675 * At least one caller needs to hold this lock across the call to this 1676 * function and other code. To avoid deadlock from a recursive mutex 1677 * enter, we ensure that all callers hold this lock. 1678 */ 1679 assert(USB_DATA_XFER_LOCK_HELD(xfer)); 1680 #endif 1681 1682 /* outstanding requests queued up */ 1683 if (dev->dev_ue->ue_data != NULL) { 1684 err = dev->dev_ue->ue_data(dev->dev_sc, xfer, 1685 epid & 0x1 ? USB_XFER_IN : USB_XFER_OUT, epid/2); 1686 if (err == USB_ERR_CANCELLED) { 1687 if (USB_DATA_GET_ERRCODE(&xfer->data[xfer->head]) == 1688 USB_NAK) 1689 err = XHCI_TRB_ERROR_SUCCESS; 1690 } else { 1691 err = pci_xhci_xfer_complete(sc, xfer, slot, epid, 1692 &do_intr); 1693 if (err == XHCI_TRB_ERROR_SUCCESS && do_intr) { 1694 pci_xhci_assert_interrupt(sc); 1695 } 1696 1697 1698 /* XXX should not do it if error? */ 1699 USB_DATA_XFER_RESET(xfer); 1700 } 1701 } 1702 1703 #ifdef __FreeBSD__ 1704 USB_DATA_XFER_UNLOCK(xfer); 1705 #endif 1706 1707 return (err); 1708 } 1709 1710 1711 static int 1712 pci_xhci_handle_transfer(struct pci_xhci_softc *sc, 1713 struct pci_xhci_dev_emu *dev, struct pci_xhci_dev_ep *devep, 1714 struct xhci_endp_ctx *ep_ctx, struct xhci_trb *trb, uint32_t slot, 1715 uint32_t epid, uint64_t addr, uint32_t ccs, uint32_t streamid) 1716 { 1717 struct xhci_trb *setup_trb; 1718 struct usb_data_xfer *xfer; 1719 struct usb_data_xfer_block *xfer_block; 1720 uint64_t val; 1721 uint32_t trbflags; 1722 int do_intr, err; 1723 int do_retry; 1724 1725 ep_ctx->dwEpCtx0 = FIELD_REPLACE(ep_ctx->dwEpCtx0, 1726 XHCI_ST_EPCTX_RUNNING, 0x7, 0); 1727 1728 xfer = devep->ep_xfer; 1729 USB_DATA_XFER_LOCK(xfer); 1730 1731 DPRINTF(("pci_xhci handle_transfer slot %u", slot)); 1732 1733 retry: 1734 err = 0; 1735 do_retry = 0; 1736 do_intr = 0; 1737 setup_trb = NULL; 1738 1739 while (1) { 1740 pci_xhci_dump_trb(trb); 1741 1742 trbflags = trb->dwTrb3; 1743 1744 if (XHCI_TRB_3_TYPE_GET(trbflags) != XHCI_TRB_TYPE_LINK && 1745 (trbflags & XHCI_TRB_3_CYCLE_BIT) != 1746 (ccs & XHCI_TRB_3_CYCLE_BIT)) { 1747 DPRINTF(("Cycle-bit changed trbflags %x, ccs %x", 1748 trbflags & XHCI_TRB_3_CYCLE_BIT, ccs)); 1749 break; 1750 } 1751 1752 xfer_block = NULL; 1753 1754 switch (XHCI_TRB_3_TYPE_GET(trbflags)) { 1755 case XHCI_TRB_TYPE_LINK: 1756 if (trb->dwTrb3 & XHCI_TRB_3_TC_BIT) 1757 ccs ^= 0x1; 1758 1759 xfer_block = usb_data_xfer_append(xfer, NULL, 0, 1760 (void *)addr, ccs); 1761 xfer_block->processed = 1; 1762 break; 1763 1764 case XHCI_TRB_TYPE_SETUP_STAGE: 1765 if ((trbflags & XHCI_TRB_3_IDT_BIT) == 0 || 1766 XHCI_TRB_2_BYTES_GET(trb->dwTrb2) != 8) { 1767 DPRINTF(("pci_xhci: invalid setup trb")); 1768 err = XHCI_TRB_ERROR_TRB; 1769 goto errout; 1770 } 1771 setup_trb = trb; 1772 1773 val = trb->qwTrb0; 1774 if (!xfer->ureq) 1775 xfer->ureq = malloc( 1776 sizeof(struct usb_device_request)); 1777 memcpy(xfer->ureq, &val, 1778 sizeof(struct usb_device_request)); 1779 1780 xfer_block = usb_data_xfer_append(xfer, NULL, 0, 1781 (void *)addr, ccs); 1782 xfer_block->processed = 1; 1783 break; 1784 1785 case XHCI_TRB_TYPE_NORMAL: 1786 case XHCI_TRB_TYPE_ISOCH: 1787 if (setup_trb != NULL) { 1788 DPRINTF(("pci_xhci: trb not supposed to be in " 1789 "ctl scope")); 1790 err = XHCI_TRB_ERROR_TRB; 1791 goto errout; 1792 } 1793 /* fall through */ 1794 1795 case XHCI_TRB_TYPE_DATA_STAGE: 1796 xfer_block = usb_data_xfer_append(xfer, 1797 (void *)(trbflags & XHCI_TRB_3_IDT_BIT ? 1798 &trb->qwTrb0 : XHCI_GADDR(sc, trb->qwTrb0)), 1799 trb->dwTrb2 & 0x1FFFF, (void *)addr, ccs); 1800 break; 1801 1802 case XHCI_TRB_TYPE_STATUS_STAGE: 1803 xfer_block = usb_data_xfer_append(xfer, NULL, 0, 1804 (void *)addr, ccs); 1805 break; 1806 1807 case XHCI_TRB_TYPE_NOOP: 1808 xfer_block = usb_data_xfer_append(xfer, NULL, 0, 1809 (void *)addr, ccs); 1810 xfer_block->processed = 1; 1811 break; 1812 1813 case XHCI_TRB_TYPE_EVENT_DATA: 1814 xfer_block = usb_data_xfer_append(xfer, NULL, 0, 1815 (void *)addr, ccs); 1816 if ((epid > 1) && (trbflags & XHCI_TRB_3_IOC_BIT)) { 1817 xfer_block->processed = 1; 1818 } 1819 break; 1820 1821 default: 1822 DPRINTF(("pci_xhci: handle xfer unexpected trb type " 1823 "0x%x", 1824 XHCI_TRB_3_TYPE_GET(trbflags))); 1825 err = XHCI_TRB_ERROR_TRB; 1826 goto errout; 1827 } 1828 1829 trb = pci_xhci_trb_next(sc, trb, &addr); 1830 1831 DPRINTF(("pci_xhci: next trb: 0x%lx", (uint64_t)trb)); 1832 1833 if (xfer_block) { 1834 xfer_block->trbnext = addr; 1835 xfer_block->streamid = streamid; 1836 } 1837 1838 if (!setup_trb && !(trbflags & XHCI_TRB_3_CHAIN_BIT) && 1839 XHCI_TRB_3_TYPE_GET(trbflags) != XHCI_TRB_TYPE_LINK) { 1840 break; 1841 } 1842 1843 /* handle current batch that requires interrupt on complete */ 1844 if (trbflags & XHCI_TRB_3_IOC_BIT) { 1845 DPRINTF(("pci_xhci: trb IOC bit set")); 1846 if (epid == 1) 1847 do_retry = 1; 1848 break; 1849 } 1850 } 1851 1852 DPRINTF(("pci_xhci[%d]: xfer->ndata %u", __LINE__, xfer->ndata)); 1853 1854 if (xfer->ndata <= 0) 1855 goto errout; 1856 1857 if (epid == 1) { 1858 err = USB_ERR_NOT_STARTED; 1859 if (dev->dev_ue->ue_request != NULL) 1860 err = dev->dev_ue->ue_request(dev->dev_sc, xfer); 1861 setup_trb = NULL; 1862 } else { 1863 /* handle data transfer */ 1864 pci_xhci_try_usb_xfer(sc, dev, devep, ep_ctx, slot, epid); 1865 err = XHCI_TRB_ERROR_SUCCESS; 1866 goto errout; 1867 } 1868 1869 err = USB_TO_XHCI_ERR(err); 1870 if ((err == XHCI_TRB_ERROR_SUCCESS) || 1871 (err == XHCI_TRB_ERROR_STALL) || 1872 (err == XHCI_TRB_ERROR_SHORT_PKT)) { 1873 err = pci_xhci_xfer_complete(sc, xfer, slot, epid, &do_intr); 1874 if (err != XHCI_TRB_ERROR_SUCCESS) 1875 do_retry = 0; 1876 } 1877 1878 errout: 1879 if (err == XHCI_TRB_ERROR_EV_RING_FULL) 1880 DPRINTF(("pci_xhci[%d]: event ring full", __LINE__)); 1881 1882 if (!do_retry) 1883 USB_DATA_XFER_UNLOCK(xfer); 1884 1885 if (do_intr) 1886 pci_xhci_assert_interrupt(sc); 1887 1888 if (do_retry) { 1889 USB_DATA_XFER_RESET(xfer); 1890 DPRINTF(("pci_xhci[%d]: retry:continuing with next TRBs", 1891 __LINE__)); 1892 goto retry; 1893 } 1894 1895 if (epid == 1) 1896 USB_DATA_XFER_RESET(xfer); 1897 1898 return (err); 1899 } 1900 1901 static void 1902 pci_xhci_device_doorbell(struct pci_xhci_softc *sc, uint32_t slot, 1903 uint32_t epid, uint32_t streamid) 1904 { 1905 struct pci_xhci_dev_emu *dev; 1906 struct pci_xhci_dev_ep *devep; 1907 struct xhci_dev_ctx *dev_ctx; 1908 struct xhci_endp_ctx *ep_ctx; 1909 struct pci_xhci_trb_ring *sctx_tr; 1910 struct xhci_trb *trb; 1911 uint64_t ringaddr; 1912 uint32_t ccs; 1913 1914 DPRINTF(("pci_xhci doorbell slot %u epid %u stream %u", 1915 slot, epid, streamid)); 1916 1917 if (slot == 0 || slot > XHCI_MAX_SLOTS) { 1918 DPRINTF(("pci_xhci: invalid doorbell slot %u", slot)); 1919 return; 1920 } 1921 1922 if (epid == 0 || epid >= XHCI_MAX_ENDPOINTS) { 1923 DPRINTF(("pci_xhci: invalid endpoint %u", epid)); 1924 return; 1925 } 1926 1927 dev = XHCI_SLOTDEV_PTR(sc, slot); 1928 devep = &dev->eps[epid]; 1929 dev_ctx = pci_xhci_get_dev_ctx(sc, slot); 1930 if (!dev_ctx) { 1931 return; 1932 } 1933 ep_ctx = &dev_ctx->ctx_ep[epid]; 1934 1935 sctx_tr = NULL; 1936 1937 DPRINTF(("pci_xhci: device doorbell ep[%u] %08x %08x %016lx %08x", 1938 epid, ep_ctx->dwEpCtx0, ep_ctx->dwEpCtx1, ep_ctx->qwEpCtx2, 1939 ep_ctx->dwEpCtx4)); 1940 1941 if (ep_ctx->qwEpCtx2 == 0) 1942 return; 1943 1944 /* handle pending transfers */ 1945 if (devep->ep_xfer->ndata > 0) { 1946 #ifndef __FreeBSD__ 1947 USB_DATA_XFER_LOCK(devep->ep_xfer); 1948 #endif 1949 pci_xhci_try_usb_xfer(sc, dev, devep, ep_ctx, slot, epid); 1950 #ifndef __FreeBSD__ 1951 USB_DATA_XFER_UNLOCK(devep->ep_xfer); 1952 #endif 1953 return; 1954 } 1955 1956 /* get next trb work item */ 1957 if (XHCI_EPCTX_0_MAXP_STREAMS_GET(ep_ctx->dwEpCtx0) != 0) { 1958 struct xhci_stream_ctx *sctx; 1959 1960 /* 1961 * Stream IDs of 0, 65535 (any stream), and 65534 1962 * (prime) are invalid. 1963 */ 1964 if (streamid == 0 || streamid == 65534 || streamid == 65535) { 1965 DPRINTF(("pci_xhci: invalid stream %u", streamid)); 1966 return; 1967 } 1968 1969 sctx = NULL; 1970 pci_xhci_find_stream(sc, ep_ctx, streamid, &sctx); 1971 if (sctx == NULL) { 1972 DPRINTF(("pci_xhci: invalid stream %u", streamid)); 1973 return; 1974 } 1975 sctx_tr = &devep->ep_sctx_trbs[streamid]; 1976 ringaddr = sctx_tr->ringaddr; 1977 ccs = sctx_tr->ccs; 1978 trb = XHCI_GADDR(sc, sctx_tr->ringaddr & ~0xFUL); 1979 DPRINTF(("doorbell, stream %u, ccs %lx, trb ccs %x", 1980 streamid, ep_ctx->qwEpCtx2 & XHCI_TRB_3_CYCLE_BIT, 1981 trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT)); 1982 } else { 1983 if (streamid != 0) { 1984 DPRINTF(("pci_xhci: invalid stream %u", streamid)); 1985 return; 1986 } 1987 ringaddr = devep->ep_ringaddr; 1988 ccs = devep->ep_ccs; 1989 trb = devep->ep_tr; 1990 DPRINTF(("doorbell, ccs %lx, trb ccs %x", 1991 ep_ctx->qwEpCtx2 & XHCI_TRB_3_CYCLE_BIT, 1992 trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT)); 1993 } 1994 1995 if (XHCI_TRB_3_TYPE_GET(trb->dwTrb3) == 0) { 1996 DPRINTF(("pci_xhci: ring %lx trb[%lx] EP %u is RESERVED?", 1997 ep_ctx->qwEpCtx2, devep->ep_ringaddr, epid)); 1998 return; 1999 } 2000 2001 pci_xhci_handle_transfer(sc, dev, devep, ep_ctx, trb, slot, epid, 2002 ringaddr, ccs, streamid); 2003 } 2004 2005 static void 2006 pci_xhci_dbregs_write(struct pci_xhci_softc *sc, uint64_t offset, 2007 uint64_t value) 2008 { 2009 2010 offset = (offset - sc->dboff) / sizeof(uint32_t); 2011 2012 DPRINTF(("pci_xhci: doorbell write offset 0x%lx: 0x%lx", 2013 offset, value)); 2014 2015 if (XHCI_HALTED(sc)) { 2016 DPRINTF(("pci_xhci: controller halted")); 2017 return; 2018 } 2019 2020 if (offset == 0) 2021 pci_xhci_complete_commands(sc); 2022 else if (sc->portregs != NULL) 2023 pci_xhci_device_doorbell(sc, offset, 2024 XHCI_DB_TARGET_GET(value), XHCI_DB_SID_GET(value)); 2025 } 2026 2027 static void 2028 pci_xhci_rtsregs_write(struct pci_xhci_softc *sc, uint64_t offset, 2029 uint64_t value) 2030 { 2031 struct pci_xhci_rtsregs *rts; 2032 2033 offset -= sc->rtsoff; 2034 2035 if (offset == 0) { 2036 DPRINTF(("pci_xhci attempted write to MFINDEX")); 2037 return; 2038 } 2039 2040 DPRINTF(("pci_xhci: runtime regs write offset 0x%lx: 0x%lx", 2041 offset, value)); 2042 2043 offset -= 0x20; /* start of intrreg */ 2044 2045 rts = &sc->rtsregs; 2046 2047 switch (offset) { 2048 case 0x00: 2049 if (value & XHCI_IMAN_INTR_PEND) 2050 rts->intrreg.iman &= ~XHCI_IMAN_INTR_PEND; 2051 rts->intrreg.iman = (value & XHCI_IMAN_INTR_ENA) | 2052 (rts->intrreg.iman & XHCI_IMAN_INTR_PEND); 2053 2054 if (!(value & XHCI_IMAN_INTR_ENA)) 2055 pci_xhci_deassert_interrupt(sc); 2056 2057 break; 2058 2059 case 0x04: 2060 rts->intrreg.imod = value; 2061 break; 2062 2063 case 0x08: 2064 rts->intrreg.erstsz = value & 0xFFFF; 2065 break; 2066 2067 case 0x10: 2068 /* ERSTBA low bits */ 2069 rts->intrreg.erstba = MASK_64_HI(sc->rtsregs.intrreg.erstba) | 2070 (value & ~0x3F); 2071 break; 2072 2073 case 0x14: 2074 /* ERSTBA high bits */ 2075 rts->intrreg.erstba = (value << 32) | 2076 MASK_64_LO(sc->rtsregs.intrreg.erstba); 2077 2078 rts->erstba_p = XHCI_GADDR(sc, 2079 sc->rtsregs.intrreg.erstba & ~0x3FUL); 2080 2081 rts->erst_p = XHCI_GADDR(sc, 2082 sc->rtsregs.erstba_p->qwEvrsTablePtr & ~0x3FUL); 2083 2084 rts->er_enq_idx = 0; 2085 rts->er_events_cnt = 0; 2086 2087 DPRINTF(("pci_xhci: wr erstba erst (%p) ptr 0x%lx, sz %u", 2088 rts->erstba_p, 2089 rts->erstba_p->qwEvrsTablePtr, 2090 rts->erstba_p->dwEvrsTableSize)); 2091 break; 2092 2093 case 0x18: 2094 /* ERDP low bits */ 2095 rts->intrreg.erdp = 2096 MASK_64_HI(sc->rtsregs.intrreg.erdp) | 2097 (rts->intrreg.erdp & XHCI_ERDP_LO_BUSY) | 2098 (value & ~0xF); 2099 if (value & XHCI_ERDP_LO_BUSY) { 2100 rts->intrreg.erdp &= ~XHCI_ERDP_LO_BUSY; 2101 rts->intrreg.iman &= ~XHCI_IMAN_INTR_PEND; 2102 } 2103 2104 rts->er_deq_seg = XHCI_ERDP_LO_SINDEX(value); 2105 2106 break; 2107 2108 case 0x1C: 2109 /* ERDP high bits */ 2110 rts->intrreg.erdp = (value << 32) | 2111 MASK_64_LO(sc->rtsregs.intrreg.erdp); 2112 2113 if (rts->er_events_cnt > 0) { 2114 uint64_t erdp; 2115 uint32_t erdp_i; 2116 2117 erdp = rts->intrreg.erdp & ~0xF; 2118 erdp_i = (erdp - rts->erstba_p->qwEvrsTablePtr) / 2119 sizeof(struct xhci_trb); 2120 2121 if (erdp_i <= rts->er_enq_idx) 2122 rts->er_events_cnt = rts->er_enq_idx - erdp_i; 2123 else 2124 rts->er_events_cnt = 2125 rts->erstba_p->dwEvrsTableSize - 2126 (erdp_i - rts->er_enq_idx); 2127 2128 DPRINTF(("pci_xhci: erdp 0x%lx, events cnt %u", 2129 erdp, rts->er_events_cnt)); 2130 } 2131 2132 break; 2133 2134 default: 2135 DPRINTF(("pci_xhci attempted write to RTS offset 0x%lx", 2136 offset)); 2137 break; 2138 } 2139 } 2140 2141 static uint64_t 2142 pci_xhci_portregs_read(struct pci_xhci_softc *sc, uint64_t offset) 2143 { 2144 int port; 2145 uint32_t *p; 2146 2147 if (sc->portregs == NULL) 2148 return (0); 2149 2150 port = (offset - 0x3F0) / 0x10; 2151 2152 if (port > XHCI_MAX_DEVS) { 2153 DPRINTF(("pci_xhci: portregs_read port %d >= XHCI_MAX_DEVS", 2154 port)); 2155 2156 /* return default value for unused port */ 2157 return (XHCI_PS_SPEED_SET(3)); 2158 } 2159 2160 offset = (offset - 0x3F0) % 0x10; 2161 2162 p = &sc->portregs[port].portsc; 2163 p += offset / sizeof(uint32_t); 2164 2165 DPRINTF(("pci_xhci: portregs read offset 0x%lx port %u -> 0x%x", 2166 offset, port, *p)); 2167 2168 return (*p); 2169 } 2170 2171 static void 2172 pci_xhci_hostop_write(struct pci_xhci_softc *sc, uint64_t offset, 2173 uint64_t value) 2174 { 2175 offset -= XHCI_CAPLEN; 2176 2177 if (offset < 0x400) 2178 DPRINTF(("pci_xhci: hostop write offset 0x%lx: 0x%lx", 2179 offset, value)); 2180 2181 switch (offset) { 2182 case XHCI_USBCMD: 2183 sc->opregs.usbcmd = pci_xhci_usbcmd_write(sc, value & 0x3F0F); 2184 break; 2185 2186 case XHCI_USBSTS: 2187 /* clear bits on write */ 2188 sc->opregs.usbsts &= ~(value & 2189 (XHCI_STS_HSE|XHCI_STS_EINT|XHCI_STS_PCD|XHCI_STS_SSS| 2190 XHCI_STS_RSS|XHCI_STS_SRE|XHCI_STS_CNR)); 2191 break; 2192 2193 case XHCI_PAGESIZE: 2194 /* read only */ 2195 break; 2196 2197 case XHCI_DNCTRL: 2198 sc->opregs.dnctrl = value & 0xFFFF; 2199 break; 2200 2201 case XHCI_CRCR_LO: 2202 if (sc->opregs.crcr & XHCI_CRCR_LO_CRR) { 2203 sc->opregs.crcr &= ~(XHCI_CRCR_LO_CS|XHCI_CRCR_LO_CA); 2204 sc->opregs.crcr |= value & 2205 (XHCI_CRCR_LO_CS|XHCI_CRCR_LO_CA); 2206 } else { 2207 sc->opregs.crcr = MASK_64_HI(sc->opregs.crcr) | 2208 (value & (0xFFFFFFC0 | XHCI_CRCR_LO_RCS)); 2209 } 2210 break; 2211 2212 case XHCI_CRCR_HI: 2213 if (!(sc->opregs.crcr & XHCI_CRCR_LO_CRR)) { 2214 sc->opregs.crcr = MASK_64_LO(sc->opregs.crcr) | 2215 (value << 32); 2216 2217 sc->opregs.cr_p = XHCI_GADDR(sc, 2218 sc->opregs.crcr & ~0xF); 2219 } 2220 2221 if (sc->opregs.crcr & XHCI_CRCR_LO_CS) { 2222 /* Stop operation of Command Ring */ 2223 } 2224 2225 if (sc->opregs.crcr & XHCI_CRCR_LO_CA) { 2226 /* Abort command */ 2227 } 2228 2229 break; 2230 2231 case XHCI_DCBAAP_LO: 2232 sc->opregs.dcbaap = MASK_64_HI(sc->opregs.dcbaap) | 2233 (value & 0xFFFFFFC0); 2234 break; 2235 2236 case XHCI_DCBAAP_HI: 2237 sc->opregs.dcbaap = MASK_64_LO(sc->opregs.dcbaap) | 2238 (value << 32); 2239 sc->opregs.dcbaa_p = XHCI_GADDR(sc, sc->opregs.dcbaap & ~0x3FUL); 2240 2241 DPRINTF(("pci_xhci: opregs dcbaap = 0x%lx (vaddr 0x%lx)", 2242 sc->opregs.dcbaap, (uint64_t)sc->opregs.dcbaa_p)); 2243 break; 2244 2245 case XHCI_CONFIG: 2246 sc->opregs.config = value & 0x03FF; 2247 break; 2248 2249 default: 2250 if (offset >= 0x400) 2251 pci_xhci_portregs_write(sc, offset, value); 2252 2253 break; 2254 } 2255 } 2256 2257 2258 static void 2259 pci_xhci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, 2260 int baridx, uint64_t offset, int size, uint64_t value) 2261 { 2262 struct pci_xhci_softc *sc; 2263 2264 sc = pi->pi_arg; 2265 2266 assert(baridx == 0); 2267 2268 2269 pthread_mutex_lock(&sc->mtx); 2270 if (offset < XHCI_CAPLEN) /* read only registers */ 2271 WPRINTF(("pci_xhci: write RO-CAPs offset %ld", offset)); 2272 else if (offset < sc->dboff) 2273 pci_xhci_hostop_write(sc, offset, value); 2274 else if (offset < sc->rtsoff) 2275 pci_xhci_dbregs_write(sc, offset, value); 2276 else if (offset < sc->regsend) 2277 pci_xhci_rtsregs_write(sc, offset, value); 2278 else 2279 WPRINTF(("pci_xhci: write invalid offset %ld", offset)); 2280 2281 pthread_mutex_unlock(&sc->mtx); 2282 } 2283 2284 static uint64_t 2285 pci_xhci_hostcap_read(struct pci_xhci_softc *sc, uint64_t offset) 2286 { 2287 uint64_t value; 2288 2289 switch (offset) { 2290 case XHCI_CAPLENGTH: /* 0x00 */ 2291 value = sc->caplength; 2292 break; 2293 2294 case XHCI_HCSPARAMS1: /* 0x04 */ 2295 value = sc->hcsparams1; 2296 break; 2297 2298 case XHCI_HCSPARAMS2: /* 0x08 */ 2299 value = sc->hcsparams2; 2300 break; 2301 2302 case XHCI_HCSPARAMS3: /* 0x0C */ 2303 value = sc->hcsparams3; 2304 break; 2305 2306 case XHCI_HCSPARAMS0: /* 0x10 */ 2307 value = sc->hccparams1; 2308 break; 2309 2310 case XHCI_DBOFF: /* 0x14 */ 2311 value = sc->dboff; 2312 break; 2313 2314 case XHCI_RTSOFF: /* 0x18 */ 2315 value = sc->rtsoff; 2316 break; 2317 2318 case XHCI_HCCPRAMS2: /* 0x1C */ 2319 value = sc->hccparams2; 2320 break; 2321 2322 default: 2323 value = 0; 2324 break; 2325 } 2326 2327 DPRINTF(("pci_xhci: hostcap read offset 0x%lx -> 0x%lx", 2328 offset, value)); 2329 2330 return (value); 2331 } 2332 2333 static uint64_t 2334 pci_xhci_hostop_read(struct pci_xhci_softc *sc, uint64_t offset) 2335 { 2336 uint64_t value; 2337 2338 offset = (offset - XHCI_CAPLEN); 2339 2340 switch (offset) { 2341 case XHCI_USBCMD: /* 0x00 */ 2342 value = sc->opregs.usbcmd; 2343 break; 2344 2345 case XHCI_USBSTS: /* 0x04 */ 2346 value = sc->opregs.usbsts; 2347 break; 2348 2349 case XHCI_PAGESIZE: /* 0x08 */ 2350 value = sc->opregs.pgsz; 2351 break; 2352 2353 case XHCI_DNCTRL: /* 0x14 */ 2354 value = sc->opregs.dnctrl; 2355 break; 2356 2357 case XHCI_CRCR_LO: /* 0x18 */ 2358 value = sc->opregs.crcr & XHCI_CRCR_LO_CRR; 2359 break; 2360 2361 case XHCI_CRCR_HI: /* 0x1C */ 2362 value = 0; 2363 break; 2364 2365 case XHCI_DCBAAP_LO: /* 0x30 */ 2366 value = sc->opregs.dcbaap & 0xFFFFFFFF; 2367 break; 2368 2369 case XHCI_DCBAAP_HI: /* 0x34 */ 2370 value = (sc->opregs.dcbaap >> 32) & 0xFFFFFFFF; 2371 break; 2372 2373 case XHCI_CONFIG: /* 0x38 */ 2374 value = sc->opregs.config; 2375 break; 2376 2377 default: 2378 if (offset >= 0x400) 2379 value = pci_xhci_portregs_read(sc, offset); 2380 else 2381 value = 0; 2382 2383 break; 2384 } 2385 2386 if (offset < 0x400) 2387 DPRINTF(("pci_xhci: hostop read offset 0x%lx -> 0x%lx", 2388 offset, value)); 2389 2390 return (value); 2391 } 2392 2393 static uint64_t 2394 pci_xhci_dbregs_read(struct pci_xhci_softc *sc, uint64_t offset) 2395 { 2396 2397 /* read doorbell always returns 0 */ 2398 return (0); 2399 } 2400 2401 static uint64_t 2402 pci_xhci_rtsregs_read(struct pci_xhci_softc *sc, uint64_t offset) 2403 { 2404 uint32_t value; 2405 2406 offset -= sc->rtsoff; 2407 value = 0; 2408 2409 if (offset == XHCI_MFINDEX) { 2410 value = sc->rtsregs.mfindex; 2411 } else if (offset >= 0x20) { 2412 int item; 2413 uint32_t *p; 2414 2415 offset -= 0x20; 2416 item = offset % 32; 2417 2418 assert(offset < sizeof(sc->rtsregs.intrreg)); 2419 2420 p = &sc->rtsregs.intrreg.iman; 2421 p += item / sizeof(uint32_t); 2422 value = *p; 2423 } 2424 2425 DPRINTF(("pci_xhci: rtsregs read offset 0x%lx -> 0x%x", 2426 offset, value)); 2427 2428 return (value); 2429 } 2430 2431 static uint64_t 2432 pci_xhci_xecp_read(struct pci_xhci_softc *sc, uint64_t offset) 2433 { 2434 uint32_t value; 2435 2436 offset -= sc->regsend; 2437 value = 0; 2438 2439 switch (offset) { 2440 case 0: 2441 /* rev major | rev minor | next-cap | cap-id */ 2442 value = (0x02 << 24) | (4 << 8) | XHCI_ID_PROTOCOLS; 2443 break; 2444 case 4: 2445 /* name string = "USB" */ 2446 value = 0x20425355; 2447 break; 2448 case 8: 2449 /* psic | proto-defined | compat # | compat offset */ 2450 value = ((XHCI_MAX_DEVS/2) << 8) | sc->usb2_port_start; 2451 break; 2452 case 12: 2453 break; 2454 case 16: 2455 /* rev major | rev minor | next-cap | cap-id */ 2456 value = (0x03 << 24) | XHCI_ID_PROTOCOLS; 2457 break; 2458 case 20: 2459 /* name string = "USB" */ 2460 value = 0x20425355; 2461 break; 2462 case 24: 2463 /* psic | proto-defined | compat # | compat offset */ 2464 value = ((XHCI_MAX_DEVS/2) << 8) | sc->usb3_port_start; 2465 break; 2466 case 28: 2467 break; 2468 default: 2469 DPRINTF(("pci_xhci: xecp invalid offset 0x%lx", offset)); 2470 break; 2471 } 2472 2473 DPRINTF(("pci_xhci: xecp read offset 0x%lx -> 0x%x", 2474 offset, value)); 2475 2476 return (value); 2477 } 2478 2479 2480 static uint64_t 2481 pci_xhci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2482 uint64_t offset, int size) 2483 { 2484 struct pci_xhci_softc *sc; 2485 uint32_t value; 2486 2487 sc = pi->pi_arg; 2488 2489 assert(baridx == 0); 2490 2491 pthread_mutex_lock(&sc->mtx); 2492 if (offset < XHCI_CAPLEN) 2493 value = pci_xhci_hostcap_read(sc, offset); 2494 else if (offset < sc->dboff) 2495 value = pci_xhci_hostop_read(sc, offset); 2496 else if (offset < sc->rtsoff) 2497 value = pci_xhci_dbregs_read(sc, offset); 2498 else if (offset < sc->regsend) 2499 value = pci_xhci_rtsregs_read(sc, offset); 2500 else if (offset < (sc->regsend + 4*32)) 2501 value = pci_xhci_xecp_read(sc, offset); 2502 else { 2503 value = 0; 2504 WPRINTF(("pci_xhci: read invalid offset %ld", offset)); 2505 } 2506 2507 pthread_mutex_unlock(&sc->mtx); 2508 2509 switch (size) { 2510 case 1: 2511 value &= 0xFF; 2512 break; 2513 case 2: 2514 value &= 0xFFFF; 2515 break; 2516 case 4: 2517 value &= 0xFFFFFFFF; 2518 break; 2519 } 2520 2521 return (value); 2522 } 2523 2524 static void 2525 pci_xhci_reset_port(struct pci_xhci_softc *sc, int portn, int warm) 2526 { 2527 struct pci_xhci_portregs *port; 2528 struct pci_xhci_dev_emu *dev; 2529 struct xhci_trb evtrb; 2530 int error; 2531 2532 assert(portn <= XHCI_MAX_DEVS); 2533 2534 DPRINTF(("xhci reset port %d", portn)); 2535 2536 port = XHCI_PORTREG_PTR(sc, portn); 2537 dev = XHCI_DEVINST_PTR(sc, portn); 2538 if (dev) { 2539 port->portsc &= ~(XHCI_PS_PLS_MASK | XHCI_PS_PR | XHCI_PS_PRC); 2540 port->portsc |= XHCI_PS_PED | 2541 XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed); 2542 2543 if (warm && dev->dev_ue->ue_usbver == 3) { 2544 port->portsc |= XHCI_PS_WRC; 2545 } 2546 2547 if ((port->portsc & XHCI_PS_PRC) == 0) { 2548 port->portsc |= XHCI_PS_PRC; 2549 2550 pci_xhci_set_evtrb(&evtrb, portn, 2551 XHCI_TRB_ERROR_SUCCESS, 2552 XHCI_TRB_EVENT_PORT_STS_CHANGE); 2553 error = pci_xhci_insert_event(sc, &evtrb, 1); 2554 if (error != XHCI_TRB_ERROR_SUCCESS) 2555 DPRINTF(("xhci reset port insert event " 2556 "failed")); 2557 } 2558 } 2559 } 2560 2561 static void 2562 pci_xhci_init_port(struct pci_xhci_softc *sc, int portn) 2563 { 2564 struct pci_xhci_portregs *port; 2565 struct pci_xhci_dev_emu *dev; 2566 2567 port = XHCI_PORTREG_PTR(sc, portn); 2568 dev = XHCI_DEVINST_PTR(sc, portn); 2569 if (dev) { 2570 port->portsc = XHCI_PS_CCS | /* connected */ 2571 XHCI_PS_PP; /* port power */ 2572 2573 if (dev->dev_ue->ue_usbver == 2) { 2574 port->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_POLL) | 2575 XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed); 2576 } else { 2577 port->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_U0) | 2578 XHCI_PS_PED | /* enabled */ 2579 XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed); 2580 } 2581 2582 DPRINTF(("Init port %d 0x%x", portn, port->portsc)); 2583 } else { 2584 port->portsc = XHCI_PS_PLS_SET(UPS_PORT_LS_RX_DET) | XHCI_PS_PP; 2585 DPRINTF(("Init empty port %d 0x%x", portn, port->portsc)); 2586 } 2587 } 2588 2589 static int 2590 pci_xhci_dev_intr(struct usb_hci *hci, int epctx) 2591 { 2592 struct pci_xhci_dev_emu *dev; 2593 struct xhci_dev_ctx *dev_ctx; 2594 struct xhci_trb evtrb; 2595 struct pci_xhci_softc *sc; 2596 struct pci_xhci_portregs *p; 2597 struct xhci_endp_ctx *ep_ctx; 2598 int error = 0; 2599 int dir_in; 2600 int epid; 2601 2602 dir_in = epctx & 0x80; 2603 epid = epctx & ~0x80; 2604 2605 /* HW endpoint contexts are 0-15; convert to epid based on dir */ 2606 epid = (epid * 2) + (dir_in ? 1 : 0); 2607 2608 assert(epid >= 1 && epid <= 31); 2609 2610 dev = hci->hci_sc; 2611 sc = dev->xsc; 2612 2613 /* check if device is ready; OS has to initialise it */ 2614 if (sc->rtsregs.erstba_p == NULL || 2615 (sc->opregs.usbcmd & XHCI_CMD_RS) == 0 || 2616 dev->dev_ctx == NULL) 2617 return (0); 2618 2619 p = XHCI_PORTREG_PTR(sc, hci->hci_port); 2620 2621 /* raise event if link U3 (suspended) state */ 2622 if (XHCI_PS_PLS_GET(p->portsc) == 3) { 2623 p->portsc &= ~XHCI_PS_PLS_MASK; 2624 p->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_RESUME); 2625 if ((p->portsc & XHCI_PS_PLC) != 0) 2626 return (0); 2627 2628 p->portsc |= XHCI_PS_PLC; 2629 2630 pci_xhci_set_evtrb(&evtrb, hci->hci_port, 2631 XHCI_TRB_ERROR_SUCCESS, XHCI_TRB_EVENT_PORT_STS_CHANGE); 2632 error = pci_xhci_insert_event(sc, &evtrb, 0); 2633 if (error != XHCI_TRB_ERROR_SUCCESS) 2634 goto done; 2635 } 2636 2637 dev_ctx = dev->dev_ctx; 2638 ep_ctx = &dev_ctx->ctx_ep[epid]; 2639 if ((ep_ctx->dwEpCtx0 & 0x7) == XHCI_ST_EPCTX_DISABLED) { 2640 DPRINTF(("xhci device interrupt on disabled endpoint %d", 2641 epid)); 2642 return (0); 2643 } 2644 2645 DPRINTF(("xhci device interrupt on endpoint %d", epid)); 2646 2647 pci_xhci_device_doorbell(sc, hci->hci_port, epid, 0); 2648 2649 done: 2650 return (error); 2651 } 2652 2653 static int 2654 pci_xhci_dev_event(struct usb_hci *hci, enum hci_usbev evid, void *param) 2655 { 2656 2657 DPRINTF(("xhci device event port %d", hci->hci_port)); 2658 return (0); 2659 } 2660 2661 /* 2662 * Each controller contains a "slot" node which contains a list of 2663 * child nodes each of which is a device. Each slot node's name 2664 * corresponds to a specific controller slot. These nodes 2665 * contain a "device" variable identifying the device model of the 2666 * USB device. For example: 2667 * 2668 * pci.0.1.0 2669 * .device="xhci" 2670 * .slot 2671 * .1 2672 * .device="tablet" 2673 */ 2674 static int 2675 pci_xhci_legacy_config(nvlist_t *nvl, const char *opts) 2676 { 2677 char node_name[16]; 2678 nvlist_t *slots_nvl, *slot_nvl; 2679 char *cp, *opt, *str, *tofree; 2680 int slot; 2681 2682 if (opts == NULL) 2683 return (0); 2684 2685 slots_nvl = create_relative_config_node(nvl, "slot"); 2686 slot = 1; 2687 tofree = str = strdup(opts); 2688 while ((opt = strsep(&str, ",")) != NULL) { 2689 /* device[=<config>] */ 2690 cp = strchr(opt, '='); 2691 if (cp != NULL) { 2692 *cp = '\0'; 2693 cp++; 2694 } 2695 2696 snprintf(node_name, sizeof(node_name), "%d", slot); 2697 slot++; 2698 slot_nvl = create_relative_config_node(slots_nvl, node_name); 2699 set_config_value_node(slot_nvl, "device", opt); 2700 2701 /* 2702 * NB: Given that we split on commas above, the legacy 2703 * format only supports a single option. 2704 */ 2705 if (cp != NULL && *cp != '\0') 2706 pci_parse_legacy_config(slot_nvl, cp); 2707 } 2708 free(tofree); 2709 return (0); 2710 } 2711 2712 static int 2713 pci_xhci_parse_devices(struct pci_xhci_softc *sc, nvlist_t *nvl) 2714 { 2715 struct pci_xhci_dev_emu *dev; 2716 struct usb_devemu *ue; 2717 const nvlist_t *slots_nvl, *slot_nvl; 2718 const char *name, *device; 2719 char *cp; 2720 void *devsc, *cookie; 2721 long slot; 2722 int type, usb3_port, usb2_port, i, ndevices; 2723 2724 usb3_port = sc->usb3_port_start; 2725 usb2_port = sc->usb2_port_start; 2726 2727 sc->devices = calloc(XHCI_MAX_DEVS, sizeof(struct pci_xhci_dev_emu *)); 2728 sc->slots = calloc(XHCI_MAX_SLOTS, sizeof(struct pci_xhci_dev_emu *)); 2729 2730 /* port and slot numbering start from 1 */ 2731 sc->devices--; 2732 sc->slots--; 2733 2734 ndevices = 0; 2735 2736 slots_nvl = find_relative_config_node(nvl, "slot"); 2737 if (slots_nvl == NULL) 2738 goto portsfinal; 2739 2740 cookie = NULL; 2741 while ((name = nvlist_next(slots_nvl, &type, &cookie)) != NULL) { 2742 if (usb2_port == ((sc->usb2_port_start) + XHCI_MAX_DEVS/2) || 2743 usb3_port == ((sc->usb3_port_start) + XHCI_MAX_DEVS/2)) { 2744 WPRINTF(("pci_xhci max number of USB 2 or 3 " 2745 "devices reached, max %d", XHCI_MAX_DEVS/2)); 2746 goto bad; 2747 } 2748 2749 if (type != NV_TYPE_NVLIST) { 2750 EPRINTLN( 2751 "pci_xhci: config variable '%s' under slot node", 2752 name); 2753 goto bad; 2754 } 2755 2756 slot = strtol(name, &cp, 0); 2757 if (*cp != '\0' || slot <= 0 || slot > XHCI_MAX_SLOTS) { 2758 EPRINTLN("pci_xhci: invalid slot '%s'", name); 2759 goto bad; 2760 } 2761 2762 if (XHCI_SLOTDEV_PTR(sc, slot) != NULL) { 2763 EPRINTLN("pci_xhci: duplicate slot '%s'", name); 2764 goto bad; 2765 } 2766 2767 slot_nvl = nvlist_get_nvlist(slots_nvl, name); 2768 device = get_config_value_node(slot_nvl, "device"); 2769 if (device == NULL) { 2770 EPRINTLN( 2771 "pci_xhci: missing \"device\" value for slot '%s'", 2772 name); 2773 goto bad; 2774 } 2775 2776 ue = usb_emu_finddev(device); 2777 if (ue == NULL) { 2778 EPRINTLN("pci_xhci: unknown device model \"%s\"", 2779 device); 2780 goto bad; 2781 } 2782 2783 DPRINTF(("pci_xhci adding device %s", device)); 2784 2785 dev = calloc(1, sizeof(struct pci_xhci_dev_emu)); 2786 dev->xsc = sc; 2787 dev->hci.hci_sc = dev; 2788 dev->hci.hci_intr = pci_xhci_dev_intr; 2789 dev->hci.hci_event = pci_xhci_dev_event; 2790 2791 if (ue->ue_usbver == 2) { 2792 if (usb2_port == sc->usb2_port_start + 2793 XHCI_MAX_DEVS / 2) { 2794 WPRINTF(("pci_xhci max number of USB 2 devices " 2795 "reached, max %d", XHCI_MAX_DEVS / 2)); 2796 goto bad; 2797 } 2798 dev->hci.hci_port = usb2_port; 2799 usb2_port++; 2800 } else { 2801 if (usb3_port == sc->usb3_port_start + 2802 XHCI_MAX_DEVS / 2) { 2803 WPRINTF(("pci_xhci max number of USB 3 devices " 2804 "reached, max %d", XHCI_MAX_DEVS / 2)); 2805 goto bad; 2806 } 2807 dev->hci.hci_port = usb3_port; 2808 usb3_port++; 2809 } 2810 XHCI_DEVINST_PTR(sc, dev->hci.hci_port) = dev; 2811 2812 dev->hci.hci_address = 0; 2813 devsc = ue->ue_init(&dev->hci, nvl); 2814 if (devsc == NULL) { 2815 goto bad; 2816 } 2817 2818 dev->dev_ue = ue; 2819 dev->dev_sc = devsc; 2820 2821 XHCI_SLOTDEV_PTR(sc, slot) = dev; 2822 ndevices++; 2823 } 2824 2825 portsfinal: 2826 sc->portregs = calloc(XHCI_MAX_DEVS, sizeof(struct pci_xhci_portregs)); 2827 sc->portregs--; 2828 2829 if (ndevices > 0) { 2830 for (i = 1; i <= XHCI_MAX_DEVS; i++) { 2831 pci_xhci_init_port(sc, i); 2832 } 2833 } else { 2834 WPRINTF(("pci_xhci no USB devices configured")); 2835 } 2836 return (0); 2837 2838 bad: 2839 for (i = 1; i <= XHCI_MAX_DEVS; i++) { 2840 free(XHCI_DEVINST_PTR(sc, i)); 2841 } 2842 2843 free(sc->devices + 1); 2844 free(sc->slots + 1); 2845 2846 return (-1); 2847 } 2848 2849 static int 2850 pci_xhci_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl) 2851 { 2852 struct pci_xhci_softc *sc; 2853 int error; 2854 2855 if (xhci_in_use) { 2856 WPRINTF(("pci_xhci controller already defined")); 2857 return (-1); 2858 } 2859 xhci_in_use = 1; 2860 2861 sc = calloc(1, sizeof(struct pci_xhci_softc)); 2862 pi->pi_arg = sc; 2863 sc->xsc_pi = pi; 2864 2865 sc->usb2_port_start = (XHCI_MAX_DEVS/2) + 1; 2866 sc->usb3_port_start = 1; 2867 2868 /* discover devices */ 2869 error = pci_xhci_parse_devices(sc, nvl); 2870 if (error < 0) 2871 goto done; 2872 else 2873 error = 0; 2874 2875 sc->caplength = XHCI_SET_CAPLEN(XHCI_CAPLEN) | 2876 XHCI_SET_HCIVERSION(0x0100); 2877 sc->hcsparams1 = XHCI_SET_HCSP1_MAXPORTS(XHCI_MAX_DEVS) | 2878 XHCI_SET_HCSP1_MAXINTR(1) | /* interrupters */ 2879 XHCI_SET_HCSP1_MAXSLOTS(XHCI_MAX_SLOTS); 2880 sc->hcsparams2 = XHCI_SET_HCSP2_ERSTMAX(XHCI_ERST_MAX) | 2881 XHCI_SET_HCSP2_IST(0x04); 2882 sc->hcsparams3 = 0; /* no latency */ 2883 sc->hccparams1 = XHCI_SET_HCCP1_AC64(1) | /* 64-bit addrs */ 2884 XHCI_SET_HCCP1_NSS(1) | /* no 2nd-streams */ 2885 XHCI_SET_HCCP1_SPC(1) | /* short packet */ 2886 XHCI_SET_HCCP1_MAXPSA(XHCI_STREAMS_MAX); 2887 sc->hccparams2 = XHCI_SET_HCCP2_LEC(1) | 2888 XHCI_SET_HCCP2_U3C(1); 2889 sc->dboff = XHCI_SET_DOORBELL(XHCI_CAPLEN + XHCI_PORTREGS_START + 2890 XHCI_MAX_DEVS * sizeof(struct pci_xhci_portregs)); 2891 2892 /* dboff must be 32-bit aligned */ 2893 if (sc->dboff & 0x3) 2894 sc->dboff = (sc->dboff + 0x3) & ~0x3; 2895 2896 /* rtsoff must be 32-bytes aligned */ 2897 sc->rtsoff = XHCI_SET_RTSOFFSET(sc->dboff + (XHCI_MAX_SLOTS+1) * 32); 2898 if (sc->rtsoff & 0x1F) 2899 sc->rtsoff = (sc->rtsoff + 0x1F) & ~0x1F; 2900 2901 DPRINTF(("pci_xhci dboff: 0x%x, rtsoff: 0x%x", sc->dboff, 2902 sc->rtsoff)); 2903 2904 sc->opregs.usbsts = XHCI_STS_HCH; 2905 sc->opregs.pgsz = XHCI_PAGESIZE_4K; 2906 2907 pci_xhci_reset(sc); 2908 2909 sc->regsend = sc->rtsoff + 0x20 + 32; /* only 1 intrpter */ 2910 2911 /* 2912 * Set extended capabilities pointer to be after regsend; 2913 * value of xecp field is 32-bit offset. 2914 */ 2915 sc->hccparams1 |= XHCI_SET_HCCP1_XECP(sc->regsend/4); 2916 2917 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x1E31); 2918 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086); 2919 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_SERIALBUS); 2920 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_SERIALBUS_USB); 2921 pci_set_cfgdata8(pi, PCIR_PROGIF,PCIP_SERIALBUS_USB_XHCI); 2922 pci_set_cfgdata8(pi, PCI_USBREV, PCI_USB_REV_3_0); 2923 2924 pci_emul_add_msicap(pi, 1); 2925 2926 /* regsend + xecp registers */ 2927 pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, sc->regsend + 4*32); 2928 DPRINTF(("pci_xhci pci_emu_alloc: %d", sc->regsend + 4*32)); 2929 2930 2931 pci_lintr_request(pi); 2932 2933 pthread_mutex_init(&sc->mtx, NULL); 2934 2935 done: 2936 if (error) { 2937 free(sc); 2938 } 2939 2940 return (error); 2941 } 2942 2943 struct pci_devemu pci_de_xhci = { 2944 .pe_emu = "xhci", 2945 .pe_init = pci_xhci_init, 2946 .pe_legacy_config = pci_xhci_legacy_config, 2947 .pe_barwrite = pci_xhci_write, 2948 .pe_barread = pci_xhci_read 2949 }; 2950 PCI_EMUL_SET(pci_de_xhci); 2951