1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2011 NetApp, Inc.
5 * Copyright (c) 2018 Joyent, Inc.
6 * Copyright 2021 Oxide Computer Company
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 #include <sys/cdefs.h>
32 #ifndef __FreeBSD__
33 #include <errno.h>
34 #include <stdlib.h>
35 #include <stdio.h>
36 #include <strings.h>
37 #include <err.h>
38 #endif
39
40 #include <stdlib.h>
41
42 #include "config.h"
43 #include "pci_emul.h"
44 #ifndef __FreeBSD__
45 #include "bhyverun.h"
46 #endif
47
48 #ifndef __FreeBSD__
49 static struct pci_hostbridge_model {
50 const char *phm_model;
51 uint16_t phm_vendor;
52 uint16_t phm_device;
53 } pci_hb_models[] = {
54 { "amd", 0x1022, 0x7432 }, /* AMD/made-up */
55 { "netapp", 0x1275, 0x1275 }, /* NetApp/NetApp */
56 { "i440fx", 0x8086, 0x1237 }, /* Intel/82441 */
57 { "q35", 0x8086, 0x29b0 }, /* Intel/Q35 HB */
58 };
59
60 #define NUM_HB_MODELS (sizeof (pci_hb_models) / sizeof (pci_hb_models[0]))
61 #endif
62
63 static int
pci_hostbridge_init(struct pci_devinst * pi,nvlist_t * nvl)64 pci_hostbridge_init(struct pci_devinst *pi, nvlist_t *nvl)
65 {
66 const char *value;
67 u_int vendor, device;
68
69 #ifdef __FreeBSD__
70 vendor = 0x1275; /* NetApp */
71 device = 0x1275; /* NetApp */
72 #else
73 vendor = device = 0;
74 #endif
75
76 value = get_config_value_node(nvl, "vendor");
77 if (value != NULL)
78 vendor = strtol(value, NULL, 0);
79 else
80 vendor = pci_config_read_reg(NULL, nvl, PCIR_VENDOR, 2, vendor);
81 value = get_config_value_node(nvl, "devid");
82 if (value != NULL)
83 device = strtol(value, NULL, 0);
84 else
85 device = pci_config_read_reg(NULL, nvl, PCIR_DEVICE, 2, device);
86
87 #ifndef __FreeBSD__
88 const char *model = get_config_value_node(nvl, "model");
89
90 if (model != NULL && (vendor != 0 || device != 0)) {
91 warnx("pci_hostbridge: cannot specify model and vendor/device");
92 return (-1);
93 } else if ((vendor != 0 && device == 0) ||
94 (vendor == 0 && device != 0)) {
95 warnx("pci_hostbridge: must specify both vendor and "
96 "device for custom hostbridge");
97 return (-1);
98 }
99 if (model == NULL && vendor == 0 && device == 0)
100 model = "netapp";
101
102 if (model != NULL) {
103 for (uint_t i = 0; i < NUM_HB_MODELS; i++) {
104 if (strcmp(model, pci_hb_models[i].phm_model) != 0)
105 continue;
106
107 /* found a model match */
108 vendor = pci_hb_models[i].phm_vendor;
109 device = pci_hb_models[i].phm_device;
110 break;
111 }
112 if (vendor == 0) {
113 warnx("pci_hostbridge: invalid model '%s'", model);
114 return (-1);
115 }
116 }
117
118 /* Both i440fx and Q35 chipsets feature the concept of Programmable
119 * Address Memory (PAM), where certain physical address ranges can be
120 * configured to direct reads/writes to either DRAM, or to the PCI MMIO
121 * space instead. At boot, they default to bypassing DRAM, so in order
122 * to cheaply paper over our lack of emulation, the memory in PAM0
123 * (0xf0000-0xfffff, the System BIOS segment) should be zeroed.
124 *
125 * If this emulation is expanded in the future to truly support PAM
126 * behavior, this hack can be removed.
127 */
128 if (vendor == 0x8086 && (device == 0x1237 || device == 0x29b0)) {
129 const uintptr_t start = 0xf0000;
130 const size_t len = 0x10000;
131 void *system_bios_region = paddr_guest2host(pi->pi_vmctx,
132 start, len);
133 assert(system_bios_region != NULL);
134 bzero(system_bios_region, len);
135 }
136 #endif /* !__FreeBSD__ */
137
138 /* config space */
139 pci_set_cfgdata16(pi, PCIR_VENDOR, vendor);
140 pci_set_cfgdata16(pi, PCIR_DEVICE, device);
141 pci_set_cfgdata8(pi, PCIR_HDRTYPE, PCIM_HDRTYPE_NORMAL);
142 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_BRIDGE);
143 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_BRIDGE_HOST);
144
145 pci_emul_add_pciecap(pi, PCIEM_TYPE_ROOT_PORT);
146
147 return (0);
148 }
149
150 static int
pci_amd_hostbridge_legacy_config(nvlist_t * nvl,const char * opts __unused)151 pci_amd_hostbridge_legacy_config(nvlist_t *nvl, const char *opts __unused)
152 {
153 nvlist_t *pci_regs;
154
155 pci_regs = create_relative_config_node(nvl, "pcireg");
156 if (pci_regs == NULL) {
157 warnx("amd_hostbridge: failed to create pciregs node");
158 return (-1);
159 }
160 set_config_value_node(pci_regs, "vendor", "0x1022"); /* AMD */
161 set_config_value_node(pci_regs, "device", "0x7432"); /* made up */
162
163 return (0);
164 }
165
166 static const struct pci_devemu pci_de_amd_hostbridge = {
167 .pe_emu = "amd_hostbridge",
168 .pe_legacy_config = pci_amd_hostbridge_legacy_config,
169 .pe_alias = "hostbridge",
170 };
171 PCI_EMUL_SET(pci_de_amd_hostbridge);
172
173 static const struct pci_devemu pci_de_hostbridge = {
174 .pe_emu = "hostbridge",
175 .pe_init = pci_hostbridge_init,
176 };
177 PCI_EMUL_SET(pci_de_hostbridge);
178