xref: /illumos-gate/usr/src/cmd/bhyve/pci_hda.c (revision 2b948146)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2016 Alex Teaca <iateaca@FreeBSD.org>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  *
28  */
29 
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32 
33 #include <time.h>
34 
35 #include "pci_hda.h"
36 #include "bhyverun.h"
37 #include "config.h"
38 #include "pci_emul.h"
39 #include "hdac_reg.h"
40 
41 /*
42  * HDA defines
43  */
44 #define PCIR_HDCTL		0x40
45 #define INTEL_VENDORID		0x8086
46 #define HDA_INTEL_82801G	0x27d8
47 
48 #define HDA_IOSS_NO		0x08
49 #define HDA_OSS_NO		0x04
50 #define HDA_ISS_NO		0x04
51 #define HDA_CODEC_MAX		0x0f
52 #define HDA_LAST_OFFSET						\
53 	(0x2084 + ((HDA_ISS_NO) * 0x20) + ((HDA_OSS_NO) * 0x20))
54 #define HDA_SET_REG_TABLE_SZ					\
55 	(0x80 + ((HDA_ISS_NO) * 0x20) + ((HDA_OSS_NO) * 0x20))
56 #define HDA_CORB_ENTRY_LEN	0x04
57 #define HDA_RIRB_ENTRY_LEN	0x08
58 #define HDA_BDL_ENTRY_LEN	0x10
59 #define HDA_DMA_PIB_ENTRY_LEN	0x08
60 #define HDA_STREAM_TAGS_CNT	0x10
61 #define HDA_STREAM_REGS_BASE	0x80
62 #define HDA_STREAM_REGS_LEN	0x20
63 
64 #define HDA_DMA_ACCESS_LEN	(sizeof(uint32_t))
65 #define HDA_BDL_MAX_LEN		0x0100
66 
67 #define HDAC_SDSTS_FIFORDY	(1 << 5)
68 
69 #define HDA_RIRBSTS_IRQ_MASK	(HDAC_RIRBSTS_RINTFL | HDAC_RIRBSTS_RIRBOIS)
70 #define HDA_STATESTS_IRQ_MASK	((1 << HDA_CODEC_MAX) - 1)
71 #define HDA_SDSTS_IRQ_MASK					\
72 	(HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS)
73 
74 /*
75  * HDA data structures
76  */
77 
78 struct hda_softc;
79 
80 typedef void (*hda_set_reg_handler)(struct hda_softc *sc, uint32_t offset,
81 		uint32_t old);
82 
83 struct hda_bdle {
84 	uint32_t addrl;
85 	uint32_t addrh;
86 	uint32_t len;
87 	uint32_t ioc;
88 } __packed;
89 
90 struct hda_bdle_desc {
91 	void *addr;
92 	uint8_t ioc;
93 	uint32_t len;
94 };
95 
96 struct hda_codec_cmd_ctl {
97 	char *name;
98 	void *dma_vaddr;
99 	uint8_t run;
100 	uint16_t rp;
101 	uint16_t size;
102 	uint16_t wp;
103 };
104 
105 struct hda_stream_desc {
106 	uint8_t dir;
107 	uint8_t run;
108 	uint8_t stream;
109 
110 	/* bp is the no. of bytes transferred in the current bdle */
111 	uint32_t bp;
112 	/* be is the no. of bdles transferred in the bdl */
113 	uint32_t be;
114 
115 	uint32_t bdl_cnt;
116 	struct hda_bdle_desc bdl[HDA_BDL_MAX_LEN];
117 };
118 
119 struct hda_softc {
120 	struct pci_devinst *pci_dev;
121 	uint32_t regs[HDA_LAST_OFFSET];
122 
123 	uint8_t lintr;
124 	uint8_t rirb_cnt;
125 	uint64_t wall_clock_start;
126 
127 	struct hda_codec_cmd_ctl corb;
128 	struct hda_codec_cmd_ctl rirb;
129 
130 	uint8_t codecs_no;
131 	struct hda_codec_inst *codecs[HDA_CODEC_MAX];
132 
133 	/* Base Address of the DMA Position Buffer */
134 	void *dma_pib_vaddr;
135 
136 	struct hda_stream_desc streams[HDA_IOSS_NO];
137 	/* 2 tables for output and input */
138 	uint8_t stream_map[2][HDA_STREAM_TAGS_CNT];
139 };
140 
141 /*
142  * HDA module function declarations
143  */
144 static inline void hda_set_reg_by_offset(struct hda_softc *sc, uint32_t offset,
145     uint32_t value);
146 static inline uint32_t hda_get_reg_by_offset(struct hda_softc *sc,
147     uint32_t offset);
148 static inline void hda_set_field_by_offset(struct hda_softc *sc,
149     uint32_t offset, uint32_t mask, uint32_t value);
150 
151 static struct hda_softc *hda_init(nvlist_t *nvl);
152 static void hda_update_intr(struct hda_softc *sc);
153 static void hda_response_interrupt(struct hda_softc *sc);
154 static int hda_codec_constructor(struct hda_softc *sc,
155     struct hda_codec_class *codec, const char *play, const char *rec);
156 static struct hda_codec_class *hda_find_codec_class(const char *name);
157 
158 static int hda_send_command(struct hda_softc *sc, uint32_t verb);
159 static int hda_notify_codecs(struct hda_softc *sc, uint8_t run,
160     uint8_t stream, uint8_t dir);
161 static void hda_reset(struct hda_softc *sc);
162 static void hda_reset_regs(struct hda_softc *sc);
163 static void hda_stream_reset(struct hda_softc *sc, uint8_t stream_ind);
164 static int hda_stream_start(struct hda_softc *sc, uint8_t stream_ind);
165 static int hda_stream_stop(struct hda_softc *sc, uint8_t stream_ind);
166 static uint32_t hda_read(struct hda_softc *sc, uint32_t offset);
167 static int hda_write(struct hda_softc *sc, uint32_t offset, uint8_t size,
168     uint32_t value);
169 
170 static inline void hda_print_cmd_ctl_data(struct hda_codec_cmd_ctl *p);
171 static int hda_corb_start(struct hda_softc *sc);
172 static int hda_corb_run(struct hda_softc *sc);
173 static int hda_rirb_start(struct hda_softc *sc);
174 
175 static void *hda_dma_get_vaddr(struct hda_softc *sc, uint64_t dma_paddr,
176     size_t len);
177 static void hda_dma_st_dword(void *dma_vaddr, uint32_t data);
178 static uint32_t hda_dma_ld_dword(void *dma_vaddr);
179 
180 static inline uint8_t hda_get_stream_by_offsets(uint32_t offset,
181     uint8_t reg_offset);
182 static inline uint32_t hda_get_offset_stream(uint8_t stream_ind);
183 
184 static void hda_set_gctl(struct hda_softc *sc, uint32_t offset, uint32_t old);
185 static void hda_set_statests(struct hda_softc *sc, uint32_t offset,
186     uint32_t old);
187 static void hda_set_corbwp(struct hda_softc *sc, uint32_t offset, uint32_t old);
188 static void hda_set_corbctl(struct hda_softc *sc, uint32_t offset,
189     uint32_t old);
190 static void hda_set_rirbctl(struct hda_softc *sc, uint32_t offset,
191     uint32_t old);
192 static void hda_set_rirbsts(struct hda_softc *sc, uint32_t offset,
193     uint32_t old);
194 static void hda_set_dpiblbase(struct hda_softc *sc, uint32_t offset,
195     uint32_t old);
196 static void hda_set_sdctl(struct hda_softc *sc, uint32_t offset, uint32_t old);
197 static void hda_set_sdctl2(struct hda_softc *sc, uint32_t offset, uint32_t old);
198 static void hda_set_sdsts(struct hda_softc *sc, uint32_t offset, uint32_t old);
199 
200 static int hda_signal_state_change(struct hda_codec_inst *hci);
201 static int hda_response(struct hda_codec_inst *hci, uint32_t response,
202     uint8_t unsol);
203 static int hda_transfer(struct hda_codec_inst *hci, uint8_t stream,
204     uint8_t dir, void *buf, size_t count);
205 
206 static void hda_set_pib(struct hda_softc *sc, uint8_t stream_ind, uint32_t pib);
207 static uint64_t hda_get_clock_ns(void);
208 
209 /*
210  * PCI HDA function declarations
211  */
212 static int pci_hda_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl);
213 static void pci_hda_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
214     int baridx, uint64_t offset, int size, uint64_t value);
215 static uint64_t pci_hda_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
216     int baridx, uint64_t offset, int size);
217 /*
218  * HDA global data
219  */
220 
221 static const hda_set_reg_handler hda_set_reg_table[] = {
222 	[HDAC_GCTL] = hda_set_gctl,
223 	[HDAC_STATESTS] = hda_set_statests,
224 	[HDAC_CORBWP] = hda_set_corbwp,
225 	[HDAC_CORBCTL] = hda_set_corbctl,
226 	[HDAC_RIRBCTL] = hda_set_rirbctl,
227 	[HDAC_RIRBSTS] = hda_set_rirbsts,
228 	[HDAC_DPIBLBASE] = hda_set_dpiblbase,
229 
230 #define HDAC_ISTREAM(n, iss, oss)				\
231 	[_HDAC_ISDCTL(n, iss, oss)] = hda_set_sdctl,		\
232 	[_HDAC_ISDCTL(n, iss, oss) + 2] = hda_set_sdctl2,	\
233 	[_HDAC_ISDSTS(n, iss, oss)] = hda_set_sdsts,		\
234 
235 #define HDAC_OSTREAM(n, iss, oss)				\
236 	[_HDAC_OSDCTL(n, iss, oss)] = hda_set_sdctl,		\
237 	[_HDAC_OSDCTL(n, iss, oss) + 2] = hda_set_sdctl2,	\
238 	[_HDAC_OSDSTS(n, iss, oss)] = hda_set_sdsts,		\
239 
240 	HDAC_ISTREAM(0, HDA_ISS_NO, HDA_OSS_NO)
241 	HDAC_ISTREAM(1, HDA_ISS_NO, HDA_OSS_NO)
242 	HDAC_ISTREAM(2, HDA_ISS_NO, HDA_OSS_NO)
243 	HDAC_ISTREAM(3, HDA_ISS_NO, HDA_OSS_NO)
244 
245 	HDAC_OSTREAM(0, HDA_ISS_NO, HDA_OSS_NO)
246 	HDAC_OSTREAM(1, HDA_ISS_NO, HDA_OSS_NO)
247 	HDAC_OSTREAM(2, HDA_ISS_NO, HDA_OSS_NO)
248 	HDAC_OSTREAM(3, HDA_ISS_NO, HDA_OSS_NO)
249 
250 	[HDA_SET_REG_TABLE_SZ] = NULL,
251 };
252 
253 static const uint16_t hda_corb_sizes[] = {
254 	[HDAC_CORBSIZE_CORBSIZE_2]	= 2,
255 	[HDAC_CORBSIZE_CORBSIZE_16]	= 16,
256 	[HDAC_CORBSIZE_CORBSIZE_256]	= 256,
257 	[HDAC_CORBSIZE_CORBSIZE_MASK]	= 0,
258 };
259 
260 static const uint16_t hda_rirb_sizes[] = {
261 	[HDAC_RIRBSIZE_RIRBSIZE_2]	= 2,
262 	[HDAC_RIRBSIZE_RIRBSIZE_16]	= 16,
263 	[HDAC_RIRBSIZE_RIRBSIZE_256]	= 256,
264 	[HDAC_RIRBSIZE_RIRBSIZE_MASK]	= 0,
265 };
266 
267 static struct hda_ops hops = {
268 	.signal		= hda_signal_state_change,
269 	.response	= hda_response,
270 	.transfer	= hda_transfer,
271 };
272 
273 struct pci_devemu pci_de_hda = {
274 	.pe_emu		= "hda",
275 	.pe_init	= pci_hda_init,
276 	.pe_barwrite	= pci_hda_write,
277 	.pe_barread	= pci_hda_read
278 };
279 
280 PCI_EMUL_SET(pci_de_hda);
281 
282 SET_DECLARE(hda_codec_class_set, struct hda_codec_class);
283 
284 #if DEBUG_HDA == 1
285 FILE *dbg;
286 #endif
287 
288 /*
289  * HDA module function definitions
290  */
291 
292 static inline void
hda_set_reg_by_offset(struct hda_softc * sc,uint32_t offset,uint32_t value)293 hda_set_reg_by_offset(struct hda_softc *sc, uint32_t offset, uint32_t value)
294 {
295 	assert(offset < HDA_LAST_OFFSET);
296 	sc->regs[offset] = value;
297 }
298 
299 static inline uint32_t
hda_get_reg_by_offset(struct hda_softc * sc,uint32_t offset)300 hda_get_reg_by_offset(struct hda_softc *sc, uint32_t offset)
301 {
302 	assert(offset < HDA_LAST_OFFSET);
303 	return sc->regs[offset];
304 }
305 
306 static inline void
hda_set_field_by_offset(struct hda_softc * sc,uint32_t offset,uint32_t mask,uint32_t value)307 hda_set_field_by_offset(struct hda_softc *sc, uint32_t offset,
308     uint32_t mask, uint32_t value)
309 {
310 	uint32_t reg_value = 0;
311 
312 	reg_value = hda_get_reg_by_offset(sc, offset);
313 
314 	reg_value &= ~mask;
315 	reg_value |= (value & mask);
316 
317 	hda_set_reg_by_offset(sc, offset, reg_value);
318 }
319 
320 static struct hda_softc *
hda_init(nvlist_t * nvl)321 hda_init(nvlist_t *nvl)
322 {
323 	struct hda_softc *sc = NULL;
324 	struct hda_codec_class *codec = NULL;
325 	const char *value;
326 	char *play;
327 	char *rec;
328 	int err;
329 
330 #if DEBUG_HDA == 1
331 	dbg = fopen("/tmp/bhyve_hda.log", "w+");
332 #endif
333 
334 	sc = calloc(1, sizeof(*sc));
335 	if (!sc)
336 		return (NULL);
337 
338 	hda_reset_regs(sc);
339 
340 	/*
341 	 * TODO search all configured codecs
342 	 * For now we play with one single codec
343 	 */
344 	codec = hda_find_codec_class("hda_codec");
345 	if (codec) {
346 		value = get_config_value_node(nvl, "play");
347 		if (value == NULL)
348 			play = NULL;
349 		else
350 			play = strdup(value);
351 		value = get_config_value_node(nvl, "rec");
352 		if (value == NULL)
353 			rec = NULL;
354 		else
355 			rec = strdup(value);
356 		DPRINTF("play: %s rec: %s", play, rec);
357 		if (play != NULL || rec != NULL) {
358 			err = hda_codec_constructor(sc, codec, play, rec);
359 			assert(!err);
360 		}
361 		free(play);
362 		free(rec);
363 	}
364 
365 	return (sc);
366 }
367 
368 static void
hda_update_intr(struct hda_softc * sc)369 hda_update_intr(struct hda_softc *sc)
370 {
371 	struct pci_devinst *pi = sc->pci_dev;
372 	uint32_t intctl = hda_get_reg_by_offset(sc, HDAC_INTCTL);
373 	uint32_t intsts = 0;
374 	uint32_t sdsts = 0;
375 	uint32_t rirbsts = 0;
376 	uint32_t wakeen = 0;
377 	uint32_t statests = 0;
378 	uint32_t off = 0;
379 	int i;
380 
381 	/* update the CIS bits */
382 	rirbsts = hda_get_reg_by_offset(sc, HDAC_RIRBSTS);
383 	if (rirbsts & (HDAC_RIRBSTS_RINTFL | HDAC_RIRBSTS_RIRBOIS))
384 		intsts |= HDAC_INTSTS_CIS;
385 
386 	wakeen = hda_get_reg_by_offset(sc, HDAC_WAKEEN);
387 	statests = hda_get_reg_by_offset(sc, HDAC_STATESTS);
388 	if (statests & wakeen)
389 		intsts |= HDAC_INTSTS_CIS;
390 
391 	/* update the SIS bits */
392 	for (i = 0; i < HDA_IOSS_NO; i++) {
393 		off = hda_get_offset_stream(i);
394 		sdsts = hda_get_reg_by_offset(sc, off + HDAC_SDSTS);
395 		if (sdsts & HDAC_SDSTS_BCIS)
396 			intsts |= (1 << i);
397 	}
398 
399 	/* update the GIS bit */
400 	if (intsts)
401 		intsts |= HDAC_INTSTS_GIS;
402 
403 	hda_set_reg_by_offset(sc, HDAC_INTSTS, intsts);
404 
405 	if ((intctl & HDAC_INTCTL_GIE) && ((intsts &			\
406 		~HDAC_INTSTS_GIS) & intctl)) {
407 		if (!sc->lintr) {
408 			pci_lintr_assert(pi);
409 			sc->lintr = 1;
410 		}
411 	} else {
412 		if (sc->lintr) {
413 			pci_lintr_deassert(pi);
414 			sc->lintr = 0;
415 		}
416 	}
417 }
418 
419 static void
hda_response_interrupt(struct hda_softc * sc)420 hda_response_interrupt(struct hda_softc *sc)
421 {
422 	uint8_t rirbctl = hda_get_reg_by_offset(sc, HDAC_RIRBCTL);
423 
424 	if ((rirbctl & HDAC_RIRBCTL_RINTCTL) && sc->rirb_cnt) {
425 		sc->rirb_cnt = 0;
426 		hda_set_field_by_offset(sc, HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL,
427 				HDAC_RIRBSTS_RINTFL);
428 		hda_update_intr(sc);
429 	}
430 }
431 
432 static int
hda_codec_constructor(struct hda_softc * sc,struct hda_codec_class * codec,const char * play,const char * rec)433 hda_codec_constructor(struct hda_softc *sc, struct hda_codec_class *codec,
434     const char *play, const char *rec)
435 {
436 	struct hda_codec_inst *hci = NULL;
437 
438 	if (sc->codecs_no >= HDA_CODEC_MAX)
439 		return (-1);
440 
441 	hci = calloc(1, sizeof(struct hda_codec_inst));
442 	if (!hci)
443 		return (-1);
444 
445 	hci->hda = sc;
446 	hci->hops = &hops;
447 	hci->cad = sc->codecs_no;
448 	hci->codec = codec;
449 
450 	sc->codecs[sc->codecs_no++] = hci;
451 
452 	if (!codec->init) {
453 		DPRINTF("This codec does not implement the init function");
454 		return (-1);
455 	}
456 
457 	return (codec->init(hci, play, rec));
458 }
459 
460 static struct hda_codec_class *
hda_find_codec_class(const char * name)461 hda_find_codec_class(const char *name)
462 {
463 	struct hda_codec_class **pdpp = NULL, *pdp = NULL;
464 
465 	SET_FOREACH(pdpp, hda_codec_class_set) {
466 		pdp = *pdpp;
467 		if (!strcmp(pdp->name, name)) {
468 			return (pdp);
469 		}
470 	}
471 
472 	return (NULL);
473 }
474 
475 static int
hda_send_command(struct hda_softc * sc,uint32_t verb)476 hda_send_command(struct hda_softc *sc, uint32_t verb)
477 {
478 	struct hda_codec_inst *hci = NULL;
479 	struct hda_codec_class *codec = NULL;
480 	uint8_t cad = (verb >> HDA_CMD_CAD_SHIFT) & 0x0f;
481 
482 	hci = sc->codecs[cad];
483 	if (!hci)
484 		return (-1);
485 
486 	DPRINTF("cad: 0x%x verb: 0x%x", cad, verb);
487 
488 	codec = hci->codec;
489 	assert(codec);
490 
491 	if (!codec->command) {
492 		DPRINTF("This codec does not implement the command function");
493 		return (-1);
494 	}
495 
496 	return (codec->command(hci, verb));
497 }
498 
499 static int
hda_notify_codecs(struct hda_softc * sc,uint8_t run,uint8_t stream,uint8_t dir)500 hda_notify_codecs(struct hda_softc *sc, uint8_t run, uint8_t stream,
501     uint8_t dir)
502 {
503 	struct hda_codec_inst *hci = NULL;
504 	struct hda_codec_class *codec = NULL;
505 	int err;
506 	int i;
507 
508 	/* Notify each codec */
509 	for (i = 0; i < sc->codecs_no; i++) {
510 		hci = sc->codecs[i];
511 		assert(hci);
512 
513 		codec = hci->codec;
514 		assert(codec);
515 
516 		if (codec->notify) {
517 			err = codec->notify(hci, run, stream, dir);
518 			if (!err)
519 				break;
520 		}
521 	}
522 
523 	return (i == sc->codecs_no ? (-1) : 0);
524 }
525 
526 static void
hda_reset(struct hda_softc * sc)527 hda_reset(struct hda_softc *sc)
528 {
529 	int i;
530 	struct hda_codec_inst *hci = NULL;
531 	struct hda_codec_class *codec = NULL;
532 
533 	hda_reset_regs(sc);
534 
535 	/* Reset each codec */
536 	for (i = 0; i < sc->codecs_no; i++) {
537 		hci = sc->codecs[i];
538 		assert(hci);
539 
540 		codec = hci->codec;
541 		assert(codec);
542 
543 		if (codec->reset)
544 			codec->reset(hci);
545 	}
546 
547 	sc->wall_clock_start = hda_get_clock_ns();
548 }
549 
550 static void
hda_reset_regs(struct hda_softc * sc)551 hda_reset_regs(struct hda_softc *sc)
552 {
553 	uint32_t off = 0;
554 	uint8_t i;
555 
556 	DPRINTF("Reset the HDA controller registers ...");
557 
558 	memset(sc->regs, 0, sizeof(sc->regs));
559 
560 	hda_set_reg_by_offset(sc, HDAC_GCAP,
561 			HDAC_GCAP_64OK |
562 			(HDA_ISS_NO << HDAC_GCAP_ISS_SHIFT) |
563 			(HDA_OSS_NO << HDAC_GCAP_OSS_SHIFT));
564 	hda_set_reg_by_offset(sc, HDAC_VMAJ, 0x01);
565 	hda_set_reg_by_offset(sc, HDAC_OUTPAY, 0x3c);
566 	hda_set_reg_by_offset(sc, HDAC_INPAY, 0x1d);
567 	hda_set_reg_by_offset(sc, HDAC_CORBSIZE,
568 	    HDAC_CORBSIZE_CORBSZCAP_256 | HDAC_CORBSIZE_CORBSIZE_256);
569 	hda_set_reg_by_offset(sc, HDAC_RIRBSIZE,
570 	    HDAC_RIRBSIZE_RIRBSZCAP_256 | HDAC_RIRBSIZE_RIRBSIZE_256);
571 
572 	for (i = 0; i < HDA_IOSS_NO; i++) {
573 		off = hda_get_offset_stream(i);
574 		hda_set_reg_by_offset(sc, off + HDAC_SDFIFOS, HDA_FIFO_SIZE);
575 	}
576 }
577 
578 static void
hda_stream_reset(struct hda_softc * sc,uint8_t stream_ind)579 hda_stream_reset(struct hda_softc *sc, uint8_t stream_ind)
580 {
581 	struct hda_stream_desc *st = &sc->streams[stream_ind];
582 	uint32_t off = hda_get_offset_stream(stream_ind);
583 
584 	DPRINTF("Reset the HDA stream: 0x%x", stream_ind);
585 
586 	/* Reset the Stream Descriptor registers */
587 	memset(sc->regs + HDA_STREAM_REGS_BASE + off, 0, HDA_STREAM_REGS_LEN);
588 
589 	/* Reset the Stream Descriptor */
590 	memset(st, 0, sizeof(*st));
591 
592 	hda_set_field_by_offset(sc, off + HDAC_SDSTS,
593 	    HDAC_SDSTS_FIFORDY, HDAC_SDSTS_FIFORDY);
594 	hda_set_field_by_offset(sc, off + HDAC_SDCTL0,
595 	    HDAC_SDCTL_SRST, HDAC_SDCTL_SRST);
596 }
597 
598 static int
hda_stream_start(struct hda_softc * sc,uint8_t stream_ind)599 hda_stream_start(struct hda_softc *sc, uint8_t stream_ind)
600 {
601 	struct hda_stream_desc *st = &sc->streams[stream_ind];
602 	struct hda_bdle_desc *bdle_desc = NULL;
603 	struct hda_bdle *bdle = NULL;
604 	uint32_t lvi = 0;
605 	uint32_t bdl_cnt = 0;
606 	uint64_t bdpl = 0;
607 	uint64_t bdpu = 0;
608 	uint64_t bdl_paddr = 0;
609 	void *bdl_vaddr = NULL;
610 	uint32_t bdle_sz = 0;
611 	uint64_t bdle_addrl = 0;
612 	uint64_t bdle_addrh = 0;
613 	uint64_t bdle_paddr = 0;
614 	void *bdle_vaddr = NULL;
615 	uint32_t off = hda_get_offset_stream(stream_ind);
616 	uint32_t sdctl = 0;
617 	uint8_t strm = 0;
618 	uint8_t dir = 0;
619 	int i;
620 
621 	assert(!st->run);
622 
623 	lvi = hda_get_reg_by_offset(sc, off + HDAC_SDLVI);
624 	bdpl = hda_get_reg_by_offset(sc, off + HDAC_SDBDPL);
625 	bdpu = hda_get_reg_by_offset(sc, off + HDAC_SDBDPU);
626 
627 	bdl_cnt = lvi + 1;
628 	assert(bdl_cnt <= HDA_BDL_MAX_LEN);
629 
630 	bdl_paddr = bdpl | (bdpu << 32);
631 	bdl_vaddr = hda_dma_get_vaddr(sc, bdl_paddr,
632 	    HDA_BDL_ENTRY_LEN * bdl_cnt);
633 	if (!bdl_vaddr) {
634 		DPRINTF("Fail to get the guest virtual address");
635 		return (-1);
636 	}
637 
638 	DPRINTF("stream: 0x%x bdl_cnt: 0x%x bdl_paddr: 0x%lx",
639 	    stream_ind, bdl_cnt, bdl_paddr);
640 
641 	st->bdl_cnt = bdl_cnt;
642 
643 	bdle = (struct hda_bdle *)bdl_vaddr;
644 	for (i = 0; i < bdl_cnt; i++, bdle++) {
645 		bdle_sz = bdle->len;
646 		assert(!(bdle_sz % HDA_DMA_ACCESS_LEN));
647 
648 		bdle_addrl = bdle->addrl;
649 		bdle_addrh = bdle->addrh;
650 
651 		bdle_paddr = bdle_addrl | (bdle_addrh << 32);
652 		bdle_vaddr = hda_dma_get_vaddr(sc, bdle_paddr, bdle_sz);
653 		if (!bdle_vaddr) {
654 			DPRINTF("Fail to get the guest virtual address");
655 			return (-1);
656 		}
657 
658 		bdle_desc = &st->bdl[i];
659 		bdle_desc->addr = bdle_vaddr;
660 		bdle_desc->len = bdle_sz;
661 		bdle_desc->ioc = bdle->ioc;
662 
663 		DPRINTF("bdle: 0x%x bdle_sz: 0x%x", i, bdle_sz);
664 	}
665 
666 	sdctl = hda_get_reg_by_offset(sc, off + HDAC_SDCTL0);
667 	strm = (sdctl >> 20) & 0x0f;
668 	dir = stream_ind >= HDA_ISS_NO;
669 
670 	DPRINTF("strm: 0x%x, dir: 0x%x", strm, dir);
671 
672 	sc->stream_map[dir][strm] = stream_ind;
673 	st->stream = strm;
674 	st->dir = dir;
675 	st->bp = 0;
676 	st->be = 0;
677 
678 	hda_set_pib(sc, stream_ind, 0);
679 
680 	st->run = 1;
681 
682 	hda_notify_codecs(sc, 1, strm, dir);
683 
684 	return (0);
685 }
686 
687 static int
hda_stream_stop(struct hda_softc * sc,uint8_t stream_ind)688 hda_stream_stop(struct hda_softc *sc, uint8_t stream_ind)
689 {
690 	struct hda_stream_desc *st = &sc->streams[stream_ind];
691 	uint8_t strm = st->stream;
692 	uint8_t dir = st->dir;
693 
694 	DPRINTF("stream: 0x%x, strm: 0x%x, dir: 0x%x", stream_ind, strm, dir);
695 
696 	st->run = 0;
697 
698 	hda_notify_codecs(sc, 0, strm, dir);
699 
700 	return (0);
701 }
702 
703 static uint32_t
hda_read(struct hda_softc * sc,uint32_t offset)704 hda_read(struct hda_softc *sc, uint32_t offset)
705 {
706 	if (offset == HDAC_WALCLK)
707 		return (24 * (hda_get_clock_ns() -			\
708 			sc->wall_clock_start) / 1000);
709 
710 	return (hda_get_reg_by_offset(sc, offset));
711 }
712 
713 static int
hda_write(struct hda_softc * sc,uint32_t offset,uint8_t size,uint32_t value)714 hda_write(struct hda_softc *sc, uint32_t offset, uint8_t size, uint32_t value)
715 {
716 	uint32_t old = hda_get_reg_by_offset(sc, offset);
717 	uint32_t masks[] = {0x00000000, 0x000000ff, 0x0000ffff,
718 			0x00ffffff, 0xffffffff};
719 	hda_set_reg_handler set_reg_handler = hda_set_reg_table[offset];
720 
721 	hda_set_field_by_offset(sc, offset, masks[size], value);
722 
723 	if (set_reg_handler)
724 		set_reg_handler(sc, offset, old);
725 
726 	return (0);
727 }
728 
729 static inline void
hda_print_cmd_ctl_data(struct hda_codec_cmd_ctl * p)730 hda_print_cmd_ctl_data(struct hda_codec_cmd_ctl *p)
731 {
732 #if DEBUG_HDA == 1
733 	char *name = p->name;
734 #endif
735 	DPRINTF("%s size: %d", name, p->size);
736 	DPRINTF("%s dma_vaddr: %p", name, p->dma_vaddr);
737 	DPRINTF("%s wp: 0x%x", name, p->wp);
738 	DPRINTF("%s rp: 0x%x", name, p->rp);
739 }
740 
741 static int
hda_corb_start(struct hda_softc * sc)742 hda_corb_start(struct hda_softc *sc)
743 {
744 	struct hda_codec_cmd_ctl *corb = &sc->corb;
745 	uint8_t corbsize = 0;
746 	uint64_t corblbase = 0;
747 	uint64_t corbubase = 0;
748 	uint64_t corbpaddr = 0;
749 
750 	corb->name = "CORB";
751 
752 	corbsize = hda_get_reg_by_offset(sc, HDAC_CORBSIZE) &		\
753 		   HDAC_CORBSIZE_CORBSIZE_MASK;
754 	corb->size = hda_corb_sizes[corbsize];
755 
756 	if (!corb->size) {
757 		DPRINTF("Invalid corb size");
758 		return (-1);
759 	}
760 
761 	corblbase = hda_get_reg_by_offset(sc, HDAC_CORBLBASE);
762 	corbubase = hda_get_reg_by_offset(sc, HDAC_CORBUBASE);
763 
764 	corbpaddr = corblbase | (corbubase << 32);
765 	DPRINTF("CORB dma_paddr: %p", (void *)corbpaddr);
766 
767 	corb->dma_vaddr = hda_dma_get_vaddr(sc, corbpaddr,
768 			HDA_CORB_ENTRY_LEN * corb->size);
769 	if (!corb->dma_vaddr) {
770 		DPRINTF("Fail to get the guest virtual address");
771 		return (-1);
772 	}
773 
774 	corb->wp = hda_get_reg_by_offset(sc, HDAC_CORBWP);
775 	corb->rp = hda_get_reg_by_offset(sc, HDAC_CORBRP);
776 
777 	corb->run = 1;
778 
779 	hda_print_cmd_ctl_data(corb);
780 
781 	return (0);
782 }
783 
784 static int
hda_corb_run(struct hda_softc * sc)785 hda_corb_run(struct hda_softc *sc)
786 {
787 	struct hda_codec_cmd_ctl *corb = &sc->corb;
788 	uint32_t verb = 0;
789 	int err;
790 
791 	corb->wp = hda_get_reg_by_offset(sc, HDAC_CORBWP);
792 
793 	while (corb->rp != corb->wp && corb->run) {
794 		corb->rp++;
795 		corb->rp %= corb->size;
796 
797 		verb = hda_dma_ld_dword(corb->dma_vaddr +		\
798 				HDA_CORB_ENTRY_LEN * corb->rp);
799 
800 		err = hda_send_command(sc, verb);
801 		assert(!err);
802 	}
803 
804 	hda_set_reg_by_offset(sc, HDAC_CORBRP, corb->rp);
805 
806 	if (corb->run)
807 		hda_response_interrupt(sc);
808 
809 	return (0);
810 }
811 
812 static int
hda_rirb_start(struct hda_softc * sc)813 hda_rirb_start(struct hda_softc *sc)
814 {
815 	struct hda_codec_cmd_ctl *rirb = &sc->rirb;
816 	uint8_t rirbsize = 0;
817 	uint64_t rirblbase = 0;
818 	uint64_t rirbubase = 0;
819 	uint64_t rirbpaddr = 0;
820 
821 	rirb->name = "RIRB";
822 
823 	rirbsize = hda_get_reg_by_offset(sc, HDAC_RIRBSIZE) &		\
824 		   HDAC_RIRBSIZE_RIRBSIZE_MASK;
825 	rirb->size = hda_rirb_sizes[rirbsize];
826 
827 	if (!rirb->size) {
828 		DPRINTF("Invalid rirb size");
829 		return (-1);
830 	}
831 
832 	rirblbase = hda_get_reg_by_offset(sc, HDAC_RIRBLBASE);
833 	rirbubase = hda_get_reg_by_offset(sc, HDAC_RIRBUBASE);
834 
835 	rirbpaddr = rirblbase | (rirbubase << 32);
836 	DPRINTF("RIRB dma_paddr: %p", (void *)rirbpaddr);
837 
838 	rirb->dma_vaddr = hda_dma_get_vaddr(sc, rirbpaddr,
839 			HDA_RIRB_ENTRY_LEN * rirb->size);
840 	if (!rirb->dma_vaddr) {
841 		DPRINTF("Fail to get the guest virtual address");
842 		return (-1);
843 	}
844 
845 	rirb->wp = hda_get_reg_by_offset(sc, HDAC_RIRBWP);
846 	rirb->rp = 0x0000;
847 
848 	rirb->run = 1;
849 
850 	hda_print_cmd_ctl_data(rirb);
851 
852 	return (0);
853 }
854 
855 static void *
hda_dma_get_vaddr(struct hda_softc * sc,uint64_t dma_paddr,size_t len)856 hda_dma_get_vaddr(struct hda_softc *sc, uint64_t dma_paddr, size_t len)
857 {
858 	struct pci_devinst *pi = sc->pci_dev;
859 
860 	assert(pi);
861 
862 	return (paddr_guest2host(pi->pi_vmctx, (uintptr_t)dma_paddr, len));
863 }
864 
865 static void
hda_dma_st_dword(void * dma_vaddr,uint32_t data)866 hda_dma_st_dword(void *dma_vaddr, uint32_t data)
867 {
868 	*(uint32_t*)dma_vaddr = data;
869 }
870 
871 static uint32_t
hda_dma_ld_dword(void * dma_vaddr)872 hda_dma_ld_dword(void *dma_vaddr)
873 {
874 	return (*(uint32_t*)dma_vaddr);
875 }
876 
877 static inline uint8_t
hda_get_stream_by_offsets(uint32_t offset,uint8_t reg_offset)878 hda_get_stream_by_offsets(uint32_t offset, uint8_t reg_offset)
879 {
880 	uint8_t stream_ind = (offset - reg_offset) >> 5;
881 
882 	assert(stream_ind < HDA_IOSS_NO);
883 
884 	return (stream_ind);
885 }
886 
887 static inline uint32_t
hda_get_offset_stream(uint8_t stream_ind)888 hda_get_offset_stream(uint8_t stream_ind)
889 {
890 	return (stream_ind << 5);
891 }
892 
893 static void
hda_set_gctl(struct hda_softc * sc,uint32_t offset,uint32_t old)894 hda_set_gctl(struct hda_softc *sc, uint32_t offset, uint32_t old)
895 {
896 	uint32_t value = hda_get_reg_by_offset(sc, offset);
897 
898 	if (!(value & HDAC_GCTL_CRST)) {
899 		hda_reset(sc);
900 	}
901 }
902 
903 static void
hda_set_statests(struct hda_softc * sc,uint32_t offset,uint32_t old)904 hda_set_statests(struct hda_softc *sc, uint32_t offset, uint32_t old)
905 {
906 	uint32_t value = hda_get_reg_by_offset(sc, offset);
907 
908 	hda_set_reg_by_offset(sc, offset, old);
909 
910 	/* clear the corresponding bits written by the software (guest) */
911 	hda_set_field_by_offset(sc, offset, value & HDA_STATESTS_IRQ_MASK, 0);
912 
913 	hda_update_intr(sc);
914 }
915 
916 static void
hda_set_corbwp(struct hda_softc * sc,uint32_t offset,uint32_t old)917 hda_set_corbwp(struct hda_softc *sc, uint32_t offset, uint32_t old)
918 {
919 	hda_corb_run(sc);
920 }
921 
922 static void
hda_set_corbctl(struct hda_softc * sc,uint32_t offset,uint32_t old)923 hda_set_corbctl(struct hda_softc *sc, uint32_t offset, uint32_t old)
924 {
925 	uint32_t value = hda_get_reg_by_offset(sc, offset);
926 	int err;
927 	struct hda_codec_cmd_ctl *corb = NULL;
928 
929 	if (value & HDAC_CORBCTL_CORBRUN) {
930 		if (!(old & HDAC_CORBCTL_CORBRUN)) {
931 			err = hda_corb_start(sc);
932 			assert(!err);
933 		}
934 	} else {
935 		corb = &sc->corb;
936 		memset(corb, 0, sizeof(*corb));
937 	}
938 
939 	hda_corb_run(sc);
940 }
941 
942 static void
hda_set_rirbctl(struct hda_softc * sc,uint32_t offset,uint32_t old)943 hda_set_rirbctl(struct hda_softc *sc, uint32_t offset, uint32_t old)
944 {
945 	uint32_t value = hda_get_reg_by_offset(sc, offset);
946 	int err;
947 	struct hda_codec_cmd_ctl *rirb = NULL;
948 
949 	if (value & HDAC_RIRBCTL_RIRBDMAEN) {
950 		err = hda_rirb_start(sc);
951 		assert(!err);
952 	} else {
953 		rirb = &sc->rirb;
954 		memset(rirb, 0, sizeof(*rirb));
955 	}
956 }
957 
958 static void
hda_set_rirbsts(struct hda_softc * sc,uint32_t offset,uint32_t old)959 hda_set_rirbsts(struct hda_softc *sc, uint32_t offset, uint32_t old)
960 {
961 	uint32_t value = hda_get_reg_by_offset(sc, offset);
962 
963 	hda_set_reg_by_offset(sc, offset, old);
964 
965 	/* clear the corresponding bits written by the software (guest) */
966 	hda_set_field_by_offset(sc, offset, value & HDA_RIRBSTS_IRQ_MASK, 0);
967 
968 	hda_update_intr(sc);
969 }
970 
971 static void
hda_set_dpiblbase(struct hda_softc * sc,uint32_t offset,uint32_t old)972 hda_set_dpiblbase(struct hda_softc *sc, uint32_t offset, uint32_t old)
973 {
974 	uint32_t value = hda_get_reg_by_offset(sc, offset);
975 	uint64_t dpiblbase = 0;
976 	uint64_t dpibubase = 0;
977 	uint64_t dpibpaddr = 0;
978 
979 	if ((value & HDAC_DPLBASE_DPLBASE_DMAPBE) != (old &		\
980 				HDAC_DPLBASE_DPLBASE_DMAPBE)) {
981 		if (value & HDAC_DPLBASE_DPLBASE_DMAPBE) {
982 			dpiblbase = value & HDAC_DPLBASE_DPLBASE_MASK;
983 			dpibubase = hda_get_reg_by_offset(sc, HDAC_DPIBUBASE);
984 
985 			dpibpaddr = dpiblbase | (dpibubase << 32);
986 			DPRINTF("DMA Position In Buffer dma_paddr: %p",
987 			    (void *)dpibpaddr);
988 
989 			sc->dma_pib_vaddr = hda_dma_get_vaddr(sc, dpibpaddr,
990 					HDA_DMA_PIB_ENTRY_LEN * HDA_IOSS_NO);
991 			if (!sc->dma_pib_vaddr) {
992 				DPRINTF("Fail to get the guest \
993 					 virtual address");
994 				assert(0);
995 			}
996 		} else {
997 			DPRINTF("DMA Position In Buffer Reset");
998 			sc->dma_pib_vaddr = NULL;
999 		}
1000 	}
1001 }
1002 
1003 static void
hda_set_sdctl(struct hda_softc * sc,uint32_t offset,uint32_t old)1004 hda_set_sdctl(struct hda_softc *sc, uint32_t offset, uint32_t old)
1005 {
1006 	uint8_t stream_ind = hda_get_stream_by_offsets(offset, HDAC_SDCTL0);
1007 	uint32_t value = hda_get_reg_by_offset(sc, offset);
1008 	int err;
1009 
1010 	DPRINTF("stream_ind: 0x%x old: 0x%x value: 0x%x",
1011 	    stream_ind, old, value);
1012 
1013 	if (value & HDAC_SDCTL_SRST) {
1014 		hda_stream_reset(sc, stream_ind);
1015 	}
1016 
1017 	if ((value & HDAC_SDCTL_RUN) != (old & HDAC_SDCTL_RUN)) {
1018 		if (value & HDAC_SDCTL_RUN) {
1019 			err = hda_stream_start(sc, stream_ind);
1020 			assert(!err);
1021 		} else {
1022 			err = hda_stream_stop(sc, stream_ind);
1023 			assert(!err);
1024 		}
1025 	}
1026 }
1027 
1028 static void
hda_set_sdctl2(struct hda_softc * sc,uint32_t offset,uint32_t old)1029 hda_set_sdctl2(struct hda_softc *sc, uint32_t offset, uint32_t old)
1030 {
1031 	uint32_t value = hda_get_reg_by_offset(sc, offset);
1032 
1033 	hda_set_field_by_offset(sc, offset - 2, 0x00ff0000, value << 16);
1034 }
1035 
1036 static void
hda_set_sdsts(struct hda_softc * sc,uint32_t offset,uint32_t old)1037 hda_set_sdsts(struct hda_softc *sc, uint32_t offset, uint32_t old)
1038 {
1039 	uint32_t value = hda_get_reg_by_offset(sc, offset);
1040 
1041 	hda_set_reg_by_offset(sc, offset, old);
1042 
1043 	/* clear the corresponding bits written by the software (guest) */
1044 	hda_set_field_by_offset(sc, offset, value & HDA_SDSTS_IRQ_MASK, 0);
1045 
1046 	hda_update_intr(sc);
1047 }
1048 
1049 static int
hda_signal_state_change(struct hda_codec_inst * hci)1050 hda_signal_state_change(struct hda_codec_inst *hci)
1051 {
1052 	struct hda_softc *sc = NULL;
1053 	uint32_t sdiwake = 0;
1054 
1055 	assert(hci);
1056 	assert(hci->hda);
1057 
1058 	DPRINTF("cad: 0x%x", hci->cad);
1059 
1060 	sc = hci->hda;
1061 	sdiwake = 1 << hci->cad;
1062 
1063 	hda_set_field_by_offset(sc, HDAC_STATESTS, sdiwake, sdiwake);
1064 	hda_update_intr(sc);
1065 
1066 	return (0);
1067 }
1068 
1069 static int
hda_response(struct hda_codec_inst * hci,uint32_t response,uint8_t unsol)1070 hda_response(struct hda_codec_inst *hci, uint32_t response, uint8_t unsol)
1071 {
1072 	struct hda_softc *sc = NULL;
1073 	struct hda_codec_cmd_ctl *rirb = NULL;
1074 	uint32_t response_ex = 0;
1075 	uint8_t rintcnt = 0;
1076 
1077 	assert(hci);
1078 	assert(hci->cad <= HDA_CODEC_MAX);
1079 
1080 	response_ex = hci->cad | unsol;
1081 
1082 	sc = hci->hda;
1083 	assert(sc);
1084 
1085 	rirb = &sc->rirb;
1086 
1087 	if (rirb->run) {
1088 		rirb->wp++;
1089 		rirb->wp %= rirb->size;
1090 
1091 		hda_dma_st_dword(rirb->dma_vaddr + HDA_RIRB_ENTRY_LEN *	\
1092 				rirb->wp, response);
1093 		hda_dma_st_dword(rirb->dma_vaddr + HDA_RIRB_ENTRY_LEN *	\
1094 				rirb->wp + 0x04, response_ex);
1095 
1096 		hda_set_reg_by_offset(sc, HDAC_RIRBWP, rirb->wp);
1097 
1098 		sc->rirb_cnt++;
1099 	}
1100 
1101 	rintcnt = hda_get_reg_by_offset(sc, HDAC_RINTCNT);
1102 	if (sc->rirb_cnt == rintcnt)
1103 		hda_response_interrupt(sc);
1104 
1105 	return (0);
1106 }
1107 
1108 static int
hda_transfer(struct hda_codec_inst * hci,uint8_t stream,uint8_t dir,void * buf,size_t count)1109 hda_transfer(struct hda_codec_inst *hci, uint8_t stream, uint8_t dir,
1110     void *buf, size_t count)
1111 {
1112 	struct hda_softc *sc = NULL;
1113 	struct hda_stream_desc *st = NULL;
1114 	struct hda_bdle_desc *bdl = NULL;
1115 	struct hda_bdle_desc *bdle_desc = NULL;
1116 	uint8_t stream_ind = 0;
1117 	uint32_t lpib = 0;
1118 	uint32_t off = 0;
1119 	size_t left = 0;
1120 	uint8_t irq = 0;
1121 
1122 	assert(hci);
1123 	assert(hci->hda);
1124 	assert(buf);
1125 	assert(!(count % HDA_DMA_ACCESS_LEN));
1126 
1127 	if (!stream) {
1128 		DPRINTF("Invalid stream");
1129 		return (-1);
1130 	}
1131 
1132 	sc = hci->hda;
1133 
1134 	assert(stream < HDA_STREAM_TAGS_CNT);
1135 	stream_ind = sc->stream_map[dir][stream];
1136 
1137 	if (!dir)
1138 		assert(stream_ind < HDA_ISS_NO);
1139 	else
1140 		assert(stream_ind >= HDA_ISS_NO && stream_ind < HDA_IOSS_NO);
1141 
1142 	st = &sc->streams[stream_ind];
1143 	if (!st->run) {
1144 		DPRINTF("Stream 0x%x stopped", stream);
1145 		return (-1);
1146 	}
1147 
1148 	assert(st->stream == stream);
1149 
1150 	off = hda_get_offset_stream(stream_ind);
1151 
1152 	lpib = hda_get_reg_by_offset(sc, off + HDAC_SDLPIB);
1153 
1154 	bdl = st->bdl;
1155 
1156 	assert(st->be < st->bdl_cnt);
1157 	assert(st->bp < bdl[st->be].len);
1158 
1159 	left = count;
1160 	while (left) {
1161 		bdle_desc = &bdl[st->be];
1162 
1163 		if (dir)
1164 			*(uint32_t *)buf =				\
1165 			    hda_dma_ld_dword(bdle_desc->addr + st->bp);
1166 		else
1167 			hda_dma_st_dword(bdle_desc->addr + st->bp,
1168 					*(uint32_t *)buf);
1169 
1170 		buf += HDA_DMA_ACCESS_LEN;
1171 		st->bp += HDA_DMA_ACCESS_LEN;
1172 		lpib += HDA_DMA_ACCESS_LEN;
1173 		left -= HDA_DMA_ACCESS_LEN;
1174 
1175 		if (st->bp == bdle_desc->len) {
1176 			st->bp = 0;
1177 			if (bdle_desc->ioc)
1178 				irq = 1;
1179 			st->be++;
1180 			if (st->be == st->bdl_cnt) {
1181 				st->be = 0;
1182 				lpib = 0;
1183 			}
1184 			bdle_desc = &bdl[st->be];
1185 		}
1186 	}
1187 
1188 	hda_set_pib(sc, stream_ind, lpib);
1189 
1190 	if (irq) {
1191 		hda_set_field_by_offset(sc, off + HDAC_SDSTS,
1192 				HDAC_SDSTS_BCIS, HDAC_SDSTS_BCIS);
1193 		hda_update_intr(sc);
1194 	}
1195 
1196 	return (0);
1197 }
1198 
1199 static void
hda_set_pib(struct hda_softc * sc,uint8_t stream_ind,uint32_t pib)1200 hda_set_pib(struct hda_softc *sc, uint8_t stream_ind, uint32_t pib)
1201 {
1202 	uint32_t off = hda_get_offset_stream(stream_ind);
1203 
1204 	hda_set_reg_by_offset(sc, off + HDAC_SDLPIB, pib);
1205 	/* LPIB Alias */
1206 	hda_set_reg_by_offset(sc, 0x2000 + off + HDAC_SDLPIB, pib);
1207 	if (sc->dma_pib_vaddr)
1208 		*(uint32_t *)(sc->dma_pib_vaddr + stream_ind *	\
1209 				HDA_DMA_PIB_ENTRY_LEN) = pib;
1210 }
1211 
hda_get_clock_ns(void)1212 static uint64_t hda_get_clock_ns(void)
1213 {
1214 	struct timespec ts;
1215 	int err;
1216 
1217 	err = clock_gettime(CLOCK_MONOTONIC, &ts);
1218 	assert(!err);
1219 
1220 	return (ts.tv_sec * 1000000000LL + ts.tv_nsec);
1221 }
1222 
1223 /*
1224  * PCI HDA function definitions
1225  */
1226 static int
pci_hda_init(struct vmctx * ctx,struct pci_devinst * pi,nvlist_t * nvl)1227 pci_hda_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
1228 {
1229 	struct hda_softc *sc = NULL;
1230 
1231 	assert(ctx != NULL);
1232 	assert(pi != NULL);
1233 
1234 	pci_set_cfgdata16(pi, PCIR_VENDOR, INTEL_VENDORID);
1235 	pci_set_cfgdata16(pi, PCIR_DEVICE, HDA_INTEL_82801G);
1236 
1237 	pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_MULTIMEDIA_HDA);
1238 	pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_MULTIMEDIA);
1239 
1240 	/* select the Intel HDA mode */
1241 	pci_set_cfgdata8(pi, PCIR_HDCTL, 0x01);
1242 
1243 	/* allocate one BAR register for the Memory address offsets */
1244 	pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, HDA_LAST_OFFSET);
1245 
1246 	/* allocate an IRQ pin for our slot */
1247 	pci_lintr_request(pi);
1248 
1249 	sc = hda_init(nvl);
1250 	if (!sc)
1251 		return (-1);
1252 
1253 	sc->pci_dev = pi;
1254 	pi->pi_arg = sc;
1255 
1256 	return (0);
1257 }
1258 
1259 static void
pci_hda_write(struct vmctx * ctx,int vcpu,struct pci_devinst * pi,int baridx,uint64_t offset,int size,uint64_t value)1260 pci_hda_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
1261     int baridx, uint64_t offset, int size, uint64_t value)
1262 {
1263 	struct hda_softc *sc = pi->pi_arg;
1264 	int err;
1265 
1266 	assert(sc);
1267 	assert(baridx == 0);
1268 	assert(size <= 4);
1269 
1270 	DPRINTF("offset: 0x%lx value: 0x%lx", offset, value);
1271 
1272 	err = hda_write(sc, offset, size, value);
1273 	assert(!err);
1274 }
1275 
1276 static uint64_t
pci_hda_read(struct vmctx * ctx,int vcpu,struct pci_devinst * pi,int baridx,uint64_t offset,int size)1277 pci_hda_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
1278     int baridx, uint64_t offset, int size)
1279 {
1280 	struct hda_softc *sc = pi->pi_arg;
1281 	uint64_t value = 0;
1282 
1283 	assert(sc);
1284 	assert(baridx == 0);
1285 	assert(size <= 4);
1286 
1287 	value = hda_read(sc, offset);
1288 
1289 	DPRINTF("offset: 0x%lx value: 0x%lx", offset, value);
1290 
1291 	return (value);
1292 }
1293