xref: /illumos-gate/usr/src/cmd/bhyve/pci_emul.h (revision d7b72f7b)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2011 NetApp, Inc.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  *
28  * $FreeBSD$
29  */
30 /*
31  * Copyright 2018 Joyent, Inc.
32  */
33 
34 #ifndef _PCI_EMUL_H_
35 #define _PCI_EMUL_H_
36 
37 #include <sys/types.h>
38 #include <sys/queue.h>
39 #include <sys/kernel.h>
40 #include <sys/nv.h>
41 #include <sys/_pthreadtypes.h>
42 
43 #include <dev/pci/pcireg.h>
44 
45 #include <assert.h>
46 
47 #define	PCI_BARMAX	PCIR_MAX_BAR_0	/* BAR registers in a Type 0 header */
48 #define PCI_BARMAX_WITH_ROM (PCI_BARMAX + 1)
49 #define PCI_ROM_IDX (PCI_BARMAX + 1)
50 
51 struct vmctx;
52 struct pci_devinst;
53 struct memory_region;
54 
55 struct pci_devemu {
56 	char      *pe_emu;		/* Name of device emulation */
57 
58 	/* instance creation */
59 	int       (*pe_init)(struct vmctx *, struct pci_devinst *,
60 			     nvlist_t *);
61 	int	(*pe_legacy_config)(nvlist_t *, const char *);
62 	const char *pe_alias;
63 
64 	/* ACPI DSDT enumeration */
65 	void	(*pe_write_dsdt)(struct pci_devinst *);
66 
67 	/* config space read/write callbacks */
68 	int	(*pe_cfgwrite)(struct vmctx *ctx, int vcpu,
69 			       struct pci_devinst *pi, int offset,
70 			       int bytes, uint32_t val);
71 	int	(*pe_cfgread)(struct vmctx *ctx, int vcpu,
72 			      struct pci_devinst *pi, int offset,
73 			      int bytes, uint32_t *retval);
74 
75 	/* BAR read/write callbacks */
76 	void      (*pe_barwrite)(struct vmctx *ctx, int vcpu,
77 				 struct pci_devinst *pi, int baridx,
78 				 uint64_t offset, int size, uint64_t value);
79 	uint64_t  (*pe_barread)(struct vmctx *ctx, int vcpu,
80 				struct pci_devinst *pi, int baridx,
81 				uint64_t offset, int size);
82 
83 	void	(*pe_baraddr)(struct vmctx *ctx, struct pci_devinst *pi,
84 			      int baridx, int enabled, uint64_t address);
85 #ifndef __FreeBSD__
86 	void	(*pe_lintrupdate)(struct pci_devinst *pi);
87 #endif /* __FreeBSD__ */
88 };
89 
90 #define PCI_EMUL_SET(x)   DATA_SET(pci_devemu_set, x);
91 
92 enum pcibar_type {
93 	PCIBAR_NONE,
94 	PCIBAR_IO,
95 	PCIBAR_MEM32,
96 	PCIBAR_MEM64,
97 	PCIBAR_MEMHI64,
98 	PCIBAR_ROM,
99 };
100 
101 struct pcibar {
102 	enum pcibar_type	type;		/* io or memory */
103 	uint64_t		size;
104 	uint64_t		addr;
105 	uint8_t			lobits;
106 };
107 
108 #define PI_NAMESZ	40
109 
110 struct msix_table_entry {
111 	uint64_t	addr;
112 	uint32_t	msg_data;
113 	uint32_t	vector_control;
114 } __packed;
115 
116 /*
117  * In case the structure is modified to hold extra information, use a define
118  * for the size that should be emulated.
119  */
120 #define	MSIX_TABLE_ENTRY_SIZE	16
121 #define MAX_MSIX_TABLE_ENTRIES	2048
122 #define	PBA_SIZE(msgnum)	(roundup2((msgnum), 64) / 8)
123 
124 enum lintr_stat {
125 	IDLE,
126 	ASSERTED,
127 	PENDING
128 };
129 
130 struct pci_devinst {
131 	struct pci_devemu *pi_d;
132 	struct vmctx *pi_vmctx;
133 	uint8_t	  pi_bus, pi_slot, pi_func;
134 	char	  pi_name[PI_NAMESZ];
135 	int	  pi_bar_getsize;
136 	int	  pi_prevcap;
137 	int	  pi_capend;
138 
139 	struct {
140 		int8_t    	pin;
141 		enum lintr_stat	state;
142 		int		pirq_pin;
143 		int	  	ioapic_irq;
144 		pthread_mutex_t	lock;
145 	} pi_lintr;
146 
147 	struct {
148 		int		enabled;
149 		uint64_t	addr;
150 		uint64_t	msg_data;
151 		int		maxmsgnum;
152 	} pi_msi;
153 
154 	struct {
155 		int	enabled;
156 		int	table_bar;
157 		int	pba_bar;
158 		uint32_t table_offset;
159 		int	table_count;
160 		uint32_t pba_offset;
161 		int	pba_size;
162 		int	function_mask;
163 		struct msix_table_entry *table;	/* allocated at runtime */
164 		void	*pba_page;
165 		int	pba_page_offset;
166 		uint8_t *mapped_addr;
167 		size_t	mapped_size;
168 	} pi_msix;
169 
170 	void      *pi_arg;		/* devemu-private data */
171 
172 	u_char	  pi_cfgdata[PCI_REGMAX + 1];
173 	/* ROM is handled like a BAR */
174 	struct pcibar pi_bar[PCI_BARMAX_WITH_ROM + 1];
175 	uint64_t pi_romoffset;
176 };
177 
178 struct msicap {
179 	uint8_t		capid;
180 	uint8_t		nextptr;
181 	uint16_t	msgctrl;
182 	uint32_t	addrlo;
183 	uint32_t	addrhi;
184 	uint16_t	msgdata;
185 } __packed;
186 static_assert(sizeof(struct msicap) == 14, "compile-time assertion failed");
187 
188 struct msixcap {
189 	uint8_t		capid;
190 	uint8_t		nextptr;
191 	uint16_t	msgctrl;
192 	uint32_t	table_info;	/* bar index and offset within it */
193 	uint32_t	pba_info;	/* bar index and offset within it */
194 } __packed;
195 static_assert(sizeof(struct msixcap) == 12, "compile-time assertion failed");
196 
197 struct pciecap {
198 	uint8_t		capid;
199 	uint8_t		nextptr;
200 	uint16_t	pcie_capabilities;
201 
202 	uint32_t	dev_capabilities;	/* all devices */
203 	uint16_t	dev_control;
204 	uint16_t	dev_status;
205 
206 	uint32_t	link_capabilities;	/* devices with links */
207 	uint16_t	link_control;
208 	uint16_t	link_status;
209 
210 	uint32_t	slot_capabilities;	/* ports with slots */
211 	uint16_t	slot_control;
212 	uint16_t	slot_status;
213 
214 	uint16_t	root_control;		/* root ports */
215 	uint16_t	root_capabilities;
216 	uint32_t	root_status;
217 
218 	uint32_t	dev_capabilities2;	/* all devices */
219 	uint16_t	dev_control2;
220 	uint16_t	dev_status2;
221 
222 	uint32_t	link_capabilities2;	/* devices with links */
223 	uint16_t	link_control2;
224 	uint16_t	link_status2;
225 
226 	uint32_t	slot_capabilities2;	/* ports with slots */
227 	uint16_t	slot_control2;
228 	uint16_t	slot_status2;
229 } __packed;
230 static_assert(sizeof(struct pciecap) == 60, "compile-time assertion failed");
231 
232 typedef void (*pci_lintr_cb)(int b, int s, int pin, int pirq_pin,
233     int ioapic_irq, void *arg);
234 
235 int	init_pci(struct vmctx *ctx);
236 void	pci_callback(void);
237 int	pci_emul_alloc_bar(struct pci_devinst *pdi, int idx,
238 	    enum pcibar_type type, uint64_t size);
239 int 	pci_emul_alloc_rom(struct pci_devinst *const pdi, const uint64_t size,
240     	    void **const addr);
241 int	pci_emul_add_msicap(struct pci_devinst *pi, int msgnum);
242 int	pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type);
243 void	pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes,
244 	    uint32_t val, uint8_t capoff, int capid);
245 void	pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old);
246 void	pci_generate_msi(struct pci_devinst *pi, int msgnum);
247 void	pci_generate_msix(struct pci_devinst *pi, int msgnum);
248 void	pci_lintr_assert(struct pci_devinst *pi);
249 void	pci_lintr_deassert(struct pci_devinst *pi);
250 void	pci_lintr_request(struct pci_devinst *pi);
251 int	pci_msi_enabled(struct pci_devinst *pi);
252 int	pci_msix_enabled(struct pci_devinst *pi);
253 int	pci_msix_table_bar(struct pci_devinst *pi);
254 int	pci_msix_pba_bar(struct pci_devinst *pi);
255 int	pci_msi_maxmsgnum(struct pci_devinst *pi);
256 int	pci_parse_legacy_config(nvlist_t *nvl, const char *opt);
257 int	pci_parse_slot(char *opt);
258 void    pci_print_supported_devices();
259 void	pci_populate_msicap(struct msicap *cap, int msgs, int nextptr);
260 int	pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum);
261 int	pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
262 			     uint64_t value);
263 uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size);
264 int	pci_count_lintr(int bus);
265 void	pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg);
266 void	pci_write_dsdt(void);
267 uint64_t pci_ecfg_base(void);
268 int	pci_bus_configured(int bus);
269 
270 static __inline void
pci_set_cfgdata8(struct pci_devinst * pi,int offset,uint8_t val)271 pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val)
272 {
273 	assert(offset <= PCI_REGMAX);
274 	*(uint8_t *)(pi->pi_cfgdata + offset) = val;
275 }
276 
277 static __inline void
pci_set_cfgdata16(struct pci_devinst * pi,int offset,uint16_t val)278 pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val)
279 {
280 	assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
281 	*(uint16_t *)(pi->pi_cfgdata + offset) = val;
282 }
283 
284 static __inline void
pci_set_cfgdata32(struct pci_devinst * pi,int offset,uint32_t val)285 pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val)
286 {
287 	assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
288 	*(uint32_t *)(pi->pi_cfgdata + offset) = val;
289 }
290 
291 static __inline uint8_t
pci_get_cfgdata8(struct pci_devinst * pi,int offset)292 pci_get_cfgdata8(struct pci_devinst *pi, int offset)
293 {
294 	assert(offset <= PCI_REGMAX);
295 	return (*(uint8_t *)(pi->pi_cfgdata + offset));
296 }
297 
298 static __inline uint16_t
pci_get_cfgdata16(struct pci_devinst * pi,int offset)299 pci_get_cfgdata16(struct pci_devinst *pi, int offset)
300 {
301 	assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
302 	return (*(uint16_t *)(pi->pi_cfgdata + offset));
303 }
304 
305 static __inline uint32_t
pci_get_cfgdata32(struct pci_devinst * pi,int offset)306 pci_get_cfgdata32(struct pci_devinst *pi, int offset)
307 {
308 	assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
309 	return (*(uint32_t *)(pi->pi_cfgdata + offset));
310 }
311 
312 #endif /* _PCI_EMUL_H_ */
313