1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 /* 31 * Copyright 2018 Joyent, Inc. 32 */ 33 34 #ifndef _PCI_EMUL_H_ 35 #define _PCI_EMUL_H_ 36 37 #include <sys/types.h> 38 #include <sys/queue.h> 39 #include <sys/kernel.h> 40 #include <sys/_pthreadtypes.h> 41 42 #include <dev/pci/pcireg.h> 43 44 #include <assert.h> 45 46 #define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */ 47 48 struct vmctx; 49 struct pci_devinst; 50 struct memory_region; 51 52 struct pci_devemu { 53 char *pe_emu; /* Name of device emulation */ 54 55 /* instance creation */ 56 int (*pe_init)(struct vmctx *, struct pci_devinst *, 57 char *opts); 58 59 /* ACPI DSDT enumeration */ 60 void (*pe_write_dsdt)(struct pci_devinst *); 61 62 /* config space read/write callbacks */ 63 int (*pe_cfgwrite)(struct vmctx *ctx, int vcpu, 64 struct pci_devinst *pi, int offset, 65 int bytes, uint32_t val); 66 int (*pe_cfgread)(struct vmctx *ctx, int vcpu, 67 struct pci_devinst *pi, int offset, 68 int bytes, uint32_t *retval); 69 70 /* BAR read/write callbacks */ 71 void (*pe_barwrite)(struct vmctx *ctx, int vcpu, 72 struct pci_devinst *pi, int baridx, 73 uint64_t offset, int size, uint64_t value); 74 uint64_t (*pe_barread)(struct vmctx *ctx, int vcpu, 75 struct pci_devinst *pi, int baridx, 76 uint64_t offset, int size); 77 78 #ifndef __FreeBSD__ 79 void (*pe_lintrupdate)(struct pci_devinst *pi); 80 #endif /* __FreeBSD__ */ 81 }; 82 #define PCI_EMUL_SET(x) DATA_SET(pci_devemu_set, x); 83 84 enum pcibar_type { 85 PCIBAR_NONE, 86 PCIBAR_IO, 87 PCIBAR_MEM32, 88 PCIBAR_MEM64, 89 PCIBAR_MEMHI64 90 }; 91 92 struct pcibar { 93 enum pcibar_type type; /* io or memory */ 94 uint64_t size; 95 uint64_t addr; 96 }; 97 98 #define PI_NAMESZ 40 99 100 struct msix_table_entry { 101 uint64_t addr; 102 uint32_t msg_data; 103 uint32_t vector_control; 104 } __packed; 105 106 /* 107 * In case the structure is modified to hold extra information, use a define 108 * for the size that should be emulated. 109 */ 110 #define MSIX_TABLE_ENTRY_SIZE 16 111 #define MAX_MSIX_TABLE_ENTRIES 2048 112 #define PBA_SIZE(msgnum) (roundup2((msgnum), 64) / 8) 113 114 enum lintr_stat { 115 IDLE, 116 ASSERTED, 117 PENDING 118 }; 119 120 struct pci_devinst { 121 struct pci_devemu *pi_d; 122 struct vmctx *pi_vmctx; 123 uint8_t pi_bus, pi_slot, pi_func; 124 char pi_name[PI_NAMESZ]; 125 int pi_bar_getsize; 126 int pi_prevcap; 127 int pi_capend; 128 129 struct { 130 int8_t pin; 131 enum lintr_stat state; 132 int pirq_pin; 133 int ioapic_irq; 134 pthread_mutex_t lock; 135 } pi_lintr; 136 137 struct { 138 int enabled; 139 uint64_t addr; 140 uint64_t msg_data; 141 int maxmsgnum; 142 } pi_msi; 143 144 struct { 145 int enabled; 146 int table_bar; 147 int pba_bar; 148 uint32_t table_offset; 149 int table_count; 150 uint32_t pba_offset; 151 int pba_size; 152 int function_mask; 153 struct msix_table_entry *table; /* allocated at runtime */ 154 void *pba_page; 155 int pba_page_offset; 156 } pi_msix; 157 158 void *pi_arg; /* devemu-private data */ 159 160 u_char pi_cfgdata[PCI_REGMAX + 1]; 161 struct pcibar pi_bar[PCI_BARMAX + 1]; 162 }; 163 164 struct msicap { 165 uint8_t capid; 166 uint8_t nextptr; 167 uint16_t msgctrl; 168 uint32_t addrlo; 169 uint32_t addrhi; 170 uint16_t msgdata; 171 } __packed; 172 static_assert(sizeof(struct msicap) == 14, "compile-time assertion failed"); 173 174 struct msixcap { 175 uint8_t capid; 176 uint8_t nextptr; 177 uint16_t msgctrl; 178 uint32_t table_info; /* bar index and offset within it */ 179 uint32_t pba_info; /* bar index and offset within it */ 180 } __packed; 181 static_assert(sizeof(struct msixcap) == 12, "compile-time assertion failed"); 182 183 struct pciecap { 184 uint8_t capid; 185 uint8_t nextptr; 186 uint16_t pcie_capabilities; 187 188 uint32_t dev_capabilities; /* all devices */ 189 uint16_t dev_control; 190 uint16_t dev_status; 191 192 uint32_t link_capabilities; /* devices with links */ 193 uint16_t link_control; 194 uint16_t link_status; 195 196 uint32_t slot_capabilities; /* ports with slots */ 197 uint16_t slot_control; 198 uint16_t slot_status; 199 200 uint16_t root_control; /* root ports */ 201 uint16_t root_capabilities; 202 uint32_t root_status; 203 204 uint32_t dev_capabilities2; /* all devices */ 205 uint16_t dev_control2; 206 uint16_t dev_status2; 207 208 uint32_t link_capabilities2; /* devices with links */ 209 uint16_t link_control2; 210 uint16_t link_status2; 211 212 uint32_t slot_capabilities2; /* ports with slots */ 213 uint16_t slot_control2; 214 uint16_t slot_status2; 215 } __packed; 216 static_assert(sizeof(struct pciecap) == 60, "compile-time assertion failed"); 217 218 typedef void (*pci_lintr_cb)(int b, int s, int pin, int pirq_pin, 219 int ioapic_irq, void *arg); 220 221 int init_pci(struct vmctx *ctx); 222 void pci_callback(void); 223 int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, 224 enum pcibar_type type, uint64_t size); 225 int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum); 226 int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type); 227 void pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, 228 uint32_t val, uint8_t capoff, int capid); 229 void pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old); 230 void pci_generate_msi(struct pci_devinst *pi, int msgnum); 231 void pci_generate_msix(struct pci_devinst *pi, int msgnum); 232 void pci_lintr_assert(struct pci_devinst *pi); 233 void pci_lintr_deassert(struct pci_devinst *pi); 234 void pci_lintr_request(struct pci_devinst *pi); 235 int pci_msi_enabled(struct pci_devinst *pi); 236 int pci_msix_enabled(struct pci_devinst *pi); 237 int pci_msix_table_bar(struct pci_devinst *pi); 238 int pci_msix_pba_bar(struct pci_devinst *pi); 239 int pci_msi_maxmsgnum(struct pci_devinst *pi); 240 int pci_parse_slot(char *opt); 241 void pci_print_supported_devices(); 242 void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr); 243 int pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum); 244 int pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 245 uint64_t value); 246 uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size); 247 int pci_count_lintr(int bus); 248 void pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg); 249 void pci_write_dsdt(void); 250 uint64_t pci_ecfg_base(void); 251 int pci_bus_configured(int bus); 252 253 static __inline void 254 pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val) 255 { 256 assert(offset <= PCI_REGMAX); 257 *(uint8_t *)(pi->pi_cfgdata + offset) = val; 258 } 259 260 static __inline void 261 pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val) 262 { 263 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0); 264 *(uint16_t *)(pi->pi_cfgdata + offset) = val; 265 } 266 267 static __inline void 268 pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val) 269 { 270 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); 271 *(uint32_t *)(pi->pi_cfgdata + offset) = val; 272 } 273 274 static __inline uint8_t 275 pci_get_cfgdata8(struct pci_devinst *pi, int offset) 276 { 277 assert(offset <= PCI_REGMAX); 278 return (*(uint8_t *)(pi->pi_cfgdata + offset)); 279 } 280 281 static __inline uint16_t 282 pci_get_cfgdata16(struct pci_devinst *pi, int offset) 283 { 284 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0); 285 return (*(uint16_t *)(pi->pi_cfgdata + offset)); 286 } 287 288 static __inline uint32_t 289 pci_get_cfgdata32(struct pci_devinst *pi, int offset) 290 { 291 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); 292 return (*(uint32_t *)(pi->pi_cfgdata + offset)); 293 } 294 295 #endif /* _PCI_EMUL_H_ */ 296