1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 /* 31 * Copyright 2018 Joyent, Inc. 32 */ 33 34 #ifndef _PCI_EMUL_H_ 35 #define _PCI_EMUL_H_ 36 37 #include <sys/types.h> 38 #include <sys/queue.h> 39 #include <sys/kernel.h> 40 #include <sys/nv.h> 41 #include <sys/_pthreadtypes.h> 42 43 #include <dev/pci/pcireg.h> 44 45 #include <assert.h> 46 47 #define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */ 48 49 struct vmctx; 50 struct pci_devinst; 51 struct memory_region; 52 53 struct pci_devemu { 54 char *pe_emu; /* Name of device emulation */ 55 56 /* instance creation */ 57 int (*pe_init)(struct vmctx *, struct pci_devinst *, 58 nvlist_t *); 59 int (*pe_legacy_config)(nvlist_t *, const char *); 60 const char *pe_alias; 61 62 /* ACPI DSDT enumeration */ 63 void (*pe_write_dsdt)(struct pci_devinst *); 64 65 /* config space read/write callbacks */ 66 int (*pe_cfgwrite)(struct vmctx *ctx, int vcpu, 67 struct pci_devinst *pi, int offset, 68 int bytes, uint32_t val); 69 int (*pe_cfgread)(struct vmctx *ctx, int vcpu, 70 struct pci_devinst *pi, int offset, 71 int bytes, uint32_t *retval); 72 73 /* BAR read/write callbacks */ 74 void (*pe_barwrite)(struct vmctx *ctx, int vcpu, 75 struct pci_devinst *pi, int baridx, 76 uint64_t offset, int size, uint64_t value); 77 uint64_t (*pe_barread)(struct vmctx *ctx, int vcpu, 78 struct pci_devinst *pi, int baridx, 79 uint64_t offset, int size); 80 81 void (*pe_baraddr)(struct vmctx *ctx, struct pci_devinst *pi, 82 int baridx, int enabled, uint64_t address); 83 #ifndef __FreeBSD__ 84 void (*pe_lintrupdate)(struct pci_devinst *pi); 85 #endif /* __FreeBSD__ */ 86 }; 87 88 #define PCI_EMUL_SET(x) DATA_SET(pci_devemu_set, x); 89 90 enum pcibar_type { 91 PCIBAR_NONE, 92 PCIBAR_IO, 93 PCIBAR_MEM32, 94 PCIBAR_MEM64, 95 PCIBAR_MEMHI64 96 }; 97 98 struct pcibar { 99 enum pcibar_type type; /* io or memory */ 100 uint64_t size; 101 uint64_t addr; 102 }; 103 104 #define PI_NAMESZ 40 105 106 struct msix_table_entry { 107 uint64_t addr; 108 uint32_t msg_data; 109 uint32_t vector_control; 110 } __packed; 111 112 /* 113 * In case the structure is modified to hold extra information, use a define 114 * for the size that should be emulated. 115 */ 116 #define MSIX_TABLE_ENTRY_SIZE 16 117 #define MAX_MSIX_TABLE_ENTRIES 2048 118 #define PBA_SIZE(msgnum) (roundup2((msgnum), 64) / 8) 119 120 enum lintr_stat { 121 IDLE, 122 ASSERTED, 123 PENDING 124 }; 125 126 struct pci_devinst { 127 struct pci_devemu *pi_d; 128 struct vmctx *pi_vmctx; 129 uint8_t pi_bus, pi_slot, pi_func; 130 char pi_name[PI_NAMESZ]; 131 int pi_bar_getsize; 132 int pi_prevcap; 133 int pi_capend; 134 135 struct { 136 int8_t pin; 137 enum lintr_stat state; 138 int pirq_pin; 139 int ioapic_irq; 140 pthread_mutex_t lock; 141 } pi_lintr; 142 143 struct { 144 int enabled; 145 uint64_t addr; 146 uint64_t msg_data; 147 int maxmsgnum; 148 } pi_msi; 149 150 struct { 151 int enabled; 152 int table_bar; 153 int pba_bar; 154 uint32_t table_offset; 155 int table_count; 156 uint32_t pba_offset; 157 int pba_size; 158 int function_mask; 159 struct msix_table_entry *table; /* allocated at runtime */ 160 void *pba_page; 161 int pba_page_offset; 162 } pi_msix; 163 164 void *pi_arg; /* devemu-private data */ 165 166 u_char pi_cfgdata[PCI_REGMAX + 1]; 167 struct pcibar pi_bar[PCI_BARMAX + 1]; 168 }; 169 170 struct msicap { 171 uint8_t capid; 172 uint8_t nextptr; 173 uint16_t msgctrl; 174 uint32_t addrlo; 175 uint32_t addrhi; 176 uint16_t msgdata; 177 } __packed; 178 static_assert(sizeof(struct msicap) == 14, "compile-time assertion failed"); 179 180 struct msixcap { 181 uint8_t capid; 182 uint8_t nextptr; 183 uint16_t msgctrl; 184 uint32_t table_info; /* bar index and offset within it */ 185 uint32_t pba_info; /* bar index and offset within it */ 186 } __packed; 187 static_assert(sizeof(struct msixcap) == 12, "compile-time assertion failed"); 188 189 struct pciecap { 190 uint8_t capid; 191 uint8_t nextptr; 192 uint16_t pcie_capabilities; 193 194 uint32_t dev_capabilities; /* all devices */ 195 uint16_t dev_control; 196 uint16_t dev_status; 197 198 uint32_t link_capabilities; /* devices with links */ 199 uint16_t link_control; 200 uint16_t link_status; 201 202 uint32_t slot_capabilities; /* ports with slots */ 203 uint16_t slot_control; 204 uint16_t slot_status; 205 206 uint16_t root_control; /* root ports */ 207 uint16_t root_capabilities; 208 uint32_t root_status; 209 210 uint32_t dev_capabilities2; /* all devices */ 211 uint16_t dev_control2; 212 uint16_t dev_status2; 213 214 uint32_t link_capabilities2; /* devices with links */ 215 uint16_t link_control2; 216 uint16_t link_status2; 217 218 uint32_t slot_capabilities2; /* ports with slots */ 219 uint16_t slot_control2; 220 uint16_t slot_status2; 221 } __packed; 222 static_assert(sizeof(struct pciecap) == 60, "compile-time assertion failed"); 223 224 typedef void (*pci_lintr_cb)(int b, int s, int pin, int pirq_pin, 225 int ioapic_irq, void *arg); 226 227 int init_pci(struct vmctx *ctx); 228 void pci_callback(void); 229 int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, 230 enum pcibar_type type, uint64_t size); 231 int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum); 232 int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type); 233 void pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, 234 uint32_t val, uint8_t capoff, int capid); 235 void pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old); 236 void pci_generate_msi(struct pci_devinst *pi, int msgnum); 237 void pci_generate_msix(struct pci_devinst *pi, int msgnum); 238 void pci_lintr_assert(struct pci_devinst *pi); 239 void pci_lintr_deassert(struct pci_devinst *pi); 240 void pci_lintr_request(struct pci_devinst *pi); 241 int pci_msi_enabled(struct pci_devinst *pi); 242 int pci_msix_enabled(struct pci_devinst *pi); 243 int pci_msix_table_bar(struct pci_devinst *pi); 244 int pci_msix_pba_bar(struct pci_devinst *pi); 245 int pci_msi_maxmsgnum(struct pci_devinst *pi); 246 int pci_parse_legacy_config(nvlist_t *nvl, const char *opt); 247 int pci_parse_slot(char *opt); 248 void pci_print_supported_devices(); 249 void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr); 250 int pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum); 251 int pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 252 uint64_t value); 253 uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size); 254 int pci_count_lintr(int bus); 255 void pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg); 256 void pci_write_dsdt(void); 257 uint64_t pci_ecfg_base(void); 258 int pci_bus_configured(int bus); 259 260 static __inline void 261 pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val) 262 { 263 assert(offset <= PCI_REGMAX); 264 *(uint8_t *)(pi->pi_cfgdata + offset) = val; 265 } 266 267 static __inline void 268 pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val) 269 { 270 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0); 271 *(uint16_t *)(pi->pi_cfgdata + offset) = val; 272 } 273 274 static __inline void 275 pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val) 276 { 277 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); 278 *(uint32_t *)(pi->pi_cfgdata + offset) = val; 279 } 280 281 static __inline uint8_t 282 pci_get_cfgdata8(struct pci_devinst *pi, int offset) 283 { 284 assert(offset <= PCI_REGMAX); 285 return (*(uint8_t *)(pi->pi_cfgdata + offset)); 286 } 287 288 static __inline uint16_t 289 pci_get_cfgdata16(struct pci_devinst *pi, int offset) 290 { 291 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0); 292 return (*(uint16_t *)(pi->pi_cfgdata + offset)); 293 } 294 295 static __inline uint32_t 296 pci_get_cfgdata32(struct pci_devinst *pi, int offset) 297 { 298 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); 299 return (*(uint32_t *)(pi->pi_cfgdata + offset)); 300 } 301 302 #endif /* _PCI_EMUL_H_ */ 303