1bf21cd93STycho Nightingale /*-
2*32640292SAndy Fiddaman * SPDX-License-Identifier: BSD-2-Clause
34c87aefeSPatrick Mooney *
4bf21cd93STycho Nightingale * Copyright (c) 2011 NetApp, Inc.
5bf21cd93STycho Nightingale * All rights reserved.
6bf21cd93STycho Nightingale *
7bf21cd93STycho Nightingale * Redistribution and use in source and binary forms, with or without
8bf21cd93STycho Nightingale * modification, are permitted provided that the following conditions
9bf21cd93STycho Nightingale * are met:
10bf21cd93STycho Nightingale * 1. Redistributions of source code must retain the above copyright
11bf21cd93STycho Nightingale * notice, this list of conditions and the following disclaimer.
12bf21cd93STycho Nightingale * 2. Redistributions in binary form must reproduce the above copyright
13bf21cd93STycho Nightingale * notice, this list of conditions and the following disclaimer in the
14bf21cd93STycho Nightingale * documentation and/or other materials provided with the distribution.
15bf21cd93STycho Nightingale *
16bf21cd93STycho Nightingale * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17bf21cd93STycho Nightingale * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18bf21cd93STycho Nightingale * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19bf21cd93STycho Nightingale * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20bf21cd93STycho Nightingale * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21bf21cd93STycho Nightingale * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22bf21cd93STycho Nightingale * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23bf21cd93STycho Nightingale * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24bf21cd93STycho Nightingale * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25bf21cd93STycho Nightingale * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26bf21cd93STycho Nightingale * SUCH DAMAGE.
27bf21cd93STycho Nightingale */
28b22a70abSPatrick Mooney /*
29b22a70abSPatrick Mooney * Copyright 2018 Joyent, Inc.
30b22a70abSPatrick Mooney */
31bf21cd93STycho Nightingale
32bf21cd93STycho Nightingale #ifndef _PCI_EMUL_H_
33bf21cd93STycho Nightingale #define _PCI_EMUL_H_
34bf21cd93STycho Nightingale
35bf21cd93STycho Nightingale #include <sys/types.h>
36bf21cd93STycho Nightingale #include <sys/queue.h>
37bf21cd93STycho Nightingale #include <sys/kernel.h>
382b948146SAndy Fiddaman #include <sys/nv.h>
39*32640292SAndy Fiddaman #include <sys/pciio.h>
40bf21cd93STycho Nightingale #include <sys/_pthreadtypes.h>
41bf21cd93STycho Nightingale
42bf21cd93STycho Nightingale #include <dev/pci/pcireg.h>
43bf21cd93STycho Nightingale
44bf21cd93STycho Nightingale #include <assert.h>
45bf21cd93STycho Nightingale
46bf21cd93STycho Nightingale #define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */
47d7b72f7bSAndy Fiddaman #define PCI_BARMAX_WITH_ROM (PCI_BARMAX + 1)
48d7b72f7bSAndy Fiddaman #define PCI_ROM_IDX (PCI_BARMAX + 1)
49bf21cd93STycho Nightingale
50bf21cd93STycho Nightingale struct vmctx;
51bf21cd93STycho Nightingale struct pci_devinst;
52bf21cd93STycho Nightingale struct memory_region;
53bf21cd93STycho Nightingale
54bf21cd93STycho Nightingale struct pci_devemu {
554f3f3e9aSAndy Fiddaman const char *pe_emu; /* Name of device emulation */
56bf21cd93STycho Nightingale
57bf21cd93STycho Nightingale /* instance creation */
58*32640292SAndy Fiddaman int (*pe_init)(struct pci_devinst *, nvlist_t *);
592b948146SAndy Fiddaman int (*pe_legacy_config)(nvlist_t *, const char *);
602b948146SAndy Fiddaman const char *pe_alias;
61bf21cd93STycho Nightingale
62bf21cd93STycho Nightingale /* ACPI DSDT enumeration */
63bf21cd93STycho Nightingale void (*pe_write_dsdt)(struct pci_devinst *);
64bf21cd93STycho Nightingale
65bf21cd93STycho Nightingale /* config space read/write callbacks */
66*32640292SAndy Fiddaman int (*pe_cfgwrite)(struct pci_devinst *pi, int offset,
67bf21cd93STycho Nightingale int bytes, uint32_t val);
68*32640292SAndy Fiddaman int (*pe_cfgread)(struct pci_devinst *pi, int offset,
69bf21cd93STycho Nightingale int bytes, uint32_t *retval);
70bf21cd93STycho Nightingale
71bf21cd93STycho Nightingale /* BAR read/write callbacks */
72*32640292SAndy Fiddaman void (*pe_barwrite)(struct pci_devinst *pi, int baridx,
73bf21cd93STycho Nightingale uint64_t offset, int size, uint64_t value);
74*32640292SAndy Fiddaman uint64_t (*pe_barread)(struct pci_devinst *pi, int baridx,
75bf21cd93STycho Nightingale uint64_t offset, int size);
76b22a70abSPatrick Mooney
77*32640292SAndy Fiddaman void (*pe_baraddr)(struct pci_devinst *pi,
782b948146SAndy Fiddaman int baridx, int enabled, uint64_t address);
79b22a70abSPatrick Mooney #ifndef __FreeBSD__
80b22a70abSPatrick Mooney void (*pe_lintrupdate)(struct pci_devinst *pi);
81b22a70abSPatrick Mooney #endif /* __FreeBSD__ */
82bf21cd93STycho Nightingale };
83*32640292SAndy Fiddaman #define PCI_EMUL_SET(x) DATA_SET(pci_devemu_set, x)
84bf21cd93STycho Nightingale
85bf21cd93STycho Nightingale enum pcibar_type {
86bf21cd93STycho Nightingale PCIBAR_NONE,
87bf21cd93STycho Nightingale PCIBAR_IO,
88bf21cd93STycho Nightingale PCIBAR_MEM32,
89bf21cd93STycho Nightingale PCIBAR_MEM64,
90d7b72f7bSAndy Fiddaman PCIBAR_MEMHI64,
91d7b72f7bSAndy Fiddaman PCIBAR_ROM,
92bf21cd93STycho Nightingale };
93bf21cd93STycho Nightingale
94bf21cd93STycho Nightingale struct pcibar {
95bf21cd93STycho Nightingale enum pcibar_type type; /* io or memory */
96bf21cd93STycho Nightingale uint64_t size;
97bf21cd93STycho Nightingale uint64_t addr;
986dc98349SAndy Fiddaman uint8_t lobits;
99bf21cd93STycho Nightingale };
100bf21cd93STycho Nightingale
101bf21cd93STycho Nightingale #define PI_NAMESZ 40
102bf21cd93STycho Nightingale
103bf21cd93STycho Nightingale struct msix_table_entry {
104bf21cd93STycho Nightingale uint64_t addr;
105bf21cd93STycho Nightingale uint32_t msg_data;
106bf21cd93STycho Nightingale uint32_t vector_control;
107bf21cd93STycho Nightingale } __packed;
108bf21cd93STycho Nightingale
1096dc98349SAndy Fiddaman /*
110bf21cd93STycho Nightingale * In case the structure is modified to hold extra information, use a define
111bf21cd93STycho Nightingale * for the size that should be emulated.
112bf21cd93STycho Nightingale */
113bf21cd93STycho Nightingale #define MSIX_TABLE_ENTRY_SIZE 16
114bf21cd93STycho Nightingale #define MAX_MSIX_TABLE_ENTRIES 2048
115bf21cd93STycho Nightingale #define PBA_SIZE(msgnum) (roundup2((msgnum), 64) / 8)
116bf21cd93STycho Nightingale
117bf21cd93STycho Nightingale enum lintr_stat {
118bf21cd93STycho Nightingale IDLE,
119bf21cd93STycho Nightingale ASSERTED,
120bf21cd93STycho Nightingale PENDING
121bf21cd93STycho Nightingale };
122bf21cd93STycho Nightingale
123bf21cd93STycho Nightingale struct pci_devinst {
124bf21cd93STycho Nightingale struct pci_devemu *pi_d;
125bf21cd93STycho Nightingale struct vmctx *pi_vmctx;
126bf21cd93STycho Nightingale uint8_t pi_bus, pi_slot, pi_func;
127bf21cd93STycho Nightingale char pi_name[PI_NAMESZ];
128bf21cd93STycho Nightingale int pi_bar_getsize;
129bf21cd93STycho Nightingale int pi_prevcap;
130bf21cd93STycho Nightingale int pi_capend;
131bf21cd93STycho Nightingale
132bf21cd93STycho Nightingale struct {
133bf21cd93STycho Nightingale int8_t pin;
134bf21cd93STycho Nightingale enum lintr_stat state;
135bf21cd93STycho Nightingale int pirq_pin;
136bf21cd93STycho Nightingale int ioapic_irq;
137bf21cd93STycho Nightingale pthread_mutex_t lock;
138bf21cd93STycho Nightingale } pi_lintr;
139bf21cd93STycho Nightingale
140bf21cd93STycho Nightingale struct {
141bf21cd93STycho Nightingale int enabled;
142bf21cd93STycho Nightingale uint64_t addr;
143bf21cd93STycho Nightingale uint64_t msg_data;
144bf21cd93STycho Nightingale int maxmsgnum;
145bf21cd93STycho Nightingale } pi_msi;
146bf21cd93STycho Nightingale
147bf21cd93STycho Nightingale struct {
148bf21cd93STycho Nightingale int enabled;
149bf21cd93STycho Nightingale int table_bar;
150bf21cd93STycho Nightingale int pba_bar;
151bf21cd93STycho Nightingale uint32_t table_offset;
152bf21cd93STycho Nightingale int table_count;
153bf21cd93STycho Nightingale uint32_t pba_offset;
154bf21cd93STycho Nightingale int pba_size;
1556dc98349SAndy Fiddaman int function_mask;
156bf21cd93STycho Nightingale struct msix_table_entry *table; /* allocated at runtime */
1574c87aefeSPatrick Mooney void *pba_page;
1584c87aefeSPatrick Mooney int pba_page_offset;
1596dc98349SAndy Fiddaman uint8_t *mapped_addr;
1606dc98349SAndy Fiddaman size_t mapped_size;
161bf21cd93STycho Nightingale } pi_msix;
162bf21cd93STycho Nightingale
163bf21cd93STycho Nightingale void *pi_arg; /* devemu-private data */
164bf21cd93STycho Nightingale
165bf21cd93STycho Nightingale u_char pi_cfgdata[PCI_REGMAX + 1];
166d7b72f7bSAndy Fiddaman /* ROM is handled like a BAR */
167d7b72f7bSAndy Fiddaman struct pcibar pi_bar[PCI_BARMAX_WITH_ROM + 1];
168d7b72f7bSAndy Fiddaman uint64_t pi_romoffset;
169bf21cd93STycho Nightingale };
170bf21cd93STycho Nightingale
171bf21cd93STycho Nightingale struct msicap {
172bf21cd93STycho Nightingale uint8_t capid;
173bf21cd93STycho Nightingale uint8_t nextptr;
174bf21cd93STycho Nightingale uint16_t msgctrl;
175bf21cd93STycho Nightingale uint32_t addrlo;
176bf21cd93STycho Nightingale uint32_t addrhi;
177bf21cd93STycho Nightingale uint16_t msgdata;
178bf21cd93STycho Nightingale } __packed;
1794c87aefeSPatrick Mooney static_assert(sizeof(struct msicap) == 14, "compile-time assertion failed");
180bf21cd93STycho Nightingale
181bf21cd93STycho Nightingale struct msixcap {
182bf21cd93STycho Nightingale uint8_t capid;
183bf21cd93STycho Nightingale uint8_t nextptr;
184bf21cd93STycho Nightingale uint16_t msgctrl;
185bf21cd93STycho Nightingale uint32_t table_info; /* bar index and offset within it */
186bf21cd93STycho Nightingale uint32_t pba_info; /* bar index and offset within it */
187bf21cd93STycho Nightingale } __packed;
1884c87aefeSPatrick Mooney static_assert(sizeof(struct msixcap) == 12, "compile-time assertion failed");
189bf21cd93STycho Nightingale
190bf21cd93STycho Nightingale struct pciecap {
191bf21cd93STycho Nightingale uint8_t capid;
192bf21cd93STycho Nightingale uint8_t nextptr;
193bf21cd93STycho Nightingale uint16_t pcie_capabilities;
194bf21cd93STycho Nightingale
195bf21cd93STycho Nightingale uint32_t dev_capabilities; /* all devices */
196bf21cd93STycho Nightingale uint16_t dev_control;
197bf21cd93STycho Nightingale uint16_t dev_status;
198bf21cd93STycho Nightingale
199bf21cd93STycho Nightingale uint32_t link_capabilities; /* devices with links */
200bf21cd93STycho Nightingale uint16_t link_control;
201bf21cd93STycho Nightingale uint16_t link_status;
202bf21cd93STycho Nightingale
203bf21cd93STycho Nightingale uint32_t slot_capabilities; /* ports with slots */
204bf21cd93STycho Nightingale uint16_t slot_control;
205bf21cd93STycho Nightingale uint16_t slot_status;
206bf21cd93STycho Nightingale
207bf21cd93STycho Nightingale uint16_t root_control; /* root ports */
208bf21cd93STycho Nightingale uint16_t root_capabilities;
209bf21cd93STycho Nightingale uint32_t root_status;
210bf21cd93STycho Nightingale
211bf21cd93STycho Nightingale uint32_t dev_capabilities2; /* all devices */
212bf21cd93STycho Nightingale uint16_t dev_control2;
213bf21cd93STycho Nightingale uint16_t dev_status2;
214bf21cd93STycho Nightingale
215bf21cd93STycho Nightingale uint32_t link_capabilities2; /* devices with links */
216bf21cd93STycho Nightingale uint16_t link_control2;
217bf21cd93STycho Nightingale uint16_t link_status2;
218bf21cd93STycho Nightingale
219bf21cd93STycho Nightingale uint32_t slot_capabilities2; /* ports with slots */
220bf21cd93STycho Nightingale uint16_t slot_control2;
221bf21cd93STycho Nightingale uint16_t slot_status2;
222bf21cd93STycho Nightingale } __packed;
2234c87aefeSPatrick Mooney static_assert(sizeof(struct pciecap) == 60, "compile-time assertion failed");
224bf21cd93STycho Nightingale
225bf21cd93STycho Nightingale typedef void (*pci_lintr_cb)(int b, int s, int pin, int pirq_pin,
226bf21cd93STycho Nightingale int ioapic_irq, void *arg);
227bf21cd93STycho Nightingale
228bf21cd93STycho Nightingale int init_pci(struct vmctx *ctx);
229bf21cd93STycho Nightingale void pci_callback(void);
230*32640292SAndy Fiddaman uint32_t pci_config_read_reg(const struct pcisel *host_sel, nvlist_t *nvl,
231*32640292SAndy Fiddaman uint32_t reg, uint8_t size, uint32_t def);
232bf21cd93STycho Nightingale int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx,
233bf21cd93STycho Nightingale enum pcibar_type type, uint64_t size);
234d7b72f7bSAndy Fiddaman int pci_emul_alloc_rom(struct pci_devinst *const pdi, const uint64_t size,
235d7b72f7bSAndy Fiddaman void **const addr);
236*32640292SAndy Fiddaman int pci_emul_add_boot_device(struct pci_devinst *const pi,
237*32640292SAndy Fiddaman const int bootindex);
238bf21cd93STycho Nightingale int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum);
239bf21cd93STycho Nightingale int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type);
240154972afSPatrick Mooney void pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes,
241154972afSPatrick Mooney uint32_t val, uint8_t capoff, int capid);
24284659b24SMichael Zeller void pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old);
243bf21cd93STycho Nightingale void pci_generate_msi(struct pci_devinst *pi, int msgnum);
244bf21cd93STycho Nightingale void pci_generate_msix(struct pci_devinst *pi, int msgnum);
245bf21cd93STycho Nightingale void pci_lintr_assert(struct pci_devinst *pi);
246bf21cd93STycho Nightingale void pci_lintr_deassert(struct pci_devinst *pi);
247bf21cd93STycho Nightingale void pci_lintr_request(struct pci_devinst *pi);
248bf21cd93STycho Nightingale int pci_msi_enabled(struct pci_devinst *pi);
249bf21cd93STycho Nightingale int pci_msix_enabled(struct pci_devinst *pi);
250bf21cd93STycho Nightingale int pci_msix_table_bar(struct pci_devinst *pi);
251bf21cd93STycho Nightingale int pci_msix_pba_bar(struct pci_devinst *pi);
2524c87aefeSPatrick Mooney int pci_msi_maxmsgnum(struct pci_devinst *pi);
2532b948146SAndy Fiddaman int pci_parse_legacy_config(nvlist_t *nvl, const char *opt);
254bf21cd93STycho Nightingale int pci_parse_slot(char *opt);
2554f3f3e9aSAndy Fiddaman void pci_print_supported_devices(void);
256bf21cd93STycho Nightingale void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr);
257bf21cd93STycho Nightingale int pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum);
258bf21cd93STycho Nightingale int pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
259bf21cd93STycho Nightingale uint64_t value);
260bf21cd93STycho Nightingale uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size);
261bf21cd93STycho Nightingale int pci_count_lintr(int bus);
262bf21cd93STycho Nightingale void pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg);
263bf21cd93STycho Nightingale void pci_write_dsdt(void);
264bf21cd93STycho Nightingale uint64_t pci_ecfg_base(void);
265bf21cd93STycho Nightingale int pci_bus_configured(int bus);
266bf21cd93STycho Nightingale
2676dc98349SAndy Fiddaman static __inline void
pci_set_cfgdata8(struct pci_devinst * pi,int offset,uint8_t val)268bf21cd93STycho Nightingale pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val)
269bf21cd93STycho Nightingale {
270bf21cd93STycho Nightingale assert(offset <= PCI_REGMAX);
271bf21cd93STycho Nightingale *(uint8_t *)(pi->pi_cfgdata + offset) = val;
272bf21cd93STycho Nightingale }
273bf21cd93STycho Nightingale
2746dc98349SAndy Fiddaman static __inline void
pci_set_cfgdata16(struct pci_devinst * pi,int offset,uint16_t val)275bf21cd93STycho Nightingale pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val)
276bf21cd93STycho Nightingale {
277bf21cd93STycho Nightingale assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
278bf21cd93STycho Nightingale *(uint16_t *)(pi->pi_cfgdata + offset) = val;
279bf21cd93STycho Nightingale }
280bf21cd93STycho Nightingale
2816dc98349SAndy Fiddaman static __inline void
pci_set_cfgdata32(struct pci_devinst * pi,int offset,uint32_t val)282bf21cd93STycho Nightingale pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val)
283bf21cd93STycho Nightingale {
284bf21cd93STycho Nightingale assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
285bf21cd93STycho Nightingale *(uint32_t *)(pi->pi_cfgdata + offset) = val;
286bf21cd93STycho Nightingale }
287bf21cd93STycho Nightingale
288bf21cd93STycho Nightingale static __inline uint8_t
pci_get_cfgdata8(struct pci_devinst * pi,int offset)289bf21cd93STycho Nightingale pci_get_cfgdata8(struct pci_devinst *pi, int offset)
290bf21cd93STycho Nightingale {
291bf21cd93STycho Nightingale assert(offset <= PCI_REGMAX);
292bf21cd93STycho Nightingale return (*(uint8_t *)(pi->pi_cfgdata + offset));
293bf21cd93STycho Nightingale }
294bf21cd93STycho Nightingale
295bf21cd93STycho Nightingale static __inline uint16_t
pci_get_cfgdata16(struct pci_devinst * pi,int offset)296bf21cd93STycho Nightingale pci_get_cfgdata16(struct pci_devinst *pi, int offset)
297bf21cd93STycho Nightingale {
298bf21cd93STycho Nightingale assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
299bf21cd93STycho Nightingale return (*(uint16_t *)(pi->pi_cfgdata + offset));
300bf21cd93STycho Nightingale }
301bf21cd93STycho Nightingale
302bf21cd93STycho Nightingale static __inline uint32_t
pci_get_cfgdata32(struct pci_devinst * pi,int offset)303bf21cd93STycho Nightingale pci_get_cfgdata32(struct pci_devinst *pi, int offset)
304bf21cd93STycho Nightingale {
305bf21cd93STycho Nightingale assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
306bf21cd93STycho Nightingale return (*(uint32_t *)(pi->pi_cfgdata + offset));
307bf21cd93STycho Nightingale }
308bf21cd93STycho Nightingale
309bf21cd93STycho Nightingale #endif /* _PCI_EMUL_H_ */
310