1199767f8SToomas Soome /*- 2199767f8SToomas Soome * Copyright (c) 1991 The Regents of the University of California. 3199767f8SToomas Soome * All rights reserved. 4199767f8SToomas Soome * 5199767f8SToomas Soome * Redistribution and use in source and binary forms, with or without 6199767f8SToomas Soome * modification, are permitted provided that the following conditions 7199767f8SToomas Soome * are met: 8199767f8SToomas Soome * 1. Redistributions of source code must retain the above copyright 9199767f8SToomas Soome * notice, this list of conditions and the following disclaimer. 10199767f8SToomas Soome * 2. Redistributions in binary form must reproduce the above copyright 11199767f8SToomas Soome * notice, this list of conditions and the following disclaimer in the 12199767f8SToomas Soome * documentation and/or other materials provided with the distribution. 13199767f8SToomas Soome * 4. Neither the name of the University nor the names of its contributors 14199767f8SToomas Soome * may be used to endorse or promote products derived from this software 15199767f8SToomas Soome * without specific prior written permission. 16199767f8SToomas Soome * 17199767f8SToomas Soome * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18199767f8SToomas Soome * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19199767f8SToomas Soome * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20199767f8SToomas Soome * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21199767f8SToomas Soome * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22199767f8SToomas Soome * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23199767f8SToomas Soome * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24199767f8SToomas Soome * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25199767f8SToomas Soome * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26199767f8SToomas Soome * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27199767f8SToomas Soome * SUCH DAMAGE. 28199767f8SToomas Soome * 29199767f8SToomas Soome * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 30199767f8SToomas Soome * $FreeBSD$ 31199767f8SToomas Soome */ 32199767f8SToomas Soome 33199767f8SToomas Soome #ifndef _MACHINE_SPECIALREG_H_ 34199767f8SToomas Soome #define _MACHINE_SPECIALREG_H_ 35199767f8SToomas Soome 36199767f8SToomas Soome /* 37199767f8SToomas Soome * Bits in 386 special registers: 38199767f8SToomas Soome */ 39199767f8SToomas Soome #define CR0_PE 0x00000001 /* Protected mode Enable */ 40199767f8SToomas Soome #define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 41199767f8SToomas Soome #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 42199767f8SToomas Soome #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 43199767f8SToomas Soome #define CR0_PG 0x80000000 /* PaGing enable */ 44199767f8SToomas Soome 45199767f8SToomas Soome /* 46199767f8SToomas Soome * Bits in 486 special registers: 47199767f8SToomas Soome */ 48199767f8SToomas Soome #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 49199767f8SToomas Soome #define CR0_WP 0x00010000 /* Write Protect (honor page protect in 50199767f8SToomas Soome all modes) */ 51199767f8SToomas Soome #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 52199767f8SToomas Soome #define CR0_NW 0x20000000 /* Not Write-through */ 53199767f8SToomas Soome #define CR0_CD 0x40000000 /* Cache Disable */ 54199767f8SToomas Soome 55199767f8SToomas Soome #define CR3_PCID_SAVE 0x8000000000000000 56199767f8SToomas Soome #define CR3_PCID_MASK 0xfff 57199767f8SToomas Soome 58199767f8SToomas Soome /* 59199767f8SToomas Soome * Bits in PPro special registers 60199767f8SToomas Soome */ 61199767f8SToomas Soome #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 62199767f8SToomas Soome #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 63199767f8SToomas Soome #define CR4_TSD 0x00000004 /* Time stamp disable */ 64199767f8SToomas Soome #define CR4_DE 0x00000008 /* Debugging extensions */ 65199767f8SToomas Soome #define CR4_PSE 0x00000010 /* Page size extensions */ 66199767f8SToomas Soome #define CR4_PAE 0x00000020 /* Physical address extension */ 67199767f8SToomas Soome #define CR4_MCE 0x00000040 /* Machine check enable */ 68199767f8SToomas Soome #define CR4_PGE 0x00000080 /* Page global enable */ 69199767f8SToomas Soome #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 70199767f8SToomas Soome #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 71199767f8SToomas Soome #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 72199767f8SToomas Soome #define CR4_VMXE 0x00002000 /* enable VMX operation (Intel-specific) */ 73199767f8SToomas Soome #define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE accessing instructions */ 74199767f8SToomas Soome #define CR4_PCIDE 0x00020000 /* Enable Context ID */ 75199767f8SToomas Soome #define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */ 76199767f8SToomas Soome #define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevention */ 77199767f8SToomas Soome 78199767f8SToomas Soome /* 79199767f8SToomas Soome * Bits in AMD64 special registers. EFER is 64 bits wide. 80199767f8SToomas Soome */ 81199767f8SToomas Soome #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */ 82199767f8SToomas Soome #define EFER_LME 0x000000100 /* Long mode enable (R/W) */ 83199767f8SToomas Soome #define EFER_LMA 0x000000400 /* Long mode active (R) */ 84199767f8SToomas Soome #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 85199767f8SToomas Soome #define EFER_SVM 0x000001000 /* SVM enable bit for AMD, reserved for Intel */ 86199767f8SToomas Soome #define EFER_LMSLE 0x000002000 /* Long Mode Segment Limit Enable */ 87199767f8SToomas Soome #define EFER_FFXSR 0x000004000 /* Fast FXSAVE/FSRSTOR */ 88199767f8SToomas Soome #define EFER_TCE 0x000008000 /* Translation Cache Extension */ 89199767f8SToomas Soome 90199767f8SToomas Soome /* 91199767f8SToomas Soome * Intel Extended Features registers 92199767f8SToomas Soome */ 93199767f8SToomas Soome #define XCR0 0 /* XFEATURE_ENABLED_MASK register */ 94199767f8SToomas Soome 95199767f8SToomas Soome #define XFEATURE_ENABLED_X87 0x00000001 96199767f8SToomas Soome #define XFEATURE_ENABLED_SSE 0x00000002 97199767f8SToomas Soome #define XFEATURE_ENABLED_YMM_HI128 0x00000004 98199767f8SToomas Soome #define XFEATURE_ENABLED_AVX XFEATURE_ENABLED_YMM_HI128 99199767f8SToomas Soome #define XFEATURE_ENABLED_BNDREGS 0x00000008 100199767f8SToomas Soome #define XFEATURE_ENABLED_BNDCSR 0x00000010 101199767f8SToomas Soome #define XFEATURE_ENABLED_OPMASK 0x00000020 102199767f8SToomas Soome #define XFEATURE_ENABLED_ZMM_HI256 0x00000040 103199767f8SToomas Soome #define XFEATURE_ENABLED_HI16_ZMM 0x00000080 104199767f8SToomas Soome 105199767f8SToomas Soome #define XFEATURE_AVX \ 106199767f8SToomas Soome (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX) 107199767f8SToomas Soome #define XFEATURE_AVX512 \ 108199767f8SToomas Soome (XFEATURE_ENABLED_OPMASK | XFEATURE_ENABLED_ZMM_HI256 | \ 109199767f8SToomas Soome XFEATURE_ENABLED_HI16_ZMM) 110199767f8SToomas Soome #define XFEATURE_MPX \ 111199767f8SToomas Soome (XFEATURE_ENABLED_BNDREGS | XFEATURE_ENABLED_BNDCSR) 112199767f8SToomas Soome 113199767f8SToomas Soome /* 114199767f8SToomas Soome * CPUID instruction features register 115199767f8SToomas Soome */ 116199767f8SToomas Soome #define CPUID_FPU 0x00000001 117199767f8SToomas Soome #define CPUID_VME 0x00000002 118199767f8SToomas Soome #define CPUID_DE 0x00000004 119199767f8SToomas Soome #define CPUID_PSE 0x00000008 120199767f8SToomas Soome #define CPUID_TSC 0x00000010 121199767f8SToomas Soome #define CPUID_MSR 0x00000020 122199767f8SToomas Soome #define CPUID_PAE 0x00000040 123199767f8SToomas Soome #define CPUID_MCE 0x00000080 124199767f8SToomas Soome #define CPUID_CX8 0x00000100 125199767f8SToomas Soome #define CPUID_APIC 0x00000200 126199767f8SToomas Soome #define CPUID_B10 0x00000400 127199767f8SToomas Soome #define CPUID_SEP 0x00000800 128199767f8SToomas Soome #define CPUID_MTRR 0x00001000 129199767f8SToomas Soome #define CPUID_PGE 0x00002000 130199767f8SToomas Soome #define CPUID_MCA 0x00004000 131199767f8SToomas Soome #define CPUID_CMOV 0x00008000 132199767f8SToomas Soome #define CPUID_PAT 0x00010000 133199767f8SToomas Soome #define CPUID_PSE36 0x00020000 134199767f8SToomas Soome #define CPUID_PSN 0x00040000 135199767f8SToomas Soome #define CPUID_CLFSH 0x00080000 136199767f8SToomas Soome #define CPUID_B20 0x00100000 137199767f8SToomas Soome #define CPUID_DS 0x00200000 138199767f8SToomas Soome #define CPUID_ACPI 0x00400000 139199767f8SToomas Soome #define CPUID_MMX 0x00800000 140199767f8SToomas Soome #define CPUID_FXSR 0x01000000 141199767f8SToomas Soome #define CPUID_SSE 0x02000000 142199767f8SToomas Soome #define CPUID_XMM 0x02000000 143199767f8SToomas Soome #define CPUID_SSE2 0x04000000 144199767f8SToomas Soome #define CPUID_SS 0x08000000 145199767f8SToomas Soome #define CPUID_HTT 0x10000000 146199767f8SToomas Soome #define CPUID_TM 0x20000000 147199767f8SToomas Soome #define CPUID_IA64 0x40000000 148199767f8SToomas Soome #define CPUID_PBE 0x80000000 149199767f8SToomas Soome 150199767f8SToomas Soome #define CPUID2_SSE3 0x00000001 151199767f8SToomas Soome #define CPUID2_PCLMULQDQ 0x00000002 152199767f8SToomas Soome #define CPUID2_DTES64 0x00000004 153199767f8SToomas Soome #define CPUID2_MON 0x00000008 154199767f8SToomas Soome #define CPUID2_DS_CPL 0x00000010 155199767f8SToomas Soome #define CPUID2_VMX 0x00000020 156199767f8SToomas Soome #define CPUID2_SMX 0x00000040 157199767f8SToomas Soome #define CPUID2_EST 0x00000080 158199767f8SToomas Soome #define CPUID2_TM2 0x00000100 159199767f8SToomas Soome #define CPUID2_SSSE3 0x00000200 160199767f8SToomas Soome #define CPUID2_CNXTID 0x00000400 161199767f8SToomas Soome #define CPUID2_SDBG 0x00000800 162199767f8SToomas Soome #define CPUID2_FMA 0x00001000 163199767f8SToomas Soome #define CPUID2_CX16 0x00002000 164199767f8SToomas Soome #define CPUID2_XTPR 0x00004000 165199767f8SToomas Soome #define CPUID2_PDCM 0x00008000 166199767f8SToomas Soome #define CPUID2_PCID 0x00020000 167199767f8SToomas Soome #define CPUID2_DCA 0x00040000 168199767f8SToomas Soome #define CPUID2_SSE41 0x00080000 169199767f8SToomas Soome #define CPUID2_SSE42 0x00100000 170199767f8SToomas Soome #define CPUID2_X2APIC 0x00200000 171199767f8SToomas Soome #define CPUID2_MOVBE 0x00400000 172199767f8SToomas Soome #define CPUID2_POPCNT 0x00800000 173199767f8SToomas Soome #define CPUID2_TSCDLT 0x01000000 174199767f8SToomas Soome #define CPUID2_AESNI 0x02000000 175199767f8SToomas Soome #define CPUID2_XSAVE 0x04000000 176199767f8SToomas Soome #define CPUID2_OSXSAVE 0x08000000 177199767f8SToomas Soome #define CPUID2_AVX 0x10000000 178199767f8SToomas Soome #define CPUID2_F16C 0x20000000 179199767f8SToomas Soome #define CPUID2_RDRAND 0x40000000 180199767f8SToomas Soome #define CPUID2_HV 0x80000000 181199767f8SToomas Soome 182199767f8SToomas Soome /* 183199767f8SToomas Soome * Important bits in the Thermal and Power Management flags 184199767f8SToomas Soome * CPUID.6 EAX and ECX. 185199767f8SToomas Soome */ 186199767f8SToomas Soome #define CPUTPM1_SENSOR 0x00000001 187199767f8SToomas Soome #define CPUTPM1_TURBO 0x00000002 188199767f8SToomas Soome #define CPUTPM1_ARAT 0x00000004 189199767f8SToomas Soome #define CPUTPM2_EFFREQ 0x00000001 190199767f8SToomas Soome 191199767f8SToomas Soome /* 192199767f8SToomas Soome * Important bits in the AMD extended cpuid flags 193199767f8SToomas Soome */ 194199767f8SToomas Soome #define AMDID_SYSCALL 0x00000800 195199767f8SToomas Soome #define AMDID_MP 0x00080000 196199767f8SToomas Soome #define AMDID_NX 0x00100000 197199767f8SToomas Soome #define AMDID_EXT_MMX 0x00400000 198199767f8SToomas Soome #define AMDID_FFXSR 0x02000000 199199767f8SToomas Soome #define AMDID_PAGE1GB 0x04000000 200199767f8SToomas Soome #define AMDID_RDTSCP 0x08000000 201199767f8SToomas Soome #define AMDID_LM 0x20000000 202199767f8SToomas Soome #define AMDID_EXT_3DNOW 0x40000000 203199767f8SToomas Soome #define AMDID_3DNOW 0x80000000 204199767f8SToomas Soome 205199767f8SToomas Soome #define AMDID2_LAHF 0x00000001 206199767f8SToomas Soome #define AMDID2_CMP 0x00000002 207199767f8SToomas Soome #define AMDID2_SVM 0x00000004 208199767f8SToomas Soome #define AMDID2_EXT_APIC 0x00000008 209199767f8SToomas Soome #define AMDID2_CR8 0x00000010 210199767f8SToomas Soome #define AMDID2_ABM 0x00000020 211199767f8SToomas Soome #define AMDID2_SSE4A 0x00000040 212199767f8SToomas Soome #define AMDID2_MAS 0x00000080 213199767f8SToomas Soome #define AMDID2_PREFETCH 0x00000100 214199767f8SToomas Soome #define AMDID2_OSVW 0x00000200 215199767f8SToomas Soome #define AMDID2_IBS 0x00000400 216199767f8SToomas Soome #define AMDID2_XOP 0x00000800 217199767f8SToomas Soome #define AMDID2_SKINIT 0x00001000 218199767f8SToomas Soome #define AMDID2_WDT 0x00002000 219199767f8SToomas Soome #define AMDID2_LWP 0x00008000 220199767f8SToomas Soome #define AMDID2_FMA4 0x00010000 221199767f8SToomas Soome #define AMDID2_TCE 0x00020000 222199767f8SToomas Soome #define AMDID2_NODE_ID 0x00080000 223199767f8SToomas Soome #define AMDID2_TBM 0x00200000 224199767f8SToomas Soome #define AMDID2_TOPOLOGY 0x00400000 225199767f8SToomas Soome #define AMDID2_PCXC 0x00800000 226199767f8SToomas Soome #define AMDID2_PNXC 0x01000000 227199767f8SToomas Soome #define AMDID2_DBE 0x04000000 228199767f8SToomas Soome #define AMDID2_PTSC 0x08000000 229199767f8SToomas Soome #define AMDID2_PTSCEL2I 0x10000000 230199767f8SToomas Soome 231199767f8SToomas Soome /* 232199767f8SToomas Soome * CPUID instruction 1 eax info 233199767f8SToomas Soome */ 234199767f8SToomas Soome #define CPUID_STEPPING 0x0000000f 235199767f8SToomas Soome #define CPUID_MODEL 0x000000f0 236199767f8SToomas Soome #define CPUID_FAMILY 0x00000f00 237199767f8SToomas Soome #define CPUID_EXT_MODEL 0x000f0000 238199767f8SToomas Soome #define CPUID_EXT_FAMILY 0x0ff00000 239199767f8SToomas Soome #ifdef __i386__ 240199767f8SToomas Soome #define CPUID_TO_MODEL(id) \ 241199767f8SToomas Soome ((((id) & CPUID_MODEL) >> 4) | \ 242199767f8SToomas Soome ((((id) & CPUID_FAMILY) >= 0x600) ? \ 243199767f8SToomas Soome (((id) & CPUID_EXT_MODEL) >> 12) : 0)) 244199767f8SToomas Soome #define CPUID_TO_FAMILY(id) \ 245199767f8SToomas Soome ((((id) & CPUID_FAMILY) >> 8) + \ 246199767f8SToomas Soome ((((id) & CPUID_FAMILY) == 0xf00) ? \ 247199767f8SToomas Soome (((id) & CPUID_EXT_FAMILY) >> 20) : 0)) 248199767f8SToomas Soome #else 249199767f8SToomas Soome #define CPUID_TO_MODEL(id) \ 250199767f8SToomas Soome ((((id) & CPUID_MODEL) >> 4) | \ 251199767f8SToomas Soome (((id) & CPUID_EXT_MODEL) >> 12)) 252199767f8SToomas Soome #define CPUID_TO_FAMILY(id) \ 253199767f8SToomas Soome ((((id) & CPUID_FAMILY) >> 8) + \ 254199767f8SToomas Soome (((id) & CPUID_EXT_FAMILY) >> 20)) 255199767f8SToomas Soome #endif 256199767f8SToomas Soome 257199767f8SToomas Soome /* 258199767f8SToomas Soome * CPUID instruction 1 ebx info 259199767f8SToomas Soome */ 260199767f8SToomas Soome #define CPUID_BRAND_INDEX 0x000000ff 261199767f8SToomas Soome #define CPUID_CLFUSH_SIZE 0x0000ff00 262199767f8SToomas Soome #define CPUID_HTT_CORES 0x00ff0000 263199767f8SToomas Soome #define CPUID_LOCAL_APIC_ID 0xff000000 264199767f8SToomas Soome 265199767f8SToomas Soome /* 266199767f8SToomas Soome * CPUID instruction 5 info 267199767f8SToomas Soome */ 268199767f8SToomas Soome #define CPUID5_MON_MIN_SIZE 0x0000ffff /* eax */ 269199767f8SToomas Soome #define CPUID5_MON_MAX_SIZE 0x0000ffff /* ebx */ 270199767f8SToomas Soome #define CPUID5_MON_MWAIT_EXT 0x00000001 /* ecx */ 271199767f8SToomas Soome #define CPUID5_MWAIT_INTRBREAK 0x00000002 /* ecx */ 272199767f8SToomas Soome 273199767f8SToomas Soome /* 274199767f8SToomas Soome * MWAIT cpu power states. Lower 4 bits are sub-states. 275199767f8SToomas Soome */ 276199767f8SToomas Soome #define MWAIT_C0 0xf0 277199767f8SToomas Soome #define MWAIT_C1 0x00 278199767f8SToomas Soome #define MWAIT_C2 0x10 279199767f8SToomas Soome #define MWAIT_C3 0x20 280199767f8SToomas Soome #define MWAIT_C4 0x30 281199767f8SToomas Soome 282199767f8SToomas Soome /* 283199767f8SToomas Soome * MWAIT extensions. 284199767f8SToomas Soome */ 285199767f8SToomas Soome /* Interrupt breaks MWAIT even when masked. */ 286199767f8SToomas Soome #define MWAIT_INTRBREAK 0x00000001 287199767f8SToomas Soome 288199767f8SToomas Soome /* 289199767f8SToomas Soome * CPUID instruction 6 ecx info 290199767f8SToomas Soome */ 291199767f8SToomas Soome #define CPUID_PERF_STAT 0x00000001 292199767f8SToomas Soome #define CPUID_PERF_BIAS 0x00000008 293199767f8SToomas Soome 294*55fea89dSDan Cross /* 295199767f8SToomas Soome * CPUID instruction 0xb ebx info. 296199767f8SToomas Soome */ 297199767f8SToomas Soome #define CPUID_TYPE_INVAL 0 298199767f8SToomas Soome #define CPUID_TYPE_SMT 1 299199767f8SToomas Soome #define CPUID_TYPE_CORE 2 300199767f8SToomas Soome 301199767f8SToomas Soome /* 302199767f8SToomas Soome * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1 303199767f8SToomas Soome */ 304199767f8SToomas Soome #define CPUID_EXTSTATE_XSAVEOPT 0x00000001 305199767f8SToomas Soome #define CPUID_EXTSTATE_XSAVEC 0x00000002 306199767f8SToomas Soome #define CPUID_EXTSTATE_XINUSE 0x00000004 307199767f8SToomas Soome #define CPUID_EXTSTATE_XSAVES 0x00000008 308199767f8SToomas Soome 309199767f8SToomas Soome /* 310199767f8SToomas Soome * AMD extended function 8000_0007h edx info 311199767f8SToomas Soome */ 312199767f8SToomas Soome #define AMDPM_TS 0x00000001 313199767f8SToomas Soome #define AMDPM_FID 0x00000002 314199767f8SToomas Soome #define AMDPM_VID 0x00000004 315199767f8SToomas Soome #define AMDPM_TTP 0x00000008 316199767f8SToomas Soome #define AMDPM_TM 0x00000010 317199767f8SToomas Soome #define AMDPM_STC 0x00000020 318199767f8SToomas Soome #define AMDPM_100MHZ_STEPS 0x00000040 319199767f8SToomas Soome #define AMDPM_HW_PSTATE 0x00000080 320199767f8SToomas Soome #define AMDPM_TSC_INVARIANT 0x00000100 321199767f8SToomas Soome #define AMDPM_CPB 0x00000200 322199767f8SToomas Soome 323199767f8SToomas Soome /* 324199767f8SToomas Soome * AMD extended function 8000_0008h ecx info 325199767f8SToomas Soome */ 326199767f8SToomas Soome #define AMDID_CMP_CORES 0x000000ff 327199767f8SToomas Soome #define AMDID_COREID_SIZE 0x0000f000 328199767f8SToomas Soome #define AMDID_COREID_SIZE_SHIFT 12 329199767f8SToomas Soome 330199767f8SToomas Soome /* 331199767f8SToomas Soome * CPUID instruction 7 Structured Extended Features, leaf 0 ebx info 332199767f8SToomas Soome */ 333199767f8SToomas Soome #define CPUID_STDEXT_FSGSBASE 0x00000001 334199767f8SToomas Soome #define CPUID_STDEXT_TSC_ADJUST 0x00000002 335199767f8SToomas Soome #define CPUID_STDEXT_BMI1 0x00000008 336199767f8SToomas Soome #define CPUID_STDEXT_HLE 0x00000010 337199767f8SToomas Soome #define CPUID_STDEXT_AVX2 0x00000020 338199767f8SToomas Soome #define CPUID_STDEXT_FDP_EXC 0x00000040 339199767f8SToomas Soome #define CPUID_STDEXT_SMEP 0x00000080 340199767f8SToomas Soome #define CPUID_STDEXT_BMI2 0x00000100 341199767f8SToomas Soome #define CPUID_STDEXT_ERMS 0x00000200 342199767f8SToomas Soome #define CPUID_STDEXT_INVPCID 0x00000400 343199767f8SToomas Soome #define CPUID_STDEXT_RTM 0x00000800 344199767f8SToomas Soome #define CPUID_STDEXT_MPX 0x00004000 345199767f8SToomas Soome #define CPUID_STDEXT_AVX512F 0x00010000 346199767f8SToomas Soome #define CPUID_STDEXT_AVX512DQ 0x00020000 347199767f8SToomas Soome #define CPUID_STDEXT_RDSEED 0x00040000 348199767f8SToomas Soome #define CPUID_STDEXT_ADX 0x00080000 349199767f8SToomas Soome #define CPUID_STDEXT_SMAP 0x00100000 350199767f8SToomas Soome #define CPUID_STDEXT_AVX512IFMA 0x00200000 351199767f8SToomas Soome #define CPUID_STDEXT_PCOMMIT 0x00400000 352199767f8SToomas Soome #define CPUID_STDEXT_CLFLUSHOPT 0x00800000 353199767f8SToomas Soome #define CPUID_STDEXT_CLWB 0x01000000 354199767f8SToomas Soome #define CPUID_STDEXT_PROCTRACE 0x02000000 355199767f8SToomas Soome #define CPUID_STDEXT_AVX512PF 0x04000000 356199767f8SToomas Soome #define CPUID_STDEXT_AVX512ER 0x08000000 357199767f8SToomas Soome #define CPUID_STDEXT_AVX512CD 0x10000000 358199767f8SToomas Soome #define CPUID_STDEXT_SHA 0x20000000 359199767f8SToomas Soome #define CPUID_STDEXT_AVX512BW 0x40000000 360199767f8SToomas Soome 361199767f8SToomas Soome /* 362199767f8SToomas Soome * CPUID manufacturers identifiers 363199767f8SToomas Soome */ 364199767f8SToomas Soome #define AMD_VENDOR_ID "AuthenticAMD" 365199767f8SToomas Soome #define CENTAUR_VENDOR_ID "CentaurHauls" 366199767f8SToomas Soome #define CYRIX_VENDOR_ID "CyrixInstead" 367199767f8SToomas Soome #define INTEL_VENDOR_ID "GenuineIntel" 368199767f8SToomas Soome #define NEXGEN_VENDOR_ID "NexGenDriven" 369199767f8SToomas Soome #define NSC_VENDOR_ID "Geode by NSC" 370199767f8SToomas Soome #define RISE_VENDOR_ID "RiseRiseRise" 371199767f8SToomas Soome #define SIS_VENDOR_ID "SiS SiS SiS " 372199767f8SToomas Soome #define TRANSMETA_VENDOR_ID "GenuineTMx86" 373199767f8SToomas Soome #define UMC_VENDOR_ID "UMC UMC UMC " 374199767f8SToomas Soome 375199767f8SToomas Soome /* 376199767f8SToomas Soome * Model-specific registers for the i386 family 377199767f8SToomas Soome */ 378199767f8SToomas Soome #define MSR_P5_MC_ADDR 0x000 379199767f8SToomas Soome #define MSR_P5_MC_TYPE 0x001 380199767f8SToomas Soome #define MSR_TSC 0x010 381199767f8SToomas Soome #define MSR_P5_CESR 0x011 382199767f8SToomas Soome #define MSR_P5_CTR0 0x012 383199767f8SToomas Soome #define MSR_P5_CTR1 0x013 384199767f8SToomas Soome #define MSR_IA32_PLATFORM_ID 0x017 385199767f8SToomas Soome #define MSR_APICBASE 0x01b 386199767f8SToomas Soome #define MSR_EBL_CR_POWERON 0x02a 387199767f8SToomas Soome #define MSR_TEST_CTL 0x033 388199767f8SToomas Soome #define MSR_IA32_FEATURE_CONTROL 0x03a 389199767f8SToomas Soome #define MSR_BIOS_UPDT_TRIG 0x079 390199767f8SToomas Soome #define MSR_BBL_CR_D0 0x088 391199767f8SToomas Soome #define MSR_BBL_CR_D1 0x089 392199767f8SToomas Soome #define MSR_BBL_CR_D2 0x08a 393199767f8SToomas Soome #define MSR_BIOS_SIGN 0x08b 394199767f8SToomas Soome #define MSR_PERFCTR0 0x0c1 395199767f8SToomas Soome #define MSR_PERFCTR1 0x0c2 396199767f8SToomas Soome #define MSR_PLATFORM_INFO 0x0ce 397199767f8SToomas Soome #define MSR_MPERF 0x0e7 398199767f8SToomas Soome #define MSR_APERF 0x0e8 399199767f8SToomas Soome #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 400199767f8SToomas Soome #define MSR_MTRRcap 0x0fe 401199767f8SToomas Soome #define MSR_BBL_CR_ADDR 0x116 402199767f8SToomas Soome #define MSR_BBL_CR_DECC 0x118 403199767f8SToomas Soome #define MSR_BBL_CR_CTL 0x119 404199767f8SToomas Soome #define MSR_BBL_CR_TRIG 0x11a 405199767f8SToomas Soome #define MSR_BBL_CR_BUSY 0x11b 406199767f8SToomas Soome #define MSR_BBL_CR_CTL3 0x11e 407199767f8SToomas Soome #define MSR_SYSENTER_CS_MSR 0x174 408199767f8SToomas Soome #define MSR_SYSENTER_ESP_MSR 0x175 409199767f8SToomas Soome #define MSR_SYSENTER_EIP_MSR 0x176 410199767f8SToomas Soome #define MSR_MCG_CAP 0x179 411199767f8SToomas Soome #define MSR_MCG_STATUS 0x17a 412199767f8SToomas Soome #define MSR_MCG_CTL 0x17b 413199767f8SToomas Soome #define MSR_EVNTSEL0 0x186 414199767f8SToomas Soome #define MSR_EVNTSEL1 0x187 415199767f8SToomas Soome #define MSR_THERM_CONTROL 0x19a 416199767f8SToomas Soome #define MSR_THERM_INTERRUPT 0x19b 417199767f8SToomas Soome #define MSR_THERM_STATUS 0x19c 418199767f8SToomas Soome #define MSR_IA32_MISC_ENABLE 0x1a0 419199767f8SToomas Soome #define MSR_IA32_TEMPERATURE_TARGET 0x1a2 420199767f8SToomas Soome #define MSR_TURBO_RATIO_LIMIT 0x1ad 421199767f8SToomas Soome #define MSR_TURBO_RATIO_LIMIT1 0x1ae 422199767f8SToomas Soome #define MSR_DEBUGCTLMSR 0x1d9 423199767f8SToomas Soome #define MSR_LASTBRANCHFROMIP 0x1db 424199767f8SToomas Soome #define MSR_LASTBRANCHTOIP 0x1dc 425199767f8SToomas Soome #define MSR_LASTINTFROMIP 0x1dd 426199767f8SToomas Soome #define MSR_LASTINTTOIP 0x1de 427199767f8SToomas Soome #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 428199767f8SToomas Soome #define MSR_MTRRVarBase 0x200 429199767f8SToomas Soome #define MSR_MTRR64kBase 0x250 430199767f8SToomas Soome #define MSR_MTRR16kBase 0x258 431199767f8SToomas Soome #define MSR_MTRR4kBase 0x268 432199767f8SToomas Soome #define MSR_PAT 0x277 433199767f8SToomas Soome #define MSR_MC0_CTL2 0x280 434199767f8SToomas Soome #define MSR_MTRRdefType 0x2ff 435199767f8SToomas Soome #define MSR_MC0_CTL 0x400 436199767f8SToomas Soome #define MSR_MC0_STATUS 0x401 437199767f8SToomas Soome #define MSR_MC0_ADDR 0x402 438199767f8SToomas Soome #define MSR_MC0_MISC 0x403 439199767f8SToomas Soome #define MSR_MC1_CTL 0x404 440199767f8SToomas Soome #define MSR_MC1_STATUS 0x405 441199767f8SToomas Soome #define MSR_MC1_ADDR 0x406 442199767f8SToomas Soome #define MSR_MC1_MISC 0x407 443199767f8SToomas Soome #define MSR_MC2_CTL 0x408 444199767f8SToomas Soome #define MSR_MC2_STATUS 0x409 445199767f8SToomas Soome #define MSR_MC2_ADDR 0x40a 446199767f8SToomas Soome #define MSR_MC2_MISC 0x40b 447199767f8SToomas Soome #define MSR_MC3_CTL 0x40c 448199767f8SToomas Soome #define MSR_MC3_STATUS 0x40d 449199767f8SToomas Soome #define MSR_MC3_ADDR 0x40e 450199767f8SToomas Soome #define MSR_MC3_MISC 0x40f 451199767f8SToomas Soome #define MSR_MC4_CTL 0x410 452199767f8SToomas Soome #define MSR_MC4_STATUS 0x411 453199767f8SToomas Soome #define MSR_MC4_ADDR 0x412 454199767f8SToomas Soome #define MSR_MC4_MISC 0x413 455199767f8SToomas Soome #define MSR_RAPL_POWER_UNIT 0x606 456199767f8SToomas Soome #define MSR_PKG_ENERGY_STATUS 0x611 457199767f8SToomas Soome #define MSR_DRAM_ENERGY_STATUS 0x619 458199767f8SToomas Soome #define MSR_PP0_ENERGY_STATUS 0x639 459199767f8SToomas Soome #define MSR_PP1_ENERGY_STATUS 0x641 460199767f8SToomas Soome 461199767f8SToomas Soome /* 462199767f8SToomas Soome * VMX MSRs 463199767f8SToomas Soome */ 464199767f8SToomas Soome #define MSR_VMX_BASIC 0x480 465199767f8SToomas Soome #define MSR_VMX_PINBASED_CTLS 0x481 466199767f8SToomas Soome #define MSR_VMX_PROCBASED_CTLS 0x482 467199767f8SToomas Soome #define MSR_VMX_EXIT_CTLS 0x483 468199767f8SToomas Soome #define MSR_VMX_ENTRY_CTLS 0x484 469199767f8SToomas Soome #define MSR_VMX_CR0_FIXED0 0x486 470199767f8SToomas Soome #define MSR_VMX_CR0_FIXED1 0x487 471199767f8SToomas Soome #define MSR_VMX_CR4_FIXED0 0x488 472199767f8SToomas Soome #define MSR_VMX_CR4_FIXED1 0x489 473199767f8SToomas Soome #define MSR_VMX_PROCBASED_CTLS2 0x48b 474199767f8SToomas Soome #define MSR_VMX_EPT_VPID_CAP 0x48c 475199767f8SToomas Soome #define MSR_VMX_TRUE_PINBASED_CTLS 0x48d 476199767f8SToomas Soome #define MSR_VMX_TRUE_PROCBASED_CTLS 0x48e 477199767f8SToomas Soome #define MSR_VMX_TRUE_EXIT_CTLS 0x48f 478199767f8SToomas Soome #define MSR_VMX_TRUE_ENTRY_CTLS 0x490 479199767f8SToomas Soome 480199767f8SToomas Soome /* 481199767f8SToomas Soome * X2APIC MSRs 482199767f8SToomas Soome */ 483199767f8SToomas Soome #define MSR_APIC_000 0x800 484199767f8SToomas Soome #define MSR_APIC_ID 0x802 485199767f8SToomas Soome #define MSR_APIC_VERSION 0x803 486199767f8SToomas Soome #define MSR_APIC_TPR 0x808 487199767f8SToomas Soome #define MSR_APIC_EOI 0x80b 488199767f8SToomas Soome #define MSR_APIC_LDR 0x80d 489199767f8SToomas Soome #define MSR_APIC_SVR 0x80f 490199767f8SToomas Soome #define MSR_APIC_ISR0 0x810 491199767f8SToomas Soome #define MSR_APIC_ISR1 0x811 492199767f8SToomas Soome #define MSR_APIC_ISR2 0x812 493199767f8SToomas Soome #define MSR_APIC_ISR3 0x813 494199767f8SToomas Soome #define MSR_APIC_ISR4 0x814 495199767f8SToomas Soome #define MSR_APIC_ISR5 0x815 496199767f8SToomas Soome #define MSR_APIC_ISR6 0x816 497199767f8SToomas Soome #define MSR_APIC_ISR7 0x817 498199767f8SToomas Soome #define MSR_APIC_TMR0 0x818 499199767f8SToomas Soome #define MSR_APIC_IRR0 0x820 500199767f8SToomas Soome #define MSR_APIC_ESR 0x828 501199767f8SToomas Soome #define MSR_APIC_LVT_CMCI 0x82F 502199767f8SToomas Soome #define MSR_APIC_ICR 0x830 503199767f8SToomas Soome #define MSR_APIC_LVT_TIMER 0x832 504199767f8SToomas Soome #define MSR_APIC_LVT_THERMAL 0x833 505199767f8SToomas Soome #define MSR_APIC_LVT_PCINT 0x834 506199767f8SToomas Soome #define MSR_APIC_LVT_LINT0 0x835 507199767f8SToomas Soome #define MSR_APIC_LVT_LINT1 0x836 508199767f8SToomas Soome #define MSR_APIC_LVT_ERROR 0x837 509199767f8SToomas Soome #define MSR_APIC_ICR_TIMER 0x838 510199767f8SToomas Soome #define MSR_APIC_CCR_TIMER 0x839 511199767f8SToomas Soome #define MSR_APIC_DCR_TIMER 0x83e 512199767f8SToomas Soome #define MSR_APIC_SELF_IPI 0x83f 513199767f8SToomas Soome 514199767f8SToomas Soome #define MSR_IA32_XSS 0xda0 515199767f8SToomas Soome 516199767f8SToomas Soome /* 517199767f8SToomas Soome * Constants related to MSR's. 518199767f8SToomas Soome */ 519199767f8SToomas Soome #define APICBASE_RESERVED 0x000002ff 520199767f8SToomas Soome #define APICBASE_BSP 0x00000100 521199767f8SToomas Soome #define APICBASE_X2APIC 0x00000400 522199767f8SToomas Soome #define APICBASE_ENABLED 0x00000800 523199767f8SToomas Soome #define APICBASE_ADDRESS 0xfffff000 524199767f8SToomas Soome 525199767f8SToomas Soome /* MSR_IA32_FEATURE_CONTROL related */ 526199767f8SToomas Soome #define IA32_FEATURE_CONTROL_LOCK 0x01 /* lock bit */ 527199767f8SToomas Soome #define IA32_FEATURE_CONTROL_SMX_EN 0x02 /* enable VMX inside SMX */ 528199767f8SToomas Soome #define IA32_FEATURE_CONTROL_VMX_EN 0x04 /* enable VMX outside SMX */ 529199767f8SToomas Soome 530199767f8SToomas Soome /* MSR IA32_MISC_ENABLE */ 531199767f8SToomas Soome #define IA32_MISC_EN_FASTSTR 0x0000000000000001ULL 532199767f8SToomas Soome #define IA32_MISC_EN_ATCCE 0x0000000000000008ULL 533199767f8SToomas Soome #define IA32_MISC_EN_PERFMON 0x0000000000000080ULL 534199767f8SToomas Soome #define IA32_MISC_EN_PEBSU 0x0000000000001000ULL 535199767f8SToomas Soome #define IA32_MISC_EN_ESSTE 0x0000000000010000ULL 536199767f8SToomas Soome #define IA32_MISC_EN_MONE 0x0000000000040000ULL 537199767f8SToomas Soome #define IA32_MISC_EN_LIMCPUID 0x0000000000400000ULL 538199767f8SToomas Soome #define IA32_MISC_EN_xTPRD 0x0000000000800000ULL 539199767f8SToomas Soome #define IA32_MISC_EN_XDD 0x0000000400000000ULL 540199767f8SToomas Soome 541199767f8SToomas Soome /* 542199767f8SToomas Soome * PAT modes. 543199767f8SToomas Soome */ 544199767f8SToomas Soome #define PAT_UNCACHEABLE 0x00 545199767f8SToomas Soome #define PAT_WRITE_COMBINING 0x01 546199767f8SToomas Soome #define PAT_WRITE_THROUGH 0x04 547199767f8SToomas Soome #define PAT_WRITE_PROTECTED 0x05 548199767f8SToomas Soome #define PAT_WRITE_BACK 0x06 549199767f8SToomas Soome #define PAT_UNCACHED 0x07 550199767f8SToomas Soome #define PAT_VALUE(i, m) ((long long)(m) << (8 * (i))) 551199767f8SToomas Soome #define PAT_MASK(i) PAT_VALUE(i, 0xff) 552199767f8SToomas Soome 553199767f8SToomas Soome /* 554199767f8SToomas Soome * Constants related to MTRRs 555199767f8SToomas Soome */ 556199767f8SToomas Soome #define MTRR_UNCACHEABLE 0x00 557199767f8SToomas Soome #define MTRR_WRITE_COMBINING 0x01 558199767f8SToomas Soome #define MTRR_WRITE_THROUGH 0x04 559199767f8SToomas Soome #define MTRR_WRITE_PROTECTED 0x05 560199767f8SToomas Soome #define MTRR_WRITE_BACK 0x06 561199767f8SToomas Soome #define MTRR_N64K 8 /* numbers of fixed-size entries */ 562199767f8SToomas Soome #define MTRR_N16K 16 563199767f8SToomas Soome #define MTRR_N4K 64 564199767f8SToomas Soome #define MTRR_CAP_WC 0x0000000000000400 565199767f8SToomas Soome #define MTRR_CAP_FIXED 0x0000000000000100 566199767f8SToomas Soome #define MTRR_CAP_VCNT 0x00000000000000ff 567199767f8SToomas Soome #define MTRR_DEF_ENABLE 0x0000000000000800 568199767f8SToomas Soome #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400 569199767f8SToomas Soome #define MTRR_DEF_TYPE 0x00000000000000ff 570199767f8SToomas Soome #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000 571199767f8SToomas Soome #define MTRR_PHYSBASE_TYPE 0x00000000000000ff 572199767f8SToomas Soome #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000 573199767f8SToomas Soome #define MTRR_PHYSMASK_VALID 0x0000000000000800 574199767f8SToomas Soome 575199767f8SToomas Soome /* 576199767f8SToomas Soome * Cyrix configuration registers, accessible as IO ports. 577199767f8SToomas Soome */ 578199767f8SToomas Soome #define CCR0 0xc0 /* Configuration control register 0 */ 579199767f8SToomas Soome #define CCR0_NC0 0x01 /* First 64K of each 1M memory region is 580199767f8SToomas Soome non-cacheable */ 581199767f8SToomas Soome #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 582199767f8SToomas Soome #define CCR0_A20M 0x04 /* Enables A20M# input pin */ 583199767f8SToomas Soome #define CCR0_KEN 0x08 /* Enables KEN# input pin */ 584199767f8SToomas Soome #define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ 585199767f8SToomas Soome #define CCR0_BARB 0x20 /* Flushes internal cache when entering hold 586199767f8SToomas Soome state */ 587199767f8SToomas Soome #define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set 588199767f8SToomas Soome assoc */ 589199767f8SToomas Soome #define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ 590199767f8SToomas Soome 591199767f8SToomas Soome #define CCR1 0xc1 /* Configuration control register 1 */ 592199767f8SToomas Soome #define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ 593199767f8SToomas Soome #define CCR1_SMI 0x02 /* Enables SMM pins */ 594199767f8SToomas Soome #define CCR1_SMAC 0x04 /* System management memory access */ 595199767f8SToomas Soome #define CCR1_MMAC 0x08 /* Main memory access */ 596199767f8SToomas Soome #define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ 597199767f8SToomas Soome #define CCR1_SM3 0x80 /* SMM address space address region 3 */ 598199767f8SToomas Soome 599199767f8SToomas Soome #define CCR2 0xc2 600199767f8SToomas Soome #define CCR2_WB 0x02 /* Enables WB cache interface pins */ 601199767f8SToomas Soome #define CCR2_SADS 0x02 /* Slow ADS */ 602199767f8SToomas Soome #define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ 603199767f8SToomas Soome #define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ 604199767f8SToomas Soome #define CCR2_WT1 0x10 /* WT region 1 */ 605199767f8SToomas Soome #define CCR2_WPR1 0x10 /* Write-protect region 1 */ 606199767f8SToomas Soome #define CCR2_BARB 0x20 /* Flushes write-back cache when entering 607199767f8SToomas Soome hold state. */ 608199767f8SToomas Soome #define CCR2_BWRT 0x40 /* Enables burst write cycles */ 609199767f8SToomas Soome #define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ 610199767f8SToomas Soome 611199767f8SToomas Soome #define CCR3 0xc3 612199767f8SToomas Soome #define CCR3_SMILOCK 0x01 /* SMM register lock */ 613199767f8SToomas Soome #define CCR3_NMI 0x02 /* Enables NMI during SMM */ 614199767f8SToomas Soome #define CCR3_LINBRST 0x04 /* Linear address burst cycles */ 615199767f8SToomas Soome #define CCR3_SMMMODE 0x08 /* SMM Mode */ 616199767f8SToomas Soome #define CCR3_MAPEN0 0x10 /* Enables Map0 */ 617199767f8SToomas Soome #define CCR3_MAPEN1 0x20 /* Enables Map1 */ 618199767f8SToomas Soome #define CCR3_MAPEN2 0x40 /* Enables Map2 */ 619199767f8SToomas Soome #define CCR3_MAPEN3 0x80 /* Enables Map3 */ 620199767f8SToomas Soome 621199767f8SToomas Soome #define CCR4 0xe8 622199767f8SToomas Soome #define CCR4_IOMASK 0x07 623199767f8SToomas Soome #define CCR4_MEM 0x08 /* Enables momory bypassing */ 624199767f8SToomas Soome #define CCR4_DTE 0x10 /* Enables directory table entry cache */ 625199767f8SToomas Soome #define CCR4_FASTFPE 0x20 /* Fast FPU exception */ 626199767f8SToomas Soome #define CCR4_CPUID 0x80 /* Enables CPUID instruction */ 627199767f8SToomas Soome 628199767f8SToomas Soome #define CCR5 0xe9 629199767f8SToomas Soome #define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ 630199767f8SToomas Soome #define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ 631199767f8SToomas Soome #define CCR5_LBR1 0x10 /* Local bus region 1 */ 632199767f8SToomas Soome #define CCR5_ARREN 0x20 /* Enables ARR region */ 633199767f8SToomas Soome 634199767f8SToomas Soome #define CCR6 0xea 635199767f8SToomas Soome 636199767f8SToomas Soome #define CCR7 0xeb 637199767f8SToomas Soome 638199767f8SToomas Soome /* Performance Control Register (5x86 only). */ 639199767f8SToomas Soome #define PCR0 0x20 640199767f8SToomas Soome #define PCR0_RSTK 0x01 /* Enables return stack */ 641199767f8SToomas Soome #define PCR0_BTB 0x02 /* Enables branch target buffer */ 642199767f8SToomas Soome #define PCR0_LOOP 0x04 /* Enables loop */ 643199767f8SToomas Soome #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 644199767f8SToomas Soome serialize pipe. */ 645199767f8SToomas Soome #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 646199767f8SToomas Soome #define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 647199767f8SToomas Soome #define PCR0_LSSER 0x80 /* Disable reorder */ 648199767f8SToomas Soome 649199767f8SToomas Soome /* Device Identification Registers */ 650199767f8SToomas Soome #define DIR0 0xfe 651199767f8SToomas Soome #define DIR1 0xff 652199767f8SToomas Soome 653199767f8SToomas Soome /* 654199767f8SToomas Soome * Machine Check register constants. 655199767f8SToomas Soome */ 656199767f8SToomas Soome #define MCG_CAP_COUNT 0x000000ff 657199767f8SToomas Soome #define MCG_CAP_CTL_P 0x00000100 658199767f8SToomas Soome #define MCG_CAP_EXT_P 0x00000200 659199767f8SToomas Soome #define MCG_CAP_CMCI_P 0x00000400 660199767f8SToomas Soome #define MCG_CAP_TES_P 0x00000800 661199767f8SToomas Soome #define MCG_CAP_EXT_CNT 0x00ff0000 662199767f8SToomas Soome #define MCG_CAP_SER_P 0x01000000 663199767f8SToomas Soome #define MCG_STATUS_RIPV 0x00000001 664199767f8SToomas Soome #define MCG_STATUS_EIPV 0x00000002 665199767f8SToomas Soome #define MCG_STATUS_MCIP 0x00000004 666199767f8SToomas Soome #define MCG_CTL_ENABLE 0xffffffffffffffff 667199767f8SToomas Soome #define MCG_CTL_DISABLE 0x0000000000000000 668199767f8SToomas Soome #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) 669199767f8SToomas Soome #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) 670199767f8SToomas Soome #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) 671199767f8SToomas Soome #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) 672199767f8SToomas Soome #define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */ 673199767f8SToomas Soome #define MC_STATUS_MCA_ERROR 0x000000000000ffff 674199767f8SToomas Soome #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000 675199767f8SToomas Soome #define MC_STATUS_OTHER_INFO 0x01ffffff00000000 676199767f8SToomas Soome #define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */ 677199767f8SToomas Soome #define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */ 678199767f8SToomas Soome #define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */ 679199767f8SToomas Soome #define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */ 680199767f8SToomas Soome #define MC_STATUS_PCC 0x0200000000000000 681199767f8SToomas Soome #define MC_STATUS_ADDRV 0x0400000000000000 682199767f8SToomas Soome #define MC_STATUS_MISCV 0x0800000000000000 683199767f8SToomas Soome #define MC_STATUS_EN 0x1000000000000000 684199767f8SToomas Soome #define MC_STATUS_UC 0x2000000000000000 685199767f8SToomas Soome #define MC_STATUS_OVER 0x4000000000000000 686199767f8SToomas Soome #define MC_STATUS_VAL 0x8000000000000000 687199767f8SToomas Soome #define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */ 688199767f8SToomas Soome #define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */ 689199767f8SToomas Soome #define MC_CTL2_THRESHOLD 0x0000000000007fff 690199767f8SToomas Soome #define MC_CTL2_CMCI_EN 0x0000000040000000 691199767f8SToomas Soome 692199767f8SToomas Soome /* 693199767f8SToomas Soome * The following four 3-byte registers control the non-cacheable regions. 694199767f8SToomas Soome * These registers must be written as three separate bytes. 695199767f8SToomas Soome * 696199767f8SToomas Soome * NCRx+0: A31-A24 of starting address 697199767f8SToomas Soome * NCRx+1: A23-A16 of starting address 698199767f8SToomas Soome * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 699199767f8SToomas Soome * 700199767f8SToomas Soome * The non-cacheable region's starting address must be aligned to the 701199767f8SToomas Soome * size indicated by the NCR_SIZE_xx field. 702199767f8SToomas Soome */ 703199767f8SToomas Soome #define NCR1 0xc4 704199767f8SToomas Soome #define NCR2 0xc7 705199767f8SToomas Soome #define NCR3 0xca 706199767f8SToomas Soome #define NCR4 0xcd 707199767f8SToomas Soome 708199767f8SToomas Soome #define NCR_SIZE_0K 0 709199767f8SToomas Soome #define NCR_SIZE_4K 1 710199767f8SToomas Soome #define NCR_SIZE_8K 2 711199767f8SToomas Soome #define NCR_SIZE_16K 3 712199767f8SToomas Soome #define NCR_SIZE_32K 4 713199767f8SToomas Soome #define NCR_SIZE_64K 5 714199767f8SToomas Soome #define NCR_SIZE_128K 6 715199767f8SToomas Soome #define NCR_SIZE_256K 7 716199767f8SToomas Soome #define NCR_SIZE_512K 8 717199767f8SToomas Soome #define NCR_SIZE_1M 9 718199767f8SToomas Soome #define NCR_SIZE_2M 10 719199767f8SToomas Soome #define NCR_SIZE_4M 11 720199767f8SToomas Soome #define NCR_SIZE_8M 12 721199767f8SToomas Soome #define NCR_SIZE_16M 13 722199767f8SToomas Soome #define NCR_SIZE_32M 14 723199767f8SToomas Soome #define NCR_SIZE_4G 15 724199767f8SToomas Soome 725199767f8SToomas Soome /* 726199767f8SToomas Soome * The address region registers are used to specify the location and 727199767f8SToomas Soome * size for the eight address regions. 728199767f8SToomas Soome * 729199767f8SToomas Soome * ARRx + 0: A31-A24 of start address 730199767f8SToomas Soome * ARRx + 1: A23-A16 of start address 731199767f8SToomas Soome * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 732199767f8SToomas Soome */ 733199767f8SToomas Soome #define ARR0 0xc4 734199767f8SToomas Soome #define ARR1 0xc7 735199767f8SToomas Soome #define ARR2 0xca 736199767f8SToomas Soome #define ARR3 0xcd 737199767f8SToomas Soome #define ARR4 0xd0 738199767f8SToomas Soome #define ARR5 0xd3 739199767f8SToomas Soome #define ARR6 0xd6 740199767f8SToomas Soome #define ARR7 0xd9 741199767f8SToomas Soome 742199767f8SToomas Soome #define ARR_SIZE_0K 0 743199767f8SToomas Soome #define ARR_SIZE_4K 1 744199767f8SToomas Soome #define ARR_SIZE_8K 2 745199767f8SToomas Soome #define ARR_SIZE_16K 3 746199767f8SToomas Soome #define ARR_SIZE_32K 4 747199767f8SToomas Soome #define ARR_SIZE_64K 5 748199767f8SToomas Soome #define ARR_SIZE_128K 6 749199767f8SToomas Soome #define ARR_SIZE_256K 7 750199767f8SToomas Soome #define ARR_SIZE_512K 8 751199767f8SToomas Soome #define ARR_SIZE_1M 9 752199767f8SToomas Soome #define ARR_SIZE_2M 10 753199767f8SToomas Soome #define ARR_SIZE_4M 11 754199767f8SToomas Soome #define ARR_SIZE_8M 12 755199767f8SToomas Soome #define ARR_SIZE_16M 13 756199767f8SToomas Soome #define ARR_SIZE_32M 14 757199767f8SToomas Soome #define ARR_SIZE_4G 15 758199767f8SToomas Soome 759199767f8SToomas Soome /* 760199767f8SToomas Soome * The region control registers specify the attributes associated with 761199767f8SToomas Soome * the ARRx addres regions. 762199767f8SToomas Soome */ 763199767f8SToomas Soome #define RCR0 0xdc 764199767f8SToomas Soome #define RCR1 0xdd 765199767f8SToomas Soome #define RCR2 0xde 766199767f8SToomas Soome #define RCR3 0xdf 767199767f8SToomas Soome #define RCR4 0xe0 768199767f8SToomas Soome #define RCR5 0xe1 769199767f8SToomas Soome #define RCR6 0xe2 770199767f8SToomas Soome #define RCR7 0xe3 771199767f8SToomas Soome 772199767f8SToomas Soome #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 773199767f8SToomas Soome #define RCR_RCE 0x01 /* Enables caching for ARR7. */ 774199767f8SToomas Soome #define RCR_WWO 0x02 /* Weak write ordering. */ 775199767f8SToomas Soome #define RCR_WL 0x04 /* Weak locking. */ 776199767f8SToomas Soome #define RCR_WG 0x08 /* Write gathering. */ 777199767f8SToomas Soome #define RCR_WT 0x10 /* Write-through. */ 778199767f8SToomas Soome #define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 779199767f8SToomas Soome 780199767f8SToomas Soome /* AMD Write Allocate Top-Of-Memory and Control Register */ 781199767f8SToomas Soome #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 782199767f8SToomas Soome #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 783199767f8SToomas Soome #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 784199767f8SToomas Soome 785199767f8SToomas Soome /* AMD64 MSR's */ 786199767f8SToomas Soome #define MSR_EFER 0xc0000080 /* extended features */ 787199767f8SToomas Soome #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */ 788199767f8SToomas Soome #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */ 789199767f8SToomas Soome #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */ 790199767f8SToomas Soome #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */ 791199767f8SToomas Soome #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */ 792199767f8SToomas Soome #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */ 793199767f8SToomas Soome #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */ 794199767f8SToomas Soome #define MSR_PERFEVSEL0 0xc0010000 795199767f8SToomas Soome #define MSR_PERFEVSEL1 0xc0010001 796199767f8SToomas Soome #define MSR_PERFEVSEL2 0xc0010002 797199767f8SToomas Soome #define MSR_PERFEVSEL3 0xc0010003 798199767f8SToomas Soome #define MSR_K7_PERFCTR0 0xc0010004 799199767f8SToomas Soome #define MSR_K7_PERFCTR1 0xc0010005 800199767f8SToomas Soome #define MSR_K7_PERFCTR2 0xc0010006 801199767f8SToomas Soome #define MSR_K7_PERFCTR3 0xc0010007 802199767f8SToomas Soome #define MSR_SYSCFG 0xc0010010 803199767f8SToomas Soome #define MSR_HWCR 0xc0010015 804199767f8SToomas Soome #define MSR_IORRBASE0 0xc0010016 805199767f8SToomas Soome #define MSR_IORRMASK0 0xc0010017 806199767f8SToomas Soome #define MSR_IORRBASE1 0xc0010018 807199767f8SToomas Soome #define MSR_IORRMASK1 0xc0010019 808199767f8SToomas Soome #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ 809199767f8SToomas Soome #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ 810199767f8SToomas Soome #define MSR_NB_CFG1 0xc001001f /* NB configuration 1 */ 811199767f8SToomas Soome #define MSR_P_STATE_LIMIT 0xc0010061 /* P-state Current Limit Register */ 812199767f8SToomas Soome #define MSR_P_STATE_CONTROL 0xc0010062 /* P-state Control Register */ 813199767f8SToomas Soome #define MSR_P_STATE_STATUS 0xc0010063 /* P-state Status Register */ 814199767f8SToomas Soome #define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */ 815199767f8SToomas Soome #define MSR_SMM_ADDR 0xc0010112 /* SMM TSEG base address */ 816199767f8SToomas Soome #define MSR_SMM_MASK 0xc0010113 /* SMM TSEG address mask */ 817199767f8SToomas Soome #define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */ 818199767f8SToomas Soome #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ 819199767f8SToomas Soome #define MSR_MC0_CTL_MASK 0xc0010044 820199767f8SToomas Soome #define MSR_VM_CR 0xc0010114 /* SVM: feature control */ 821199767f8SToomas Soome #define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */ 822199767f8SToomas Soome 823199767f8SToomas Soome /* MSR_VM_CR related */ 824199767f8SToomas Soome #define VM_CR_SVMDIS 0x10 /* SVM: disabled by BIOS */ 825199767f8SToomas Soome 826199767f8SToomas Soome /* VIA ACE crypto featureset: for via_feature_rng */ 827199767f8SToomas Soome #define VIA_HAS_RNG 1 /* cpu has RNG */ 828199767f8SToomas Soome 829199767f8SToomas Soome /* VIA ACE crypto featureset: for via_feature_xcrypt */ 830199767f8SToomas Soome #define VIA_HAS_AES 1 /* cpu has AES */ 831199767f8SToomas Soome #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 832199767f8SToomas Soome #define VIA_HAS_MM 4 /* cpu has RSA instructions */ 833199767f8SToomas Soome #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 834199767f8SToomas Soome 835199767f8SToomas Soome /* Centaur Extended Feature flags */ 836199767f8SToomas Soome #define VIA_CPUID_HAS_RNG 0x000004 837199767f8SToomas Soome #define VIA_CPUID_DO_RNG 0x000008 838199767f8SToomas Soome #define VIA_CPUID_HAS_ACE 0x000040 839199767f8SToomas Soome #define VIA_CPUID_DO_ACE 0x000080 840199767f8SToomas Soome #define VIA_CPUID_HAS_ACE2 0x000100 841199767f8SToomas Soome #define VIA_CPUID_DO_ACE2 0x000200 842199767f8SToomas Soome #define VIA_CPUID_HAS_PHE 0x000400 843199767f8SToomas Soome #define VIA_CPUID_DO_PHE 0x000800 844199767f8SToomas Soome #define VIA_CPUID_HAS_PMM 0x001000 845199767f8SToomas Soome #define VIA_CPUID_DO_PMM 0x002000 846199767f8SToomas Soome 847199767f8SToomas Soome /* VIA ACE xcrypt-* instruction context control options */ 848199767f8SToomas Soome #define VIA_CRYPT_CWLO_ROUND_M 0x0000000f 849199767f8SToomas Soome #define VIA_CRYPT_CWLO_ALG_M 0x00000070 850199767f8SToomas Soome #define VIA_CRYPT_CWLO_ALG_AES 0x00000000 851199767f8SToomas Soome #define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 852199767f8SToomas Soome #define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 853199767f8SToomas Soome #define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 854199767f8SToomas Soome #define VIA_CRYPT_CWLO_NORMAL 0x00000000 855199767f8SToomas Soome #define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 856199767f8SToomas Soome #define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 857199767f8SToomas Soome #define VIA_CRYPT_CWLO_DECRYPT 0x00000200 858199767f8SToomas Soome #define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 859199767f8SToomas Soome #define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 860199767f8SToomas Soome #define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 861199767f8SToomas Soome 862199767f8SToomas Soome #endif /* !_MACHINE_SPECIALREG_H_ */ 863