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Searched refs:width (Results 1 – 24 of 24) sorted by relevance

/gfx-drm/usr/src/uts/intel/io/i915/
H A Dintel_panel.c63 int x, y, width, height; in intel_pch_panel_fitting() local
68 x = y = width = height = 0; in intel_pch_panel_fitting()
77 width = mode->hdisplay; in intel_pch_panel_fitting()
90 if (width & 1) in intel_pch_panel_fitting()
91 width++; in intel_pch_panel_fitting()
101 width = adjusted_mode->hdisplay; in intel_pch_panel_fitting()
104 width = adjusted_mode->hdisplay; in intel_pch_panel_fitting()
112 width = adjusted_mode->hdisplay; in intel_pch_panel_fitting()
128 int width) in centre_horizontally() argument
140 mode->crtc_hdisplay = width; in centre_horizontally()
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H A Dintel_fb.c60 mode_cmd.width = sizes->surface_width; in intelfb_create()
63 mode_cmd.pitches[0] = ALIGN(mode_cmd.width * ((sizes->surface_bpp + 7) / in intelfb_create()
H A Ddvo_ivch.c159 uint16_t width, height; member
270 (void) ivch_read(dvo, VR20, &priv->width); in ivch_init()
H A Dintel_sdvo.c746 uint16_t width, in intel_sdvo_create_preferred_input_timing() argument
753 args.width = width; in intel_sdvo_create_preferred_input_timing()
758 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || in intel_sdvo_create_preferred_input_timing()
784 uint16_t width, height; in intel_sdvo_get_dtd_from_mode() local
789 width = mode->hdisplay; in intel_sdvo_get_dtd_from_mode()
806 dtd->part1.h_active = width & 0xff; in intel_sdvo_get_dtd_from_mode()
808 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | in intel_sdvo_get_dtd_from_mode()
H A Dintel_overlay.c455 static int packed_width_bytes(u32 format, short width) in packed_width_bytes() argument
459 return width << 1; in packed_width_bytes()
493 static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width) in calc_swidthsw() argument
503 ret = ((offset + width + mask) >> shift) - (offset >> shift); in calc_swidthsw()
H A Dintel_sdvo_regs.h119 u16 width; member
H A Di915_reg.h2821 #define DP_PORT_WIDTH(width) (((width) - 1) << 19) argument
4300 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) argument
4914 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) argument
H A Dintel_display.c6503 if (x > (int) crtc->fb->width) in intel_crtc_update_cursor()
6548 uint32_t width, uint32_t height) in intel_crtc_cursor_set() argument
6567 if (width != 64 || height != 64) { in intel_crtc_cursor_set()
6576 if (obj->base.size < width * height * 4) { in intel_crtc_cursor_set()
6629 I915_WRITE(CURSIZE, (height << 12) | width); in intel_crtc_cursor_set()
6645 intel_crtc->cursor_width = (int16_t)width; in intel_crtc_cursor_set()
6739 intel_framebuffer_pitch_for_width(int width, int bpp) in intel_framebuffer_pitch_for_width() argument
6741 u32 pitch = DIV_ROUND_UP(width * bpp, 8); in intel_framebuffer_pitch_for_width()
6767 mode_cmd.width = mode->hdisplay; in intel_framebuffer_create_for_mode()
6769 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, in intel_framebuffer_create_for_mode()
H A Dintel_sprite.c670 if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) { in intel_update_plane()
H A Di915_gem.c229 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); in i915_gem_dumb_create()
/gfx-drm/usr/src/uts/common/io/drm/
H A Ddrm_fb_helper.c448 if (drm_mode_width(mode) > width || in drm_has_preferred_mode()
466 int width, int height) in drm_pick_cmdline_mode() argument
619 bool *enabled, int width, int height) in drm_target_preferred() argument
655 int n, int width, int height) in drm_pick_crtcs() argument
722 width, height); in drm_pick_crtcs()
742 int width, height; in drm_setup_crtcs() local
747 width = dev->mode_config.max_width; in drm_setup_crtcs()
771 enabled, width, height))) { in drm_setup_crtcs()
778 modes, enabled, width, height)) in drm_setup_crtcs()
782 width, height); in drm_setup_crtcs()
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H A Ddrm_crtc.c1882 fb_width = fb->width << 16; in drm_mode_setplane()
2070 if (hdisplay > fb->width || in drm_mode_setcrtc()
2075 fb->width, fb->height, in drm_mode_setcrtc()
2188 req->width, req->height); in drm_mode_cursor_common()
2287 r.width = or->width; in drm_mode_addfb()
2296 if ((config->min_width > r.width) || (r.width > config->max_width)) in drm_mode_addfb()
2403 if (r->width == 0 || r->width % hsub) { in framebuffer_check()
2414 unsigned int width = r->width / (i != 0 ? hsub : 1); in framebuffer_check() local
2467 if ((config->min_width > r->width) || (r->width > config->max_width)) { in drm_mode_addfb2()
2579 r->width = fb->width; in drm_mode_getfb()
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H A Ddrm_edid.c2097 int width, height; in drm_cvt_modes() local
2107 width = height * 4 / 3; in drm_cvt_modes()
2110 width = height * 16 / 9; in drm_cvt_modes()
2113 width = height * 16 / 10; in drm_cvt_modes()
2116 width = height * 15 / 9; in drm_cvt_modes()
2122 newmode = drm_cvt_mode(dev, width, height, in drm_cvt_modes()
H A Ddrm_crtc_helper.c906 fb->width = mode_cmd->width; in drm_helper_mode_fill_fb_struct()
/gfx-drm/usr/src/uts/common/drm/
H A Ddrm_mode.h362 __u32 width; member
376 __u32 width; member
477 __u32 width; member
488 __u32 width; member
594 __u32 width; member
H A Ddrm_sarea.h64 unsigned int width; member
H A Ddrm_fb_helper.h77 bool *enabled, int width, int height);
H A Ddrm_crtc.h270 unsigned int width; member
344 uint32_t handle, uint32_t width, uint32_t height);
346 uint32_t handle, uint32_t width, uint32_t height,
H A Di915_drm.h130 int width, height; /* screen size in pixels */ member
/gfx-drm/usr/src/uts/intel/io/radeon/
H A Dradeon_io32.h92 unsigned int width, height; member
100 int width; member
H A Dradeon_state.c1748 tex_width = tex->width * 4; in radeon_cp_dispatch_texture()
1749 blit_width = image->width * 4; in radeon_cp_dispatch_texture()
1758 tex_width = tex->width * 2; in radeon_cp_dispatch_texture()
1759 blit_width = image->width * 2; in radeon_cp_dispatch_texture()
1764 tex_width = tex->width * 1; in radeon_cp_dispatch_texture()
1765 blit_width = image->width * 1; in radeon_cp_dispatch_texture()
1791 image->x, image->y, image->width, image->height); in radeon_cp_dispatch_texture()
1827 image32.width = image->width; in radeon_cp_dispatch_texture()
1949 OUT_RING((image->width << 16) | height); in radeon_cp_dispatch_texture()
2555 tex.width = tex32.width; in radeon_cp_texture()
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H A Dradeon_drm.h668 unsigned int width, height; member
676 int width; /* Texture image coordinates */ member
/gfx-drm/usr/src/common/libdrm/patches/
H A Dincl-drm-i915-drm-h.patch34 int width, height; /* screen size in pixels */
/gfx-drm/usr/src/cmd/mdb/i915/
H A Di915.c1844 fb.width, in i915_gem_framebuffer_info()