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Searched refs:t1_read_reg_4 (Results 1 – 14 of 14) sorted by relevance

/illumos-gate/usr/src/uts/common/io/chxge/com/
H A Dmc4.c89 val = t1_read_reg_4(adapter, A_MC4_CFG); in t1_mc4_init()
182 val = t1_read_reg_4(adapter, A_MC4_CFG); in t1_mc4_init()
255 t1_read_reg_4(adapter, A_MC4_CE_DATA0), in t1_mc4_intr_handler()
256 t1_read_reg_4(adapter, A_MC4_CE_DATA1), in t1_mc4_intr_handler()
257 t1_read_reg_4(adapter, A_MC4_CE_DATA2), in t1_mc4_intr_handler()
258 t1_read_reg_4(adapter, A_MC4_CE_DATA3), in t1_mc4_intr_handler()
259 t1_read_reg_4(adapter, A_MC4_CE_DATA4)); in t1_mc4_intr_handler()
268 t1_read_reg_4(adapter, A_MC4_UE_DATA0), in t1_mc4_intr_handler()
269 t1_read_reg_4(adapter, A_MC4_UE_DATA1), in t1_mc4_intr_handler()
311 val = t1_read_reg_4(adap, A_MC4_BD_OP); in t1_mc4_bd_read()
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H A Dmc3.c117 cause = t1_read_reg_4(adapter, cause_reg); in t1_mc3_intr_handler()
125 t1_read_reg_4(adapter, A_MC3_CE_DATA0), in t1_mc3_intr_handler()
126 t1_read_reg_4(adapter, A_MC3_CE_DATA1), in t1_mc3_intr_handler()
127 t1_read_reg_4(adapter, A_MC3_CE_DATA2), in t1_mc3_intr_handler()
128 t1_read_reg_4(adapter, A_MC3_CE_DATA3), in t1_mc3_intr_handler()
129 t1_read_reg_4(adapter, A_MC3_CE_DATA4)); in t1_mc3_intr_handler()
138 t1_read_reg_4(adapter, A_MC3_UE_DATA0), in t1_mc3_intr_handler()
139 t1_read_reg_4(adapter, A_MC3_UE_DATA1), in t1_mc3_intr_handler()
200 val = t1_read_reg_4(adapter, A_MC3_CFG); in t1_mc3_init()
227 val = t1_read_reg_4(adapter, A_MC3_CFG); in t1_mc3_init()
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H A Dch_mac.c94 mac_intr = t1_read_reg_4(mac->adapter, in mac_intr_enable()
120 mac_intr = t1_read_reg_4(mac->adapter, in mac_intr_disable()
145 mac_intr = t1_read_reg_4(mac->adapter, in mac_intr_clear()
159 data32_lo = t1_read_reg_4(mac->adapter, in mac_get_address()
161 data32_hi = t1_read_reg_4(mac->adapter, in mac_get_address()
184 data32 = t1_read_reg_4(mac->adapter, in mac_reset()
204 val = t1_read_reg_4(mac->adapter, in mac_set_rx_mode()
220 data32 = t1_read_reg_4(mac->adapter, in mac_set_speed_duplex_fc()
255 val = t1_read_reg_4(mac->adapter, in mac_enable()
270 val = t1_read_reg_4(mac->adapter, in mac_disable()
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H A Despi.c83 status = t1_read_reg_4(adapter, A_ESPI_GOSTAT);
99 if (!(t1_read_reg_4(adapter, A_ESPI_RX_RESET) & F_RX_CLK_STATUS)) { in tricn_init()
127 u32 enable, pl_intr = t1_read_reg_4(espi->adapter, A_PL_ENABLE); in t1_espi_intr_enable()
143 (void) t1_read_reg_4(espi->adapter, A_ESPI_DIP2_ERR_COUNT); in t1_espi_intr_clear()
150 u32 pl_intr = t1_read_reg_4(espi->adapter, A_PL_ENABLE); in t1_espi_intr_disable()
158 u32 status = t1_read_reg_4(espi->adapter, A_ESPI_INTR_STATUS); in t1_espi_intr_handler()
172 (void) t1_read_reg_4(espi->adapter, A_ESPI_DIP2_ERR_COUNT); in t1_espi_intr_handler()
297 espi->misc_ctrl = t1_read_reg_4(adapter, A_ESPI_MISC_CONTROL); in t1_espi_init()
355 sel = t1_read_reg_4(adapter, A_ESPI_SCH_TOKEN3); in t1_espi_get_mon()
360 sel = t1_read_reg_4(adapter, A_ESPI_SCH_TOKEN3); in t1_espi_get_mon()
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H A Dtp.c91 u32 tr = t1_read_reg_4(adap, A_TP_TIMER_RESOLUTION); in tp_delayed_ack_ticks()
98 u32 tr = t1_read_reg_4(adap, A_TP_TIMER_RESOLUTION); in t1_tp_ticks_per_sec()
122 tp_scnt = t1_read_reg_4(adapter, A_TP_SHIFT_CNT); in tp_set_tcp_time_params()
139 val = t1_read_reg_4(tp->adapter, A_TP_PARA_REG3); in t1_tp_set_coalescing_size()
167 *data++ = t1_read_reg_4(adap, A_TP_MIB_DATA); in t1_tp_get_mib_statistics()
266 val = t1_read_reg_4(ap, A_TP_PC_CONFIG); in tp_init()
317 u32 tp_intr = t1_read_reg_4(tp->adapter, A_PL_ENABLE); in t1_tp_intr_enable()
338 u32 tp_intr = t1_read_reg_4(tp->adapter, A_PL_ENABLE); in t1_tp_intr_disable()
379 cause = t1_read_reg_4(tp->adapter, A_TP_INT_CAUSE); in t1_tp_intr_handler()
386 u32 val = t1_read_reg_4(tp->adapter, A_TP_GLOBAL_CONFIG); in set_csum_offload()
H A Dmc5.c147 return t1_read_reg_4(mc5->adapter, A_MC5_ROUTING_TABLE_INDEX); in t1_mc5_get_tcam_rtbl_base()
167 return t1_read_reg_4(mc5->adapter, A_MC5_SERVER_INDEX); in t1_mc5_get_tcam_server_base()
194 *v1 = t1_read_reg_4(adapter, A_MC5_DBGI_RSP_DATA0); in dbgi_rd_rsp3()
195 *v2 = t1_read_reg_4(adapter, A_MC5_DBGI_RSP_DATA1); in dbgi_rd_rsp3()
196 *v3 = t1_read_reg_4(adapter, A_MC5_DBGI_RSP_DATA2); in dbgi_rd_rsp3()
410 cfg = t1_read_reg_4(adap, A_MC5_CONFIG) & ~F_MODE; in t1_mc5_init()
518 u32 pl_intr = t1_read_reg_4(mc5->adapter, A_PL_ENABLE); in t1_mc5_intr_enable()
536 u32 pl_intr = t1_read_reg_4(mc5->adapter, A_PL_ENABLE); in t1_mc5_intr_disable()
563 u32 cause = t1_read_reg_4(adap, A_MC5_INT_CAUSE); in t1_mc5_intr_handler()
646 cfg = t1_read_reg_4(adapter, A_MC5_CONFIG); in t1_mc5_create()
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H A Dulp.c45 u32 pl_intr = t1_read_reg_4(ulp->adapter, A_PL_ENABLE); in t1_ulp_intr_enable()
64 u32 pl_intr = t1_read_reg_4(ulp->adapter, A_PL_ENABLE); in t1_ulp_intr_disable()
74 u32 cause = t1_read_reg_4(ulp->adapter, A_ULP_INT_CAUSE); in t1_ulp_intr_handler()
H A Dch_subr.c65 u32 val = t1_read_reg_4(adapter, reg) & mask; in t1_wait_op_done()
129 *valp = t1_read_reg_4(adapter, A_TPI_RD_DATA); in __t1_tpi_read()
224 u32 cause = t1_read_reg_4(adapter, A_PL_CAUSE); in fpga_slow_intr()
238 u32 tp_cause = t1_read_reg_4(adapter, in fpga_slow_intr()
281 if (t1_read_reg_4(adapter, A_MI0_CSR) & F_MI0_BUSY) { in fpga_mdio_read()
288 *val = t1_read_reg_4(adapter, A_MI0_DATA_EXT); in fpga_mdio_read()
300 if (t1_read_reg_4(adapter, A_MI0_CSR) & F_MI0_BUSY) { in fpga_mdio_write()
1088 u32 pl_intr = t1_read_reg_4(adapter, A_PL_CAUSE); in t1_interrupts_clear()
1104 u32 cause = t1_read_reg_4(adapter, A_PL_CAUSE); in asic_slow_intr()
1171 u32 val = t1_read_reg_4(adapter, A_TP_PC_CONFIG); in t1_get_board_rev()
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H A Dcspi.c48 *status = t1_read_reg_4(cspi->adapter, A_CSPI_INTR_STATUS); in t1_cspi_intr_status_read()
H A Dpm3393.c165 pl_intr = t1_read_reg_4(cmac->adapter, A_PL_ENABLE); in pm3393_interrupt_enable()
247 pl_intr = t1_read_reg_4(cmac->adapter, A_PL_CAUSE); in pm3393_interrupt_clear()
/illumos-gate/usr/src/uts/common/io/chxge/
H A Dglue.c90 t1_read_reg_4(ch_t *obj, uint32_t reg_val) in t1_read_reg_4() function
222 pe->pe_reg_val = reg = t1_read_reg_4(chp, pe->addr); in pe_ioctl()
240 reg = t1_read_reg_4(chp, pe->addr); in pe_ioctl()
H A Dch.h283 uint32_t t1_read_reg_4(ch_t *obj, uint32_t reg_val);
H A Dsge.c288 status = t1_read_reg_4(sge->obj, A_SG_INT_CAUSE); in sge_stop()
506 u32 val = t1_read_reg_4(sge->obj, A_PL_ENABLE); in t1_sge_intr_disable()
523 u32 val = t1_read_reg_4(sge->obj, A_PL_ENABLE); in t1_sge_intr_enable()
550 u32 cause = t1_read_reg_4(obj, A_SG_INT_CAUSE); in t1_sge_intr_error_handler()
1136 u32 irq_reg = t1_read_reg_4(sge->obj, A_SG_INT_ENABLE); in freelQs_empty()
H A Dpe.c1520 enable = t1_read_reg_4(adapter, A_PL_ENABLE); in ext_intr_task()
1531 u32 enable = t1_read_reg_4(adapter, A_PL_ENABLE); in t1_os_elmer0_ext_intr()