xref: /illumos-gate/usr/src/uts/sun/sys/socalreg.h (revision db194e27)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 1998 Sun Microsystems, Inc. All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef _SYS_SOCALREG_H
27 #define	_SYS_SOCALREG_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34 
35 /*
36  * socalreg.h:
37  *
38  * 	SOC+ Register Definitions, Interface Adaptor to Fiber Channel
39  */
40 
41 #define	N_SOCAL_NPORTS	2
42 
43 /*
44  * Define the SOC+ configuration register bits.
45  */
46 typedef union socal_cr_register {
47 	struct cr {
48 		uint_t	aaa:5;
49 		uint_t	ramsel:3;	/* Ram bank select. */
50 		uint_t	bbb:6;
51 		uint_t	eepromsel:2;	/* Eeprom bank select. */
52 		uint_t	ccc:5;
53 		uint_t	burst64:3;	/* Sbus Burst size, 64 bit mode. */
54 		uint_t	ddd:2;
55 		uint_t	parenable:1;	/* Partity test enable. */
56 		uint_t	parsbus:1;	/* Sbus Parity checking. */
57 		uint_t	sbusmode:1;	/* Enhanced Sbus mode. */
58 		uint_t	sbusburst:3;	/* Sbus burst size. */
59 	} reg;
60 	uint32_t	w;
61 } socal_cr_reg_t;
62 
63 /*
64  * Define Configuration register bits.
65  */
66 
67 #define	SOCAL_CR_SBUS_BURST_SIZE_MASK		0x007
68 #define	SOCAL_CR_SBUS_BURST_SIZE_64BIT_MASK	0x700
69 #define	SOCAL_CR_SBUS_BURST_SIZE_64BIT(a)	\
70 	(((a) & SOCAL_CR_SBUS_BURST_SIZE_64BIT_MASK) >> 8)
71 
72 #define	SOCAL_CR_BURST_4		0x0
73 #define	SOCAL_CR_BURST_8		0x3
74 #define	SOCAL_CR_BURST_16		0x4
75 #define	SOCAL_CR_BURST_32		0x5
76 #define	SOCAL_CR_BURST_64		0x6
77 #define	SOCAL_CR_BURST_128		0x7
78 
79 #define	SOCAL_CR_SBUS_ENHANCED		0x08
80 #define	SOCAL_CR_SBUS_PARITY_CHK	0x10
81 #define	SOCAL_CR_SBUS_PARITY_TEST	0x20
82 
83 #define	SOCAL_CR_EEPROM_BANK_MASK	0x30000
84 #define	SOCAL_CR_EEPROM_BANK(a)	(((a) & SOCAL_CR_EEPROM_BANK_MASK) >> 16)
85 
86 #define	SOCAL_CR_EXTERNAL_RAM_BANK_MASK	0x7000000
87 #define	SOCAL_CR_EXTERNAL_RAM_BANK(a) \
88 	(((a) & SOCAL_CR_EXTERNAL_RAM_BANK_MASK) >> 24)
89 
90 /*
91  * Define SOC+ Slave Access Register.
92  */
93 typedef union socal_sae_register {
94 	struct sae {
95 		uint_t	aaa:29;			/* Reserved. */
96 		uint_t	alignment_err:1;	/* Soc Alignment Error. */
97 		uint_t	bad_size_err:1;		/* Bad Size error. */
98 		uint_t	parity_err:1;		/* Parity Error. */
99 	} reg;
100 	uint32_t	w;
101 } socal_sae_reg_t;
102 
103 /*
104  * Define the Slave Access Regsiter Bits.
105  */
106 
107 #define	SOCAL_SAE_PARITY_ERROR		0x01
108 #define	SOCAL_SAE_UNSUPPORTED_TRANSFER	0x02
109 #define	SOCAL_SAE_ALIGNMENT_ERROR	0x04
110 
111 /*
112  * Define SOC+ Command and Status Register.
113  */
114 typedef union socal_csr_register {
115 	struct csr {
116 		uint_t	comm_param:8;	/* Communication Parameters. */
117 		uint_t	aaa:4;
118 		uint_t	socal_to_host:4;	/* Soc to host attention. */
119 		uint_t	bbb:4;
120 		uint_t	host_to_socal:4;	/* Host to soc+ attention. */
121 		uint_t	sae:1;		/* Slave access error indicator. */
122 		uint_t	ccc:3;
123 		uint_t	int_pending:1;	/* Interrupt Pending. */
124 		uint_t	nqcmd:1;	/* Non queued command */
125 		uint_t	idle:1;		/* SOC+ idle indicator. */
126 		uint_t	reset:1;	/* Software Reset. */
127 	} reg;
128 	uint32_t	w;
129 } socal_csr_reg_t;
130 
131 
132 /*
133  * Define SOC+ CSR Register Macros.
134  */
135 #define	SOCAL_CSR_ZEROS		0x00000070
136 #define	SOCAL_CSR_SOCAL_TO_HOST	0x000f0000
137 #define	SOCAL_CSR_HOST_TO_SOCAL	0x00000f00
138 #define	SOCAL_CSR_SLV_ACC_ERR	0x00000080
139 #define	SOCAL_CSR_INT_PENDING	0x00000008
140 #define	SOCAL_CSR_NON_Q_CMD	0x00000004
141 #define	SOCAL_CSR_IDLE		0x00000002
142 #define	SOCAL_CSR_SOFT_RESET	0x00000001
143 
144 #define	SOCAL_CSR_1ST_S_TO_H	0x00010000
145 #define	SOCAL_CSR_1ST_H_TO_S	0x00000100
146 
147 #define	SOCAL_CSR_RSP_QUE_0	SOCAL_CSR_1ST_S_TO_H
148 #define	SOCAL_CSR_RSP_QUE_1	0x00020000
149 #define	SOCAL_CSR_RSP_QUE_2	0x00040000
150 #define	SOCAL_CSR_RSP_QUE_3	0x00080000
151 
152 #define	SOCAL_CSR_REQ_QUE_0	SOCAL_CSR_1ST_H_TO_S
153 #define	SOCAL_CSR_REQ_QUE_1	0x00000200
154 #define	SOCAL_CSR_REQ_QUE_2	0x00000400
155 #define	SOCAL_CSR_REQ_QUE_3	0x00000800
156 
157 /*
158  * Define SOC Interrupt Mask Register Bits.
159  */
160 
161 #define	SOCAL_IMR_NON_QUEUED_STATE	0x04
162 #define	SOCAL_IMR_SLAVE_ACCESS_ERROR	0x80
163 
164 #define	SOCAL_IMR_REQUEST_QUEUE_0	0x100
165 #define	SOCAL_IMR_REQUEST_QUEUE_1	0x200
166 #define	SOCAL_IMR_REQUEST_QUEUE_2	0x400
167 #define	SOCAL_IMR_REQUEST_QUEUE_3	0x800
168 
169 #define	SOCAL_IMR_RESPONSE_QUEUE_0	0x10000
170 #define	SOCAL_IMR_RESPONSE_QUEUE_1	0x20000
171 #define	SOCAL_IMR_RESPONSE_QUEUE_2	0x40000
172 #define	SOCAL_IMR_RESPONSE_QUEUE_3	0x80000
173 
174 /*
175  * Define SOC+ Request Queue Index Register
176  */
177 typedef union socal_reqp_register {
178 	struct reqp {
179 		uint_t	reqq0_index:8;
180 		uint_t	reqq1_index:8;
181 		uint_t	reqq2_index:8;
182 		uint_t	reqq3_index:8;
183 	} reg;
184 	uint32_t	w;
185 } socal_reqp_reg_t;
186 
187 #define	SOCAL_REQUESTQ0_MASK	0xff000000
188 #define	SOCAL_REQUESTQ1_MASK	0x00ff0000
189 #define	SOCAL_REQUESTQ2_MASK	0x0000ff00
190 #define	SOCAL_REQUESTQ3_MASK	0x000000ff
191 
192 #define	SOCAL_REQUESTQ0_INDEX(a) (((a) & SOCAL_REQUESTQ0_MASK) >> 24)
193 #define	SOCAL_REQUESTQ1_INDEX(a) (((a) & SOCAL_REQUESTQ1_MASK) >> 16)
194 #define	SOCAL_REQUESTQ2_INDEX(a) (((a) & SOCAL_REQUESTQ2_MASK) >> 8)
195 #define	SOCAL_REQUESTQ3_INDEX(a) ((a) & SOCAL_REQUESTQ3_MASK)
196 
197 #define	SOCAL_REQUESTQ_INDEX(a, b) ((b)>>((3-(a))<<3) & 0xff)
198 
199 /*
200  * Define SOC+ Response Queue Index Register
201  */
202 typedef union socal_rspp_register {
203 	struct rspp {
204 		uint_t	rspq0_index:8;
205 		uint_t	rspq1_index:8;
206 		uint_t	rspq2_index:8;
207 		uint_t	rspq3_index:8;
208 	} reg;
209 	uint32_t	w;
210 } socal_rspp_reg_t;
211 
212 #define	SOCAL_RESPONSEQ0_MASK	0xff000000
213 #define	SOCAL_RESPONSEQ1_MASK	0x00ff0000
214 #define	SOCAL_RESPONSEQ2_MASK	0x0000ff00
215 #define	SOCAL_RESPONSEQ3_MASK	0x000000ff
216 
217 #define	SOCAL_RESPONSEQ0_INDEX(a) (((a) & SOCAL_RESPONSEQ0_MASK) >> 24)
218 #define	SOCAL_RESPONSEQ1_INDEX(a) (((a) & SOCAL_RESPONSEQ1_MASK) >> 16)
219 #define	SOCAL_RESPONSEQ2_INDEX(a) (((a) & SOCAL_RESPONSEQ2_MASK) >> 8)
220 #define	SOCAL_RESPONSEQ3_INDEX(a) ((a) & SOCAL_RESPONSEQ3_MASK)
221 
222 #define	SOCAL_RESPONSEQ_INDEX(a, b) ((b)>>((3-(a))<<3) & 0xff)
223 
224 typedef struct _socalreg_ {
225 	socal_cr_reg_t		socal_cr;	/* Configuration reg */
226 	socal_sae_reg_t		socal_sae;	/* Slave access error reg */
227 	socal_csr_reg_t		socal_csr;	/* Command Status reg */
228 	uint32_t		socal_imr;	/* Interrupt Mask reg */
229 	socal_reqp_reg_t	socal_reqp;	/* request queue index reg */
230 	socal_rspp_reg_t	socal_rspp;	/* response queue index reg */
231 } socal_reg_t;
232 
233 /*
234  * Device Address Space Offsets.
235  */
236 
237 #define	SOCAL_XRAM_OFFSET	0x10000
238 #define	SOCAL_XRAM_SIZE		0x10000
239 
240 #define	SOCAL_MAX_XCHG		1024
241 
242 #define	SOCAL_REG_OFFSET	(SOCAL_XRAM_OFFSET + SOCAL_XRAM_SIZE)
243 
244 #define	SOCAL_CQ_REQUEST_OFFSET (SOCAL_XRAM_OFFSET + 0x200)
245 #define	SOCAL_CQ_RESPONSE_OFFSET (SOCAL_XRAM_OFFSET + 0x220)
246 
247 
248 #define	SOCAL_INTR_CAUSE(socalp, csr) \
249 	(((csr) & SOCAL_CSR_SOCAL_TO_HOST) | \
250 	((~csr) & (SOCAL_CSR_HOST_TO_SOCAL))) & socalp->socal_k_imr
251 
252 /*
253  * Bus dma burst sizes
254  */
255 #ifndef BURSTSIZE
256 #define	BURSTSIZE
257 #define	BURST1			0x01
258 #define	BURST2			0x02
259 #define	BURST4			0x04
260 #define	BURST8			0x08
261 #define	BURST16			0x10
262 #define	BURST32			0x20
263 #define	BURST64			0x40
264 #define	BURST128		0x80
265 #define	BURSTSIZE_MASK		0xff
266 #define	DEFAULT_BURSTSIZE	BURST16|BURST8|BURST4|BURST2|BURST1
267 #endif  /* BURSTSIZE */
268 
269 #ifdef __cplusplus
270 }
271 #endif
272 
273 #endif /* !_SYS_SOCALREG_H */
274