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Searched refs:scr1 (Results 1 – 18 of 18) sorted by relevance

/illumos-gate/usr/src/uts/sun4u/sys/
H A Dcheetahasm.h65 add scr1, off_reg, scr1
258 add scr1, 8, scr1; \
292 sllx scr1, 32, scr1; \
321 sllx scr1, 32, scr1; \
370 or scr3, scr1, scr1; \
383 add scr1, 8, scr1; \
477 sllx scr1, 32, scr1; \
526 add scr1, 8, scr1; \
537 add scr1, 8, scr1; \
607 srlx scr1, 1, scr1
[all …]
H A Dtraptrace.h181 rdpr %pstate, scr1; \
182 andcc scr1, PSTATE_IE | PSTATE_AM, scr1; \
187 sll scr1, TRAPTR_SIZE_SHIFT, scr1; \
189 add ptr, scr1, scr1; \
202 ld [scr1 + TRAPTR_OFFSET], scr1; \
204 add ptr, scr1, ptr;
219 wr %g0, scr1, %asi; \
221 ld [scr1 + %lo(trap_freeze)], scr1; \
227 add scr1, TRAP_ENT_SIZE, scr1; \
229 cmp scr1, scr3; \
[all …]
H A Dmachthread.h169 rdpr %tl, scr1; \
170 cmp scr1, 2; \
179 cmp scr1, scr2; \
190 and scr1, TSTATE_CWP, scr1; \
202 add scr1, 4, scr1; \
212 sllx scr1, WSTATE_SHIFT, scr1; \
221 ld [scr1 + %lo(nwin_minus_one)], scr1; \
250 ldxa [scr1]ASI_MMU_CTX, scr1; \
251 xor scr2, scr1, scr1; \
252 srlx scr1, CTXREG_NEXT_SHIFT, scr1; \
[all …]
H A Dmachclock.h42 #define RD_TICK_NO_SUSPEND_CHECK(out, scr1) \ argument
47 #define RD_TICK(out, scr1, scr2, label) \ argument
48 RD_TICK_NO_SUSPEND_CHECK(out, scr1);
58 #define RD_CLOCK_TICK(out, scr1, scr2, label) \ argument
60 RD_TICK(out,scr1,scr2,label)
62 #define RD_CLOCK_TICK_NO_SUSPEND_CHECK(out, scr1) \ argument
64 RD_TICK_NO_SUSPEND_CHECK(out,scr1)
/illumos-gate/usr/src/uts/sun4v/sys/
H A Dtraptrace.h239 andcc scr1, PSTATE_IE | PSTATE_AM, scr1; \
244 sll scr1, TRAPTR_SIZE_SHIFT, scr1; \
246 add ptr, scr1, scr1; \
259 ld [scr1 + TRAPTR_OFFSET], scr1; \
261 add ptr, scr1, ptr;
276 wr %g0, scr1, %asi; \
278 ld [scr1 + %lo(trap_freeze)], scr1; \
284 add scr1, TRAP_ENT_SIZE, scr1; \
286 cmp scr1, scr3; \
294 rdpr %tl, scr1; \
[all …]
H A Dmachclock.h60 ldx [scr1 + %lo(native_stick_offset)], scr1; \
66 add out, scr1, out
85 ldx [scr1 + %lo(native_stick_offset)], scr1; \
108 ldx [scr1 + %lo(native_tick_offset)], scr1; \
118 ldx [scr1 + %lo(native_tick_offset)], scr1; \
153 lduw [scr1 + %lo(use_stick)], scr1; \
158 ldx [scr1 + %lo(native_stick_offset)], scr1; \
162 ldx [scr1 + %lo(native_tick_offset)], scr1; \
172 ldx [scr1 + %lo(native_stick_offset)], scr1; \
180 ldx [scr1 + %lo(native_stick_offset)], scr1; \
[all …]
/illumos-gate/usr/src/uts/sparc/v7/sys/
H A Dtraptrace.h103 CPU_INDEX(scr1); \
104 sll scr1, TRAPTR_SIZE_SHIFT, scr1; \
106 ld [ptr + scr1], ptr; \
107 set panicstr, scr1; \
108 ld [scr1], scr1; \
109 tst scr1; \
123 add scr2, scr1, scr1; \
135 st ptr, [scr1]
146 ld [scr1 + CPU_BASE_SPL], scr1; \
148 subcc scr1, scr2, scr1; \
[all …]
/illumos-gate/usr/src/uts/intel/sys/
H A Dtraptrace.h124 addq scr2, scr1; \
125 movq TRAPTR_NEXT(scr1), ptr; \
142 addl $trap_trace_ctl, scr1; \
174 xorq scr1, scr1; \
177 movq scr2, (ptr, scr1, 1); \
178 addq $CLONGSIZE, scr1; \
179 cmpq $REGSIZE, scr1; \
189 xorl scr1, scr1; \
192 movl scr2, (ptr, scr1, 1); \
193 addl $CLONGSIZE, scr1; \
[all …]
/illumos-gate/usr/src/uts/sun4v/vm/
H A Dmach_sfmmu.h88 rdpr %tpc, scr1; \
91 cmp scr1, scr2; \
164 sllx scr1, TTARGET_CTX_SHIFT, scr1; \
167 or ttarget, scr1, ttarget
237 mov %o0, scr1; \
251 mov scr1, %o0; \
264 mov %o0, scr1; \
278 mov scr1, %o0; \
303 set 1, scr1; \
305 sllx scr1, scr3, scr1; \
[all …]
/illumos-gate/usr/src/uts/sun4/sys/
H A Dclock.h244 #define NATIVE_TIME_TO_NSEC_SCALE(out, scr1, scr2, shift) \ argument
248 mulx out, scr1, out; /* delay: 32-bit fast path */ \
251 mulx scr2, scr1, scr2; /* scr2 = (H*F) */ \
253 mulx out, scr1, scr1; /* scr1 = (L*F) */ \
254 srlx scr1, 32, scr1; /* scr1 = (L*F) >> 32 */ \
256 add scr1, scr2, out; /* out = (H*F) + ((L*F) >> 32) */\
261 #define NATIVE_TIME_TO_NSEC(out, scr1, scr2) \ argument
262 sethi %hi(nsec_scale), scr1; /* load scaling factor */ \
263 ld [scr1 + %lo(nsec_scale)], scr1; \
264 NATIVE_TIME_TO_NSEC_SCALE(out, scr1, scr2, NSEC_SHIFT);
/illumos-gate/usr/src/uts/sun4u/cpu/
H A Dus3_jalapeno_asm.S105 andn scr1, scr2, scr1; \
107 or scr1, scr2, scr1; \
150 andn scr1, scr2, scr1; \
152 or scr1, scr2, scr1; \
277 add scr1, index, scr1; \
283 add scr1, index, scr1; \
289 add scr1, index, scr1; \
304 and physaddr, scr1, scr1; \
305 or scr2, scr1, scr1; \
315 mulx scr1, CPU_NODE_SIZE, scr1; \
[all …]
H A Dus3_cheetah_asm.S61 #define ECACHE_FLUSH_LINE(physaddr, ecache_size, scr1, scr2) \ argument
62 xor physaddr, ecache_size, scr1; \
65 and scr1, scr2, scr1; \
67 add scr1, scr2, scr1; \
68 ECACHE_REFLUSH_LINE(ecache_size, scr1, scr2)
H A Dopl_olympus_asm.S450 sll scr1, TRAPTR_SIZE_SHIFT, scr1; \
452 add ptr, scr1, scr1; \
457 ld [scr1 + TRAPTR_OFFSET], scr1; \
458 add ptr, scr1, ptr; \
461 rd STICK, scr1; \
463 rdpr %tl, scr1; \
465 rdpr %tt, scr1; \
467 rdpr %tpc, scr1; \
469 rdpr %tstate, scr1; \
485 add scr1, TRAP_ENT_SIZE, scr1; \
[all …]
H A Dus3_cheetahplus_asm.S74 #define ECACHE_FLUSH_LINE(physaddr, ec_set_size, scr1, scr2) \ argument
75 sub ec_set_size, 1, scr1; \
76 and physaddr, scr1, scr1; \
78 or scr2, scr1, scr1; \
79 ECACHE_REFLUSH_LINE(ec_set_size, scr1, scr2)
H A Dcommon_asm.S52 #define GET_NATIVE_TIME(out, scr1, scr2) \ argument
54 #define DELTA_NATIVE_TIME(delta, reg, scr1, scr2, scr3) \ argument
60 #define WR_TICKCMPR(in, scr1, scr2, label) \ argument
182 #define GET_NATIVE_TIME(out, scr1, scr2) \ argument
184 #define DELTA_NATIVE_TIME(delta, reg, scr1, scr2, scr3) \ argument
199 #define WR_TICKCMPR(cmpr,scr1,scr2,label) \ argument
206 #define WR_TICKCMPR(in,scr1,scr2,label) \ argument
H A Dspitfire_asm.S311 #define GET_CPU_PRIVATE_PTR(r_or_s, scr1, scr2, label) \ argument
312 CPU_ADDR(scr1, scr2); \
313 ldn [scr1 + CPU_PRIVATE], scr1; \
314 cmp scr1, 0; \
317 add scr1, r_or_s, scr1; \
/illumos-gate/usr/src/uts/sun4u/vm/
H A Dmach_sfmmu.h121 rdpr %tpc, scr1; \
124 cmp scr1, scr2; \
166 ldxa [scr1]ASI_DMMU, tagacc
191 ldxa [scr1]ASI_IMMU, itagacc
205 andn daddr, scr1, daddr
241 and scr1, TTE_SZ_BITS, scr1; /* scr1 = tte_size */ \
244 or scr1, scr3, scr1; \
245 sllx scr1, 1, scr2; \
254 set 1, scr1; \
256 sllx scr1, scr3, scr1; \
[all …]
/illumos-gate/usr/src/lib/libc/sparcv9/gen/
H A Dstrcmp.S131 cmp %o3, %g1 ! *scr1 == *src2 ?