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Searched refs:sarea_priv (Results 1 – 8 of 8) sorted by relevance

/gfx-drm/usr/src/uts/intel/io/radeon/
H A Dradeon_state.c863 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; in radeon_cp_dispatch_clear() local
1401 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; in radeon_cp_dispatch_swap() local
1555 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; in radeon_cp_dispatch_vertex() local
1652 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; in radeon_cp_dispatch_indices() local
2216 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; in radeon_cp_clear() local
2323 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; in radeon_cp_swap() local
2357 sarea_priv = dev_priv->sarea_priv; in radeon_cp_vertex()
2445 sarea_priv = dev_priv->sarea_priv; in radeon_cp_indices()
2495 sarea_priv->dirty)) { in radeon_cp_indices()
2717 sarea_priv = dev_priv->sarea_priv; in radeon_cp_vertex2()
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H A Dradeon_drv.h224 drm_radeon_sarea_t *sarea_priv; member
1104 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
1105 if (sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE) { \
1109 sarea_priv->last_dispatch = 0; \
H A Dradeon_cp.c1223 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0; in radeon_cp_init_ring_buffer()
1224 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame); in radeon_cp_init_ring_buffer()
1226 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0; in radeon_cp_init_ring_buffer()
1228 dev_priv->sarea_priv->last_dispatch); in radeon_cp_init_ring_buffer()
1230 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0; in radeon_cp_init_ring_buffer()
1231 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear); in radeon_cp_init_ring_buffer()
1526 dev_priv->sarea_priv = (drm_radeon_sarea_t *)(uintptr_t) in radeon_do_init_cp()
H A Dr300_cmdbuf.c737 buf_priv->age = ++dev_priv->sarea_priv->last_dispatch; in r300_discard_buffer()
980 RADEON_DISPATCH_AGE(dev_priv->sarea_priv->last_dispatch); in r300_do_cp_cmdbuf()
/gfx-drm/usr/src/uts/intel/io/i915/
H A Di915_dma.c91 if (master_priv->sarea_priv) in i915_update_dri1_breadcrumb()
217 if (master_priv->sarea_priv) in i915_initialize()
435 if (master_priv->sarea_priv) in i915_emit_breadcrumb()
550 if (!master_priv->sarea_priv) in i915_dispatch_flip()
626 master_priv->sarea_priv; in i915_batchbuffer()
667 if (sarea_priv) in i915_batchbuffer()
682 master_priv->sarea_priv; in i915_cmdbuffer()
734 if (sarea_priv) in i915_cmdbuffer()
757 if (master_priv->sarea_priv) in i915_emit_irq()
782 if (master_priv->sarea_priv) in i915_wait_irq()
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H A Dintel_ringbuffer.c1497 if (master_priv->sarea_priv) in ring_wait_for_space()
1498 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; in ring_wait_for_space()
H A Dintel_display.c2146 if (!master_priv->sarea_priv) in intel_crtc_update_sarea_pos()
2151 master_priv->sarea_priv->pipeA_x = x; in intel_crtc_update_sarea_pos()
2152 master_priv->sarea_priv->pipeA_y = y; in intel_crtc_update_sarea_pos()
2155 master_priv->sarea_priv->pipeB_x = x; in intel_crtc_update_sarea_pos()
2156 master_priv->sarea_priv->pipeB_y = y; in intel_crtc_update_sarea_pos()
3758 if (!master_priv->sarea_priv) in intel_crtc_update_sarea()
3763 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; in intel_crtc_update_sarea()
3764 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; in intel_crtc_update_sarea()
3767 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; in intel_crtc_update_sarea()
3768 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; in intel_crtc_update_sarea()
H A Di915_drv.h245 struct _drm_i915_sarea *sarea_priv; member