Searched refs:pcie_link_width (Results 1 – 4 of 4) sorted by relevance
463 uint32_t pcie_link_width; member
3944 ethstat->lanes.value.ul = mgp->pcie_link_width; in myri10ge_nic_stat_kstat_update()4407 if (mgp->pcie_link_width != 0 && mgp->pcie_link_width < 8) { in myri10ge_select_firmware()4409 mgp->name, mgp->pcie_link_width); in myri10ge_select_firmware()5840 mgp->pcie_link_width = link_width; in myri10ge_attach()
300 typedef enum pcie_link_width { enum
94 array set pcie_link_width {0 {BB_16 lanes} 1 {1 lane} 2 {2 lanes} 3 {4 lanes} 4 {8 lanes} }216 …e 4 128,elementSize 0 128,stringFormat {^(\d+)$} 128,listType enum 128,allowedList pcie_link_width\