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/gfx-drm/usr/src/common/libdrm/patches/
H A Dxf86drmMode-c.patch11 +/* for now return 0 on solaris */
H A Dincl-drm-drm-h.patch107 + _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
121 - _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
H A Dincl-drm-i915-drm-h.patch95 /* Userspace can request & wait on irq's:
/gfx-drm/
H A DREADME59 the kernel build parts of this gate are based on the
60 "ON skeleton" gate: https://github.com/gwr/on-skel
/gfx-drm/usr/src/uts/intel/ml/
H A Dia32.il181 * The pause instruction is a NOP on all other IA-32 processors.
191 * prefetch is an SSE extension which is not supported on older 32-bit processors
H A Damd64.il176 * The pause instruction is a NOP on all other IA-32 processors.
/gfx-drm/usr/src/pkg/transforms/
H A Dpublish39 # won't abort based on the action.
/gfx-drm/usr/src/common/mapfiles/common/
H A Dmap.bssalign27 # specification may be machine-specific, and may lose its benefit on different
H A Dmap.execdata24 # an executable for applications which rely on this. This is the default
H A Dmap.noexbss25 # can be used on x86 architectures to create a non-executable data
H A Dmap.noexdata24 # within an executable. Note that this only functions properly on the
/gfx-drm/usr/src/uts/intel/io/radeon/
H A Dradeon_cp.c1300 static void radeon_set_pciegart(drm_radeon_private_t *dev_priv, int on) in radeon_set_pciegart() argument
1303 if (on) { in radeon_set_pciegart()
1329 static void radeon_set_pcigart(drm_radeon_private_t *dev_priv, int on) in radeon_set_pcigart() argument
1334 radeon_set_pciegart(dev_priv, on); in radeon_set_pcigart()
1340 if (on) { in radeon_set_pcigart()
/gfx-drm/usr/src/pkg/manifests/
H A Ddriver-graphics-agpgart.mf49 # This driver is not used on Gen6 or later (Sandy Bridge etc.)
/gfx-drm/usr/src/uts/intel/io/i915/
H A Dintel_display.c1418 WARN_ON(!pll->on); in ironlake_enable_shared_dpll()
1422 WARN_ON(pll->on); in ironlake_enable_shared_dpll()
1426 pll->on = true; in ironlake_enable_shared_dpll()
1456 WARN_ON(!pll->on); in intel_disable_shared_dpll()
1462 pll->on = false; in intel_disable_shared_dpll()
3040 WARN_ON(pll->on); in intel_put_shared_dpll()
3111 WARN_ON(pll->on); in intel_get_shared_dpll()
6488 bool on) in intel_crtc_update_cursor() argument
8379 if(pll->on != active) in check_shared_dpll_state()
8381 pll->on, active); in check_shared_dpll_state()
[all …]
H A Di915_drv.h152 bool on; /* is the PLL actually active? Disabled during modeset */ member
/gfx-drm/usr/src/common/libdrm/
H A DLICENSE_LIBDRM6 based on information made available to Oracle by the third party
1564 on the rights to use, copy, modify, merge, publish, distribute, sub
1592 on the rights to use, copy, modify, merge, publish, distribute, sub