1
2 /*****************************************************************************
3 * CDDL HEADER START
4 *
5 * The contents of this file are subject to the terms of the
6 * Common Development and Distribution License (the "License").
7 * You may not use this file except in compliance with the License.
8 *
9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 * or http://www.opensolaris.org/os/licensing.
11 * See the License for the specific language governing permissions
12 * and limitations under the License.
13 *
14 * When distributing Covered Code, include this CDDL HEADER in each
15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 * If applicable, add the following below this CDDL HEADER, with the
17 * fields enclosed by brackets "[]" replaced with your own identifying
18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 *
20 * CDDL HEADER END
21 *
22 * Copyright 2014 QLogic Corporation
23 * The contents of this file are subject to the terms of the
24 * QLogic End User License (the "License").
25 * You may not use this file except in compliance with the License.
26 *
27 * You can obtain a copy of the License at
28 * http://www.qlogic.com/Resources/Documents/DriverDownloadHelp/
29 * QLogic_End_User_Software_License.txt
30 * See the License for the specific language governing permissions
31 * and limitations under the License.
32 *
33 *****************************************************************************/
34
35 #include <minmax.h>
36
37 // portable integer type of the pointer size for current platform (64/32)
38 typedef u64_t mm_int_ptr_t;
39
40 typedef int mm_spin_lock_t;
41
42 #define mm_read_barrier_imp()
43 #define mm_write_barrier_imp()
44 #define mm_barrier_imp()
45
mm_atomic_set_imp(u32_t * p,u32_t v)46 static __inline void mm_atomic_set_imp(u32_t *p, u32_t v)
47 {
48 *p = v;
49 }
50
mm_atomic_dec_imp(u32_t * p)51 static __inline s32_t mm_atomic_dec_imp(u32_t *p)
52 {
53 return --(*p);
54 }
55
mm_atomic_inc_imp(u32_t * p)56 static __inline s32_t mm_atomic_inc_imp(u32_t *p)
57 {
58 return ++(*p);
59 }
60
61
62 #define MM_WRITE_DOORBELL_IMP(PDEV, BAR, CID, VAL) \
63 LM_BAR_WR32_ADDRESS((PDEV), ((u8_t *)PFDEV(PDEV)->context_info->array[VF_TO_PF_CID((PDEV),(CID))].cid_resc.mapped_cid_bar_addr + (DPM_TRIGER_TYPE)), (VAL))
64
65 #define MM_REGISTER_LPME_IMP(_pdev, _func, _b_fw_access, _b_queue_for_fw) \
66 (LM_STATUS_SUCCESS)
67
68
69 #define MM_ACQUIRE_SPQ_LOCK_IMP(pdev) \
70 DbgMessage(pdev, VERBOSEi, "Acquiring global SPQ lock\n");
71 #define MM_RELEASE_SPQ_LOCK_IMP(pdev) \
72 DbgMessage(pdev, VERBOSEi, "Releasing global SPQ lock\n");
73 #define MM_ACQUIRE_SPQ_LOCK_DPC_IMP(pdev) \
74 DbgMessage(pdev, VERBOSEi, "Acquiring global SPQ lock\n");
75 #define MM_RELEASE_SPQ_LOCK_DPC_IMP(pdev) \
76 DbgMessage(pdev, VERBOSEi, "Releasing global SPQ lock\n");
77
78 #define MM_ACQUIRE_CID_LOCK_IMP(pdev) \
79 DbgMessage(pdev, VERBOSEi, "Acquiring global CID lock\n");
80 #define MM_RELEASE_CID_LOCK_IMP(pdev) \
81 DbgMessage(pdev, VERBOSEi, "Releasing global CID lock\n");
82
83 #define MM_ACQUIRE_REQUEST_LOCK_IMP(pdev) \
84 DbgMessage(pdev, VERBOSEi, "Acquiring ramrod lock\n");
85 #define MM_RELEASE_REQUEST_LOCK_IMP(pdev) \
86 DbgMessage(pdev, VERBOSEi, "Releasing ramrod lock\n");
87
88 #define MM_ACQUIRE_PHY_LOCK_IMP(pdev) \
89 DbgMessage(pdev, VERBOSEi, "Acquiring phy lock\n");
90 #define MM_RELEASE_PHY_LOCK_IMP(pdev) \
91 DbgMessage(pdev, VERBOSEi, "Releasing phy lock\n");
92 #define MM_ACQUIRE_PHY_LOCK_DPC_IMP(pdev) \
93 DbgMessage(pdev, VERBOSEi, "Acquiring phy lock\n");
94 #define MM_RELEASE_PHY_LOCK_DPC_IMP(pdev) \
95 DbgMessage(pdev, VERBOSEi, "Releasing phy lock\n");
96
97 #define MM_ACQUIRE_MCP_LOCK_IMP(pdev)
98 #define MM_RELEASE_MCP_LOCK_IMP(pdev)
99
100 #define MM_ACQUIRE_ISLES_CONTROL_LOCK_IMP(pdev) \
101 DbgMessage(pdev, VERBOSEi, "Acquiring isles control lock\n");
102 #define MM_RELEASE_ISLES_CONTROL_LOCK_IMP(pdev) \
103 DbgMessage(pdev, VERBOSEi, "Releasing isles control lock\n");
104 #define MM_ACQUIRE_ISLES_CONTROL_LOCK_DPC_IMP(pdev) \
105 DbgMessage(pdev, VERBOSEi, "Acquiring isles control lock\n");
106 #define MM_RELEASE_ISLES_CONTROL_LOCK_DPC_IMP(pdev) \
107 DbgMessage(pdev, VERBOSEi, "Releasing isles control lock\n");
108
109 #define MM_ACQUIRE_IND_REG_LOCK_IMP(pdev) \
110 DbgMessage(pdev, VERBOSEi, "Acquiring ind_reg lock\n");
111 #define MM_RELEASE_IND_REG_LOCK_IMP(pdev) \
112 DbgMessage(pdev, VERBOSEi, "Releasing ind_reg lock\n");
113
114 #define MM_ACQUIRE_LOADER_LOCK_IMP() \
115 DbgMessage(pdev, VERBOSEi, "Acquiring loader lock\n");
116 #define MM_RELEASE_LOADER_LOCK_IMP() \
117 DbgMessage(pdev, VERBOSEi, "Releasing loader lock\n");
118
119 #define MM_ACQUIRE_SP_REQ_MGR_LOCK_IMP(pdev) \
120 DbgMessage(pdev, VERBOSEi, "Acquiring sp_req_mgr lock\n");
121 #define MM_RELEASE_SP_REQ_MGR_LOCK_IMP(pdev) \
122 DbgMessage(pdev, VERBOSEi, "Releasing sp_req_mgr lock\n");
123
124 #define MM_ACQUIRE_SB_LOCK_IMP(pdev, sb_idx) \
125 DbgMessage(pdev, VERBOSEi, "Acquiring sb lock\n");
126 #define MM_RELEASE_SB_LOCK_IMP(pdev, sb_idx) \
127 DbgMessage(pdev, VERBOSEi, "Releasing sb lock\n");
128
129 #define MM_ACQUIRE_ETH_CON_LOCK_IMP(pdev) \
130 DbgMessage(pdev, VERBOSEi, "Acquiring eth con lock\n");
131 #define MM_RELEASE_ETH_CON_LOCK_IMP(pdev) \
132 DbgMessage(pdev, VERBOSEi, "Releasing eth con lock\n");
133
mm_init_lock(struct _lm_device_t * _pdev,mm_spin_lock_t * lock)134 static void mm_init_lock(struct _lm_device_t *_pdev,
135 mm_spin_lock_t *lock)
136 {
137 /* Do nothing */
138 }
139
mm_acquire_lock(mm_spin_lock_t * spinlock)140 static __inline lm_status_t mm_acquire_lock(mm_spin_lock_t *spinlock)
141 {
142 DbgMessage(NULL, VERBOSEi, "Acquiring lock #%d\n", (u32_t)spinlock);
143 return LM_STATUS_SUCCESS;
144 }
145
mm_release_lock(mm_spin_lock_t * spinlock)146 static __inline lm_status_t mm_release_lock(mm_spin_lock_t *spinlock)
147 {
148 DbgMessage(NULL, VERBOSEi, "Releasing lock #%d\n", (u32_t)spinlock);
149 return LM_STATUS_SUCCESS;
150 }
151
152
153 #ifdef VF_INVOLVED
154
155 #define MM_ACQUIRE_PF_LOCK_IMP(pdev) \
156 DbgMessage(pdev, VERBOSEi, "Acquiring pf lock\n");
157 #define MM_RELEASE_PF_LOCK_IMP(pdev) \
158 DbgMessage(pdev, VERBOSEi, "Releasing pf lock\n");
159
160 #define MM_ACQUIRE_VFS_STATS_LOCK_IMP(pdev) \
161 DbgMessage(pdev, VERBOSEi, "Acquiring vfs stats lock\n");
162 #define MM_RELEASE_VFS_STATS_LOCK_IMP(pdev) \
163 DbgMessage(pdev, VERBOSEi, "Releasing vfs stats lock\n");
164 #define MM_ACQUIRE_VFS_STATS_LOCK_DPC_IMP(pdev) \
165 DbgMessage(pdev, VERBOSEi, "Acquiring vfs stats lock\n");
166 #define MM_RELEASE_VFS_STATS_LOCK_DPC_IMP(pdev) \
167 DbgMessage(pdev, VERBOSEi, "Releasing vfs stats lock\n");
168
169 #endif /* VF_INVOLVED */
170
171
172 #define mm_er_initiate_recovery_imp(pdev) \
173 (LM_STATUS_FAILURE)
174
175 #define mm_register_dpc_imp(_pdev, _func) \
176 (LM_STATUS_FAILURE)
177
178 #define mm_empty_ramrod_received_imp(pdev, lm_cli_idx)
179
180 #define mm_debug_start_if_enabled_imp(pdev)
181 #define mm_debug_stop_if_started_imp(pdev)
182
183
184 #ifdef BIG_ENDIAN
185 // LE
186 #define mm_le16_to_cpu_imp(val) SWAP_BYTES16(val)
187 #define mm_cpu_to_le16_imp(val) SWAP_BYTES16(val)
188 #define mm_le32_to_cpu_imp(val) SWAP_BYTES32(val)
189 #define mm_cpu_to_le32_imp(val) SWAP_BYTES32(val)
190 // BE
191 #define mm_be32_to_cpu_imp(val) (val)
192 #define mm_cpu_to_be32_imp(val) (val)
193 #define mm_be16_to_cpu_imp(val) (val)
194 #define mm_cpu_to_be16_imp(val) (val)
195 #else /* LITTLE_ENDIAN */
196 // LE
197 #define mm_le16_to_cpu_imp(val) (val)
198 #define mm_cpu_to_le16_imp(val) (val)
199 #define mm_le32_to_cpu_imp(val) (val)
200 #define mm_cpu_to_le32_imp(val) (val)
201 // BE
202 #define mm_be32_to_cpu_imp(val) SWAP_BYTES32(val)
203 #define mm_cpu_to_be32_imp(val) SWAP_BYTES32(val)
204 #define mm_be16_to_cpu_imp(val) SWAP_BYTES16(val)
205 #define mm_cpu_to_be16_imp(val) SWAP_BYTES16(val)
206 #endif /* ifdef BIG_ENDIAN */
207
208
209 #define mm_get_bar_offset_imp(pdev, bar_num, bar_addr) \
210 lm_get_bar_offset_direct(pdev, bar_num, bar_addr)
211
212 #define mm_get_bar_size_imp(pdev, bar_num, val_p) \
213 lm_get_bar_size_direct(pdev, bar_num, val_p)
214
215 #define MM_DCB_MP_L2_IS_ENABLE(_pdev) (FALSE)
216
217
218