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Searched refs:i (Results 1 – 25 of 65) sorted by relevance

123

/gfx-drm/usr/src/uts/common/io/drm/
H A Ddrm_dma.c56 int i; in drm_dma_setup() local
64 for (i = 0; i <= DRM_MAX_ORDER; i++) in drm_dma_setup()
83 int i, j; in drm_dma_takedown() local
89 for (i = 0; i <= DRM_MAX_ORDER; i++) { in drm_dma_takedown()
93 i, in drm_dma_takedown()
94 dma->bufs[i].buf_count, in drm_dma_takedown()
95 dma->bufs[i].seg_count); in drm_dma_takedown()
96 kfree(dma->bufs[i].seglist, in drm_dma_takedown()
106 kfree(dma->bufs[i].buflist, in drm_dma_takedown()
151 int i; in drm_core_reclaim_buffers() local
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H A Ddrm_fb_helper.c96 for (i = 0; i < fb_helper->connector_count; i++) { in drm_fb_helper_single_add_all_connectors()
112 for (i = 0; i < fb_helper->connector_count; i++) { in drm_fb_helper_parse_command_line()
141 for (i = 0; i < crtc->gamma_size; i++) in drm_fb_helper_save_lut_atomic()
142 helper->funcs->gamma_get(crtc, &r_base[i], &g_base[i], &b_base[i], i); in drm_fb_helper_save_lut_atomic()
188 for (i = 0; i < fb_helper->crtc_count; i++) { in drm_fb_helper_restore_fbdev_mode()
252 for (i = 0; i < helper->crtc_count; i++) { in drm_fb_helper_crtc_free()
284 for (i = 0; i < crtc_count; i++) { in drm_fb_helper_init()
372 for (i = 0; i < fb_helper->crtc_count; i++) { in drm_fb_helper_single_fb_probe()
411 for (i = 0; i < fb_helper->crtc_count; i++) in drm_fb_helper_single_fb_probe()
789 for (i = 0; i < fb_helper->crtc_count; i++) { in drm_setup_crtcs()
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H A Ddrm_sun_i2c.c170 int ret = 0, i; in i2c_write_byte() local
180 for (i = 7; i >= 0; i--) { in i2c_write_byte()
216 int ret, r, i; in i2c_read_byte() local
230 for (i = 7; i >= 0; i--) { in i2c_read_byte()
351 int i, ret; in i2c_write_msg() local
353 for (i = 0; i < msg->len; i++) { in i2c_write_msg()
374 int i, ret; in i2c_read_msg() local
376 for (i = 0; i < msg->len; i++) { in i2c_read_msg()
421 int i, ret = 0; in i2c_do_transfer() local
423 for (i = 0; i < num; i++) { in i2c_do_transfer()
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H A Ddrm_cache.c45 unsigned int i; in drm_clflush_page() local
50 for (i = 0; i < PAGE_SIZE; i += x86_clflush_size) in drm_clflush_page()
51 clflush_insn(page + i); in drm_clflush_page()
60 unsigned long i; in drm_clflush_pages() local
62 for (i = 0; i < num_pages; i++) in drm_clflush_pages()
63 drm_clflush_page(pages[i]); in drm_clflush_pages()
H A Ddrm_edid.c922 for (i = 0; i < EDID_LENGTH; i++) in drm_edid_block_valid()
974 for (i = 0; i <= edid->extensions; i++) in drm_edid_is_valid()
1048 for (i = 0; i < length / 4; i++) in drm_edid_is_zero()
1066 for (i = 0; i < 4; i++) { in drm_do_get_edid()
1084 for (i = 0; i < 4; i++) { in drm_do_get_edid()
1298 for (i = 0; i < n; i++) in cea_for_each_detailed_block()
1311 for (i = 0; i < n; i++) in vtb_for_each_detailed_block()
1956 for (i = 0; i < 6; i++) { in drm_est3_modes()
2035 for (i = 0; i < 6; i++) { in do_standard_modes()
2096 for (i = 0; i < 4; i++) { in drm_cvt_modes()
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H A Ddrm_bufs.c499 int i; in drm_cleanup_buf_error() local
502 for (i = 0; i < entry->seg_count; i++) { in drm_cleanup_buf_error()
514 for (i = 0; i < entry->buf_count; i++) { in drm_cleanup_buf_error()
552 int i; in drm_addbufs_agp() local
666 for (i = 0; i < entry->buf_count; i++) { in drm_addbufs_agp()
823 for (i = 0; i < entry->buf_count; i++) { in drm_addbufs_sg()
915 for (i = 0, count = 0; i < DRM_MAX_ORDER + 1; i++) { in drm_infobufs()
923 for (i = 0, count = 0; i < DRM_MAX_ORDER + 1; i++) { in drm_infobufs()
1032 for (i = 0; i < request->count; i++) { in drm_freebufs()
1126 for (i = 0; i < dma->buf_count; i++) { in drm_mapbufs()
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H A Ddrm_ioctl.c135 int i; in drm_getmap() local
141 i = 0; in drm_getmap()
144 if (i == idx) { in drm_getmap()
148 i++; in drm_getmap()
185 int i; in drm_getclient() local
188 i = 0; in drm_getclient()
192 if (i++ >= idx) { in drm_getclient()
222 int i; in drm_getstats() local
226 for (i = 0; i < dev->counters; i++) { in drm_getstats()
231 stats->data[i].value = atomic_read(&dev->counts[i]); in drm_getstats()
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H A Ddrm_irq.c77 for (i = 0; i < pdev->msi_actual; i++) { in __install_irq_handler()
91 for (i = 0; i < pdev->msi_actual; i++) in __install_irq_handler()
120 for (i = 0; i < pdev->msi_actual; i++) in __uninstall_irq_handler()
125 for (i = 0; i < pdev->msi_actual; i++){ in __uninstall_irq_handler()
191 for(i = 0; i < actual; i++) in pci_enable_msi()
200 for(i = 0; i < actual; i++) in pci_enable_msi()
214 for (i = 0; i < pdev->msi_actual; i++) in pci_disable_msi()
360 for (i = 0; i < dev->num_crtcs; i++) { in vblank_disable_fn()
452 for (i = 0; i < num_crtcs; i++) { in drm_vblank_init()
580 for (i = 0; i < dev->num_crtcs; i++) { in drm_irq_uninstall()
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H A Ddrm_crtc.c79 for (i = 0; i < ARRAY_SIZE(list); i++) { \
1056 for (i = 0; i < num_modes; i++) in drm_mode_create_tv_properties()
1374 for (i = 0; i < mode_group->num_crtcs; i++) { in drm_mode_getresources()
1873 for (i = 0; i < plane->format_count; i++) in drm_mode_setplane()
2413 for (i = 0; i < num_planes; i++) { in framebuffer_check()
2747 for (i = 0; i < num_values; i++) { in drm_property_create_enum()
2773 for (i = 0; i < num_values; i++) { in drm_property_create_bitmask()
2953 for (i = 0; i < value_count; i++) { in drm_mode_getproperty_ioctl()
3121 for (i = 0; i < property->num_values; i++) in drm_property_change_is_valid()
3129 for (i = 0; i < property->num_values; i++) in drm_property_change_is_valid()
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/gfx-drm/usr/src/uts/intel/io/i915/
H A Di915_suspend.c102 for (i = 0; i <= 0x24; i++) in i915_save_vga()
111 for (i = 0; i <= 0x14; i++) in i915_save_vga()
118 for (i = 0; i < 9; i++) in i915_save_vga()
130 for (i = 0; i < 8; i++) in i915_save_vga()
163 for (i = 0; i < 7; i++) in i915_restore_vga()
170 for (i = 0; i <= 0x24; i++) in i915_restore_vga()
174 for (i = 0; i < 9; i++) in i915_restore_vga()
187 for (i = 0; i <= 0x14; i++) in i915_restore_vga()
381 for (i = 0; i < 16; i++) { in i915_save_state()
385 for (i = 0; i < 3; i++) in i915_save_state()
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H A Di915_gem_debug.c697 for (i = 0; i < num_instdone_bits; i++) { in i915_gpu_top()
713 for (i = 0; i < STATS_COUNT; i++) { in i915_gpu_top()
739 for (i = 0; i < samples_per_sec; i++) { in i915_gpu_top()
771 for (i = 0; i < STATS_COUNT; i++) { in i915_gpu_top()
791 for (i = 0; i < num_instdone_bits; i++) { in i915_gpu_top()
824 for (i = 0; i < max_lines; i++) { in i915_gpu_top()
839 stats[i] - last_stats[i]); in i915_gpu_top()
840 last_stats[i] = stats[i]; in i915_gpu_top()
847 for (i = 0; i < num_instdone_bits; i++) { in i915_gpu_top()
851 last_stats[i] = stats[i]; in i915_gpu_top()
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H A Di915_gem_execbuffer.c247 for (i = 0; i < entry->relocation_count; i++) { in i915_gem_execbuffer_relocate_object_slow()
521 for (i = 0; i < count; i++) in i915_gem_execbuffer_relocate_slow()
534 for (i = 0; i < count; i++) { in i915_gem_execbuffer_relocate_slow()
558 for (i = 0; i < count; i++) { in i915_gem_execbuffer_relocate_slow()
563 exec[i].handle, i); in i915_gem_execbuffer_relocate_slow()
646 for (i = 0; i < count; i++) { in validate_exec_list()
729 for (i = 0; i < 4; i++) { in i915_reset_gen7_sol_offsets()
908 for (i = 0; i < args->buffer_count; i++) { in i915_gem_do_execbuffer()
1015 for (i = 0; i < args->num_cliprects; i++) { in i915_gem_do_execbuffer()
1102 for (i = 0; i < args->buffer_count; i++) { in i915_gem_execbuffer()
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H A Di915_ums.c69 for (i = 0; i < 256; i++) in i915_save_palette()
70 array[i] = I915_READ(reg + (i << 2)); in i915_save_palette()
91 for (i = 0; i < 256; i++) in i915_restore_palette()
233 for (i = 0; i < 16; i++) in i915_save_display_reg()
238 for (i = 0; i < 16; i++) in i915_save_display_reg()
243 for (i = 0; i < 8; i++) in i915_save_display_reg()
247 for (i = 0; i < 8; i++) in i915_save_display_reg()
300 for (i = 0; i < 16; i++) in i915_restore_display_reg()
305 for (i = 0; i < 16; i++) in i915_restore_display_reg()
311 for (i = 0; i < 8; i++) in i915_restore_display_reg()
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H A Di915_gem_tiling.c470 int i; in i915_gem_swizzle_page() local
474 for (i = 0; i < PAGE_SIZE; i += 128) { in i915_gem_swizzle_page()
475 (void) memcpy(temp, &vaddr[i], 64); in i915_gem_swizzle_page()
476 (void) memcpy(&vaddr[i], &vaddr[i + 64], 64); in i915_gem_swizzle_page()
486 int i; in i915_gem_object_do_bit_17_swizzle() local
491 for (i = 0; i < page_count; i++) { in i915_gem_object_do_bit_17_swizzle()
494 (test_bit(i, obj->bit_17) != 0)) { in i915_gem_object_do_bit_17_swizzle()
504 int i; in i915_gem_object_save_bit_17_swizzle() local
516 for (i = 0; i < page_count; i++) { in i915_gem_object_save_bit_17_swizzle()
518 set_bit(i, obj->bit_17); in i915_gem_object_save_bit_17_swizzle()
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H A Ddvo_ch7xxx.c118 int i; in ch7xxx_get_id() local
120 for (i = 0; i < ARRAY_SIZE(ch7xxx_ids); i++) { in ch7xxx_get_id()
121 if (ch7xxx_ids[i].vid == vid) in ch7xxx_get_id()
122 return ch7xxx_ids[i].name; in ch7xxx_get_id()
130 int i; in ch7xxx_get_did() local
132 for (i = 0; i < ARRAY_SIZE(ch7xxx_dids); i++) { in ch7xxx_get_did()
133 if (ch7xxx_dids[i].did == did) in ch7xxx_get_did()
134 return ch7xxx_dids[i].name; in ch7xxx_get_did()
346 int i; in ch7xxx_dump_regs() local
348 for (i = 0; i < CH7xxx_NUM_REGS; i++) { in ch7xxx_dump_regs()
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H A Dintel_i2c.c370 return (i + 1 < num && in gmbus_is_index_read()
371 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 && in gmbus_is_index_read()
372 (msgs[i + 1].flags & I2C_M_RD)); in gmbus_is_index_read()
412 int i, reg_offset; in gmbus_xfer() local
426 for (i = 0; i < num; i++) { in gmbus_xfer()
465 ret = ret ? ret : i; in gmbus_xfer()
498 adapter->name, msgs[i].addr, in gmbus_xfer()
499 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); in gmbus_xfer()
534 int i; in intel_setup_gmbus() local
548 for (i = 0; i < GMBUS_NUM_PORTS; i++) { in intel_setup_gmbus()
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H A Dintel_sdvo.c261 for (i = 0; i < 2; i++) in intel_sdvo_write_sdvox()
423 for (i = 0; i < args_len; i++) in intel_sdvo_debug_write()
425 for (; i < 8; i++) in intel_sdvo_debug_write()
427 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { in intel_sdvo_debug_write()
468 for (i = 0; i < args_len; i++) { in intel_sdvo_write_cmd()
565 for (i = 0; i < response_len; i++) { in intel_sdvo_read_response()
904 for (i = 0; i <= av_split; i++) {
945 for (i = 0; i < hbuf_size; i += 8) { in intel_sdvo_write_infoframe()
1441 for (i = 0; i < 2; i++) in intel_enable_sdvo()
2621 for (i = 0 ; i < TV_FORMAT_NUM; i++) in intel_sdvo_tv_create_property()
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H A Di915_gem_gtt.c176 for (n = 0, i = 1; ; i++) { in i915_ppgtt_page_alloc()
207 int i; in gen6_write_pdes() local
210 for (i = 0; i < ppgtt->num_pd_entries; i++) { in gen6_write_pdes()
233 int i; in gen6_ppgtt_enable() local
306 for (i = first_pte; i < last_pte; i++) in gen6_ppgtt_clear_range()
325 for (i = first_entry, j = 0; i < ( first_entry + num_entries); i++, j++) { in gen6_ppgtt_insert_entries()
498 for (i = first_entry, j = 0; i < ( first_entry + num_entries); i++, j++) { in gen6_ggtt_insert_entries()
549 for (i = first_entry ; i < ( first_entry + num_entries); i++) { in gen6_ggtt_clear_range()
1161 for (i = first_entry, j = 0; i < ( first_entry + num_entries); i++, j++) { in intel_rw_gtt()
1168 for (i = first_entry; i < ( first_entry + num_entries); i++) { in intel_rw_gtt()
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H A Dintel_bios.c215 int i, downclock; in parse_lfp_panel_data() local
257 for (i = 0; i < 16; i++) { in parse_lfp_panel_data()
262 i); in parse_lfp_panel_data()
401 int i, child_device_num, count; in parse_sdvo_device_mapping() local
425 for (i = 0; i < child_device_num; i++) { in parse_sdvo_device_mapping()
585 int i, child_device_num, count; in parse_device_mapping() local
610 for (i = 0; i < child_device_num; i++) { in parse_device_mapping()
630 for (i = 0; i < child_device_num; i++) { in parse_device_mapping()
704 int i; in intel_parse_bios() local
711 for (i = 0; i + 4 < size; i++) { in intel_parse_bios()
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H A Di915_irq.c839 for (i = 1; i < HPD_NUM_PINS; i++) { in intel_hpd_irq_handler()
1196 for (i = 0; i < 3; i++) { in ivybridge_irq_handler()
1476 for (i = 0; i < num_pages; i++) { in i915_error_object_create_sized()
1562 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { in i915_error_state_free()
1640 for (i = 0; i < dev_priv->num_fence_regs; i++) in i915_gem_record_fences()
1645 for (i = 0; i < 16; i++) in i915_gem_record_fences()
1650 for (i = 0; i < 8; i++) in i915_gem_record_fences()
1653 for (i = 0; i < 8; i++) in i915_gem_record_fences()
1895 i++; in i915_capture_error_state()
3529 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { in i915_reenable_hotplug_timer_func()
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H A Dintel_hdmi.c81 for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) in intel_dip_infoframe_csum()
161 for (i = 0; i < len; i += 4) { in g4x_write_infoframe()
166 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) in g4x_write_infoframe()
201 for (i = 0; i < len; i += 4) { in ibx_write_infoframe()
206 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) in ibx_write_infoframe()
244 for (i = 0; i < len; i += 4) { in cpt_write_infoframe()
249 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) in cpt_write_infoframe()
284 for (i = 0; i < len; i += 4) { in vlv_write_infoframe()
289 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) in vlv_write_infoframe()
321 for (i = 0; i < len; i += 4) { in hsw_write_infoframe()
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H A Dintel_tv.c880 int i; in intel_tv_mode_lookup() local
882 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) { in intel_tv_mode_lookup()
1135 for (i = 0; i < 60; i++) in intel_tv_mode_set()
1137 for (i = 0; i < 60; i++) in intel_tv_mode_set()
1139 for (i = 0; i < 43; i++) in intel_tv_mode_set()
1141 for (i = 0; i < 43; i++) in intel_tv_mode_set()
1283 int i; in intel_tv_find_better_format() local
1291 for (i = 0; i < sizeof(tv_modes) / sizeof(*tv_modes); i++) { in intel_tv_find_better_format()
1538 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { in tv_is_present_in_vbt()
1663 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) in intel_tv_init()
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/gfx-drm/usr/src/uts/intel/io/radeon/
H A Dr300_cmdbuf.c69 int i; in r300_emit_cliprects() local
82 for (i = 0; i < nr; ++i) { in r300_emit_cliprects()
150 int i; in r300_init_reg_flags() local
153 for (i = ((reg) >> 2); i < ((reg) >> 2) + (count); i++)\ in r300_init_reg_flags()
250 int i; in r300_check_range() local
253 for (i = (reg >> 2); i < (reg >> 2) + count; i++) in r300_check_range()
277 for (i = 0; i < sz; i++) { in r300_emit_carefully_checked_packet0()
454 i++; in r300_emit_3d_load_vbpntr()
465 i++; in r300_emit_3d_load_vbpntr()
766 for (i = 0; i < header.scratch.n_bufs; i++) { in r300_scratch()
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H A Dradeon_state.c154 for (i = 0; i < 5; i++) { in radeon_check_and_fixup_packets()
170 for (i = 0; i < 5; i++) { in radeon_check_and_fixup_packets()
903 for (i = 0; i < nbox; i++) { in radeon_cp_dispatch_clear()
1034 for (i = 0; i < nbox; i++) { in radeon_cp_dispatch_clear()
1271 for (i = 0; i < nbox; i++) { in radeon_cp_dispatch_clear()
1345 for (i = 0; i < nbox; i++) { in radeon_cp_dispatch_clear()
1421 for (i = 0; i < nbox; i++) { in radeon_cp_dispatch_swap()
1885 for (i = 0; i < tex->height; i++) { in radeon_cp_dispatch_texture()
1896 for (i = 0; i < tex->height; i += 2) { in radeon_cp_dispatch_texture()
1922 for (i = 0; i < tex->height; i++) { in radeon_cp_dispatch_texture()
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H A Dradeon_cp.c876 for (i = 0; i < dev_priv->usec_timeout; i++) { in radeon_do_pixcache_flush()
897 for (i = 0; i < dev_priv->usec_timeout; i++) { in radeon_do_wait_for_fifo()
924 for (i = 0; i < dev_priv->usec_timeout; i++) { in radeon_do_wait_for_idle()
957 for (i = 0; i < 256; i++) { in radeon_cp_load_microcode()
965 for (i = 0; i < 256; i++) { in radeon_cp_load_microcode()
972 for (i = 0; i < 256; i++) { in radeon_cp_load_microcode()
1967 for (i = 0; i < RADEON_MAX_SURFACES; i++) { in radeon_do_release()
2093 for (i = start; i < dma->buf_count; i++) { in radeon_freelist_get()
2134 for (i = start; i < dma->buf_count; i++) {
2159 for (i = 0; i < dma->buf_count; i++) { in radeon_freelist_reset()
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