Home
last modified time | relevance | path

Searched refs:encp (Results 1 – 25 of 34) sorted by relevance

12

/illumos-gate/usr/src/uts/common/io/sfxge/common/
H A Dhunt_nic.c81 encp->enc_pf = pf; in hunt_board_cfg()
82 encp->enc_vf = vf; in hunt_board_cfg()
85 if (EFX_PCI_FUNCTION_IS_PF(encp)) { in hunt_board_cfg()
114 encp->enc_board_type = board_type; in hunt_board_cfg()
224 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << in hunt_board_cfg()
227 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << in hunt_board_cfg()
236 encp->enc_rx_buf_align_start = 1; in hunt_board_cfg()
248 encp->enc_evq_limit = 1024; in hunt_board_cfg()
266 encp->enc_privilege_mask = mask; in hunt_board_cfg()
277 encp->enc_intr_vec_base = base; in hunt_board_cfg()
[all …]
H A Dmedford_nic.c141 encp->enc_pf = pf; in medford_board_cfg()
142 encp->enc_vf = vf; in medford_board_cfg()
145 if (EFX_PCI_FUNCTION_IS_PF(encp)) { in medford_board_cfg()
174 encp->enc_board_type = board_type; in medford_board_cfg()
207 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << in medford_board_cfg()
215 encp->enc_rx_buf_align_start = 1; in medford_board_cfg()
231 encp->enc_evq_limit = 1024; in medford_board_cfg()
249 encp->enc_privilege_mask = mask; in medford_board_cfg()
260 encp->enc_intr_vec_base = base; in medford_board_cfg()
261 encp->enc_intr_limit = nvec; in medford_board_cfg()
[all …]
H A Dsiena_nic.c99 encp->enc_board_type = board_type; in siena_board_cfg()
102 encp->enc_clk_mult = 1; in siena_board_cfg()
108 encp->enc_clk_mult = 2; in siena_board_cfg()
112 encp->enc_evq_timer_quantum_ns = in siena_board_cfg()
114 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << in siena_board_cfg()
118 encp->enc_rx_prefix_size = 16; in siena_board_cfg()
121 encp->enc_rx_buf_align_start = 1; in siena_board_cfg()
122 encp->enc_rx_buf_align_end = 1; in siena_board_cfg()
125 encp->enc_rx_push_align = 1; in siena_board_cfg()
137 encp->enc_evq_limit = nevq; in siena_board_cfg()
[all …]
H A Dmcdi_mon.c455 encp->enc_mcdi_sensor_maskp, in mcdi_mon_stats_update()
456 encp->enc_mcdi_sensor_mask_size, in mcdi_mon_stats_update()
506 encp->enc_mcdi_sensor_mask_size, in mcdi_mon_cfg_build()
507 encp->enc_mcdi_sensor_maskp); in mcdi_mon_cfg_build()
516 encp->enc_mcdi_sensor_maskp, in mcdi_mon_cfg_build()
522 encp->enc_mcdi_sensor_maskp, in mcdi_mon_cfg_build()
523 encp->enc_mcdi_sensor_mask_size, in mcdi_mon_cfg_build()
531 encp->enc_mcdi_sensor_mask_size, in mcdi_mon_cfg_build()
532 encp->enc_mcdi_sensor_maskp); in mcdi_mon_cfg_build()
554 encp->enc_mcdi_sensor_mask_size, in mcdi_mon_cfg_free()
[all …]
H A Defx_mon.c51 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in efx_mon_name() local
55 EFSYS_ASSERT(encp->enc_mon_type != EFX_MON_INVALID); in efx_mon_name()
56 EFSYS_ASSERT3U(encp->enc_mon_type, <, EFX_MON_NTYPES); in efx_mon_name()
57 return (__efx_mon_name[encp->enc_mon_type]); in efx_mon_name()
75 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in efx_mon_init() local
90 emp->em_type = encp->enc_mon_type; in efx_mon_init()
92 EFSYS_ASSERT(encp->enc_mon_type != EFX_MON_INVALID); in efx_mon_init()
H A Def10_nic.c916 encp->enc_rx_prefix_size = 14; in ef10_get_datapath_caps()
919 encp->enc_fw_assisted_tso_enabled = in ef10_get_datapath_caps()
927 encp->enc_datapath_cap_evb = in ef10_get_datapath_caps()
935 encp->enc_rx_batching_enabled = in ef10_get_datapath_caps()
938 if (encp->enc_rx_batching_enabled) in ef10_get_datapath_caps()
939 encp->enc_rx_batch_max = 16; in ef10_get_datapath_caps()
996 if ((rc = efx_mcdi_privilege_mask(enp, encp->enc_pf, encp->enc_vf, in ef10_get_privilege_mask()
1002 if (EFX_PCI_FUNCTION_IS_PF(encp)) { in ef10_get_privilege_mask()
1167 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit)); in ef10_nic_probe()
1256 if ((encp->enc_piobuf_size == 0) || in ef10_nic_set_drv_limits()
[all …]
H A Defx_nic.c441 efx_nic_cfg_t *encp = &enp->en_nic_cfg; in efx_nic_get_vi_pool() local
459 *evq_countp = encp->enc_evq_limit; in efx_nic_get_vi_pool()
460 *rxq_countp = encp->enc_rxq_limit; in efx_nic_get_vi_pool()
461 *txq_countp = encp->enc_txq_limit; in efx_nic_get_vi_pool()
885 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in efx_mcdi_get_loopback_modes() local
925 encp->enc_loopback_types[EFX_LINK_100FDX] = modes; in efx_mcdi_get_loopback_modes()
929 encp->enc_loopback_types[EFX_LINK_1000FDX] = modes; in efx_mcdi_get_loopback_modes()
933 encp->enc_loopback_types[EFX_LINK_10000FDX] = modes; in efx_mcdi_get_loopback_modes()
942 encp->enc_loopback_types[EFX_LINK_40000FDX] = modes; in efx_mcdi_get_loopback_modes()
947 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100FDX]); in efx_mcdi_get_loopback_modes()
[all …]
H A Dsiena_sram.c40 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in siena_sram_init() local
47 rx_base = encp->enc_buftbl_limit; in siena_sram_init()
48 tx_base = rx_base + (encp->enc_rxq_limit * in siena_sram_init()
H A Defx_mcdi.c1177 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in efx_mcdi_drv_attach() local
1236 encp->enc_func_flags = flags; in efx_mcdi_drv_attach()
1384 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in efx_mcdi_get_phy_cfg() local
1411 (void) strncpy(encp->enc_phy_name, in efx_mcdi_get_phy_cfg()
1413 MIN(sizeof (encp->enc_phy_name) - 1, in efx_mcdi_get_phy_cfg()
1416 (void) memset(encp->enc_phy_revision, 0, in efx_mcdi_get_phy_cfg()
1417 sizeof (encp->enc_phy_revision)); in efx_mcdi_get_phy_cfg()
1418 (void) memcpy(encp->enc_phy_revision, in efx_mcdi_get_phy_cfg()
1450 encp->enc_mcdi_mdio_channel = in efx_mcdi_get_phy_cfg()
1454 encp->enc_mcdi_phy_stat_mask = in efx_mcdi_get_phy_cfg()
[all …]
H A Defx_phy.c79 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in efx_phy_probe() local
85 epp->ep_port = encp->enc_port; in efx_phy_probe()
86 epp->ep_phy_type = encp->enc_phy_type; in efx_phy_probe()
143 efx_nic_cfg_t *encp = (&enp->en_nic_cfg); in efx_phy_led_set() local
156 mask |= encp->enc_led_mask; in efx_phy_led_set()
H A Defx_tx.c301 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in efx_tx_qcreate() local
308 EFSYS_ASSERT3U(enp->en_tx_qcount + 1, <, encp->enc_txq_limit); in efx_tx_qcreate()
801 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in siena_tx_qpace() local
814 timer_period = 104 / encp->enc_clk_mult; in siena_tx_qpace()
895 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in siena_tx_qcreate() local
906 EFSYS_ASSERT(ISP2(EFX_TXQ_MAXNDESCS(encp))); in siena_tx_qcreate()
913 if (index >= encp->enc_txq_limit) { in siena_tx_qcreate()
918 (1 << size) <= (EFX_TXQ_MAXNDESCS(encp) / EFX_TXQ_MINNDESCS); in siena_tx_qcreate()
922 if (id + (1 << size) >= encp->enc_buftbl_limit) { in siena_tx_qcreate()
H A Def10_intr.c122 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in ef10_intr_trigger() local
125 if (encp->enc_bug41750_workaround) { in ef10_intr_trigger()
H A Dsiena_phy.c551 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in siena_phy_stats_update() local
552 uint32_t vmask = encp->enc_mcdi_phy_stat_mask; in siena_phy_stats_update()
580 EFSYS_ASSERT(smask == encp->enc_phy_stat_mask); in siena_phy_stats_update()
643 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); variable
677 encp->enc_phy_type == EFX_PHY_SFT9001B &&
756 encp->enc_phy_type == EFX_PHY_QLX111V &&
H A Dhunt_phy.c84 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); variable
147 encp->enc_phy_type == EFX_PHY_XFI_FARMI &&
H A Def10_ev.c250 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in ef10_ev_qcreate() local
263 if (index >= encp->enc_evq_limit) { in ef10_ev_qcreate()
409 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in ef10_ev_qmoderate() local
414 if (us > encp->enc_evq_timer_max_us) { in ef10_ev_qmoderate()
425 timer_val = us * 1000 / encp->enc_evq_timer_quantum_ns; in ef10_ev_qmoderate()
434 if (encp->enc_bug35388_workaround) { in ef10_ev_qmoderate()
H A Defx_port.c137 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in efx_port_loopback_set() local
147 if (EFX_TEST_QWORD_BIT(encp->enc_loopback_types[link_mode], in efx_port_loopback_set()
H A Defx_ev.c229 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in efx_ev_qcreate() local
236 EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit); in efx_ev_qcreate()
1196 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in siena_ev_qmoderate() local
1201 if (us > encp->enc_evq_timer_max_us) { in siena_ev_qmoderate()
1215 timer_val = us * 1000 / encp->enc_evq_timer_quantum_ns; in siena_ev_qmoderate()
1248 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in siena_ev_qcreate() local
1262 if (index >= encp->enc_evq_limit) { in siena_ev_qcreate()
1277 if (id + (1 << size) >= encp->enc_buftbl_limit) { in siena_ev_qcreate()
H A Def10_mcdi.c234 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in ef10_mcdi_feature_supported() local
235 uint32_t privilege_mask = encp->enc_privilege_mask; in ef10_mcdi_feature_supported()
/illumos-gate/usr/src/contrib/ast/src/lib/libast/uwin/
H A Dcrypt.c844 register char *encp; in crypt() local
866 encp = &cryptresult[0]; in crypt()
885 *encp++ = *setting++; in crypt()
892 encp[i] = t; in crypt()
896 encp += 4; in crypt()
908 encp[i] = t; in crypt()
911 encp += salt_size; in crypt()
923 encp[0] = itoa64[i]; encp += 4; in crypt()
928 encp[0] = itoa64[i]; encp += 4; in crypt()
932 encp[0] = itoa64[i]; in crypt()
[all …]
/illumos-gate/usr/src/lib/scsi/plugins/ses/SUN-Storage-J4400/common/
H A Driverwalk.c80 ses_node_t *encp; in sun_riverwalk_parse_node() local
93 for (encp = np; ses_node_type(encp) != SES_NODE_ENCLOSURE; in sun_riverwalk_parse_node()
94 encp = ses_node_parent(encp)) in sun_riverwalk_parse_node()
97 encprops = ses_node_props(encp); in sun_riverwalk_parse_node()
/illumos-gate/usr/src/lib/scsi/plugins/ses/SUN-Storage-J4500/common/
H A Dloki.c73 ses_node_t *encp; in sun_loki_parse_node() local
110 for (encp = np; ses_node_type(encp) != SES_NODE_ENCLOSURE; in sun_loki_parse_node()
111 encp = ses_node_parent(encp)) in sun_loki_parse_node()
114 encprops = ses_node_props(encp); in sun_loki_parse_node()
/illumos-gate/usr/src/uts/common/io/sfxge/
H A Dsfxge_mon.c72 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sp->s_enp); in sfxge_mon_kstat_update() local
93 if (encp->enc_mon_stat_mask[sn / EFX_MON_MASK_ELEMENT_SIZE] & in sfxge_mon_kstat_update()
128 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sp->s_enp); in sfxge_mon_kstat_init() local
144 if (encp->enc_mon_stat_mask[id / EFX_MON_MASK_ELEMENT_SIZE] & in sfxge_mon_kstat_init()
166 if (encp->enc_mon_stat_mask[id / EFX_MON_MASK_ELEMENT_SIZE] & in sfxge_mon_kstat_init()
214 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp); in sfxge_mon_init() local
228 dma_attr.sdba_length = encp->enc_mon_stat_dma_buf_size; in sfxge_mon_init()
238 smp->sm_type = encp->enc_mon_type; in sfxge_mon_init()
H A Dsfxge_phy.c81 const efx_nic_cfg_t *encp; in sfxge_phy_kstat_update() local
108 encp = efx_nic_cfg_get(enp); in sfxge_phy_kstat_update()
109 knp->value.ui64 = encp->enc_port; in sfxge_phy_kstat_update()
130 const efx_nic_cfg_t *encp; in sfxge_phy_kstat_init() local
141 encp = efx_nic_cfg_get(enp); in sfxge_phy_kstat_init()
144 encp->enc_phy_name); in sfxge_phy_kstat_init()
H A Dsfxge_mcdi.c370 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sp->s_enp); in sfxge_mcdi_ioctl() local
381 if (!(encp->enc_features & EFX_FEATURE_MCDI)) { in sfxge_mcdi_ioctl()
434 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sp->s_enp); in sfxge_mcdi2_ioctl() local
445 if (!(encp->enc_features & EFX_FEATURE_MCDI)) { in sfxge_mcdi2_ioctl()
H A Dsfxge.c69 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sp->s_enp); in sfxge_cfg_build() local
72 encp->enc_mac_addr[0], encp->enc_mac_addr[1], in sfxge_cfg_build()
73 encp->enc_mac_addr[2], encp->enc_mac_addr[3], in sfxge_cfg_build()
74 encp->enc_mac_addr[4], encp->enc_mac_addr[5]); in sfxge_cfg_build()

12