| /gfx-drm/usr/src/uts/intel/io/i915/ |
| H A D | dvo_ivch.c | 297 static void ivch_dpms(struct intel_dvo_device *dvo, bool enable) in ivch_dpms() argument
306 if (enable) in ivch_dpms()
312 if (enable) in ivch_dpms()
324 if (((vr30 & VR30_PANEL_ON) != 0) == enable) in ivch_dpms()
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| H A D | dvo_ns2501.c | 518 static void ns2501_dpms(struct intel_dvo_device *dvo, bool enable) in ns2501_dpms() argument
526 __FUNCTION__, enable); in ns2501_dpms()
530 if (enable) in ns2501_dpms()
544 enable ? 0x03 : 0x00); in ns2501_dpms()
547 enable ? 0xff : 0x00); in ns2501_dpms()
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| H A D | intel_drv.h | 115 void (*enable)(struct intel_encoder *); member
336 bool enable; member
746 int pixel_size, bool enable);
774 extern void intel_set_power_well(struct drm_device *dev, bool enable);
801 bool enable);
804 bool enable);
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| H A D | dvo_ch7017.c | 170 static void ch7017_dpms(struct intel_dvo_device *dvo, bool enable);
342 static void ch7017_dpms(struct intel_dvo_device *dvo, bool enable) in ch7017_dpms() argument
356 if (enable) { in ch7017_dpms()
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| H A D | dvo_sil164.c | 222 static void sil164_dpms(struct intel_dvo_device *dvo, bool enable) in sil164_dpms() argument
231 if (enable) in sil164_dpms()
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| H A D | dvo.h | 74 void (*dpms)(struct intel_dvo_device *dvo, bool enable);
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| H A D | dvo_tfp410.c | 250 static void tfp410_dpms(struct intel_dvo_device *dvo, bool enable) in tfp410_dpms() argument
257 if (enable) in tfp410_dpms()
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| H A D | dvo_ch7xxx.c | 324 static void ch7xxx_dpms(struct intel_dvo_device *dvo, bool enable) in ch7xxx_dpms() argument
326 if (enable) in ch7xxx_dpms()
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| H A D | i915_irq.c | 143 enum pipe pipe, bool enable) in ironlake_set_fifo_underrun_reporting() argument
149 if (enable) in ironlake_set_fifo_underrun_reporting()
156 bool enable) in ivybridge_set_fifo_underrun_reporting() argument
160 if (enable) { in ivybridge_set_fifo_underrun_reporting()
175 bool enable) in ibx_set_fifo_underrun_reporting() argument
182 if (enable) in ibx_set_fifo_underrun_reporting()
192 bool enable) in cpt_set_fifo_underrun_reporting() argument
196 if (enable) { in cpt_set_fifo_underrun_reporting()
239 if (enable == ret) in intel_set_cpu_fifo_underrun_reporting()
270 bool enable) in intel_set_pch_fifo_underrun_reporting() argument
[all …]
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| H A D | intel_pm.c | 2182 bool enable; member
2308 return result->enable; in hsw_compute_lp_wm()
2637 bool enable) in haswell_update_sprite_wm() argument
2645 intel_plane->wm.enable = enable; in haswell_update_sprite_wm()
2733 bool enable) in sandybridge_update_sprite_wm() argument
2741 if (!enable) in sandybridge_update_sprite_wm()
2856 bool enable) in intel_update_sprite_watermarks() argument
2862 pixel_size, enable); in intel_update_sprite_watermarks()
4563 if (enable) { in __intel_set_power_well()
4658 power_well->i915_request = enable; in intel_set_power_well()
[all …]
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| H A D | intel_i2c.c | 72 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) in intel_i2c_quirk_set() argument
81 if (enable) in intel_i2c_quirk_set()
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| H A D | i915_gem.c | 54 bool enable);
2333 bool enable) in i915_gem_object_update_fence() argument
2338 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); in i915_gem_object_update_fence()
2340 if (enable) { in i915_gem_object_update_fence()
2440 bool enable = obj->tiling_mode != I915_TILING_NONE; in i915_gem_object_get_fence() local
2461 } else if (enable) { in i915_gem_object_get_fence()
2478 i915_gem_object_update_fence(obj, reg, enable); in i915_gem_object_get_fence()
3577 ret = dev_priv->mm.aliasing_ppgtt->enable(dev); in i915_gem_init_hw()
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| H A D | intel_sdvo_regs.h | 618 unsigned int enable:1; member
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| H A D | intel_dvo.c | 474 intel_encoder->enable = intel_enable_dvo; in intel_dvo_init()
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| H A D | i915_drv.h | 157 void (*enable)(struct drm_i915_private *dev_priv, member
370 bool enable);
512 int (*enable)(struct drm_device *dev); member
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| H A D | intel_display.c | 1425 pll->enable(dev_priv, pll); in ironlake_enable_shared_dpll()
3249 encoder->enable(encoder); in ironlake_crtc_enable()
3359 encoder->enable(encoder); in haswell_crtc_enable()
3530 if (!enable && intel_crtc->overlay) { in intel_crtc_dpms_overlay()
3625 encoder->enable(encoder); in valleyview_crtc_enable()
3682 encoder->enable(encoder); in i9xx_crtc_enable()
3784 bool enable = false; in intel_crtc_update_dpms() local
3789 if (enable) in intel_crtc_update_dpms()
5934 bool enable = false; in haswell_modeset_global_resources() local
5943 enable = true; in haswell_modeset_global_resources()
[all …]
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| H A D | intel_crt.c | 791 crt->base.enable = intel_enable_crt; in intel_crt_init()
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| H A D | intel_lvds.c | 944 intel_encoder->enable = intel_enable_lvds; in intel_lvds_init()
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| H A D | intel_ddi.c | 1354 intel_encoder->enable = intel_enable_ddi; in intel_ddi_init()
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| H A D | i915_drv.c | 862 ret = dev_priv->mm.aliasing_ppgtt->enable(dev); in i915_reset()
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| H A D | i915_gem_gtt.c | 368 ppgtt->enable = gen6_ppgtt_enable; in gen6_ppgtt_init()
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| H A D | intel_tv.c | 1635 intel_encoder->enable = intel_enable_tv; in intel_tv_init()
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| H A D | intel_hdmi.c | 1255 intel_encoder->enable = intel_enable_hdmi; in intel_hdmi_init()
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| /gfx-drm/usr/src/uts/intel/io/agpgart/ |
| H A D | amd64_gart.c | 100 amd64_enable_gart(amd64_gart_softstate_t *sc, int enable) in amd64_enable_gart() argument
120 if (enable) { in amd64_enable_gart()
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| /gfx-drm/usr/src/uts/common/io/drm/ |
| H A D | drm_fb_helper.c | 510 bool enable; in drm_connector_enabled() local
513 enable = connector->status == connector_status_connected; in drm_connector_enabled()
515 enable = connector->status != connector_status_disconnected; in drm_connector_enabled()
517 return enable; in drm_connector_enabled()
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