/illumos-gate/usr/src/lib/libipmi/common/ |
H A D | ipmi_lancfg.c | 98 ipmi_lan_get_param(ipmi_handle_t *ihp, int channel, int param, int set, in ipmi_lan_get_param() argument 104 lcmd.ilgc_number = channel; in ipmi_lan_get_param() 133 ipmi_lan_get_config(ipmi_handle_t *ihp, int channel, ipmi_lan_config_t *cfgp) in ipmi_lan_get_config() argument 139 if (ipmi_lan_get_param(ihp, channel, IPMI_LAN_PARAM_SET_IN_PROGRESS, 0, in ipmi_lan_get_config() 150 if (ipmi_lan_get_param(ihp, channel, lep->ile_param, in ipmi_lan_get_config() 160 ipmi_lan_set_param(ipmi_handle_t *ihp, int channel, int param, void *data, in ipmi_lan_set_param() argument 166 lcmd.ilsc_number = channel; in ipmi_lan_set_param() 212 if (ipmi_lan_set_param(ihp, channel, IPMI_LAN_PARAM_SET_IN_PROGRESS, in ipmi_lan_set_config() 216 if (ipmi_lan_set_param(ihp, channel, IPMI_LAN_PARAM_SET_IN_PROGRESS, in ipmi_lan_set_config() 228 if (ipmi_lan_set_param(ihp, channel, lep->ile_param, in ipmi_lan_set_config() [all …]
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H A D | ipmi_misc.c | 128 ipmi_get_channel_auth_caps(ipmi_handle_t *ihp, uint8_t channel, uint8_t priv) in ipmi_get_channel_auth_caps() argument 134 if (channel > 0xF) { in ipmi_get_channel_auth_caps() 139 msg_data[0] = channel; in ipmi_get_channel_auth_caps() 170 uint8_t channel; in ipmi_get_channel_info() local 177 channel = (uint8_t)number; in ipmi_get_channel_info() 182 cmd.ic_data = &channel; in ipmi_get_channel_info() 183 cmd.ic_dlen = sizeof (channel); in ipmi_get_channel_info()
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H A D | ipmi_user.c | 106 ipmi_get_user_access(ipmi_handle_t *ihp, uint8_t channel, uint8_t uid) in ipmi_get_user_access() argument 111 req.igua_channel = channel; in ipmi_get_user_access() 187 uint8_t channel; in ipmi_user_iter() local 192 channel = IPMI_USER_CHANNEL_CURRENT; in ipmi_user_iter() 198 if ((resp = ipmi_get_user_access(ihp, channel, 1)) == NULL) { in ipmi_user_iter() 211 channel = 1; in ipmi_user_iter() 212 if ((resp = ipmi_get_user_access(ihp, channel, 1)) == NULL) in ipmi_user_iter() 219 channel, i)) == NULL) in ipmi_user_iter()
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/illumos-gate/usr/src/uts/common/io/hxge/ |
H A D | hpi_rxdma.h | 106 #define HXGE_RXDMA_OFFSET(x, v, channel) (x + \ argument 107 (!v ? DMC_OFFSET(channel) : \ 108 RDMC_PIOVADDR_OFFSET(channel))) 112 channel)), (data_p))\ 115 #define RXDMA_REG_READ32(handle, reg, channel, data_p) \ argument 117 channel)), (data_p)) 119 #define RXDMA_REG_WRITE64(handle, reg, channel, data) {\ argument 121 channel)), (data))\ 190 uint8_t channel, rdc_stat_t *cs_p); 192 uint8_t channel, rdc_int_mask_t *mask_p); [all …]
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H A D | hpi_rxdma.c | 527 if (!RXDMA_CHANNEL_VALID(channel)) { in hpi_rxdma_channel_rbr_empty_clear() 533 RXDMA_REG_READ64(handle, RDC_STAT, channel, &cs.value); in hpi_rxdma_channel_rbr_empty_clear() 535 RXDMA_REG_WRITE64(handle, RDC_STAT, channel, cs.value); in hpi_rxdma_channel_rbr_empty_clear() 550 if (!RXDMA_CHANNEL_VALID(channel)) { in hpi_rxdma_control_status() 552 "hpi_rxdma_control_status", "channel", channel)); in hpi_rxdma_control_status() 566 RXDMA_REG_READ64(handle, RDC_STAT, channel, &cs.value); in hpi_rxdma_control_status() 567 RXDMA_REG_WRITE64(handle, RDC_STAT, channel, in hpi_rxdma_control_status() 574 return (HPI_FAILURE | HPI_RXDMA_OPCODE_INVALID(channel)); in hpi_rxdma_control_status() 591 if (!RXDMA_CHANNEL_VALID(channel)) { in hpi_rxdma_event_mask() 593 "hpi_rxdma_event_mask", "channel", channel)); in hpi_rxdma_event_mask() [all …]
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H A D | hxge_txdma.h | 208 hxge_status_t hxge_reset_txdma_channel(p_hxge_t hxgep, uint16_t channel, 211 uint16_t channel, tdc_int_mask_t *mask_p); 212 hxge_status_t hxge_enable_txdma_channel(p_hxge_t hxgep, uint16_t channel, 227 void hxge_txdma_fix_channel(p_hxge_t hxgep, uint16_t channel); 229 uint16_t channel); 231 uint16_t channel); 235 void hxge_txdma_fix_hung_channel(p_hxge_t hxgep, uint16_t channel); 237 uint16_t channel); 242 p_tx_ring_t tx_ring_p, uint16_t channel); 244 int hxge_txdma_stop_inj_err(p_hxge_t hxgep, int channel);
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H A D | hxge_fzc.c | 174 hxge_init_fzc_rxdma_channel(p_hxge_t hxgep, uint16_t channel, in hxge_init_fzc_rxdma_channel() argument 182 status = hxge_init_fzc_rxdma_channel_pages(hxgep, channel, rbr_p); in hxge_init_fzc_rxdma_channel() 193 uint16_t channel, p_rx_rbr_ring_t rbrp) in hxge_init_fzc_rxdma_channel_pages() argument 204 rs = hpi_rxdma_cfg_logical_page_handle(handle, channel, in hxge_init_fzc_rxdma_channel_pages() 216 hxge_init_fzc_txdma_channel(p_hxge_t hxgep, uint16_t channel, in hxge_init_fzc_txdma_channel() argument 224 (void) hxge_init_fzc_txdma_channel_pages(hxgep, channel, tx_ring_p); in hxge_init_fzc_txdma_channel() 260 hxge_init_fzc_txdma_channel_pages(p_hxge_t hxgep, uint16_t channel, in hxge_init_fzc_txdma_channel_pages() argument 272 rs = hpi_txdma_log_page_handle_set(handle, channel, in hxge_init_fzc_txdma_channel_pages()
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H A D | hxge_fzc.h | 40 hxge_status_t hxge_init_fzc_txdma_channel(p_hxge_t hxgep, uint16_t channel, 43 hxge_status_t hxge_init_fzc_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 49 uint16_t channel, p_rx_rbr_ring_t rbr_p); 52 uint16_t channel, p_tx_ring_t tx_ring_p);
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/illumos-gate/usr/src/uts/common/io/xge/hal/xgehal/ |
H A D | xgehal-device-fp.c | 355 ((xge_hal_ring_t *)channel)->cmpl_cnt = 0; in xge_hal_device_poll_rx_channel() 356 channel->poll_bytes = 0; in xge_hal_device_poll_rx_channel() 359 if (channel->callback(channel, first_dtrh, in xge_hal_device_poll_rx_channel() 362 got_bytes += channel->poll_bytes + 1; in xge_hal_device_poll_rx_channel() 366 got_bytes += channel->poll_bytes + 1; in xge_hal_device_poll_rx_channel() 404 channel->poll_bytes = 0; in xge_hal_device_poll_tx_channel() 407 if (channel->callback(channel, first_dtrh, in xge_hal_device_poll_tx_channel() 410 got_bytes += channel->poll_bytes + 1; in xge_hal_device_poll_tx_channel() 414 got_bytes += channel->poll_bytes + 1; in xge_hal_device_poll_tx_channel() 445 xge_hal_channel_t *channel; in xge_hal_device_poll_rx_channels() local [all …]
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H A D | xgehal-fifo-fp.c | 68 xge_os_dma_sync(fifo->channel.pdev, in __hal_fifo_dtr_post_single() 77 fifo->channel.regh1, in __hal_fifo_dtr_post_single() 107 xge_os_pio_mem_write64(fifo->channel.pdev, fifo->channel.regh1, in __hal_fifo_dtr_post_single() 122 fifo->channel.stats.total_posts++; in __hal_fifo_dtr_post_single() 123 fifo->channel.usage_cnt++; in __hal_fifo_dtr_post_single() 124 if (fifo->channel.stats.usage_max < fifo->channel.usage_cnt) in __hal_fifo_dtr_post_single() 125 fifo->channel.stats.usage_max = fifo->channel.usage_cnt; in __hal_fifo_dtr_post_single() 668 xge_os_dma_sync(fifo->channel.pdev, in xge_hal_fifo_dtr_next_completed() 688 if (fifo->channel.usage_cnt > 0) in xge_hal_fifo_dtr_next_completed() 689 fifo->channel.usage_cnt--; in xge_hal_fifo_dtr_next_completed() [all …]
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H A D | xgehal-ring-fp.c | 506 if (channel->post_index != 0) { in xge_hal_ring_dtr_pre_post() 511 prev_dtrh = channel->work_arr[channel->post_index - 1]; in xge_hal_ring_dtr_pre_post() 554 xge_os_dma_sync(ring->channel.pdev, in xge_hal_ring_dtr_post_post() 564 if (ring->channel.usage_cnt > 0) in xge_hal_ring_dtr_post_post() 565 ring->channel.usage_cnt--; in xge_hal_ring_dtr_post_post() 591 xge_os_dma_sync(ring->channel.pdev, in xge_hal_ring_dtr_post_post_wmb() 597 if (ring->channel.usage_cnt > 0) in xge_hal_ring_dtr_post_post_wmb() 598 ring->channel.usage_cnt--; in xge_hal_ring_dtr_post_post_wmb() 729 ring->channel.usage_cnt++; in xge_hal_ring_dtr_next_completed() 730 if (ring->channel.stats.usage_max < ring->channel.usage_cnt) in xge_hal_ring_dtr_next_completed() [all …]
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H A D | xgehal-stats.c | 866 xge_hal_channel_t *channel; in xge_hal_stats_channel() local 870 if ((channel == NULL) || (channel->magic != XGE_HAL_MAGIC)) { in xge_hal_stats_channel() 880 !channel->is_open) { in xge_hal_stats_channel() 912 if (channel->stats.total_posts) { in xge_hal_stats_channel() 914 channel->stats.total_buffers / in xge_hal_stats_channel() 915 channel->stats.total_posts; in xge_hal_stats_channel() 920 channel->stats.total_posts); in xge_hal_stats_channel() 934 *channel_info = &channel->stats; in xge_hal_stats_channel() 976 xge_hal_channel_t *channel; in __hal_stats_soft_reset() local 1002 xge_os_memzero(&channel->stats, in __hal_stats_soft_reset() [all …]
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H A D | xgehal-mgmtaux.c | 882 xge_hal_channel_t *channel; in xge_hal_aux_stats_hal_read() local 971 __HAL_AUX_ENTRY(key, channel->usage_cnt, "%u"); in xge_hal_aux_stats_hal_read() 1263 xge_hal_channel_t *channel; in xge_hal_aux_channel_read() local 1279 if (channel->is_open != 1) in xge_hal_aux_channel_read() 1288 __HAL_AUX_ENTRY(key, channel->type, "%u"); in xge_hal_aux_channel_read() 1291 __HAL_AUX_ENTRY(key, channel->length, "%u"); in xge_hal_aux_channel_read() 1294 __HAL_AUX_ENTRY(key, channel->is_open, "%u"); in xge_hal_aux_channel_read() 1330 if (channel->is_open != 1) in xge_hal_aux_channel_read() 1339 __HAL_AUX_ENTRY(key, channel->type, "%u"); in xge_hal_aux_channel_read() 1342 __HAL_AUX_ENTRY(key, channel->length, "%u"); in xge_hal_aux_channel_read() [all …]
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/illumos-gate/usr/src/uts/intel/io/intel_nb5000/ |
H A D | nb5000_init.c | 180 int channel = bus & 1; in read_spd() local 182 rt = SPD_RD(branch, channel); in read_spd() 191 int channel = bus & 1; in write_spdcmd() local 192 SPDCMD_WR(branch, channel, val); in write_spdcmd() 304 read_spd_eeprom(channel, dimm, 125); in fbd_eeprom() 305 t = read_spd_eeprom(channel, dimm, 121); in fbd_eeprom() 380 nb_dimm_present(int channel, int dimm) in nb_dimm_present() argument 408 ddr2_eeprom(channel, dimm, dp); in nb_ddr2_dimm_init() 434 fbd_eeprom(channel, dimm, dp); in nb_fbd_dimm_init() 733 int channel = dimm >> 3; in x8450_dimm_label() local [all …]
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H A D | intel_nb5000.c | 97 int channel; in fat_memory_error() local 108 sp->channel = -1; in fat_memory_error() 121 sp->channel = channel; in fat_memory_error() 163 sp->channel = -1; in fat_memory_error() 250 sp->channel = -1; in nf_memory_error() 258 sp->channel = channel; in nf_memory_error() 393 int channel; in nf_mem_error() local 408 sp->channel = -1; in nf_mem_error() 417 sp->channel = -1; in nf_mem_error() 457 sp->channel = channel; in nf_mem_error() [all …]
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/illumos-gate/usr/src/uts/common/io/nxge/npi/ |
H A D | npi_txdma.h | 39 if (!TXDMA_CHANNEL_VALID(channel)) { \ 51 if (!TXDMA_CHANNEL_VALID(channel)) { \ 108 #define NXGE_TXLOG_OFFSET(x, channel) (x + TX_LOG_DMA_OFFSET(channel)) argument 115 #define NXGE_TXDMA_OFFSET(x, v, channel) (x + \ argument 116 (!v ? DMC_OFFSET(channel) : TDMC_PIOVADDR_OFFSET(channel))) 126 #define NXGE_TXDMA_DRR_OFFSET(x, channel) (x + \ argument 127 TXDMA_DRR_RNG_USE_OFFSET(channel)) 132 #define TX_LOG_REG_READ64(handle, reg, channel, val_p) \ argument 133 NXGE_REG_RD64(handle, NXGE_TXLOG_OFFSET(reg, channel), val_p) 135 #define TX_LOG_REG_WRITE64(handle, reg, channel, data) \ argument [all …]
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/illumos-gate/usr/src/uts/intel/io/intel_nhm/ |
H A D | nhm_init.c | 125 int channel; member 152 dsp->channel++; in dimm_label() 159 (dsp->channel * MAX_DIMMS_PER_CHANNEL); in dimm_label() 166 dsp->channel++; in dimm_label() 167 if (dsp->channel == in dimm_label() 169 dsp->channel = 0; in dimm_label() 175 (dsp->channel * in dimm_label() 194 dsp->channel++; in dimm_label() 195 if (dsp->channel == CHANNELS_PER_MEMORY_CONTROLLER) { in dimm_label() 196 dsp->channel = 0; in dimm_label() [all …]
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/illumos-gate/usr/src/uts/common/io/ib/mgt/ibcm/ |
H A D | ibcm_ti.c | 192 channel); in ibt_open_rc_channel() 224 channel); in ibt_open_rc_channel() 311 channel); in ibt_open_rc_channel() 358 channel); in ibt_open_rc_channel() 407 channel); in ibt_open_rc_channel() 590 statep->channel = channel; in ibt_open_rc_channel() 739 channel, statep); in ibt_open_rc_channel() 1147 channel); in ibt_prime_close_rc_channel() 1193 channel); in ibt_prime_close_rc_channel() 1226 channel); in ibt_close_rc_channel() [all …]
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/illumos-gate/usr/src/uts/i86pc/sys/ |
H A D | ioat.h | 108 #define IOAT_CMPL_INDEX(channel) \ argument 109 (((*channel->ic_cmpl & IOAT_CHAN_STS_ADDR_MASK) - \ 111 #define IOAT_CMPL_FAILED(channel) \ argument 112 (*channel->ic_cmpl & IOAT_CHAN_STS_FAIL_MASK) 347 void ioat_channel_intr(ioat_channel_t channel); 348 int ioat_cmd_alloc(void *channel, int flags, dcopy_cmd_t *cmd); 349 void ioat_cmd_free(void *channel, dcopy_cmd_t *cmd); 350 int ioat_cmd_post(void *channel, dcopy_cmd_t cmd); 351 int ioat_cmd_poll(void *channel, dcopy_cmd_t cmd);
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/illumos-gate/usr/src/uts/sun4v/sys/ |
H A D | hypervisor_api.h | 410 extern uint64_t hv_ldc_tx_qconf(uint64_t channel, uint64_t ra_base, 412 extern uint64_t hv_ldc_tx_qinfo(uint64_t channel, uint64_t *ra_base, 414 extern uint64_t hv_ldc_tx_get_state(uint64_t channel, uint64_t *headp, 416 extern uint64_t hv_ldc_tx_set_qtail(uint64_t channel, uint64_t tail); 417 extern uint64_t hv_ldc_rx_qconf(uint64_t channel, uint64_t ra_base, 419 extern uint64_t hv_ldc_rx_qinfo(uint64_t channel, uint64_t *ra_base, 421 extern uint64_t hv_ldc_rx_get_state(uint64_t channel, uint64_t *headp, 423 extern uint64_t hv_ldc_rx_set_qhead(uint64_t channel, uint64_t head); 429 extern uint64_t hv_ldc_copy(uint64_t channel, uint64_t request, 431 extern uint64_t hv_ldc_mapin(uint64_t channel, uint64_t cookie, [all …]
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/illumos-gate/usr/src/uts/intel/qlc/ |
H A D | Makefile | 38 CONF_SRCDIR = $(UTSBASE)/common/io/fibre-channel/fca/qlc 56 INC_PATH += -I$(UTSBASE)/common/sys/fibre-channel 57 INC_PATH += -I$(UTSBASE)/common/sys/fibre-channel/ulp 58 INC_PATH += -I$(UTSBASE)/common/sys/fibre-channel/fca/qlc 59 INC_PATH += -I$(UTSBASE)/common/sys/fibre-channel/impl
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/illumos-gate/usr/src/uts/common/io/nxge/ |
H A D | nxge_txc.c | 147 int channel) in nxge_txc_tdc_bind() argument 158 "==> nxge_txc_tdc_bind(port %d, channel %d)", port, channel)); in nxge_txc_tdc_bind() 175 if (bitmap & (1 << channel)) { in nxge_txc_tdc_bind() 178 channel, port)); in nxge_txc_tdc_bind() 181 bitmap |= (1 << channel); in nxge_txc_tdc_bind() 212 "<== nxge_txc_tdc_bind(port %d, channel %d)", port, channel)); in nxge_txc_tdc_bind() 249 int channel) in nxge_txc_tdc_unbind() argument 260 "==> nxge_txc_tdc_unbind(port %d, channel %d)", port, channel)); in nxge_txc_tdc_unbind() 270 bitmap &= (~(1 << channel)); in nxge_txc_tdc_unbind() 277 port, channel, rs)); in nxge_txc_tdc_unbind() [all …]
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/illumos-gate/usr/src/cmd/fm/eversholt/files/i386/i86pc/ |
H A D | intel.esc | 337 engine=serd.cpu.intel.nb.fbd.ch@dram-channel; 339 prop fault.memory.intel.fbd.ch@dram-channel (1)-> 340 ereport.cpu.intel.nb.fbd.ch@dram-channel; 342 prop fault.memory.intel.fbd.ch@dram-channel (0)-> 348 engine=serd.cpu.intel.nb.fbd_otf@dram-channel; 351 ereport.cpu.intel.nb.fbd.otf@dram-channel; 364 memory-controller/dram-channel {within(12s)}; 458 chip/memory-controller/dram-channel/dimm/rank 530 chip/memory-controller/dram-channel; 573 chip/memory-controller/dram-channel/dimm; [all …]
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/illumos-gate/usr/src/uts/common/sys/nxge/ |
H A D | nxge_defs.h | 410 #define TDMC_PIOVADDR_OFFSET(channel) (2 * DMA_CSR_SIZE * channel) argument 411 #define RDMC_PIOVADDR_OFFSET(channel) (TDMC_OFFSET(channel) + DMA_CSR_SIZE) argument 416 #define DMC_OFFSET(channel) (DMA_CSR_SIZE * channel) argument 417 #define TDMC_OFFSET(channel) (TX_RNG_CFIG + DMA_CSR_SIZE * channel) argument
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/illumos-gate/usr/src/lib/gss_mechs/mech_dh/backend/mech/ |
H A D | context_establish.c | 155 gss_channel_bindings_t channel, /* channel bindings */ in gen_accept_token() argument 178 accept->channel = GSS2DH_channel_binding(&dh_binding, channel); in gen_accept_token() 364 gss_channel_bindings_t channel, in __dh_gss_accept_sec_context() argument 465 clnt->cntx.channel); in __dh_gss_accept_sec_context() 466 if (!gss_chanbind_cmp(channel, dh_binding)) { in __dh_gss_accept_sec_context() 621 remote->cntx.channel = GSS2DH_channel_binding(&dh_binding, channel); in gen_init_token() 762 channel, results); in create_context() 854 remote_ctx->channel); in continue_context() 855 if (!gss_chanbind_cmp(channel, remote_chan)) { in continue_context() 945 (dh_principal)target, channel, req_flags, in __dh_gss_init_sec_context() [all …]
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