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Searched refs:channel (Results 1 – 25 of 243) sorted by relevance

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/illumos-gate/usr/src/uts/common/io/xge/hal/xgehal/
H A Dxgehal-channel.c41 if (channel->reserve_top >= channel->reserve_length) { in __hal_channel_dtr_next_reservelist()
45 *dtrh = channel->reserve_arr[channel->reserve_top++]; in __hal_channel_dtr_next_reservelist()
64 *dtrh = channel->free_arr[channel->free_length++]; in __hal_channel_dtr_next_freelist()
163 xge_os_free(channel->pdev, channel, size); in __hal_channel_free()
186 channel->reserve_length = channel->reserve_initial; in __hal_channel_initialize()
195 channel->free_arr = channel->saved_arr; in __hal_channel_initialize()
196 channel->free_length = channel->reserve_initial; in __hal_channel_initialize()
206 channel->length = channel->reserve_initial; in __hal_channel_initialize()
234 xge_os_free(channel->pdev, channel->work_arr, in __hal_channel_terminate()
240 xge_os_free(channel->pdev, channel->saved_arr, in __hal_channel_terminate()
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H A Dxgehal-channel-fp.c40 if (channel->reserve_length - channel->reserve_top > in __hal_channel_dtr_alloc()
49 channel->type, channel->post_qid, in __hal_channel_dtr_alloc()
50 channel->compl_qid, channel->reserve_length); in __hal_channel_dtr_alloc()
71 channel->reserve_arr = channel->free_arr; in __hal_channel_dtr_alloc()
74 channel->reserve_top = channel->free_length; in __hal_channel_dtr_alloc()
75 channel->free_length = channel->reserve_initial; in __hal_channel_dtr_alloc()
101 channel->type, channel->post_qid, in __hal_channel_dtr_alloc()
132 channel->type, channel->post_qid, channel->compl_qid, in __hal_channel_dtr_restore()
147 if (channel->post_index == channel->length) in __hal_channel_dtr_post()
170 if (++channel->compl_index == channel->length) in __hal_channel_dtr_complete()
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H A Dxgehal-ring.c220 if (channel->dtr_init) { in __hal_ring_initial_replenish()
221 status = channel->dtr_init(channel, in __hal_ring_initial_replenish()
338 ring->channel.usage_cnt = 0; in __hal_ring_open()
410 xge_os_pio_mem_write64(ring->channel.pdev, ring->channel.regh0, in __hal_ring_prc_enable()
417 ring->channel.regh0, &bar0->prc_ctrl_n[ring->channel.post_qid]); in __hal_ring_prc_enable()
440 xge_os_pio_mem_write64(ring->channel.pdev, ring->channel.regh0, in __hal_ring_prc_enable()
452 xge_os_pio_mem_write64(ring->channel.pdev, ring->channel.regh0, in __hal_ring_prc_enable()
472 ring->channel.regh0, in __hal_ring_prc_disable()
475 xge_os_pio_mem_write64(ring->channel.pdev, ring->channel.regh0, in __hal_ring_prc_disable()
619 channel = tmp; in __hal_ring_hw_initialize()
[all …]
H A Dxgehal-fifo.c88 if (fifo->channel.dtr_init) { in __hal_fifo_mempool_item_alloc()
125 xge_os_dma_unmap(fifo->channel.pdev, in __hal_fifo_mempool_item_free()
135 xge_os_dma_free(fifo->channel.pdev, in __hal_fifo_mempool_item_free()
277 fifo->channel.reserve_length, fifo->channel.reserve_top, in __hal_fifo_open()
294 mid_point = (fifo->channel.reserve_length - fifo->channel.reserve_top)/2; in __hal_fifo_open()
296 dtrh = fifo->channel.reserve_arr[i]; in __hal_fifo_open()
297 fifo->channel.reserve_arr[i] = in __hal_fifo_open()
461 xge_hal_channel_t *channel = NULL; in __hal_fifo_hw_initialize() local
474 channel = tmp; in __hal_fifo_hw_initialize()
479 if (channel) { in __hal_fifo_hw_initialize()
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/illumos-gate/usr/src/uts/i86pc/io/ioat/
H A Dioat_chan.c259 *chan = channel; in ioat_channel_alloc()
266 ioat_ring_free(channel); in ioat_channel_alloc()
296 ioat_channel_t channel; in ioat_channel_resume() local
353 bzero((void *)channel->ic_cmpl, channel->ic_cmpl_alloc_size); in ioat_channel_resume()
392 if (!channel->ic_inuse) in ioat_channel_quiesce()
418 channel = *chan; in ioat_channel_free()
571 bzero((void *)channel->ic_cmpl, channel->ic_cmpl_alloc_size); in ioat_completion_alloc()
573 (caddr_t)channel->ic_cmpl, channel->ic_cmpl_alloc_size, in ioat_completion_alloc()
582 channel->ic_phys_cmpl = channel->ic_cmpl_cookie.dmac_laddress; in ioat_completion_alloc()
666 channel->ic_desc_alloc_size = channel->ic_chan_desc_cnt * in ioat_ring_alloc()
[all …]
/illumos-gate/usr/src/uts/common/io/
H A Ddcopy.c348 if ((*channel)->ch_removing && ((*channel)->ch_ref_cnt == 0)) { in dcopy_free()
368 *channel = NULL; in dcopy_free()
433 channel->ch_cb->cb_cmd_free(channel->ch_channel_private, cmd); in dcopy_cmd_free()
633 channel = kmem_zalloc(sizeof (*channel), KM_SLEEP); in dcopy_device_register()
643 kmem_free(channel, sizeof (*channel)); in dcopy_device_register()
651 kmem_free(channel, sizeof (*channel)); in dcopy_device_register()
662 kmem_free(channel, sizeof (*channel)); in dcopy_device_register()
681 channel); in dcopy_device_register()
705 kmem_free(channel, sizeof (*channel)); in dcopy_device_register()
793 kmem_free(channel, sizeof (*channel)); in dcopy_device_cleanup()
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/illumos-gate/usr/src/uts/common/io/nxge/npi/
H A Dnpi_txdma.c34 uint8_t channel);
36 uint8_t channel);
38 uint8_t channel);
464 channel)); in npi_txdma_log_page_handle_set()
514 channel)); in npi_txdma_log_page_config()
673 channel)); in npi_txdma_log_page_vld_config()
738 channel)); in npi_txdma_channel_reset()
924 channel)); in npi_txdma_channel_control()
1041 channel)); in npi_txdma_control_status()
1106 channel)); in npi_txdma_event_mask()
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H A Dnpi_rxdma.c1795 channel, cs.value); in npi_rxdma_rdc_rcr_pktread_update()
1827 channel, cs.value); in npi_rxdma_rdc_rcr_bufread_update()
1865 channel, cs.value); in npi_rxdma_rdc_rcr_read_update()
1947 channel)); in npi_rxdma_channel_pt_drop_pkt_clear()
1970 channel)); in npi_rxdma_channel_wred_dop_clear()
1993 channel)); in npi_rxdma_channel_rcr_shfull_clear()
2016 channel)); in npi_rxdma_channel_rcr_full_clear()
2060 uint8_t channel) in npi_rxdma_channel_control() argument
2079 channel, cs.value); in npi_rxdma_channel_control()
2185 "channel", channel)); in npi_rxdma_control_status()
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H A Dnpi_txc.c271 if (!TXDMA_CHANNEL_VALID(channel)) { in npi_txc_dma_max_burst()
275 channel)); in npi_txc_dma_max_burst()
321 if (!TXDMA_CHANNEL_VALID(channel)) { in npi_txc_dma_max_burst_set()
325 channel)); in npi_txc_dma_max_burst_set()
330 channel, (uint64_t)max_burst); in npi_txc_dma_max_burst_set()
358 if (!TXDMA_CHANNEL_VALID(channel)) { in npi_txc_dma_bytes_transmitted()
362 channel)); in npi_txc_dma_bytes_transmitted()
647 uint8_t channel) in npi_txc_port_dma_channel_enable() argument
663 (val | (1 << channel))); in npi_txc_port_dma_channel_enable()
685 uint8_t channel) in npi_txc_port_dma_channel_disable() argument
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/illumos-gate/usr/src/uts/common/io/hxge/
H A Dhpi_txdma.c33 uint8_t channel);
41 if (!TXDMA_CHANNEL_VALID(channel)) { in hpi_txdma_log_page_handle_set()
87 uint8_t channel) in hpi_txdma_channel_control() argument
93 if (!TXDMA_CHANNEL_VALID(channel)) { in hpi_txdma_channel_control()
171 if (!TXDMA_CHANNEL_VALID(channel)) { in hpi_txdma_control_status()
209 if (!TXDMA_CHANNEL_VALID(channel)) { in hpi_txdma_event_mask()
212 channel)); in hpi_txdma_event_mask()
246 if (!TXDMA_CHANNEL_VALID(channel)) { in hpi_txdma_ring_config()
279 if (!TXDMA_CHANNEL_VALID(channel)) { in hpi_txdma_mbox_config()
282 channel)); in hpi_txdma_mbox_config()
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H A Dhxge_txdma.c845 channel = ldvp->channel; in hxge_tx_intr()
1089 channel); in hxge_fixup_txdma_rings()
1187 channel); in hxge_txdma_hw_kick()
1387 channel); in hxge_fixup_hung_txdma_rings()
1505 channel)); in hxge_reclaim_rings()
2525 channel = ldvp->channel; in hxge_tx_err_evnts()
2743 channel)); in hxge_txdma_fatal_err_recover()
2754 channel)); in hxge_txdma_fatal_err_recover()
2761 channel)); in hxge_txdma_fatal_err_recover()
2785 channel)); in hxge_txdma_fatal_err_recover()
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H A Dhpi_txdma.h46 #define HXGE_TXDMA_OFFSET(x, v, channel) (x + \ argument
47 (!v ? DMC_OFFSET(channel) : TDMC_PIOVADDR_OFFSET(channel)))
102 uint8_t channel, tdc_page_handle_t *hdl_p);
105 uint8_t channel);
109 uint8_t channel);
111 txdma_cs_cntl_t control, uint8_t channel);
113 uint8_t channel, tdc_stat_t *cs_p);
116 uint8_t channel, tdc_int_mask_t *mask_p);
119 uint8_t channel, uint64_t *reg_data);
121 uint8_t channel, uint64_t *mbox_addr);
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H A Dhxge_rxdma.c95 uint16_t channel);
103 uint16_t channel);
764 uint16_t channel; in hxge_rxdma_hw_mode() local
815 channel)); in hxge_rxdma_hw_mode()
820 channel)); in hxge_rxdma_hw_mode()
1084 uint8_t channel; in hxge_rx_intr() local
1412 if (channel != ldvp->channel) { in hxge_rx_pkts()
1415 vindex, ldvp->channel, channel)); in hxge_rx_pkts()
1631 uint8_t channel; in hxge_receive_packet() local
2108 channel = ldvp->channel; in hxge_rx_err_evnts()
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H A Dhxge_defs.h84 #define TDMC_PIOVADDR_OFFSET(channel) (2 * DMA_CSR_SIZE * channel) argument
85 #define RDMC_PIOVADDR_OFFSET(channel) (TDMC_OFFSET(channel) + DMA_CSR_SIZE) argument
90 #define DMC_OFFSET(channel) (DMA_CSR_SIZE * channel) argument
91 #define TDMC_OFFSET(channel) (TX_RNG_CFIG + DMA_CSR_SIZE * channel) argument
H A Dhxge_kstats.c790 for (channel = 0; channel < p_cfgp->max_rdcs; channel++) { in hxge_destroy_kstats()
796 for (channel = 0; channel < p_cfgp->max_tdcs; channel++) { in hxge_destroy_kstats()
988 for (channel = 0; channel < hxgep->nrdc; channel++) { in hxge_m_stat()
998 for (channel = 0; channel < hxgep->ntdc; channel++) { in hxge_m_stat()
1008 for (channel = 0; channel < hxgep->nrdc; channel++) { in hxge_m_stat()
1014 for (channel = 0; channel < hxgep->nrdc; channel++) { in hxge_m_stat()
1020 for (channel = 0; channel < hxgep->ntdc; channel++) { in hxge_m_stat()
1026 for (channel = 0; channel < hxgep->ntdc; channel++) { in hxge_m_stat()
1096 for (channel = 0; channel < hxgep->ntdc; channel++) { in hxge_m_stat()
1117 for (channel = 0; channel < hxgep->ntdc; channel++) { in hxge_m_stat()
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/illumos-gate/usr/src/uts/common/io/nxge/
H A Dnxge_txdma.c150 int channel) in nxge_init_txdma_channel() argument
276 channel); in nxge_reset_txdma_channel()
1131 uint8_t channel; in nxge_tx_intr() local
1168 channel = ldvp->channel; in nxge_tx_intr()
1250 int channel) in nxge_txdma_channel_disable() argument
1282 rs, channel)); in nxge_txdma_channel_disable()
2562 channel)); in nxge_map_txdma_channel_buf_ring()
3158 uint8_t channel; in nxge_tx_err_evnts() local
3169 channel = ldvp->channel; in nxge_tx_err_evnts()
3283 uint16_t channel, in nxge_txdma_fatal_err_recover() argument
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H A Dnxge_rxdma.c166 for (channel = 0; channel < NXGE_MAX_RDCS; channel++) { in nxge_init_rxdma_channels()
188 for (channel = 0; channel < NXGE_MAX_RDCS; channel++) { in nxge_init_rxdma_channels()
1796 channel = ldvp->channel; in nxge_rx_intr()
1843 channel, in nxge_rx_intr()
2064 channel, in nxge_rx_pkts()
2096 channel, in nxge_rx_pkts()
2137 channel, in nxge_rx_pkts()
3739 channel)); in nxge_map_rxdma_channel_buf_ring()
4122 i = channel; in nxge_rxdma_hw_start()
4165 channel)); in nxge_rxdma_hw_stop()
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H A Dnxge_hio.c492 dc->channel = (nxge_channel_t)channel; in nxge_grp_dc_add()
586 channel = dc->channel; in nxge_grp_dc_remove()
605 int channel) in nxge_grp_dc_find() argument
621 if (current->channel == channel) { in nxge_grp_dc_find()
699 int channel) in nxge_grp_dc_unlink() argument
717 if (current->channel == channel) { in nxge_grp_dc_unlink()
2093 int channel) in nxge_hio_tdc_share() argument
2205 int channel) in nxge_hio_rdc_share() argument
2299 int channel) in nxge_hio_dc_share() argument
2333 dc->channel = (nxge_channel_t)channel; in nxge_hio_dc_share()
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H A Dnxge_fzc.c476 uint16_t channel, in nxge_init_fzc_rdc_pages() argument
1275 channel, in nxge_init_hv_fzc_txdma_channel_pages()
1297 channel, in nxge_init_hv_fzc_txdma_channel_pages()
1311 channel, in nxge_init_hv_fzc_txdma_channel_pages()
1332 channel, in nxge_init_hv_fzc_txdma_channel_pages()
1345 channel, in nxge_init_hv_fzc_txdma_channel_pages()
1366 channel, in nxge_init_hv_fzc_txdma_channel_pages()
1414 channel, in nxge_init_hv_fzc_rxdma_channel_pages()
1437 channel, in nxge_init_hv_fzc_rxdma_channel_pages()
1460 channel, in nxge_init_hv_fzc_rxdma_channel_pages()
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H A Dnxge_intr.c73 int channel) in nxge_intr_add() argument
164 int channel) in nxge_intr_remove() argument
249 int channel) in nxge_intr_vec_find() argument
281 if (ldvp->channel == channel) in nxge_intr_vec_find()
320 int channel) in nxge_hio_intr_add() argument
423 int channel) in nxge_hio_intr_remove() argument
446 c, channel)); in nxge_hio_intr_remove()
704 int channel; in nxge_hio_intr_uninit() local
708 for (channel = 0; channel < NXGE_MAX_TDCS; channel++) { in nxge_hio_intr_uninit()
717 for (channel = 0; channel < NXGE_MAX_RDCS; channel++) { in nxge_hio_intr_uninit()
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H A Dnxge_hio_guest.c602 int channel) in nxge_tdc_lp_conf() argument
644 channel, hv_rv, in nxge_tdc_lp_conf()
679 channel, hv_rv, in nxge_tdc_lp_conf()
721 int channel) in nxge_rdc_lp_conf() argument
762 channel, hv_rv, in nxge_rdc_lp_conf()
797 channel, hv_rv, in nxge_rdc_lp_conf()
925 uint32_t channel; in nxge_hio_rdc_intr_arm() local
947 for (channel = 0; channel < NXGE_MAX_RDCS; channel++) { in nxge_hio_rdc_intr_arm()
980 uint32_t channel; in nxge_hio_rdc_enable() local
1003 for (channel = 0; channel < NXGE_MAX_RDCS; channel++) { in nxge_hio_rdc_enable()
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/illumos-gate/usr/src/uts/intel/io/intel_nhm/
H A Dmem_addr.c65 if (channel > 1) in channel_in_interleave()
72 c = 1 << channel; in channel_in_interleave()
163 channel = 0; in channel_address()
233 channel = 0; in address_to_channel()
236 channel = 1; in address_to_channel()
239 channel = 2; in address_to_channel()
251 channel = 0; in address_to_channel()
254 channel = 1; in address_to_channel()
341 channel = 0; in socket_interleave()
640 int channel; in nhm_patounum() local
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H A Dintel_nhm.h76 #define MC_CHANNEL_RANK_PRESENT_RD(cpu, channel) \ argument
78 #define MC_DOD_RD(cpu, channel, select) \ argument
80 #define MC_SAG_RD(cpu, channel, select) \ argument
82 #define MC_RIR_LIMIT_RD(cpu, channel, select) \ argument
84 #define MC_RIR_WAY_RD(cpu, channel, select) \ argument
86 #define MC_CHANNEL_DIMM_INIT_PARAMS_RD(cpu, channel) \ argument
102 #define MC_CONTROL_CHANNEL_ACTIVE(reg, channel) \ argument
103 ((reg) & (1 << (8 + (channel))) != 0)
113 #define CHANNEL_DISABLED(reg, channel) ((reg) & (1 << (channel))) argument
251 #define TAD_INTERLEAVE(list, channel) (((list) >> ((channel) * 4)) & 3) argument
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/illumos-gate/usr/src/uts/intel/io/vmm/io/
H A Dvatpit.c89 struct channel { struct
115 struct channel channel[3]; argument
131 struct channel *c; in vatpit_get_out()
135 c = &vatpit->channel[channel]; in vatpit_get_out()
193 struct channel *c = &vatpit->channel[0]; in vatpit_callout_reset()
203 struct channel *c = &vatpit->channel[0]; in pit_timer_start_cntr0()
271 c = &vatpit->channel[channel]; in pit_readback1()
520 struct channel *c = &vatpit->channel[0]; in vatpit_pause()
530 struct channel *c = &vatpit->channel[0]; in vatpit_resume()
552 const struct channel *src = &vatpit->channel[i]; in vatpit_data_read()
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/illumos-gate/usr/src/uts/sun4u/io/i2c/clients/
H A Dtda8444.c164 int channel; in tda8444_do_resume() local
175 for (channel = 0; channel < TDA8444_CHANS; channel++) { in tda8444_do_resume()
177 channel; in tda8444_do_resume()
179 unitp->tda8444_output[channel]; in tda8444_do_resume()
181 channel, unitp->tda8444_output[channel])); in tda8444_do_resume()
353 int channel = TDA8444_MINOR_TO_CHANNEL(*devp); in tda8444_open() local
376 if (unitp->tda8444_oflag[channel] != 0) { in tda8444_open()
379 unitp->tda8444_oflag[channel] = FEXCL; in tda8444_open()
382 if (unitp->tda8444_oflag[channel] == FEXCL) { in tda8444_open()
400 int channel = TDA8444_MINOR_TO_CHANNEL(dev); in tda8444_close() local
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