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Searched refs:ah_caps (Results 1 – 9 of 9) sorted by relevance

/illumos-gate/usr/src/uts/common/io/arn/
H A Darn_regd.c100 regcap = ah->ah_caps.reg_cap; in ath9k_regd_is_fcc_midband_supported()
152 bcopy(ah->ah_caps.wireless_modes, modes_allowed, in ath9k_regd_get_wmodes_nreg()
153 sizeof (ah->ah_caps.wireless_modes)); in ath9k_regd_get_wmodes_nreg()
155 if (is_set(ATH9K_MODE_11G, ah->ah_caps.wireless_modes) && in ath9k_regd_get_wmodes_nreg()
159 if (is_set(ATH9K_MODE_11A, ah->ah_caps.wireless_modes) && in ath9k_regd_get_wmodes_nreg()
163 if (is_set(ATH9K_MODE_11NG_HT20, ah->ah_caps.wireless_modes) && in ath9k_regd_get_wmodes_nreg()
167 if (is_set(ATH9K_MODE_11NA_HT20, ah->ah_caps.wireless_modes) && in ath9k_regd_get_wmodes_nreg()
455 !(ah->ah_caps.hw_caps & ATH9K_HW_CAP_CHAN_HALFRATE)) { in ath9k_regd_add_channel()
548 uint32_t regcap = ah->ah_caps.reg_cap; in ath9k_regd_add_channel()
612 regcap = ah->ah_caps.reg_cap; in ath9k_regd_japan_check()
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H A Darn_hw.c149 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; in ath9k_get_channel_edges()
2547 for (i = 0; i < ah->ah_caps.total_queues; i++) in ath9k_hw_reset()
2554 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) in ath9k_hw_reset()
2624 if (entry >= ah->ah_caps.keycache_size) { in ath9k_hw_keyreset()
2664 if (entry >= ah->ah_caps.keycache_size) { in ath9k_hw_keysetmac()
2825 if (entry < ah->ah_caps.keycache_size) { in ath9k_hw_keyisvalid()
3047 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; in ath9k_hw_getisr()
3191 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; in ath9k_hw_set_interrupts()
3789 ASSERT(gpio < ah->ah_caps.num_gpio_pins); in ath9k_hw_cfg_gpio_input()
3802 if (gpio >= ah->ah_caps.num_gpio_pins) in ath9k_hw_gpio_get()
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H A Darn_mac.c572 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; in ath9k_hw_set_txq_props()
643 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; in ath9k_hw_get_txq_props()
683 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; in ath9k_hw_setuptxqueue()
754 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; in ath9k_hw_releasetxqueue()
788 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; in ath9k_hw_resettxqueue()
1020 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; in ath9k_hw_setuprxdesc()
H A Darn_main.c1167 if (!(ah->ah_caps.hw_caps & in arn_isr()
2106 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT) in arn_open()
2111 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) in arn_open()
2132 if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) && in arn_open()
2600 rx_streams = ISP2(sc->sc_ah->ah_caps.rx_chainmask) ? 1 : 2; in arn_setup_ht_cap()
2744 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask; in arn_update_chainmask()
2745 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask; in arn_update_chainmask()
2883 sc->sc_keymax = ah->ah_caps.keycache_size; in arn_attach()
3052 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) { in arn_attach()
3071 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) { in arn_attach()
H A Darn_beacon.c59 (ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) { in arn_beacon_setup()
H A Darn_recv.c162 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) in arn_opmode_init()
H A Darn_rc.c1490 if (sc->sc_ah->ah_caps.tx_chainmask != 1 && is_rc_ds) { in arn_rc_init()
1693 sc->sc_ah->ah_caps.tx_triglevel_max; in arn_rate_init()
H A Darn_xmit.c1349 if ((ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) && bf_isdata(bf)) { in ath_buf_set_rate()
1364 if (bf_isaggr(bf) && (bf->bf_al > ah->ah_caps.rts_aggr_limit)) in ath_buf_set_rate()
H A Darn_ath9k.h802 struct ath9k_hw_capabilities ah_caps; member