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Searched refs:WM0_PIPEA_ILK (Results 1 – 2 of 2) sorted by relevance

/gfx-drm/usr/src/uts/intel/io/i915/
H A Dintel_pm.c1807 I915_WRITE(WM0_PIPEA_ILK, in ironlake_update_wm()
1890 val = I915_READ(WM0_PIPEA_ILK); in sandybridge_update_wm()
1892 I915_WRITE(WM0_PIPEA_ILK, val | in sandybridge_update_wm()
1993 val = I915_READ(WM0_PIPEA_ILK); in ivybridge_update_wm()
1995 I915_WRITE(WM0_PIPEA_ILK, val | in ivybridge_update_wm()
2525 previous.wm_pipe[0] = I915_READ(WM0_PIPEA_ILK); in hsw_write_wm_values()
2563 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); in hsw_write_wm_values()
2746 reg = WM0_PIPEA_ILK; in sandybridge_update_sprite_wm()
H A Di915_reg.h3172 #define WM0_PIPEA_ILK 0x45100 macro