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Searched refs:TRANS_DPLL_ENABLE (Results 1 – 2 of 2) sorted by relevance

/gfx-drm/usr/src/uts/intel/io/i915/
H A Di915_reg.h4076 #define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3)) macro
H A Dintel_display.c2956 temp |= TRANS_DPLL_ENABLE(pipe); in ironlake_pch_enable()
3442 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); in ironlake_crtc_disable()