Home
last modified time | relevance | path

Searched refs:TRANS_DPLLB_SEL (Results 1 – 2 of 2) sorted by relevance

/gfx-drm/usr/src/uts/intel/io/i915/
H A Dintel_display.c2957 sel = TRANS_DPLLB_SEL(pipe); in ironlake_pch_enable()
3442 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); in ironlake_crtc_disable()
5911 if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) in ironlake_get_pipe_config()
H A Di915_reg.h4074 #define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4)) macro